/***************************************************************************
 *     Copyright (c) 1999-2013, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Wed May  8 03:09:20 2013
 *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_SWITCH_REG_H__
#define BCHP_SWITCH_REG_H__

/***************************************************************************
 *SWITCH_REG
 ***************************************************************************/
#define BCHP_SWITCH_REG_SWITCH_CNTRL             0x04e40000 /* Switch Control Register */
#define BCHP_SWITCH_REG_SWITCH_STATUS            0x04e40004 /* Switch Status Register */
#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG       0x04e40008 /* Direct Data Write Register */
#define BCHP_SWITCH_REG_DIR_DATA_READ_REG        0x04e4000c /* Direct Data Read Register */
#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT 0x04e40010 /* LED Serial Refresh Time Unit Register */
#define BCHP_SWITCH_REG_SWITCH_REVISION          0x04e40018 /* SWITCH Revision Control Register */
#define BCHP_SWITCH_REG_PHY_REVISION             0x04e4001c /* PHY Revision Control Register */
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL           0x04e40020 /* PHY Test Control Register */
#define BCHP_SWITCH_REG_QPHY_CNTRL               0x04e40024 /* Quad GPHY Control Register */
#define BCHP_SWITCH_REG_QPHY_STATUS              0x04e40028 /* Quad GPHY Status Register */
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL     0x04e40088 /* LED port Blink Rate Control Register */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL         0x04e4008c /* LED Serial Control Register */
#define BCHP_SWITCH_REG_LED_0_CNTRL              0x04e40090 /* LED port 0 Control Register */
#define BCHP_SWITCH_REG_LED_1_CNTRL              0x04e40094 /* LED port 1 Control Register */
#define BCHP_SWITCH_REG_LED_2_CNTRL              0x04e40098 /* LED port 2 Control Register */
#define BCHP_SWITCH_REG_LED_3_CNTRL              0x04e4009c /* LED port 3 Control Register */
#define BCHP_SWITCH_REG_LED_7_CNTRL              0x04e400a8 /* LED port 7 Control Register */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL            0x04e400b0 /* RGMII port 9 Control Register */
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS        0x04e400b4 /* RGMII port 9 InBand Status Register */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL 0x04e400b8 /* RGMII port 9 RX Clock Delay Control Register */

/***************************************************************************
 *SWITCH_CNTRL - Switch Control Register
 ***************************************************************************/
/* SWITCH_REG :: SWITCH_CNTRL :: reserved0 [31:01] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_reserved0_MASK                0xfffffffe
#define BCHP_SWITCH_REG_SWITCH_CNTRL_reserved0_SHIFT               1

/* SWITCH_REG :: SWITCH_CNTRL :: mdio_master_sel [00:00] */
#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_MASK          0x00000001
#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_SHIFT         0
#define BCHP_SWITCH_REG_SWITCH_CNTRL_mdio_master_sel_DEFAULT       0x00000000

/***************************************************************************
 *SWITCH_STATUS - Switch Status Register
 ***************************************************************************/
/* SWITCH_REG :: SWITCH_STATUS :: reserved0 [31:01] */
#define BCHP_SWITCH_REG_SWITCH_STATUS_reserved0_MASK               0xfffffffe
#define BCHP_SWITCH_REG_SWITCH_STATUS_reserved0_SHIFT              1

/* SWITCH_REG :: SWITCH_STATUS :: sw_init_done [00:00] */
#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_MASK            0x00000001
#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_SHIFT           0
#define BCHP_SWITCH_REG_SWITCH_STATUS_sw_init_done_DEFAULT         0x00000000

/***************************************************************************
 *DIR_DATA_WRITE_REG - Direct Data Write Register
 ***************************************************************************/
/* SWITCH_REG :: DIR_DATA_WRITE_REG :: write_data [31:00] */
#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_MASK         0xffffffff
#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_SHIFT        0
#define BCHP_SWITCH_REG_DIR_DATA_WRITE_REG_write_data_DEFAULT      0x00000000

/***************************************************************************
 *DIR_DATA_READ_REG - Direct Data Read Register
 ***************************************************************************/
/* SWITCH_REG :: DIR_DATA_READ_REG :: read_data [31:00] */
#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_MASK           0xffffffff
#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_SHIFT          0
#define BCHP_SWITCH_REG_DIR_DATA_READ_REG_read_data_DEFAULT        0x00000000

/***************************************************************************
 *LED_SERIAL_REFRESH_TIME_UNIT - LED Serial Refresh Time Unit Register
 ***************************************************************************/
/* SWITCH_REG :: LED_SERIAL_REFRESH_TIME_UNIT :: reserved0 [31:24] */
#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_reserved0_MASK 0xff000000
#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_reserved0_SHIFT 24

/* SWITCH_REG :: LED_SERIAL_REFRESH_TIME_UNIT :: refresh_time_unit [23:00] */
#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_MASK 0x00ffffff
#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_SHIFT 0
#define BCHP_SWITCH_REG_LED_SERIAL_REFRESH_TIME_UNIT_refresh_time_unit_DEFAULT 0x0001e847

/***************************************************************************
 *SWITCH_REVISION - SWITCH Revision Control Register
 ***************************************************************************/
/* SWITCH_REG :: SWITCH_REVISION :: SF2_rev [31:16] */
#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_MASK               0xffff0000
#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_SHIFT              16
#define BCHP_SWITCH_REG_SWITCH_REVISION_SF2_rev_DEFAULT            0x00000000

/* SWITCH_REG :: SWITCH_REVISION :: switch_top_rev [15:00] */
#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_MASK        0x0000ffff
#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_SHIFT       0
#define BCHP_SWITCH_REG_SWITCH_REVISION_switch_top_rev_DEFAULT     0x00000000

/***************************************************************************
 *PHY_REVISION - PHY Revision Control Register
 ***************************************************************************/
/* SWITCH_REG :: PHY_REVISION :: quad_phy_rev [31:16] */
#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_MASK             0xffff0000
#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_SHIFT            16
#define BCHP_SWITCH_REG_PHY_REVISION_quad_phy_rev_DEFAULT          0x00000000

/* SWITCH_REG :: PHY_REVISION :: single_phy_rev [15:00] */
#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_MASK           0x0000ffff
#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_SHIFT          0
#define BCHP_SWITCH_REG_PHY_REVISION_single_phy_rev_DEFAULT        0x00000000

/***************************************************************************
 *PHY_TEST_CNTRL - PHY Test Control Register
 ***************************************************************************/
/* SWITCH_REG :: PHY_TEST_CNTRL :: reserved0 [31:06] */
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_reserved0_MASK              0xffffffc0
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_reserved0_SHIFT             6

/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_sel [05:03] */
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_MASK                0x00000038
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_SHIFT               3
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_sel_DEFAULT             0x00000000

/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_test_mode [02:01] */
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_MASK          0x00000006
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_SHIFT         1
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_mode_DEFAULT       0x00000000

/* SWITCH_REG :: PHY_TEST_CNTRL :: phy_test_en [00:00] */
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_MASK            0x00000001
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_SHIFT           0
#define BCHP_SWITCH_REG_PHY_TEST_CNTRL_phy_test_en_DEFAULT         0x00000000

/***************************************************************************
 *QPHY_CNTRL - Quad GPHY Control Register
 ***************************************************************************/
/* SWITCH_REG :: QPHY_CNTRL :: reserved0 [31:17] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved0_MASK                  0xfffe0000
#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved0_SHIFT                 17

/* SWITCH_REG :: QPHY_CNTRL :: phy_phyad [16:12] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_MASK                  0x0001f000
#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_SHIFT                 12
#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_phyad_DEFAULT               0x00000001

/* SWITCH_REG :: QPHY_CNTRL :: reserved1 [11:09] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved1_MASK                  0x00000e00
#define BCHP_SWITCH_REG_QPHY_CNTRL_reserved1_SHIFT                 9

/* SWITCH_REG :: QPHY_CNTRL :: phy_reset [08:08] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_MASK                  0x00000100
#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_SHIFT                 8
#define BCHP_SWITCH_REG_QPHY_CNTRL_phy_reset_DEFAULT               0x00000000

/* SWITCH_REG :: QPHY_CNTRL :: ck25_dis [07:07] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_MASK                   0x00000080
#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_SHIFT                  7
#define BCHP_SWITCH_REG_QPHY_CNTRL_ck25_dis_DEFAULT                0x00000000

/* SWITCH_REG :: QPHY_CNTRL :: iddq_global_pwr [06:06] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_MASK            0x00000040
#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_SHIFT           6
#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_global_pwr_DEFAULT         0x00000000

/* SWITCH_REG :: QPHY_CNTRL :: force_dll_en [05:05] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_MASK               0x00000020
#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_SHIFT              5
#define BCHP_SWITCH_REG_QPHY_CNTRL_force_dll_en_DEFAULT            0x00000000

/* SWITCH_REG :: QPHY_CNTRL :: ext_pwr_down [04:01] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_MASK               0x0000001e
#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_SHIFT              1
#define BCHP_SWITCH_REG_QPHY_CNTRL_ext_pwr_down_DEFAULT            0x0000000f

/* SWITCH_REG :: QPHY_CNTRL :: iddq_bias [00:00] */
#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_MASK                  0x00000001
#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_SHIFT                 0
#define BCHP_SWITCH_REG_QPHY_CNTRL_iddq_bias_DEFAULT               0x00000001

/***************************************************************************
 *QPHY_STATUS - Quad GPHY Status Register
 ***************************************************************************/
/* SWITCH_REG :: QPHY_STATUS :: reserved0 [31:09] */
#define BCHP_SWITCH_REG_QPHY_STATUS_reserved0_MASK                 0xfffffe00
#define BCHP_SWITCH_REG_QPHY_STATUS_reserved0_SHIFT                9

/* SWITCH_REG :: QPHY_STATUS :: pll_lock [08:08] */
#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_MASK                  0x00000100
#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_SHIFT                 8
#define BCHP_SWITCH_REG_QPHY_STATUS_pll_lock_DEFAULT               0x00000000

/* SWITCH_REG :: QPHY_STATUS :: energy_det_apd [07:04] */
#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_MASK            0x000000f0
#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_SHIFT           4
#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_apd_DEFAULT         0x00000000

/* SWITCH_REG :: QPHY_STATUS :: energy_det_masked [03:00] */
#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_MASK         0x0000000f
#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_SHIFT        0
#define BCHP_SWITCH_REG_QPHY_STATUS_energy_det_masked_DEFAULT      0x00000000

/***************************************************************************
 *LED_BLINK_RATE_CNTRL - LED port Blink Rate Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_BLINK_RATE_CNTRL :: led_on_time [31:16] */
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_MASK      0xffff0000
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_SHIFT     16
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_on_time_DEFAULT   0x00000320

/* SWITCH_REG :: LED_BLINK_RATE_CNTRL :: led_off_time [15:00] */
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_MASK     0x0000ffff
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_SHIFT    0
#define BCHP_SWITCH_REG_LED_BLINK_RATE_CNTRL_led_off_time_DEFAULT  0x00000320

/***************************************************************************
 *LED_SERIAL_CNTRL - LED Serial Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_SERIAL_CNTRL :: reserved0 [31:16] */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_reserved0_MASK            0xffff0000
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_reserved0_SHIFT           16

/* SWITCH_REG :: LED_SERIAL_CNTRL :: port_en [15:08] */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_MASK              0x0000ff00
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_SHIFT             8
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_port_en_DEFAULT           0x00000000

/* SWITCH_REG :: LED_SERIAL_CNTRL :: smode [07:07] */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_MASK                0x00000080
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_SHIFT               7
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_smode_DEFAULT             0x00000000

/* SWITCH_REG :: LED_SERIAL_CNTRL :: sled_clk_frequency [06:06] */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_MASK   0x00000040
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_SHIFT  6
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_frequency_DEFAULT 0x00000000

/* SWITCH_REG :: LED_SERIAL_CNTRL :: sled_clk_pol [05:05] */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_MASK         0x00000020
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_SHIFT        5
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_sled_clk_pol_DEFAULT      0x00000000

/* SWITCH_REG :: LED_SERIAL_CNTRL :: refresh_period [04:00] */
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_MASK       0x0000001f
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_SHIFT      0
#define BCHP_SWITCH_REG_LED_SERIAL_CNTRL_refresh_period_DEFAULT    0x00000004

/***************************************************************************
 *LED_0_CNTRL - LED port 0 Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_0_CNTRL :: reserved0 [31:28] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_reserved0_MASK                 0xf0000000
#define BCHP_SWITCH_REG_LED_0_CNTRL_reserved0_SHIFT                28

/* SWITCH_REG :: LED_0_CNTRL :: act_led_pol_sel [27:27] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_MASK           0x08000000
#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_SHIFT          27
#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_pol_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_src_sel [24:24] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_MASK            0x01000000
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_SHIFT           24
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: act_led_act_sel [23:22] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_MASK           0x00c00000
#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_SHIFT          22
#define BCHP_SWITCH_REG_LED_0_CNTRL_act_led_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led1_act_sel [21:20] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_SHIFT      20
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: spdlnk_led0_act_sel [19:18] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_SHIFT      18
#define BCHP_SWITCH_REG_LED_0_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: tx_en_en [17:17] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_MASK                  0x00020000
#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_SHIFT                 17
#define BCHP_SWITCH_REG_LED_0_CNTRL_tx_en_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_0_CNTRL :: rx_dv_en [16:16] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_MASK                  0x00010000
#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_SHIFT                 16
#define BCHP_SWITCH_REG_LED_0_CNTRL_rx_dv_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_0_CNTRL :: sel_1000m_encode [15:14] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_MASK          0x0000c000
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_SHIFT         14
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_1000m_encode_DEFAULT       0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: sel_100m_encode [13:12] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_MASK           0x00003000
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_SHIFT          12
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_100m_encode_DEFAULT        0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: sel_10m_encode [11:10] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_MASK            0x00000c00
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_SHIFT           10
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_10m_encode_DEFAULT         0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: sel_no_link_encode [09:08] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_MASK        0x00000300
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_SHIFT       8
#define BCHP_SWITCH_REG_LED_0_CNTRL_sel_no_link_encode_DEFAULT     0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: 1000m_encode [07:06] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_MASK              0x000000c0
#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_SHIFT             6
#define BCHP_SWITCH_REG_LED_0_CNTRL_1000m_encode_DEFAULT           0x00000000

/* SWITCH_REG :: LED_0_CNTRL :: 100m_encode [05:04] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_MASK               0x00000030
#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_SHIFT              4
#define BCHP_SWITCH_REG_LED_0_CNTRL_100m_encode_DEFAULT            0x00000001

/* SWITCH_REG :: LED_0_CNTRL :: 10m_encode [03:02] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_MASK                0x0000000c
#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_SHIFT               2
#define BCHP_SWITCH_REG_LED_0_CNTRL_10m_encode_DEFAULT             0x00000002

/* SWITCH_REG :: LED_0_CNTRL :: no_link_encode [01:00] */
#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_MASK            0x00000003
#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_SHIFT           0
#define BCHP_SWITCH_REG_LED_0_CNTRL_no_link_encode_DEFAULT         0x00000003

/***************************************************************************
 *LED_1_CNTRL - LED port 1 Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_1_CNTRL :: reserved0 [31:28] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_reserved0_MASK                 0xf0000000
#define BCHP_SWITCH_REG_LED_1_CNTRL_reserved0_SHIFT                28

/* SWITCH_REG :: LED_1_CNTRL :: act_led_pol_sel [27:27] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_MASK           0x08000000
#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_SHIFT          27
#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_pol_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_src_sel [24:24] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_MASK            0x01000000
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_SHIFT           24
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: act_led_act_sel [23:22] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_MASK           0x00c00000
#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_SHIFT          22
#define BCHP_SWITCH_REG_LED_1_CNTRL_act_led_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led1_act_sel [21:20] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_SHIFT      20
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: spdlnk_led0_act_sel [19:18] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_SHIFT      18
#define BCHP_SWITCH_REG_LED_1_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: tx_en_en [17:17] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_MASK                  0x00020000
#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_SHIFT                 17
#define BCHP_SWITCH_REG_LED_1_CNTRL_tx_en_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_1_CNTRL :: rx_dv_en [16:16] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_MASK                  0x00010000
#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_SHIFT                 16
#define BCHP_SWITCH_REG_LED_1_CNTRL_rx_dv_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_1_CNTRL :: sel_1000m_encode [15:14] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_MASK          0x0000c000
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_SHIFT         14
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_1000m_encode_DEFAULT       0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: sel_100m_encode [13:12] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_MASK           0x00003000
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_SHIFT          12
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_100m_encode_DEFAULT        0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: sel_10m_encode [11:10] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_MASK            0x00000c00
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_SHIFT           10
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_10m_encode_DEFAULT         0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: sel_no_link_encode [09:08] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_MASK        0x00000300
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_SHIFT       8
#define BCHP_SWITCH_REG_LED_1_CNTRL_sel_no_link_encode_DEFAULT     0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: 1000m_encode [07:06] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_MASK              0x000000c0
#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_SHIFT             6
#define BCHP_SWITCH_REG_LED_1_CNTRL_1000m_encode_DEFAULT           0x00000000

/* SWITCH_REG :: LED_1_CNTRL :: 100m_encode [05:04] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_MASK               0x00000030
#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_SHIFT              4
#define BCHP_SWITCH_REG_LED_1_CNTRL_100m_encode_DEFAULT            0x00000001

/* SWITCH_REG :: LED_1_CNTRL :: 10m_encode [03:02] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_MASK                0x0000000c
#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_SHIFT               2
#define BCHP_SWITCH_REG_LED_1_CNTRL_10m_encode_DEFAULT             0x00000002

/* SWITCH_REG :: LED_1_CNTRL :: no_link_encode [01:00] */
#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_MASK            0x00000003
#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_SHIFT           0
#define BCHP_SWITCH_REG_LED_1_CNTRL_no_link_encode_DEFAULT         0x00000003

/***************************************************************************
 *LED_2_CNTRL - LED port 2 Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_2_CNTRL :: reserved0 [31:28] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_reserved0_MASK                 0xf0000000
#define BCHP_SWITCH_REG_LED_2_CNTRL_reserved0_SHIFT                28

/* SWITCH_REG :: LED_2_CNTRL :: act_led_pol_sel [27:27] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_MASK           0x08000000
#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_SHIFT          27
#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_pol_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_src_sel [24:24] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_MASK            0x01000000
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_SHIFT           24
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: act_led_act_sel [23:22] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_MASK           0x00c00000
#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_SHIFT          22
#define BCHP_SWITCH_REG_LED_2_CNTRL_act_led_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led1_act_sel [21:20] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_SHIFT      20
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: spdlnk_led0_act_sel [19:18] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_SHIFT      18
#define BCHP_SWITCH_REG_LED_2_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: tx_en_en [17:17] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_MASK                  0x00020000
#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_SHIFT                 17
#define BCHP_SWITCH_REG_LED_2_CNTRL_tx_en_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_2_CNTRL :: rx_dv_en [16:16] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_MASK                  0x00010000
#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_SHIFT                 16
#define BCHP_SWITCH_REG_LED_2_CNTRL_rx_dv_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_2_CNTRL :: sel_1000m_encode [15:14] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_MASK          0x0000c000
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_SHIFT         14
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_1000m_encode_DEFAULT       0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: sel_100m_encode [13:12] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_MASK           0x00003000
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_SHIFT          12
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_100m_encode_DEFAULT        0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: sel_10m_encode [11:10] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_MASK            0x00000c00
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_SHIFT           10
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_10m_encode_DEFAULT         0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: sel_no_link_encode [09:08] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_MASK        0x00000300
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_SHIFT       8
#define BCHP_SWITCH_REG_LED_2_CNTRL_sel_no_link_encode_DEFAULT     0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: 1000m_encode [07:06] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_MASK              0x000000c0
#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_SHIFT             6
#define BCHP_SWITCH_REG_LED_2_CNTRL_1000m_encode_DEFAULT           0x00000000

/* SWITCH_REG :: LED_2_CNTRL :: 100m_encode [05:04] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_MASK               0x00000030
#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_SHIFT              4
#define BCHP_SWITCH_REG_LED_2_CNTRL_100m_encode_DEFAULT            0x00000001

/* SWITCH_REG :: LED_2_CNTRL :: 10m_encode [03:02] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_MASK                0x0000000c
#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_SHIFT               2
#define BCHP_SWITCH_REG_LED_2_CNTRL_10m_encode_DEFAULT             0x00000002

/* SWITCH_REG :: LED_2_CNTRL :: no_link_encode [01:00] */
#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_MASK            0x00000003
#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_SHIFT           0
#define BCHP_SWITCH_REG_LED_2_CNTRL_no_link_encode_DEFAULT         0x00000003

/***************************************************************************
 *LED_3_CNTRL - LED port 3 Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_3_CNTRL :: reserved0 [31:28] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_reserved0_MASK                 0xf0000000
#define BCHP_SWITCH_REG_LED_3_CNTRL_reserved0_SHIFT                28

/* SWITCH_REG :: LED_3_CNTRL :: act_led_pol_sel [27:27] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_MASK           0x08000000
#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_SHIFT          27
#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_pol_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_src_sel [24:24] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_MASK            0x01000000
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_SHIFT           24
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: act_led_act_sel [23:22] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_MASK           0x00c00000
#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_SHIFT          22
#define BCHP_SWITCH_REG_LED_3_CNTRL_act_led_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led1_act_sel [21:20] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_SHIFT      20
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: spdlnk_led0_act_sel [19:18] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_SHIFT      18
#define BCHP_SWITCH_REG_LED_3_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: tx_en_en [17:17] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_MASK                  0x00020000
#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_SHIFT                 17
#define BCHP_SWITCH_REG_LED_3_CNTRL_tx_en_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_3_CNTRL :: rx_dv_en [16:16] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_MASK                  0x00010000
#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_SHIFT                 16
#define BCHP_SWITCH_REG_LED_3_CNTRL_rx_dv_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_3_CNTRL :: sel_1000m_encode [15:14] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_MASK          0x0000c000
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_SHIFT         14
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_1000m_encode_DEFAULT       0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: sel_100m_encode [13:12] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_MASK           0x00003000
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_SHIFT          12
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_100m_encode_DEFAULT        0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: sel_10m_encode [11:10] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_MASK            0x00000c00
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_SHIFT           10
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_10m_encode_DEFAULT         0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: sel_no_link_encode [09:08] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_MASK        0x00000300
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_SHIFT       8
#define BCHP_SWITCH_REG_LED_3_CNTRL_sel_no_link_encode_DEFAULT     0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: 1000m_encode [07:06] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_MASK              0x000000c0
#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_SHIFT             6
#define BCHP_SWITCH_REG_LED_3_CNTRL_1000m_encode_DEFAULT           0x00000000

/* SWITCH_REG :: LED_3_CNTRL :: 100m_encode [05:04] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_MASK               0x00000030
#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_SHIFT              4
#define BCHP_SWITCH_REG_LED_3_CNTRL_100m_encode_DEFAULT            0x00000001

/* SWITCH_REG :: LED_3_CNTRL :: 10m_encode [03:02] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_MASK                0x0000000c
#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_SHIFT               2
#define BCHP_SWITCH_REG_LED_3_CNTRL_10m_encode_DEFAULT             0x00000002

/* SWITCH_REG :: LED_3_CNTRL :: no_link_encode [01:00] */
#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_MASK            0x00000003
#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_SHIFT           0
#define BCHP_SWITCH_REG_LED_3_CNTRL_no_link_encode_DEFAULT         0x00000003

/***************************************************************************
 *LED_7_CNTRL - LED port 7 Control Register
 ***************************************************************************/
/* SWITCH_REG :: LED_7_CNTRL :: reserved0 [31:28] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_reserved0_MASK                 0xf0000000
#define BCHP_SWITCH_REG_LED_7_CNTRL_reserved0_SHIFT                28

/* SWITCH_REG :: LED_7_CNTRL :: act_led_pol_sel [27:27] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_MASK           0x08000000
#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_SHIFT          27
#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_pol_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led1_act_pol_sel [26:26] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_MASK   0x04000000
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_SHIFT  26
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led0_act_pol_sel [25:25] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_MASK   0x02000000
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_SHIFT  25
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_pol_sel_DEFAULT 0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_src_sel [24:24] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_MASK            0x01000000
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_SHIFT           24
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_src_sel_DEFAULT         0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: act_led_act_sel [23:22] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_MASK           0x00c00000
#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_SHIFT          22
#define BCHP_SWITCH_REG_LED_7_CNTRL_act_led_act_sel_DEFAULT        0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led1_act_sel [21:20] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_MASK       0x00300000
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_SHIFT      20
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led1_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: spdlnk_led0_act_sel [19:18] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_MASK       0x000c0000
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_SHIFT      18
#define BCHP_SWITCH_REG_LED_7_CNTRL_spdlnk_led0_act_sel_DEFAULT    0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: tx_en_en [17:17] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_MASK                  0x00020000
#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_SHIFT                 17
#define BCHP_SWITCH_REG_LED_7_CNTRL_tx_en_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_7_CNTRL :: rx_dv_en [16:16] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_MASK                  0x00010000
#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_SHIFT                 16
#define BCHP_SWITCH_REG_LED_7_CNTRL_rx_dv_en_DEFAULT               0x00000001

/* SWITCH_REG :: LED_7_CNTRL :: sel_1000m_encode [15:14] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_MASK          0x0000c000
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_SHIFT         14
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_1000m_encode_DEFAULT       0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: sel_100m_encode [13:12] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_MASK           0x00003000
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_SHIFT          12
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_100m_encode_DEFAULT        0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: sel_10m_encode [11:10] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_MASK            0x00000c00
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_SHIFT           10
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_10m_encode_DEFAULT         0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: sel_no_link_encode [09:08] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_MASK        0x00000300
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_SHIFT       8
#define BCHP_SWITCH_REG_LED_7_CNTRL_sel_no_link_encode_DEFAULT     0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: 1000m_encode [07:06] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_MASK              0x000000c0
#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_SHIFT             6
#define BCHP_SWITCH_REG_LED_7_CNTRL_1000m_encode_DEFAULT           0x00000000

/* SWITCH_REG :: LED_7_CNTRL :: 100m_encode [05:04] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_MASK               0x00000030
#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_SHIFT              4
#define BCHP_SWITCH_REG_LED_7_CNTRL_100m_encode_DEFAULT            0x00000001

/* SWITCH_REG :: LED_7_CNTRL :: 10m_encode [03:02] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_MASK                0x0000000c
#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_SHIFT               2
#define BCHP_SWITCH_REG_LED_7_CNTRL_10m_encode_DEFAULT             0x00000002

/* SWITCH_REG :: LED_7_CNTRL :: no_link_encode [01:00] */
#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_MASK            0x00000003
#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_SHIFT           0
#define BCHP_SWITCH_REG_LED_7_CNTRL_no_link_encode_DEFAULT         0x00000003

/***************************************************************************
 *RGMII_9_CNTRL - RGMII port 9 Control Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_9_CNTRL :: reserved0 [31:08] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_reserved0_MASK               0xffffff00
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_reserved0_SHIFT              8

/* SWITCH_REG :: RGMII_9_CNTRL :: tx_pause_en [07:07] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_MASK             0x00000080
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_SHIFT            7
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_tx_pause_en_DEFAULT          0x00000000

/* SWITCH_REG :: RGMII_9_CNTRL :: rx_pause_en [06:06] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_MASK             0x00000040
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_SHIFT            6
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rx_pause_en_DEFAULT          0x00000000

/* SWITCH_REG :: RGMII_9_CNTRL :: rvmii_ref_sel [05:05] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_MASK           0x00000020
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_SHIFT          5
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rvmii_ref_sel_DEFAULT        0x00000000

/* SWITCH_REG :: RGMII_9_CNTRL :: port_mode [04:02] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_MASK               0x0000001c
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_SHIFT              2
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_port_mode_DEFAULT            0x00000003

/* SWITCH_REG :: RGMII_9_CNTRL :: id_mode_dis [01:01] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_MASK             0x00000002
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_SHIFT            1
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_id_mode_dis_DEFAULT          0x00000000

/* SWITCH_REG :: RGMII_9_CNTRL :: rgmii_mode_en [00:00] */
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_MASK           0x00000001
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_SHIFT          0
#define BCHP_SWITCH_REG_RGMII_9_CNTRL_rgmii_mode_en_DEFAULT        0x00000000

/***************************************************************************
 *RGMII_9_IB_STATUS - RGMII port 9 InBand Status Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_9_IB_STATUS :: reserved0 [31:04] */
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_reserved0_MASK           0xfffffff0
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_reserved0_SHIFT          4

/* SWITCH_REG :: RGMII_9_IB_STATUS :: link_decode [03:03] */
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_MASK         0x00000008
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_SHIFT        3
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_link_decode_DEFAULT      0x00000000

/* SWITCH_REG :: RGMII_9_IB_STATUS :: duplex_decode [02:02] */
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_MASK       0x00000004
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_SHIFT      2
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_duplex_decode_DEFAULT    0x00000000

/* SWITCH_REG :: RGMII_9_IB_STATUS :: speed_decode [01:00] */
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_MASK        0x00000003
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_SHIFT       0
#define BCHP_SWITCH_REG_RGMII_9_IB_STATUS_speed_decode_DEFAULT     0x00000000

/***************************************************************************
 *RGMII_9_RX_CLOCK_DELAY_CNTRL - RGMII port 9 RX Clock Delay Control Register
 ***************************************************************************/
/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: reserved0 [31:08] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_reserved0_MASK 0xffffff00
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_reserved0_SHIFT 8

/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: dly_override [07:07] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_MASK 0x00000080
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_SHIFT 7
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_override_DEFAULT 0x00000001

/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: dly_sel [06:06] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_MASK  0x00000040
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_SHIFT 6
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_dly_sel_DEFAULT 0x00000001

/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: bypass [05:05] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_MASK   0x00000020
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_SHIFT  5
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_bypass_DEFAULT 0x00000001

/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: iddq [04:04] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_MASK     0x00000010
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_SHIFT    4
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_iddq_DEFAULT  0x00000000

/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: drng [03:02] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_MASK     0x0000000c
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_SHIFT    2
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_drng_DEFAULT  0x00000000

/* SWITCH_REG :: RGMII_9_RX_CLOCK_DELAY_CNTRL :: ctri [01:00] */
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_MASK     0x00000003
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_SHIFT    0
#define BCHP_SWITCH_REG_RGMII_9_RX_CLOCK_DELAY_CNTRL_ctri_DEFAULT  0x00000000

#endif /* #ifndef BCHP_SWITCH_REG_H__ */

/* End of File */