/***************************************************************************
 *     Copyright (c) 1999-2013, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Wed May  8 03:09:20 2013
 *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_SWITCH_INDIR_RW_H__
#define BCHP_SWITCH_INDIR_RW_H__

/***************************************************************************
 *SWITCH_INDIR_RW
 ***************************************************************************/
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0    0x04e40300 /* Indirect Address Register 0 */
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_0 0x04e40304 /* Indirect Data Low Register 0 */
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_0 0x04e40308 /* Indirect Data High Register 0 */
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1    0x04e4030c /* Indirect Address Register 1 */
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_1 0x04e40310 /* Indirect Data Low Register 1 */
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_1 0x04e40314 /* Indirect Data High Register 1 */

/***************************************************************************
 *INDIR_ADDR_REG_0 - Indirect Address Register 0
 ***************************************************************************/
/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: reserved0 [31:18] */
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reserved0_MASK       0xfffc0000
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reserved0_SHIFT      18

/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: start_busy [17:17] */
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_start_busy_MASK      0x00020000
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_start_busy_SHIFT     17
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_start_busy_DEFAULT   0x00000000

/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: r_w [16:16] */
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_r_w_MASK             0x00010000
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_r_w_SHIFT            16
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_r_w_DEFAULT          0x00000000

/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: reg_page [15:08] */
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_page_MASK        0x0000ff00
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_page_SHIFT       8
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_page_DEFAULT     0x00000000

/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_0 :: reg_offset [07:00] */
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_offset_MASK      0x000000ff
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_offset_SHIFT     0
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_0_reg_offset_DEFAULT   0x00000000

/***************************************************************************
 *INDIR_DATA_LOW_REG_0 - Indirect Data Low Register 0
 ***************************************************************************/
/* SWITCH_INDIR_RW :: INDIR_DATA_LOW_REG_0 :: data_low [31:00] */
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_0_data_low_MASK    0xffffffff
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_0_data_low_SHIFT   0
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_0_data_low_DEFAULT 0x00000000

/***************************************************************************
 *INDIR_DATA_HIGH_REG_0 - Indirect Data High Register 0
 ***************************************************************************/
/* SWITCH_INDIR_RW :: INDIR_DATA_HIGH_REG_0 :: data_high [31:00] */
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_0_data_high_MASK  0xffffffff
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_0_data_high_SHIFT 0
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_0_data_high_DEFAULT 0x00000000

/***************************************************************************
 *INDIR_ADDR_REG_1 - Indirect Address Register 1
 ***************************************************************************/
/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: reserved0 [31:18] */
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reserved0_MASK       0xfffc0000
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reserved0_SHIFT      18

/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: start_busy [17:17] */
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_start_busy_MASK      0x00020000
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_start_busy_SHIFT     17
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_start_busy_DEFAULT   0x00000000

/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: r_w [16:16] */
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_r_w_MASK             0x00010000
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_r_w_SHIFT            16
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_r_w_DEFAULT          0x00000000

/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: reg_page [15:08] */
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_page_MASK        0x0000ff00
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_page_SHIFT       8
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_page_DEFAULT     0x00000000

/* SWITCH_INDIR_RW :: INDIR_ADDR_REG_1 :: reg_offset [07:00] */
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_offset_MASK      0x000000ff
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_offset_SHIFT     0
#define BCHP_SWITCH_INDIR_RW_INDIR_ADDR_REG_1_reg_offset_DEFAULT   0x00000000

/***************************************************************************
 *INDIR_DATA_LOW_REG_1 - Indirect Data Low Register 1
 ***************************************************************************/
/* SWITCH_INDIR_RW :: INDIR_DATA_LOW_REG_1 :: data_low [31:00] */
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_1_data_low_MASK    0xffffffff
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_1_data_low_SHIFT   0
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_LOW_REG_1_data_low_DEFAULT 0x00000000

/***************************************************************************
 *INDIR_DATA_HIGH_REG_1 - Indirect Data High Register 1
 ***************************************************************************/
/* SWITCH_INDIR_RW :: INDIR_DATA_HIGH_REG_1 :: data_high [31:00] */
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_1_data_high_MASK  0xffffffff
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_1_data_high_SHIFT 0
#define BCHP_SWITCH_INDIR_RW_INDIR_DATA_HIGH_REG_1_data_high_DEFAULT 0x00000000

#endif /* #ifndef BCHP_SWITCH_INDIR_RW_H__ */

/* End of File */