| /**************************************************************************** |
| * Driver for Solarflare network controllers and boards |
| * Copyright 2009-2013 Solarflare Communications Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License version 2 as published |
| * by the Free Software Foundation, incorporated herein by reference. |
| */ |
| |
| |
| #ifndef MCDI_PCOL_H |
| #define MCDI_PCOL_H |
| |
| /* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ |
| /* Power-on reset state */ |
| #define MC_FW_STATE_POR (1) |
| /* If this is set in MC_RESET_STATE_REG then it should be |
| * possible to jump into IMEM without loading code from flash. */ |
| #define MC_FW_WARM_BOOT_OK (2) |
| /* The MC main image has started to boot. */ |
| #define MC_FW_STATE_BOOTING (4) |
| /* The Scheduler has started. */ |
| #define MC_FW_STATE_SCHED (8) |
| /* If this is set in MC_RESET_STATE_REG then it should be |
| * possible to jump into IMEM without loading code from flash. |
| * Unlike a warm boot, assume DMEM has been reloaded, so that |
| * the MC persistent data must be reinitialised. */ |
| #define MC_FW_TEPID_BOOT_OK (16) |
| /* BIST state has been initialized */ |
| #define MC_FW_BIST_INIT_OK (128) |
| |
| /* Siena MC shared memmory offsets */ |
| /* The 'doorbell' addresses are hard-wired to alert the MC when written */ |
| #define MC_SMEM_P0_DOORBELL_OFST 0x000 |
| #define MC_SMEM_P1_DOORBELL_OFST 0x004 |
| /* The rest of these are firmware-defined */ |
| #define MC_SMEM_P0_PDU_OFST 0x008 |
| #define MC_SMEM_P1_PDU_OFST 0x108 |
| #define MC_SMEM_PDU_LEN 0x100 |
| #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0 |
| #define MC_SMEM_P0_STATUS_OFST 0x7f8 |
| #define MC_SMEM_P1_STATUS_OFST 0x7fc |
| |
| /* Values to be written to the per-port status dword in shared |
| * memory on reboot and assert */ |
| #define MC_STATUS_DWORD_REBOOT (0xb007b007) |
| #define MC_STATUS_DWORD_ASSERT (0xdeaddead) |
| |
| /* Check whether an mcfw version (in host order) belongs to a bootloader */ |
| #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007) |
| |
| /* The current version of the MCDI protocol. |
| * |
| * Note that the ROM burnt into the card only talks V0, so at the very |
| * least every driver must support version 0 and MCDI_PCOL_VERSION |
| */ |
| #define MCDI_PCOL_VERSION 2 |
| |
| /* Unused commands: 0x23, 0x27, 0x30, 0x31 */ |
| |
| /* MCDI version 1 |
| * |
| * Each MCDI request starts with an MCDI_HEADER, which is a 32bit |
| * structure, filled in by the client. |
| * |
| * 0 7 8 16 20 22 23 24 31 |
| * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | |
| * | | | |
| * | | \--- Response |
| * | \------- Error |
| * \------------------------------ Resync (always set) |
| * |
| * The client writes it's request into MC shared memory, and rings the |
| * doorbell. Each request is completed by either by the MC writting |
| * back into shared memory, or by writting out an event. |
| * |
| * All MCDI commands support completion by shared memory response. Each |
| * request may also contain additional data (accounted for by HEADER.LEN), |
| * and some response's may also contain additional data (again, accounted |
| * for by HEADER.LEN). |
| * |
| * Some MCDI commands support completion by event, in which any associated |
| * response data is included in the event. |
| * |
| * The protocol requires one response to be delivered for every request, a |
| * request should not be sent unless the response for the previous request |
| * has been received (either by polling shared memory, or by receiving |
| * an event). |
| */ |
| |
| /** Request/Response structure */ |
| #define MCDI_HEADER_OFST 0 |
| #define MCDI_HEADER_CODE_LBN 0 |
| #define MCDI_HEADER_CODE_WIDTH 7 |
| #define MCDI_HEADER_RESYNC_LBN 7 |
| #define MCDI_HEADER_RESYNC_WIDTH 1 |
| #define MCDI_HEADER_DATALEN_LBN 8 |
| #define MCDI_HEADER_DATALEN_WIDTH 8 |
| #define MCDI_HEADER_SEQ_LBN 16 |
| #define MCDI_HEADER_SEQ_WIDTH 4 |
| #define MCDI_HEADER_RSVD_LBN 20 |
| #define MCDI_HEADER_RSVD_WIDTH 1 |
| #define MCDI_HEADER_NOT_EPOCH_LBN 21 |
| #define MCDI_HEADER_NOT_EPOCH_WIDTH 1 |
| #define MCDI_HEADER_ERROR_LBN 22 |
| #define MCDI_HEADER_ERROR_WIDTH 1 |
| #define MCDI_HEADER_RESPONSE_LBN 23 |
| #define MCDI_HEADER_RESPONSE_WIDTH 1 |
| #define MCDI_HEADER_XFLAGS_LBN 24 |
| #define MCDI_HEADER_XFLAGS_WIDTH 8 |
| /* Request response using event */ |
| #define MCDI_HEADER_XFLAGS_EVREQ 0x01 |
| |
| /* Maximum number of payload bytes */ |
| #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc |
| #define MCDI_CTL_SDU_LEN_MAX_V2 0x400 |
| |
| #define MCDI_CTL_SDU_LEN_MAX MCDI_CTL_SDU_LEN_MAX_V2 |
| |
| |
| /* The MC can generate events for two reasons: |
| * - To complete a shared memory request if XFLAGS_EVREQ was set |
| * - As a notification (link state, i2c event), controlled |
| * via MC_CMD_LOG_CTRL |
| * |
| * Both events share a common structure: |
| * |
| * 0 32 33 36 44 52 60 |
| * | Data | Cont | Level | Src | Code | Rsvd | |
| * | |
| * \ There is another event pending in this notification |
| * |
| * If Code==CMDDONE, then the fields are further interpreted as: |
| * |
| * - LEVEL==INFO Command succeeded |
| * - LEVEL==ERR Command failed |
| * |
| * 0 8 16 24 32 |
| * | Seq | Datalen | Errno | Rsvd | |
| * |
| * These fields are taken directly out of the standard MCDI header, i.e., |
| * LEVEL==ERR, Datalen == 0 => Reboot |
| * |
| * Events can be squirted out of the UART (using LOG_CTRL) without a |
| * MCDI header. An event can be distinguished from a MCDI response by |
| * examining the first byte which is 0xc0. This corresponds to the |
| * non-existent MCDI command MC_CMD_DEBUG_LOG. |
| * |
| * 0 7 8 |
| * | command | Resync | = 0xc0 |
| * |
| * Since the event is written in big-endian byte order, this works |
| * providing bits 56-63 of the event are 0xc0. |
| * |
| * 56 60 63 |
| * | Rsvd | Code | = 0xc0 |
| * |
| * Which means for convenience the event code is 0xc for all MC |
| * generated events. |
| */ |
| #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc |
| |
| |
| /* Operation not permitted. */ |
| #define MC_CMD_ERR_EPERM 1 |
| /* Non-existent command target */ |
| #define MC_CMD_ERR_ENOENT 2 |
| /* assert() has killed the MC */ |
| #define MC_CMD_ERR_EINTR 4 |
| /* I/O failure */ |
| #define MC_CMD_ERR_EIO 5 |
| /* Try again */ |
| #define MC_CMD_ERR_EAGAIN 11 |
| /* Out of memory */ |
| #define MC_CMD_ERR_ENOMEM 12 |
| /* Caller does not hold required locks */ |
| #define MC_CMD_ERR_EACCES 13 |
| /* Resource is currently unavailable (e.g. lock contention) */ |
| #define MC_CMD_ERR_EBUSY 16 |
| /* No such device */ |
| #define MC_CMD_ERR_ENODEV 19 |
| /* Invalid argument to target */ |
| #define MC_CMD_ERR_EINVAL 22 |
| /* Out of range */ |
| #define MC_CMD_ERR_ERANGE 34 |
| /* Non-recursive resource is already acquired */ |
| #define MC_CMD_ERR_EDEADLK 35 |
| /* Operation not implemented */ |
| #define MC_CMD_ERR_ENOSYS 38 |
| /* Operation timed out */ |
| #define MC_CMD_ERR_ETIME 62 |
| /* Link has been severed */ |
| #define MC_CMD_ERR_ENOLINK 67 |
| /* Protocol error */ |
| #define MC_CMD_ERR_EPROTO 71 |
| /* Operation not supported */ |
| #define MC_CMD_ERR_ENOTSUP 95 |
| /* Address not available */ |
| #define MC_CMD_ERR_EADDRNOTAVAIL 99 |
| /* Not connected */ |
| #define MC_CMD_ERR_ENOTCONN 107 |
| /* Operation already in progress */ |
| #define MC_CMD_ERR_EALREADY 114 |
| |
| /* Resource allocation failed. */ |
| #define MC_CMD_ERR_ALLOC_FAIL 0x1000 |
| /* V-adaptor not found. */ |
| #define MC_CMD_ERR_NO_VADAPTOR 0x1001 |
| /* EVB port not found. */ |
| #define MC_CMD_ERR_NO_EVB_PORT 0x1002 |
| /* V-switch not found. */ |
| #define MC_CMD_ERR_NO_VSWITCH 0x1003 |
| /* Too many VLAN tags. */ |
| #define MC_CMD_ERR_VLAN_LIMIT 0x1004 |
| /* Bad PCI function number. */ |
| #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005 |
| /* Invalid VLAN mode. */ |
| #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006 |
| /* Invalid v-switch type. */ |
| #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007 |
| /* Invalid v-port type. */ |
| #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008 |
| /* MAC address exists. */ |
| #define MC_CMD_ERR_MAC_EXIST 0x1009 |
| /* Slave core not present */ |
| #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a |
| /* The datapath is disabled. */ |
| #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b |
| |
| #define MC_CMD_ERR_CODE_OFST 0 |
| |
| /* We define 8 "escape" commands to allow |
| for command number space extension */ |
| |
| #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78 |
| #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79 |
| #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A |
| #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B |
| #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C |
| #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D |
| #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E |
| #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F |
| |
| /* Vectors in the boot ROM */ |
| /* Point to the copycode entry point. */ |
| #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4) |
| #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4) |
| /* Points to the recovery mode entry point. */ |
| #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4) |
| #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4) |
| |
| /* The command set exported by the boot ROM (MCDI v0) */ |
| #define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ |
| (1 << MC_CMD_READ32) | \ |
| (1 << MC_CMD_WRITE32) | \ |
| (1 << MC_CMD_COPYCODE) | \ |
| (1 << MC_CMD_GET_VERSION), \ |
| 0, 0, 0 } |
| |
| #define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ |
| (MC_CMD_SENSOR_ENTRY_OFST + (_x)) |
| |
| #define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(n) \ |
| (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ |
| MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST + \ |
| (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) |
| |
| #define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(n) \ |
| (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ |
| MC_CMD_DBIWROP_TYPEDEF_BYTE_MASK_OFST + \ |
| (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) |
| |
| #define MC_CMD_DBI_WRITE_IN_VALUE_OFST(n) \ |
| (MC_CMD_DBI_WRITE_IN_DBIWROP_OFST + \ |
| MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST + \ |
| (n) * MC_CMD_DBIWROP_TYPEDEF_LEN) |
| |
| |
| /* Version 2 adds an optional argument to error returns: the errno value |
| * may be followed by the (0-based) number of the first argument that |
| * could not be processed. |
| */ |
| #define MC_CMD_ERR_ARG_OFST 4 |
| |
| /* No space */ |
| #define MC_CMD_ERR_ENOSPC 28 |
| |
| /* MCDI_EVENT structuredef */ |
| #define MCDI_EVENT_LEN 8 |
| #define MCDI_EVENT_CONT_LBN 32 |
| #define MCDI_EVENT_CONT_WIDTH 1 |
| #define MCDI_EVENT_LEVEL_LBN 33 |
| #define MCDI_EVENT_LEVEL_WIDTH 3 |
| /* enum: Info. */ |
| #define MCDI_EVENT_LEVEL_INFO 0x0 |
| /* enum: Warning. */ |
| #define MCDI_EVENT_LEVEL_WARN 0x1 |
| /* enum: Error. */ |
| #define MCDI_EVENT_LEVEL_ERR 0x2 |
| /* enum: Fatal. */ |
| #define MCDI_EVENT_LEVEL_FATAL 0x3 |
| #define MCDI_EVENT_DATA_OFST 0 |
| #define MCDI_EVENT_CMDDONE_SEQ_LBN 0 |
| #define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 |
| #define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 |
| #define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 |
| #define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 |
| #define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 |
| #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 |
| #define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 |
| #define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 |
| #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 |
| /* enum: 100Mbs */ |
| #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1 |
| /* enum: 1Gbs */ |
| #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2 |
| /* enum: 10Gbs */ |
| #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3 |
| /* enum: 40Gbs */ |
| #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4 |
| #define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 |
| #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 |
| #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 |
| #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 |
| #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 |
| #define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 |
| #define MCDI_EVENT_SENSOREVT_STATE_LBN 8 |
| #define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 |
| #define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 |
| #define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 |
| #define MCDI_EVENT_FWALERT_DATA_LBN 8 |
| #define MCDI_EVENT_FWALERT_DATA_WIDTH 24 |
| #define MCDI_EVENT_FWALERT_REASON_LBN 0 |
| #define MCDI_EVENT_FWALERT_REASON_WIDTH 8 |
| /* enum: SRAM Access. */ |
| #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1 |
| #define MCDI_EVENT_FLR_VF_LBN 0 |
| #define MCDI_EVENT_FLR_VF_WIDTH 8 |
| #define MCDI_EVENT_TX_ERR_TXQ_LBN 0 |
| #define MCDI_EVENT_TX_ERR_TXQ_WIDTH 12 |
| #define MCDI_EVENT_TX_ERR_TYPE_LBN 12 |
| #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4 |
| /* enum: Descriptor loader reported failure */ |
| #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1 |
| /* enum: Descriptor ring empty and no EOP seen for packet */ |
| #define MCDI_EVENT_TX_ERR_NO_EOP 0x2 |
| /* enum: Overlength packet */ |
| #define MCDI_EVENT_TX_ERR_2BIG 0x3 |
| /* enum: Malformed option descriptor */ |
| #define MCDI_EVENT_TX_BAD_OPTDESC 0x5 |
| /* enum: Option descriptor part way through a packet */ |
| #define MCDI_EVENT_TX_OPT_IN_PKT 0x8 |
| /* enum: DMA or PIO data access error */ |
| #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9 |
| #define MCDI_EVENT_TX_ERR_INFO_LBN 16 |
| #define MCDI_EVENT_TX_ERR_INFO_WIDTH 16 |
| #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_LBN 12 |
| #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_WIDTH 1 |
| #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0 |
| #define MCDI_EVENT_TX_FLUSH_TXQ_WIDTH 12 |
| #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0 |
| #define MCDI_EVENT_PTP_ERR_TYPE_WIDTH 8 |
| /* enum: PLL lost lock */ |
| #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1 |
| /* enum: Filter overflow (PDMA) */ |
| #define MCDI_EVENT_PTP_ERR_FILTER 0x2 |
| /* enum: FIFO overflow (FPGA) */ |
| #define MCDI_EVENT_PTP_ERR_FIFO 0x3 |
| /* enum: Merge queue overflow */ |
| #define MCDI_EVENT_PTP_ERR_QUEUE 0x4 |
| #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0 |
| #define MCDI_EVENT_AOE_ERR_TYPE_WIDTH 8 |
| /* enum: AOE failed to load - no valid image? */ |
| #define MCDI_EVENT_AOE_NO_LOAD 0x1 |
| /* enum: AOE FC reported an exception */ |
| #define MCDI_EVENT_AOE_FC_ASSERT 0x2 |
| /* enum: AOE FC watchdogged */ |
| #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3 |
| /* enum: AOE FC failed to start */ |
| #define MCDI_EVENT_AOE_FC_NO_START 0x4 |
| /* enum: Generic AOE fault - likely to have been reported via other means too |
| * but intended for use by aoex driver. |
| */ |
| #define MCDI_EVENT_AOE_FAULT 0x5 |
| /* enum: Results of reprogramming the CPLD (status in AOE_ERR_DATA) */ |
| #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6 |
| /* enum: AOE loaded successfully */ |
| #define MCDI_EVENT_AOE_LOAD 0x7 |
| /* enum: AOE DMA operation completed (LSB of HOST_HANDLE in AOE_ERR_DATA) */ |
| #define MCDI_EVENT_AOE_DMA 0x8 |
| /* enum: AOE byteblaster connected/disconnected (Connection status in |
| * AOE_ERR_DATA) |
| */ |
| #define MCDI_EVENT_AOE_BYTEBLASTER 0x9 |
| /* enum: DDR ECC status update */ |
| #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa |
| #define MCDI_EVENT_AOE_ERR_DATA_LBN 8 |
| #define MCDI_EVENT_AOE_ERR_DATA_WIDTH 8 |
| #define MCDI_EVENT_RX_ERR_RXQ_LBN 0 |
| #define MCDI_EVENT_RX_ERR_RXQ_WIDTH 12 |
| #define MCDI_EVENT_RX_ERR_TYPE_LBN 12 |
| #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4 |
| #define MCDI_EVENT_RX_ERR_INFO_LBN 16 |
| #define MCDI_EVENT_RX_ERR_INFO_WIDTH 16 |
| #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_LBN 12 |
| #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_WIDTH 1 |
| #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0 |
| #define MCDI_EVENT_RX_FLUSH_RXQ_WIDTH 12 |
| #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0 |
| #define MCDI_EVENT_MC_REBOOT_COUNT_WIDTH 16 |
| #define MCDI_EVENT_DATA_LBN 0 |
| #define MCDI_EVENT_DATA_WIDTH 32 |
| #define MCDI_EVENT_SRC_LBN 36 |
| #define MCDI_EVENT_SRC_WIDTH 8 |
| #define MCDI_EVENT_EV_CODE_LBN 60 |
| #define MCDI_EVENT_EV_CODE_WIDTH 4 |
| #define MCDI_EVENT_CODE_LBN 44 |
| #define MCDI_EVENT_CODE_WIDTH 8 |
| /* enum: Bad assert. */ |
| #define MCDI_EVENT_CODE_BADSSERT 0x1 |
| /* enum: PM Notice. */ |
| #define MCDI_EVENT_CODE_PMNOTICE 0x2 |
| /* enum: Command done. */ |
| #define MCDI_EVENT_CODE_CMDDONE 0x3 |
| /* enum: Link change. */ |
| #define MCDI_EVENT_CODE_LINKCHANGE 0x4 |
| /* enum: Sensor Event. */ |
| #define MCDI_EVENT_CODE_SENSOREVT 0x5 |
| /* enum: Schedule error. */ |
| #define MCDI_EVENT_CODE_SCHEDERR 0x6 |
| /* enum: Reboot. */ |
| #define MCDI_EVENT_CODE_REBOOT 0x7 |
| /* enum: Mac stats DMA. */ |
| #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8 |
| /* enum: Firmware alert. */ |
| #define MCDI_EVENT_CODE_FWALERT 0x9 |
| /* enum: Function level reset. */ |
| #define MCDI_EVENT_CODE_FLR 0xa |
| /* enum: Transmit error */ |
| #define MCDI_EVENT_CODE_TX_ERR 0xb |
| /* enum: Tx flush has completed */ |
| #define MCDI_EVENT_CODE_TX_FLUSH 0xc |
| /* enum: PTP packet received timestamp */ |
| #define MCDI_EVENT_CODE_PTP_RX 0xd |
| /* enum: PTP NIC failure */ |
| #define MCDI_EVENT_CODE_PTP_FAULT 0xe |
| /* enum: PTP PPS event */ |
| #define MCDI_EVENT_CODE_PTP_PPS 0xf |
| /* enum: Rx flush has completed */ |
| #define MCDI_EVENT_CODE_RX_FLUSH 0x10 |
| /* enum: Receive error */ |
| #define MCDI_EVENT_CODE_RX_ERR 0x11 |
| /* enum: AOE fault */ |
| #define MCDI_EVENT_CODE_AOE 0x12 |
| /* enum: Network port calibration failed (VCAL). */ |
| #define MCDI_EVENT_CODE_VCAL_FAIL 0x13 |
| /* enum: HW PPS event */ |
| #define MCDI_EVENT_CODE_HW_PPS 0x14 |
| /* enum: The MC has rebooted (huntington and later, siena uses CODE_REBOOT and |
| * a different format) |
| */ |
| #define MCDI_EVENT_CODE_MC_REBOOT 0x15 |
| /* enum: the MC has detected a parity error */ |
| #define MCDI_EVENT_CODE_PAR_ERR 0x16 |
| /* enum: the MC has detected a correctable error */ |
| #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17 |
| /* enum: the MC has detected an uncorrectable error */ |
| #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18 |
| /* enum: The MC has entered offline BIST mode */ |
| #define MCDI_EVENT_CODE_MC_BIST 0x19 |
| /* enum: PTP tick event providing current NIC time */ |
| #define MCDI_EVENT_CODE_PTP_TIME 0x1a |
| /* enum: Artificial event generated by host and posted via MC for test |
| * purposes. |
| */ |
| #define MCDI_EVENT_CODE_TESTGEN 0xfa |
| #define MCDI_EVENT_CMDDONE_DATA_OFST 0 |
| #define MCDI_EVENT_CMDDONE_DATA_LBN 0 |
| #define MCDI_EVENT_CMDDONE_DATA_WIDTH 32 |
| #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0 |
| #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0 |
| #define MCDI_EVENT_LINKCHANGE_DATA_WIDTH 32 |
| #define MCDI_EVENT_SENSOREVT_DATA_OFST 0 |
| #define MCDI_EVENT_SENSOREVT_DATA_LBN 0 |
| #define MCDI_EVENT_SENSOREVT_DATA_WIDTH 32 |
| #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0 |
| #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 |
| #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 |
| #define MCDI_EVENT_TX_ERR_DATA_OFST 0 |
| #define MCDI_EVENT_TX_ERR_DATA_LBN 0 |
| #define MCDI_EVENT_TX_ERR_DATA_WIDTH 32 |
| /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the seconds field of |
| * timestamp |
| */ |
| #define MCDI_EVENT_PTP_SECONDS_OFST 0 |
| #define MCDI_EVENT_PTP_SECONDS_LBN 0 |
| #define MCDI_EVENT_PTP_SECONDS_WIDTH 32 |
| /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the major field of |
| * timestamp |
| */ |
| #define MCDI_EVENT_PTP_MAJOR_OFST 0 |
| #define MCDI_EVENT_PTP_MAJOR_LBN 0 |
| #define MCDI_EVENT_PTP_MAJOR_WIDTH 32 |
| /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the nanoseconds field |
| * of timestamp |
| */ |
| #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0 |
| #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0 |
| #define MCDI_EVENT_PTP_NANOSECONDS_WIDTH 32 |
| /* For CODE_PTP_RX, CODE_PTP_PPS and CODE_HW_PPS events the minor field of |
| * timestamp |
| */ |
| #define MCDI_EVENT_PTP_MINOR_OFST 0 |
| #define MCDI_EVENT_PTP_MINOR_LBN 0 |
| #define MCDI_EVENT_PTP_MINOR_WIDTH 32 |
| /* For CODE_PTP_RX events, the lowest four bytes of sourceUUID from PTP packet |
| */ |
| #define MCDI_EVENT_PTP_UUID_OFST 0 |
| #define MCDI_EVENT_PTP_UUID_LBN 0 |
| #define MCDI_EVENT_PTP_UUID_WIDTH 32 |
| #define MCDI_EVENT_RX_ERR_DATA_OFST 0 |
| #define MCDI_EVENT_RX_ERR_DATA_LBN 0 |
| #define MCDI_EVENT_RX_ERR_DATA_WIDTH 32 |
| #define MCDI_EVENT_PAR_ERR_DATA_OFST 0 |
| #define MCDI_EVENT_PAR_ERR_DATA_LBN 0 |
| #define MCDI_EVENT_PAR_ERR_DATA_WIDTH 32 |
| #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0 |
| #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0 |
| #define MCDI_EVENT_ECC_CORR_ERR_DATA_WIDTH 32 |
| #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0 |
| #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0 |
| #define MCDI_EVENT_ECC_FATAL_ERR_DATA_WIDTH 32 |
| /* For CODE_PTP_TIME events, the major value of the PTP clock */ |
| #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0 |
| #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0 |
| #define MCDI_EVENT_PTP_TIME_MAJOR_WIDTH 32 |
| /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */ |
| #define MCDI_EVENT_PTP_TIME_MINOR_26_19_LBN 36 |
| #define MCDI_EVENT_PTP_TIME_MINOR_26_19_WIDTH 8 |
| |
| /* FCDI_EVENT structuredef */ |
| #define FCDI_EVENT_LEN 8 |
| #define FCDI_EVENT_CONT_LBN 32 |
| #define FCDI_EVENT_CONT_WIDTH 1 |
| #define FCDI_EVENT_LEVEL_LBN 33 |
| #define FCDI_EVENT_LEVEL_WIDTH 3 |
| /* enum: Info. */ |
| #define FCDI_EVENT_LEVEL_INFO 0x0 |
| /* enum: Warning. */ |
| #define FCDI_EVENT_LEVEL_WARN 0x1 |
| /* enum: Error. */ |
| #define FCDI_EVENT_LEVEL_ERR 0x2 |
| /* enum: Fatal. */ |
| #define FCDI_EVENT_LEVEL_FATAL 0x3 |
| #define FCDI_EVENT_DATA_OFST 0 |
| #define FCDI_EVENT_LINK_STATE_STATUS_LBN 0 |
| #define FCDI_EVENT_LINK_STATE_STATUS_WIDTH 1 |
| #define FCDI_EVENT_LINK_DOWN 0x0 /* enum */ |
| #define FCDI_EVENT_LINK_UP 0x1 /* enum */ |
| #define FCDI_EVENT_DATA_LBN 0 |
| #define FCDI_EVENT_DATA_WIDTH 32 |
| #define FCDI_EVENT_SRC_LBN 36 |
| #define FCDI_EVENT_SRC_WIDTH 8 |
| #define FCDI_EVENT_EV_CODE_LBN 60 |
| #define FCDI_EVENT_EV_CODE_WIDTH 4 |
| #define FCDI_EVENT_CODE_LBN 44 |
| #define FCDI_EVENT_CODE_WIDTH 8 |
| /* enum: The FC was rebooted. */ |
| #define FCDI_EVENT_CODE_REBOOT 0x1 |
| /* enum: Bad assert. */ |
| #define FCDI_EVENT_CODE_ASSERT 0x2 |
| /* enum: DDR3 test result. */ |
| #define FCDI_EVENT_CODE_DDR_TEST_RESULT 0x3 |
| /* enum: Link status. */ |
| #define FCDI_EVENT_CODE_LINK_STATE 0x4 |
| /* enum: A timed read is ready to be serviced. */ |
| #define FCDI_EVENT_CODE_TIMED_READ 0x5 |
| /* enum: One or more PPS IN events */ |
| #define FCDI_EVENT_CODE_PPS_IN 0x6 |
| /* enum: Tick event from PTP clock */ |
| #define FCDI_EVENT_CODE_PTP_TICK 0x7 |
| /* enum: ECC error counters */ |
| #define FCDI_EVENT_CODE_DDR_ECC_STATUS 0x8 |
| #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_OFST 0 |
| #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_LBN 0 |
| #define FCDI_EVENT_ASSERT_INSTR_ADDRESS_WIDTH 32 |
| #define FCDI_EVENT_ASSERT_TYPE_LBN 36 |
| #define FCDI_EVENT_ASSERT_TYPE_WIDTH 8 |
| #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_LBN 36 |
| #define FCDI_EVENT_DDR_TEST_RESULT_STATUS_CODE_WIDTH 8 |
| #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_OFST 0 |
| #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_LBN 0 |
| #define FCDI_EVENT_DDR_TEST_RESULT_RESULT_WIDTH 32 |
| #define FCDI_EVENT_LINK_STATE_DATA_OFST 0 |
| #define FCDI_EVENT_LINK_STATE_DATA_LBN 0 |
| #define FCDI_EVENT_LINK_STATE_DATA_WIDTH 32 |
| #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_LBN 36 |
| #define FCDI_EVENT_DDR_ECC_STATUS_BANK_ID_WIDTH 8 |
| #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_OFST 0 |
| #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_LBN 0 |
| #define FCDI_EVENT_DDR_ECC_STATUS_STATUS_WIDTH 32 |
| |
| /* FCDI_EXTENDED_EVENT_PPS structuredef: Extended FCDI event to send PPS events |
| * to the MC. Note that this structure | is overlayed over a normal FCDI event |
| * such that bits 32-63 containing | event code, level, source etc remain the |
| * same. In this case the data | field of the header is defined to be the |
| * number of timestamps |
| */ |
| #define FCDI_EXTENDED_EVENT_PPS_LENMIN 16 |
| #define FCDI_EXTENDED_EVENT_PPS_LENMAX 248 |
| #define FCDI_EXTENDED_EVENT_PPS_LEN(num) (8+8*(num)) |
| /* Number of timestamps following */ |
| #define FCDI_EXTENDED_EVENT_PPS_COUNT_OFST 0 |
| #define FCDI_EXTENDED_EVENT_PPS_COUNT_LBN 0 |
| #define FCDI_EXTENDED_EVENT_PPS_COUNT_WIDTH 32 |
| /* Seconds field of a timestamp record */ |
| #define FCDI_EXTENDED_EVENT_PPS_SECONDS_OFST 8 |
| #define FCDI_EXTENDED_EVENT_PPS_SECONDS_LBN 64 |
| #define FCDI_EXTENDED_EVENT_PPS_SECONDS_WIDTH 32 |
| /* Nanoseconds field of a timestamp record */ |
| #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_OFST 12 |
| #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_LBN 96 |
| #define FCDI_EXTENDED_EVENT_PPS_NANOSECONDS_WIDTH 32 |
| /* Timestamp records comprising the event */ |
| #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_OFST 8 |
| #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LEN 8 |
| #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LO_OFST 8 |
| #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_HI_OFST 12 |
| #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MINNUM 1 |
| #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_MAXNUM 30 |
| #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_LBN 64 |
| #define FCDI_EXTENDED_EVENT_PPS_TIMESTAMPS_WIDTH 64 |
| |
| |
| /***********************************/ |
| /* MC_CMD_READ32 |
| * Read multiple 32byte words from MC memory. |
| */ |
| #define MC_CMD_READ32 0x1 |
| |
| /* MC_CMD_READ32_IN msgrequest */ |
| #define MC_CMD_READ32_IN_LEN 8 |
| #define MC_CMD_READ32_IN_ADDR_OFST 0 |
| #define MC_CMD_READ32_IN_NUMWORDS_OFST 4 |
| |
| /* MC_CMD_READ32_OUT msgresponse */ |
| #define MC_CMD_READ32_OUT_LENMIN 4 |
| #define MC_CMD_READ32_OUT_LENMAX 252 |
| #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num)) |
| #define MC_CMD_READ32_OUT_BUFFER_OFST 0 |
| #define MC_CMD_READ32_OUT_BUFFER_LEN 4 |
| #define MC_CMD_READ32_OUT_BUFFER_MINNUM 1 |
| #define MC_CMD_READ32_OUT_BUFFER_MAXNUM 63 |
| |
| |
| /***********************************/ |
| /* MC_CMD_WRITE32 |
| * Write multiple 32byte words to MC memory. |
| */ |
| #define MC_CMD_WRITE32 0x2 |
| |
| /* MC_CMD_WRITE32_IN msgrequest */ |
| #define MC_CMD_WRITE32_IN_LENMIN 8 |
| #define MC_CMD_WRITE32_IN_LENMAX 252 |
| #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num)) |
| #define MC_CMD_WRITE32_IN_ADDR_OFST 0 |
| #define MC_CMD_WRITE32_IN_BUFFER_OFST 4 |
| #define MC_CMD_WRITE32_IN_BUFFER_LEN 4 |
| #define MC_CMD_WRITE32_IN_BUFFER_MINNUM 1 |
| #define MC_CMD_WRITE32_IN_BUFFER_MAXNUM 62 |
| |
| /* MC_CMD_WRITE32_OUT msgresponse */ |
| #define MC_CMD_WRITE32_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_COPYCODE |
| * Copy MC code between two locations and jump. |
| */ |
| #define MC_CMD_COPYCODE 0x3 |
| |
| /* MC_CMD_COPYCODE_IN msgrequest */ |
| #define MC_CMD_COPYCODE_IN_LEN 16 |
| /* Source address */ |
| #define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 |
| /* enum: The main image should be entered via a copy of a single word from and |
| * to this address when none of the other magic behaviours are required. |
| */ |
| #define MC_CMD_COPYCODE_HUNT_NO_MAGIC_ADDR 0x10000 |
| /* enum: Entering the main image via a copy of a single word from and to this |
| * address indicates that it should not attempt to start the datapath CPUs. |
| * This is useful for certain soft rebooting scenarios. (Huntington only) |
| */ |
| #define MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR 0x1d0d0 |
| /* enum: Entering the main image via a copy of a single word from and to this |
| * address indicates that it should not attempt to parse any configuration from |
| * flash. (In addition, the datapath CPUs will not be started, as for |
| * MC_CMD_COPYCODE_HUNT_NO_DATAPATH_MAGIC_ADDR above.) This is useful for |
| * certain soft rebooting scenarios. (Huntington only) |
| */ |
| #define MC_CMD_COPYCODE_HUNT_IGNORE_CONFIG_MAGIC_ADDR 0x1badc |
| /* Destination address */ |
| #define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 |
| #define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 |
| /* Address of where to jump after copy. */ |
| #define MC_CMD_COPYCODE_IN_JUMP_OFST 12 |
| /* enum: Control should return to the caller rather than jumping */ |
| #define MC_CMD_COPYCODE_JUMP_NONE 0x1 |
| |
| /* MC_CMD_COPYCODE_OUT msgresponse */ |
| #define MC_CMD_COPYCODE_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_SET_FUNC |
| * Select function for function-specific commands. |
| */ |
| #define MC_CMD_SET_FUNC 0x4 |
| |
| /* MC_CMD_SET_FUNC_IN msgrequest */ |
| #define MC_CMD_SET_FUNC_IN_LEN 4 |
| /* Set function */ |
| #define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 |
| |
| /* MC_CMD_SET_FUNC_OUT msgresponse */ |
| #define MC_CMD_SET_FUNC_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_GET_BOOT_STATUS |
| * Get the instruction address from which the MC booted. |
| */ |
| #define MC_CMD_GET_BOOT_STATUS 0x5 |
| |
| /* MC_CMD_GET_BOOT_STATUS_IN msgrequest */ |
| #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 |
| |
| /* MC_CMD_GET_BOOT_STATUS_OUT msgresponse */ |
| #define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 |
| /* ?? */ |
| #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 |
| /* enum: indicates that the MC wasn't flash booted */ |
| #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef |
| #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 |
| #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0 |
| #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_WIDTH 1 |
| #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_LBN 1 |
| #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_WIDTH 1 |
| #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_LBN 2 |
| #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_WIDTH 1 |
| |
| |
| /***********************************/ |
| /* MC_CMD_GET_ASSERTS |
| * Get (and optionally clear) the current assertion status. Only |
| * OUT.GLOBAL_FLAGS is guaranteed to exist in the completion payload. The other |
| * fields will only be present if OUT.GLOBAL_FLAGS != NO_FAILS |
| */ |
| #define MC_CMD_GET_ASSERTS 0x6 |
| |
| /* MC_CMD_GET_ASSERTS_IN msgrequest */ |
| #define MC_CMD_GET_ASSERTS_IN_LEN 4 |
| /* Set to clear assertion */ |
| #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 |
| |
| /* MC_CMD_GET_ASSERTS_OUT msgresponse */ |
| #define MC_CMD_GET_ASSERTS_OUT_LEN 140 |
| /* Assertion status flag. */ |
| #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 |
| /* enum: No assertions have failed. */ |
| #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 |
| /* enum: A system-level assertion has failed. */ |
| #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 |
| /* enum: A thread-level assertion has failed. */ |
| #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 |
| /* enum: The system was reset by the watchdog. */ |
| #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 |
| /* enum: An illegal address trap stopped the system (huntington and later) */ |
| #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 |
| /* Failing PC value */ |
| #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 |
| /* Saved GP regs */ |
| #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 |
| #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4 |
| #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_NUM 31 |
| /* Failing thread address */ |
| #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 |
| #define MC_CMD_GET_ASSERTS_OUT_RESERVED_OFST 136 |
| |
| |
| /***********************************/ |
| /* MC_CMD_LOG_CTRL |
| * Configure the output stream for various events and messages. |
| */ |
| #define MC_CMD_LOG_CTRL 0x7 |
| |
| /* MC_CMD_LOG_CTRL_IN msgrequest */ |
| #define MC_CMD_LOG_CTRL_IN_LEN 8 |
| /* Log destination */ |
| #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 |
| /* enum: UART. */ |
| #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1 |
| /* enum: Event queue. */ |
| #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2 |
| #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 |
| |
| /* MC_CMD_LOG_CTRL_OUT msgresponse */ |
| #define MC_CMD_LOG_CTRL_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_GET_VERSION |
| * Get version information about the MC firmware. |
| */ |
| #define MC_CMD_GET_VERSION 0x8 |
| |
| /* MC_CMD_GET_VERSION_IN msgrequest */ |
| #define MC_CMD_GET_VERSION_IN_LEN 0 |
| |
| /* MC_CMD_GET_VERSION_EXT_IN msgrequest: Asks for the extended version */ |
| #define MC_CMD_GET_VERSION_EXT_IN_LEN 4 |
| /* placeholder, set to 0 */ |
| #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0 |
| |
| /* MC_CMD_GET_VERSION_V0_OUT msgresponse: deprecated version format */ |
| #define MC_CMD_GET_VERSION_V0_OUT_LEN 4 |
| #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 |
| /* enum: Reserved version number to indicate "any" version. */ |
| #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff |
| /* enum: Bootrom version value for Siena. */ |
| #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000 |
| /* enum: Bootrom version value for Huntington. */ |
| #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001 |
| |
| /* MC_CMD_GET_VERSION_OUT msgresponse */ |
| #define MC_CMD_GET_VERSION_OUT_LEN 32 |
| /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ |
| /* Enum values, see field(s): */ |
| /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ |
| #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4 |
| /* 128bit mask of functions supported by the current firmware */ |
| #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_OFST 8 |
| #define MC_CMD_GET_VERSION_OUT_SUPPORTED_FUNCS_LEN 16 |
| #define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 |
| #define MC_CMD_GET_VERSION_OUT_VERSION_LEN 8 |
| #define MC_CMD_GET_VERSION_OUT_VERSION_LO_OFST 24 |
| #define MC_CMD_GET_VERSION_OUT_VERSION_HI_OFST 28 |
| |
| /* MC_CMD_GET_VERSION_EXT_OUT msgresponse */ |
| #define MC_CMD_GET_VERSION_EXT_OUT_LEN 48 |
| /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */ |
| /* Enum values, see field(s): */ |
| /* MC_CMD_GET_VERSION_V0_OUT/MC_CMD_GET_VERSION_OUT_FIRMWARE */ |
| #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4 |
| /* 128bit mask of functions supported by the current firmware */ |
| #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_OFST 8 |
| #define MC_CMD_GET_VERSION_EXT_OUT_SUPPORTED_FUNCS_LEN 16 |
| #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_OFST 24 |
| #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LEN 8 |
| #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_OFST 24 |
| #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_OFST 28 |
| /* extra info */ |
| #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_OFST 32 |
| #define MC_CMD_GET_VERSION_EXT_OUT_EXTRA_LEN 16 |
| |
| |
| /***********************************/ |
| /* MC_CMD_PTP |
| * Perform PTP operation |
| */ |
| #define MC_CMD_PTP 0xb |
| |
| /* MC_CMD_PTP_IN msgrequest */ |
| #define MC_CMD_PTP_IN_LEN 1 |
| /* PTP operation code */ |
| #define MC_CMD_PTP_IN_OP_OFST 0 |
| #define MC_CMD_PTP_IN_OP_LEN 1 |
| /* enum: Enable PTP packet timestamping operation. */ |
| #define MC_CMD_PTP_OP_ENABLE 0x1 |
| /* enum: Disable PTP packet timestamping operation. */ |
| #define MC_CMD_PTP_OP_DISABLE 0x2 |
| /* enum: Send a PTP packet. */ |
| #define MC_CMD_PTP_OP_TRANSMIT 0x3 |
| /* enum: Read the current NIC time. */ |
| #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4 |
| /* enum: Get the current PTP status. */ |
| #define MC_CMD_PTP_OP_STATUS 0x5 |
| /* enum: Adjust the PTP NIC's time. */ |
| #define MC_CMD_PTP_OP_ADJUST 0x6 |
| /* enum: Synchronize host and NIC time. */ |
| #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7 |
| /* enum: Basic manufacturing tests. */ |
| #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8 |
| /* enum: Packet based manufacturing tests. */ |
| #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9 |
| /* enum: Reset some of the PTP related statistics */ |
| #define MC_CMD_PTP_OP_RESET_STATS 0xa |
| /* enum: Debug operations to MC. */ |
| #define MC_CMD_PTP_OP_DEBUG 0xb |
| /* enum: Read an FPGA register */ |
| #define MC_CMD_PTP_OP_FPGAREAD 0xc |
| /* enum: Write an FPGA register */ |
| #define MC_CMD_PTP_OP_FPGAWRITE 0xd |
| /* enum: Apply an offset to the NIC clock */ |
| #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe |
| /* enum: Change Apply an offset to the NIC clock */ |
| #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf |
| /* enum: Set the MC packet filter VLAN tags for received PTP packets */ |
| #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10 |
| /* enum: Set the MC packet filter UUID for received PTP packets */ |
| #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11 |
| /* enum: Set the MC packet filter Domain for received PTP packets */ |
| #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12 |
| /* enum: Set the clock source */ |
| #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13 |
| /* enum: Reset value of Timer Reg. */ |
| #define MC_CMD_PTP_OP_RST_CLK 0x14 |
| /* enum: Enable the forwarding of PPS events to the host */ |
| #define MC_CMD_PTP_OP_PPS_ENABLE 0x15 |
| /* enum: Get the time format used by this NIC for PTP operations */ |
| #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16 |
| /* enum: Get the clock attributes. NOTE- extended version of |
| * MC_CMD_PTP_OP_GET_TIME_FORMAT |
| */ |
| #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16 |
| /* enum: Get corrections that should be applied to the various different |
| * timestamps |
| */ |
| #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17 |
| /* enum: Subscribe to receive periodic time events indicating the current NIC |
| * time |
| */ |
| #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18 |
| /* enum: Unsubscribe to stop receiving time events */ |
| #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19 |
| /* enum: PPS based manfacturing tests. Requires PPS output to be looped to PPS |
| * input on the same NIC. |
| */ |
| #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a |
| /* enum: Above this for future use. */ |
| #define MC_CMD_PTP_OP_MAX 0x1b |
| |
| /* MC_CMD_PTP_IN_ENABLE msgrequest */ |
| #define MC_CMD_PTP_IN_ENABLE_LEN 16 |
| #define MC_CMD_PTP_IN_CMD_OFST 0 |
| #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4 |
| /* Event queue for PTP events */ |
| #define MC_CMD_PTP_IN_ENABLE_QUEUE_OFST 8 |
| /* PTP timestamping mode */ |
| #define MC_CMD_PTP_IN_ENABLE_MODE_OFST 12 |
| /* enum: PTP, version 1 */ |
| #define MC_CMD_PTP_MODE_V1 0x0 |
| /* enum: PTP, version 1, with VLAN headers - deprecated */ |
| #define MC_CMD_PTP_MODE_V1_VLAN 0x1 |
| /* enum: PTP, version 2 */ |
| #define MC_CMD_PTP_MODE_V2 0x2 |
| /* enum: PTP, version 2, with VLAN headers - deprecated */ |
| #define MC_CMD_PTP_MODE_V2_VLAN 0x3 |
| /* enum: PTP, version 2, with improved UUID filtering */ |
| #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4 |
| /* enum: FCoE (seconds and microseconds) */ |
| #define MC_CMD_PTP_MODE_FCOE 0x5 |
| |
| /* MC_CMD_PTP_IN_DISABLE msgrequest */ |
| #define MC_CMD_PTP_IN_DISABLE_LEN 8 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| |
| /* MC_CMD_PTP_IN_TRANSMIT msgrequest */ |
| #define MC_CMD_PTP_IN_TRANSMIT_LENMIN 13 |
| #define MC_CMD_PTP_IN_TRANSMIT_LENMAX 252 |
| #define MC_CMD_PTP_IN_TRANSMIT_LEN(num) (12+1*(num)) |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* Transmit packet length */ |
| #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_OFST 8 |
| /* Transmit packet data */ |
| #define MC_CMD_PTP_IN_TRANSMIT_PACKET_OFST 12 |
| #define MC_CMD_PTP_IN_TRANSMIT_PACKET_LEN 1 |
| #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MINNUM 1 |
| #define MC_CMD_PTP_IN_TRANSMIT_PACKET_MAXNUM 240 |
| |
| /* MC_CMD_PTP_IN_READ_NIC_TIME msgrequest */ |
| #define MC_CMD_PTP_IN_READ_NIC_TIME_LEN 8 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| |
| /* MC_CMD_PTP_IN_STATUS msgrequest */ |
| #define MC_CMD_PTP_IN_STATUS_LEN 8 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| |
| /* MC_CMD_PTP_IN_ADJUST msgrequest */ |
| #define MC_CMD_PTP_IN_ADJUST_LEN 24 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* Frequency adjustment 40 bit fixed point ns */ |
| #define MC_CMD_PTP_IN_ADJUST_FREQ_OFST 8 |
| #define MC_CMD_PTP_IN_ADJUST_FREQ_LEN 8 |
| #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_OFST 8 |
| #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_OFST 12 |
| /* enum: Number of fractional bits in frequency adjustment */ |
| #define MC_CMD_PTP_IN_ADJUST_BITS 0x28 |
| /* Time adjustment in seconds */ |
| #define MC_CMD_PTP_IN_ADJUST_SECONDS_OFST 16 |
| /* Time adjustment major value */ |
| #define MC_CMD_PTP_IN_ADJUST_MAJOR_OFST 16 |
| /* Time adjustment in nanoseconds */ |
| #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_OFST 20 |
| /* Time adjustment minor value */ |
| #define MC_CMD_PTP_IN_ADJUST_MINOR_OFST 20 |
| |
| /* MC_CMD_PTP_IN_SYNCHRONIZE msgrequest */ |
| #define MC_CMD_PTP_IN_SYNCHRONIZE_LEN 20 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* Number of time readings to capture */ |
| #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_OFST 8 |
| /* Host address in which to write "synchronization started" indication (64 |
| * bits) |
| */ |
| #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_OFST 12 |
| #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LEN 8 |
| #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_OFST 12 |
| #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_OFST 16 |
| |
| /* MC_CMD_PTP_IN_MANFTEST_BASIC msgrequest */ |
| #define MC_CMD_PTP_IN_MANFTEST_BASIC_LEN 8 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| |
| /* MC_CMD_PTP_IN_MANFTEST_PACKET msgrequest */ |
| #define MC_CMD_PTP_IN_MANFTEST_PACKET_LEN 12 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* Enable or disable packet testing */ |
| #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_OFST 8 |
| |
| /* MC_CMD_PTP_IN_RESET_STATS msgrequest */ |
| #define MC_CMD_PTP_IN_RESET_STATS_LEN 8 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* Reset PTP statistics */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| |
| /* MC_CMD_PTP_IN_DEBUG msgrequest */ |
| #define MC_CMD_PTP_IN_DEBUG_LEN 12 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* Debug operations */ |
| #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_OFST 8 |
| |
| /* MC_CMD_PTP_IN_FPGAREAD msgrequest */ |
| #define MC_CMD_PTP_IN_FPGAREAD_LEN 16 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| #define MC_CMD_PTP_IN_FPGAREAD_ADDR_OFST 8 |
| #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_OFST 12 |
| |
| /* MC_CMD_PTP_IN_FPGAWRITE msgrequest */ |
| #define MC_CMD_PTP_IN_FPGAWRITE_LENMIN 13 |
| #define MC_CMD_PTP_IN_FPGAWRITE_LENMAX 252 |
| #define MC_CMD_PTP_IN_FPGAWRITE_LEN(num) (12+1*(num)) |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_OFST 8 |
| #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_OFST 12 |
| #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_LEN 1 |
| #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MINNUM 1 |
| #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_MAXNUM 240 |
| |
| /* MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST msgrequest */ |
| #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_LEN 16 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* Time adjustment in seconds */ |
| #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_OFST 8 |
| /* Time adjustment major value */ |
| #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_OFST 8 |
| /* Time adjustment in nanoseconds */ |
| #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_OFST 12 |
| /* Time adjustment minor value */ |
| #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_OFST 12 |
| |
| /* MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST msgrequest */ |
| #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_LEN 16 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* Frequency adjustment 40 bit fixed point ns */ |
| #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_OFST 8 |
| #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LEN 8 |
| #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_OFST 8 |
| #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_OFST 12 |
| /* enum: Number of fractional bits in frequency adjustment */ |
| /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */ |
| |
| /* MC_CMD_PTP_IN_RX_SET_VLAN_FILTER msgrequest */ |
| #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_LEN 24 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* Number of VLAN tags, 0 if not VLAN */ |
| #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_OFST 8 |
| /* Set of VLAN tags to filter against */ |
| #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_OFST 12 |
| #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4 |
| #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_NUM 3 |
| |
| /* MC_CMD_PTP_IN_RX_SET_UUID_FILTER msgrequest */ |
| #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_LEN 20 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* 1 to enable UUID filtering, 0 to disable */ |
| #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_OFST 8 |
| /* UUID to filter against */ |
| #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_OFST 12 |
| #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LEN 8 |
| #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_OFST 12 |
| #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_OFST 16 |
| |
| /* MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER msgrequest */ |
| #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_LEN 16 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* 1 to enable Domain filtering, 0 to disable */ |
| #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_OFST 8 |
| /* Domain number to filter against */ |
| #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_OFST 12 |
| |
| /* MC_CMD_PTP_IN_SET_CLK_SRC msgrequest */ |
| #define MC_CMD_PTP_IN_SET_CLK_SRC_LEN 12 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* Set the clock source. */ |
| #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_OFST 8 |
| /* enum: Internal. */ |
| #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0 |
| /* enum: External. */ |
| #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1 |
| |
| /* MC_CMD_PTP_IN_RST_CLK msgrequest */ |
| #define MC_CMD_PTP_IN_RST_CLK_LEN 8 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* Reset value of Timer Reg. */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| |
| /* MC_CMD_PTP_IN_PPS_ENABLE msgrequest */ |
| #define MC_CMD_PTP_IN_PPS_ENABLE_LEN 12 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* Enable or disable */ |
| #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4 |
| /* enum: Enable */ |
| #define MC_CMD_PTP_ENABLE_PPS 0x0 |
| /* enum: Disable */ |
| #define MC_CMD_PTP_DISABLE_PPS 0x1 |
| /* Queue id to send events back */ |
| #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_OFST 8 |
| |
| /* MC_CMD_PTP_IN_GET_TIME_FORMAT msgrequest */ |
| #define MC_CMD_PTP_IN_GET_TIME_FORMAT_LEN 8 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| |
| /* MC_CMD_PTP_IN_GET_ATTRIBUTES msgrequest */ |
| #define MC_CMD_PTP_IN_GET_ATTRIBUTES_LEN 8 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| |
| /* MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS msgrequest */ |
| #define MC_CMD_PTP_IN_GET_TIMESTAMP_CORRECTIONS_LEN 8 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| |
| /* MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE msgrequest */ |
| #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_LEN 12 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* Event queue to send PTP time events to */ |
| #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_OFST 8 |
| |
| /* MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE msgrequest */ |
| #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_LEN 16 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* Unsubscribe options */ |
| #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_OFST 8 |
| /* enum: Unsubscribe a single queue */ |
| #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0 |
| /* enum: Unsubscribe all queues */ |
| #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1 |
| /* Event queue ID */ |
| #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_OFST 12 |
| |
| /* MC_CMD_PTP_IN_MANFTEST_PPS msgrequest */ |
| #define MC_CMD_PTP_IN_MANFTEST_PPS_LEN 12 |
| /* MC_CMD_PTP_IN_CMD_OFST 0 */ |
| /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */ |
| /* 1 to enable PPS test mode, 0 to disable and return result. */ |
| #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_OFST 8 |
| |
| /* MC_CMD_PTP_OUT msgresponse */ |
| #define MC_CMD_PTP_OUT_LEN 0 |
| |
| /* MC_CMD_PTP_OUT_TRANSMIT msgresponse */ |
| #define MC_CMD_PTP_OUT_TRANSMIT_LEN 8 |
| /* Value of seconds timestamp */ |
| #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0 |
| /* Timestamp major value */ |
| #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0 |
| /* Value of nanoseconds timestamp */ |
| #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4 |
| /* Timestamp minor value */ |
| #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4 |
| |
| /* MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE msgresponse */ |
| #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0 |
| |
| /* MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE msgresponse */ |
| #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0 |
| |
| /* MC_CMD_PTP_OUT_READ_NIC_TIME msgresponse */ |
| #define MC_CMD_PTP_OUT_READ_NIC_TIME_LEN 8 |
| /* Value of seconds timestamp */ |
| #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0 |
| /* Timestamp major value */ |
| #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0 |
| /* Value of nanoseconds timestamp */ |
| #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4 |
| /* Timestamp minor value */ |
| #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4 |
| |
| /* MC_CMD_PTP_OUT_STATUS msgresponse */ |
| #define MC_CMD_PTP_OUT_STATUS_LEN 64 |
| /* Frequency of NIC's hardware clock */ |
| #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0 |
| /* Number of packets transmitted and timestamped */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4 |
| /* Number of packets received and timestamped */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_RX_OFST 8 |
| /* Number of packets timestamped by the FPGA */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_TS_OFST 12 |
| /* Number of packets filter matched */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_FM_OFST 16 |
| /* Number of packets not filter matched */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_OFST 20 |
| /* Number of PPS overflows (noise on input?) */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_OFST 24 |
| /* Number of PPS bad periods */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_OFST 28 |
| /* Minimum period of PPS pulse in nanoseconds */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_OFST 32 |
| /* Maximum period of PPS pulse in nanoseconds */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_OFST 36 |
| /* Last period of PPS pulse in nanoseconds */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_OFST 40 |
| /* Mean period of PPS pulse in nanoseconds */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_OFST 44 |
| /* Minimum offset of PPS pulse in nanoseconds (signed) */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_OFST 48 |
| /* Maximum offset of PPS pulse in nanoseconds (signed) */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_OFST 52 |
| /* Last offset of PPS pulse in nanoseconds (signed) */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_OFST 56 |
| /* Mean offset of PPS pulse in nanoseconds (signed) */ |
| #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_OFST 60 |
| |
| /* MC_CMD_PTP_OUT_SYNCHRONIZE msgresponse */ |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMIN 20 |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_LENMAX 240 |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num)) |
| /* A set of host and NIC times */ |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0 |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_LEN 20 |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MINNUM 1 |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_MAXNUM 12 |
| /* Host time immediately before NIC's hardware clock read */ |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0 |
| /* Value of seconds timestamp */ |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4 |
| /* Timestamp major value */ |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4 |
| /* Value of nanoseconds timestamp */ |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_OFST 8 |
| /* Timestamp minor value */ |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_OFST 8 |
| /* Host time immediately after NIC's hardware clock read */ |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_OFST 12 |
| /* Number of nanoseconds waited after reading NIC's hardware clock */ |
| #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_OFST 16 |
| |
| /* MC_CMD_PTP_OUT_MANFTEST_BASIC msgresponse */ |
| #define MC_CMD_PTP_OUT_MANFTEST_BASIC_LEN 8 |
| /* Results of testing */ |
| #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0 |
| /* enum: Successful test */ |
| #define MC_CMD_PTP_MANF_SUCCESS 0x0 |
| /* enum: FPGA load failed */ |
| #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1 |
| /* enum: FPGA version invalid */ |
| #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2 |
| /* enum: FPGA registers incorrect */ |
| #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3 |
| /* enum: Oscillator possibly not working? */ |
| #define MC_CMD_PTP_MANF_OSCILLATOR 0x4 |
| /* enum: Timestamps not increasing */ |
| #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5 |
| /* enum: Mismatched packet count */ |
| #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6 |
| /* enum: Mismatched packet count (Siena filter and FPGA) */ |
| #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7 |
| /* enum: Not enough packets to perform timestamp check */ |
| #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8 |
| /* enum: Timestamp trigger GPIO not working */ |
| #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9 |
| /* enum: Insufficient PPS events to perform checks */ |
| #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa |
| /* enum: PPS time event period not sufficiently close to 1s. */ |
| #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb |
| /* enum: PPS time event nS reading not sufficiently close to zero. */ |
| #define MC_CMD_PTP_MANF_PPS_NS 0xc |
| /* enum: PTP peripheral registers incorrect */ |
| #define MC_CMD_PTP_MANF_REGISTERS 0xd |
| /* enum: Failed to read time from PTP peripheral */ |
| #define MC_CMD_PTP_MANF_CLOCK_READ 0xe |
| /* Presence of external oscillator */ |
| #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4 |
| |
| /* MC_CMD_PTP_OUT_MANFTEST_PACKET msgresponse */ |
| #define MC_CMD_PTP_OUT_MANFTEST_PACKET_LEN 12 |
| /* Results of testing */ |
| #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0 |
| /* Number of packets received by FPGA */ |
| #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4 |
| /* Number of packets received by Siena filters */ |
| #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_OFST 8 |
| |
| /* MC_CMD_PTP_OUT_FPGAREAD msgresponse */ |
| #define MC_CMD_PTP_OUT_FPGAREAD_LENMIN 1 |
| #define MC_CMD_PTP_OUT_FPGAREAD_LENMAX 252 |
| #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num)) |
| #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0 |
| #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_LEN 1 |
| #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MINNUM 1 |
| #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_MAXNUM 252 |
| |
| /* MC_CMD_PTP_OUT_GET_TIME_FORMAT msgresponse */ |
| #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4 |
| /* Time format required/used by for this NIC. Applies to all PTP MCDI |
| * operations that pass times between the host and firmware. If this operation |
| * is not supported (older firmware) a format of seconds and nanoseconds should |
| * be assumed. |
| */ |
| #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0 |
| /* enum: Times are in seconds and nanoseconds */ |
| #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0 |
| /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ |
| #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1 |
| /* enum: Major register has units of seconds, minor 2^-27s per tick */ |
| #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2 |
| |
| /* MC_CMD_PTP_OUT_GET_ATTRIBUTES msgresponse */ |
| #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_LEN 8 |
| /* Time format required/used by for this NIC. Applies to all PTP MCDI |
| * operations that pass times between the host and firmware. If this operation |
| * is not supported (older firmware) a format of seconds and nanoseconds should |
| * be assumed. |
| */ |
| #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0 |
| /* enum: Times are in seconds and nanoseconds */ |
| #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0 |
| /* enum: Major register has units of 16 second per tick, minor 8 ns per tick */ |
| #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1 |
| /* enum: Major register has units of seconds, minor 2^-27s per tick */ |
| #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2 |
| /* Minimum acceptable value for a corrected synchronization timeset. When |
| * comparing host and NIC clock times, the MC returns a set of samples that |
| * contain the host start and end time, the MC time when the host start was |
| * detected and the time the MC waited between reading the time and detecting |
| * the host end. The corrected sync window is the difference between the host |
| * end and start times minus the time that the MC waited for host end. |
| */ |
| #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4 |
| |
| /* MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS msgresponse */ |
| #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_LEN 16 |
| /* Uncorrected error on transmit timestamps in NIC clock format */ |
| #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0 |
| /* Uncorrected error on receive timestamps in NIC clock format */ |
| #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4 |
| /* Uncorrected error on PPS output in NIC clock format */ |
| #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_OFST 8 |
| /* Uncorrected error on PPS input in NIC clock format */ |
| #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_OFST 12 |
| |
| /* MC_CMD_PTP_OUT_MANFTEST_PPS msgresponse */ |
| #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4 |
| /* Results of testing */ |
| #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0 |
| /* Enum values, see field(s): */ |
| /* MC_CMD_PTP_OUT_MANFTEST_BASIC/TEST_RESULT */ |
| |
| |
| /***********************************/ |
| /* MC_CMD_CSR_READ32 |
| * Read 32bit words from the indirect memory map. |
| */ |
| #define MC_CMD_CSR_READ32 0xc |
| |
| /* MC_CMD_CSR_READ32_IN msgrequest */ |
| #define MC_CMD_CSR_READ32_IN_LEN 12 |
| /* Address */ |
| #define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 |
| #define MC_CMD_CSR_READ32_IN_STEP_OFST 4 |
| #define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 |
| |
| /* MC_CMD_CSR_READ32_OUT msgresponse */ |
| #define MC_CMD_CSR_READ32_OUT_LENMIN 4 |
| #define MC_CMD_CSR_READ32_OUT_LENMAX 252 |
| #define MC_CMD_CSR_READ32_OUT_LEN(num) (0+4*(num)) |
| /* The last dword is the status, not a value read */ |
| #define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 |
| #define MC_CMD_CSR_READ32_OUT_BUFFER_LEN 4 |
| #define MC_CMD_CSR_READ32_OUT_BUFFER_MINNUM 1 |
| #define MC_CMD_CSR_READ32_OUT_BUFFER_MAXNUM 63 |
| |
| |
| /***********************************/ |
| /* MC_CMD_CSR_WRITE32 |
| * Write 32bit dwords to the indirect memory map. |
| */ |
| #define MC_CMD_CSR_WRITE32 0xd |
| |
| /* MC_CMD_CSR_WRITE32_IN msgrequest */ |
| #define MC_CMD_CSR_WRITE32_IN_LENMIN 12 |
| #define MC_CMD_CSR_WRITE32_IN_LENMAX 252 |
| #define MC_CMD_CSR_WRITE32_IN_LEN(num) (8+4*(num)) |
| /* Address */ |
| #define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 |
| #define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 |
| #define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 |
| #define MC_CMD_CSR_WRITE32_IN_BUFFER_LEN 4 |
| #define MC_CMD_CSR_WRITE32_IN_BUFFER_MINNUM 1 |
| #define MC_CMD_CSR_WRITE32_IN_BUFFER_MAXNUM 61 |
| |
| /* MC_CMD_CSR_WRITE32_OUT msgresponse */ |
| #define MC_CMD_CSR_WRITE32_OUT_LEN 4 |
| #define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_HP |
| * These commands are used for HP related features. They are grouped under one |
| * MCDI command to avoid creating too many MCDI commands. |
| */ |
| #define MC_CMD_HP 0x54 |
| |
| /* MC_CMD_HP_IN msgrequest */ |
| #define MC_CMD_HP_IN_LEN 16 |
| /* HP OCSD sub-command. When address is not NULL, request activation of OCSD at |
| * the specified address with the specified interval.When address is NULL, |
| * INTERVAL is interpreted as a command: 0: stop OCSD / 1: Report OCSD current |
| * state / 2: (debug) Show temperature reported by one of the supported |
| * sensors. |
| */ |
| #define MC_CMD_HP_IN_SUBCMD_OFST 0 |
| /* enum: OCSD (Option Card Sensor Data) sub-command. */ |
| #define MC_CMD_HP_IN_OCSD_SUBCMD 0x0 |
| /* enum: Last known valid HP sub-command. */ |
| #define MC_CMD_HP_IN_LAST_SUBCMD 0x0 |
| /* The address to the array of sensor fields. (Or NULL to use a sub-command.) |
| */ |
| #define MC_CMD_HP_IN_OCSD_ADDR_OFST 4 |
| #define MC_CMD_HP_IN_OCSD_ADDR_LEN 8 |
| #define MC_CMD_HP_IN_OCSD_ADDR_LO_OFST 4 |
| #define MC_CMD_HP_IN_OCSD_ADDR_HI_OFST 8 |
| /* The requested update interval, in seconds. (Or the sub-command if ADDR is |
| * NULL.) |
| */ |
| #define MC_CMD_HP_IN_OCSD_INTERVAL_OFST 12 |
| |
| /* MC_CMD_HP_OUT msgresponse */ |
| #define MC_CMD_HP_OUT_LEN 4 |
| #define MC_CMD_HP_OUT_OCSD_STATUS_OFST 0 |
| /* enum: OCSD stopped for this card. */ |
| #define MC_CMD_HP_OUT_OCSD_STOPPED 0x1 |
| /* enum: OCSD was successfully started with the address provided. */ |
| #define MC_CMD_HP_OUT_OCSD_STARTED 0x2 |
| /* enum: OCSD was already started for this card. */ |
| #define MC_CMD_HP_OUT_OCSD_ALREADY_STARTED 0x3 |
| |
| |
| /***********************************/ |
| /* MC_CMD_STACKINFO |
| * Get stack information. |
| */ |
| #define MC_CMD_STACKINFO 0xf |
| |
| /* MC_CMD_STACKINFO_IN msgrequest */ |
| #define MC_CMD_STACKINFO_IN_LEN 0 |
| |
| /* MC_CMD_STACKINFO_OUT msgresponse */ |
| #define MC_CMD_STACKINFO_OUT_LENMIN 12 |
| #define MC_CMD_STACKINFO_OUT_LENMAX 252 |
| #define MC_CMD_STACKINFO_OUT_LEN(num) (0+12*(num)) |
| /* (thread ptr, stack size, free space) for each thread in system */ |
| #define MC_CMD_STACKINFO_OUT_THREAD_INFO_OFST 0 |
| #define MC_CMD_STACKINFO_OUT_THREAD_INFO_LEN 12 |
| #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MINNUM 1 |
| #define MC_CMD_STACKINFO_OUT_THREAD_INFO_MAXNUM 21 |
| |
| |
| /***********************************/ |
| /* MC_CMD_MDIO_READ |
| * MDIO register read. |
| */ |
| #define MC_CMD_MDIO_READ 0x10 |
| |
| /* MC_CMD_MDIO_READ_IN msgrequest */ |
| #define MC_CMD_MDIO_READ_IN_LEN 16 |
| /* Bus number; there are two MDIO buses: one for the internal PHY, and one for |
| * external devices. |
| */ |
| #define MC_CMD_MDIO_READ_IN_BUS_OFST 0 |
| /* enum: Internal. */ |
| #define MC_CMD_MDIO_BUS_INTERNAL 0x0 |
| /* enum: External. */ |
| #define MC_CMD_MDIO_BUS_EXTERNAL 0x1 |
| /* Port address */ |
| #define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 |
| /* Device Address or clause 22. */ |
| #define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 |
| /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you |
| * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. |
| */ |
| #define MC_CMD_MDIO_CLAUSE22 0x20 |
| /* Address */ |
| #define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 |
| |
| /* MC_CMD_MDIO_READ_OUT msgresponse */ |
| #define MC_CMD_MDIO_READ_OUT_LEN 8 |
| /* Value */ |
| #define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 |
| /* Status the MDIO commands return the raw status bits from the MDIO block. A |
| * "good" transaction should have the DONE bit set and all other bits clear. |
| */ |
| #define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 |
| /* enum: Good. */ |
| #define MC_CMD_MDIO_STATUS_GOOD 0x8 |
| |
| |
| /***********************************/ |
| /* MC_CMD_MDIO_WRITE |
| * MDIO register write. |
| */ |
| #define MC_CMD_MDIO_WRITE 0x11 |
| |
| /* MC_CMD_MDIO_WRITE_IN msgrequest */ |
| #define MC_CMD_MDIO_WRITE_IN_LEN 20 |
| /* Bus number; there are two MDIO buses: one for the internal PHY, and one for |
| * external devices. |
| */ |
| #define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 |
| /* enum: Internal. */ |
| /* MC_CMD_MDIO_BUS_INTERNAL 0x0 */ |
| /* enum: External. */ |
| /* MC_CMD_MDIO_BUS_EXTERNAL 0x1 */ |
| /* Port address */ |
| #define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 |
| /* Device Address or clause 22. */ |
| #define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 |
| /* enum: By default all the MCDI MDIO operations perform clause45 mode. If you |
| * want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. |
| */ |
| /* MC_CMD_MDIO_CLAUSE22 0x20 */ |
| /* Address */ |
| #define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 |
| /* Value */ |
| #define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 |
| |
| /* MC_CMD_MDIO_WRITE_OUT msgresponse */ |
| #define MC_CMD_MDIO_WRITE_OUT_LEN 4 |
| /* Status; the MDIO commands return the raw status bits from the MDIO block. A |
| * "good" transaction should have the DONE bit set and all other bits clear. |
| */ |
| #define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 |
| /* enum: Good. */ |
| /* MC_CMD_MDIO_STATUS_GOOD 0x8 */ |
| |
| |
| /***********************************/ |
| /* MC_CMD_DBI_WRITE |
| * Write DBI register(s). |
| */ |
| #define MC_CMD_DBI_WRITE 0x12 |
| |
| /* MC_CMD_DBI_WRITE_IN msgrequest */ |
| #define MC_CMD_DBI_WRITE_IN_LENMIN 12 |
| #define MC_CMD_DBI_WRITE_IN_LENMAX 252 |
| #define MC_CMD_DBI_WRITE_IN_LEN(num) (0+12*(num)) |
| /* Each write op consists of an address (offset 0), byte enable/VF/CS2 (offset |
| * 32) and value (offset 64). See MC_CMD_DBIWROP_TYPEDEF. |
| */ |
| #define MC_CMD_DBI_WRITE_IN_DBIWROP_OFST 0 |
| #define MC_CMD_DBI_WRITE_IN_DBIWROP_LEN 12 |
| #define MC_CMD_DBI_WRITE_IN_DBIWROP_MINNUM 1 |
| #define MC_CMD_DBI_WRITE_IN_DBIWROP_MAXNUM 21 |
| |
| /* MC_CMD_DBI_WRITE_OUT msgresponse */ |
| #define MC_CMD_DBI_WRITE_OUT_LEN 0 |
| |
| /* MC_CMD_DBIWROP_TYPEDEF structuredef */ |
| #define MC_CMD_DBIWROP_TYPEDEF_LEN 12 |
| #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_OFST 0 |
| #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_LBN 0 |
| #define MC_CMD_DBIWROP_TYPEDEF_ADDRESS_WIDTH 32 |
| #define MC_CMD_DBIWROP_TYPEDEF_PARMS_OFST 4 |
| #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_LBN 16 |
| #define MC_CMD_DBIWROP_TYPEDEF_VF_NUM_WIDTH 16 |
| #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_LBN 15 |
| #define MC_CMD_DBIWROP_TYPEDEF_VF_ACTIVE_WIDTH 1 |
| #define MC_CMD_DBIWROP_TYPEDEF_CS2_LBN 14 |
| #define MC_CMD_DBIWROP_TYPEDEF_CS2_WIDTH 1 |
| #define MC_CMD_DBIWROP_TYPEDEF_PARMS_LBN 32 |
| #define MC_CMD_DBIWROP_TYPEDEF_PARMS_WIDTH 32 |
| #define MC_CMD_DBIWROP_TYPEDEF_VALUE_OFST 8 |
| #define MC_CMD_DBIWROP_TYPEDEF_VALUE_LBN 64 |
| #define MC_CMD_DBIWROP_TYPEDEF_VALUE_WIDTH 32 |
| |
| |
| /***********************************/ |
| /* MC_CMD_PORT_READ32 |
| * Read a 32-bit register from the indirect port register map. The port to |
| * access is implied by the Shared memory channel used. |
| */ |
| #define MC_CMD_PORT_READ32 0x14 |
| |
| /* MC_CMD_PORT_READ32_IN msgrequest */ |
| #define MC_CMD_PORT_READ32_IN_LEN 4 |
| /* Address */ |
| #define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 |
| |
| /* MC_CMD_PORT_READ32_OUT msgresponse */ |
| #define MC_CMD_PORT_READ32_OUT_LEN 8 |
| /* Value */ |
| #define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 |
| /* Status */ |
| #define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 |
| |
| |
| /***********************************/ |
| /* MC_CMD_PORT_WRITE32 |
| * Write a 32-bit register to the indirect port register map. The port to |
| * access is implied by the Shared memory channel used. |
| */ |
| #define MC_CMD_PORT_WRITE32 0x15 |
| |
| /* MC_CMD_PORT_WRITE32_IN msgrequest */ |
| #define MC_CMD_PORT_WRITE32_IN_LEN 8 |
| /* Address */ |
| #define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 |
| /* Value */ |
| #define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 |
| |
| /* MC_CMD_PORT_WRITE32_OUT msgresponse */ |
| #define MC_CMD_PORT_WRITE32_OUT_LEN 4 |
| /* Status */ |
| #define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_PORT_READ128 |
| * Read a 128-bit register from the indirect port register map. The port to |
| * access is implied by the Shared memory channel used. |
| */ |
| #define MC_CMD_PORT_READ128 0x16 |
| |
| /* MC_CMD_PORT_READ128_IN msgrequest */ |
| #define MC_CMD_PORT_READ128_IN_LEN 4 |
| /* Address */ |
| #define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 |
| |
| /* MC_CMD_PORT_READ128_OUT msgresponse */ |
| #define MC_CMD_PORT_READ128_OUT_LEN 20 |
| /* Value */ |
| #define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 |
| #define MC_CMD_PORT_READ128_OUT_VALUE_LEN 16 |
| /* Status */ |
| #define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 |
| |
| |
| /***********************************/ |
| /* MC_CMD_PORT_WRITE128 |
| * Write a 128-bit register to the indirect port register map. The port to |
| * access is implied by the Shared memory channel used. |
| */ |
| #define MC_CMD_PORT_WRITE128 0x17 |
| |
| /* MC_CMD_PORT_WRITE128_IN msgrequest */ |
| #define MC_CMD_PORT_WRITE128_IN_LEN 20 |
| /* Address */ |
| #define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 |
| /* Value */ |
| #define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 |
| #define MC_CMD_PORT_WRITE128_IN_VALUE_LEN 16 |
| |
| /* MC_CMD_PORT_WRITE128_OUT msgresponse */ |
| #define MC_CMD_PORT_WRITE128_OUT_LEN 4 |
| /* Status */ |
| #define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 |
| |
| /* MC_CMD_CAPABILITIES structuredef */ |
| #define MC_CMD_CAPABILITIES_LEN 4 |
| /* Small buf table. */ |
| #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_LBN 0 |
| #define MC_CMD_CAPABILITIES_SMALL_BUF_TBL_WIDTH 1 |
| /* Turbo mode (for Maranello). */ |
| #define MC_CMD_CAPABILITIES_TURBO_LBN 1 |
| #define MC_CMD_CAPABILITIES_TURBO_WIDTH 1 |
| /* Turbo mode active (for Maranello). */ |
| #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_LBN 2 |
| #define MC_CMD_CAPABILITIES_TURBO_ACTIVE_WIDTH 1 |
| /* PTP offload. */ |
| #define MC_CMD_CAPABILITIES_PTP_LBN 3 |
| #define MC_CMD_CAPABILITIES_PTP_WIDTH 1 |
| /* AOE mode. */ |
| #define MC_CMD_CAPABILITIES_AOE_LBN 4 |
| #define MC_CMD_CAPABILITIES_AOE_WIDTH 1 |
| /* AOE mode active. */ |
| #define MC_CMD_CAPABILITIES_AOE_ACTIVE_LBN 5 |
| #define MC_CMD_CAPABILITIES_AOE_ACTIVE_WIDTH 1 |
| /* AOE mode active. */ |
| #define MC_CMD_CAPABILITIES_FC_ACTIVE_LBN 6 |
| #define MC_CMD_CAPABILITIES_FC_ACTIVE_WIDTH 1 |
| #define MC_CMD_CAPABILITIES_RESERVED_LBN 7 |
| #define MC_CMD_CAPABILITIES_RESERVED_WIDTH 25 |
| |
| |
| /***********************************/ |
| /* MC_CMD_GET_BOARD_CFG |
| * Returns the MC firmware configuration structure. |
| */ |
| #define MC_CMD_GET_BOARD_CFG 0x18 |
| |
| /* MC_CMD_GET_BOARD_CFG_IN msgrequest */ |
| #define MC_CMD_GET_BOARD_CFG_IN_LEN 0 |
| |
| /* MC_CMD_GET_BOARD_CFG_OUT msgresponse */ |
| #define MC_CMD_GET_BOARD_CFG_OUT_LENMIN 96 |
| #define MC_CMD_GET_BOARD_CFG_OUT_LENMAX 136 |
| #define MC_CMD_GET_BOARD_CFG_OUT_LEN(num) (72+2*(num)) |
| #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 |
| #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 |
| #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 |
| /* See MC_CMD_CAPABILITIES */ |
| #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 |
| /* See MC_CMD_CAPABILITIES */ |
| #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 |
| #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 |
| #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 |
| #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 |
| #define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 |
| #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 |
| #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 |
| #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 |
| #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 |
| /* This field contains a 16-bit value for each of the types of NVRAM area. The |
| * values are defined in the firmware/mc/platform/.c file for a specific board |
| * type, but otherwise have no meaning to the MC; they are used by the driver |
| * to manage selection of appropriate firmware updates. |
| */ |
| #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 |
| #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 2 |
| #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MINNUM 12 |
| #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_MAXNUM 32 |
| |
| |
| /***********************************/ |
| /* MC_CMD_DBI_READX |
| * Read DBI register(s) -- extended functionality |
| */ |
| #define MC_CMD_DBI_READX 0x19 |
| |
| /* MC_CMD_DBI_READX_IN msgrequest */ |
| #define MC_CMD_DBI_READX_IN_LENMIN 8 |
| #define MC_CMD_DBI_READX_IN_LENMAX 248 |
| #define MC_CMD_DBI_READX_IN_LEN(num) (0+8*(num)) |
| /* Each Read op consists of an address (offset 0), VF/CS2) */ |
| #define MC_CMD_DBI_READX_IN_DBIRDOP_OFST 0 |
| #define MC_CMD_DBI_READX_IN_DBIRDOP_LEN 8 |
| #define MC_CMD_DBI_READX_IN_DBIRDOP_LO_OFST 0 |
| #define MC_CMD_DBI_READX_IN_DBIRDOP_HI_OFST 4 |
| #define MC_CMD_DBI_READX_IN_DBIRDOP_MINNUM 1 |
| #define MC_CMD_DBI_READX_IN_DBIRDOP_MAXNUM 31 |
| |
| /* MC_CMD_DBI_READX_OUT msgresponse */ |
| #define MC_CMD_DBI_READX_OUT_LENMIN 4 |
| #define MC_CMD_DBI_READX_OUT_LENMAX 252 |
| #define MC_CMD_DBI_READX_OUT_LEN(num) (0+4*(num)) |
| /* Value */ |
| #define MC_CMD_DBI_READX_OUT_VALUE_OFST 0 |
| #define MC_CMD_DBI_READX_OUT_VALUE_LEN 4 |
| #define MC_CMD_DBI_READX_OUT_VALUE_MINNUM 1 |
| #define MC_CMD_DBI_READX_OUT_VALUE_MAXNUM 63 |
| |
| /* MC_CMD_DBIRDOP_TYPEDEF structuredef */ |
| #define MC_CMD_DBIRDOP_TYPEDEF_LEN 8 |
| #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_OFST 0 |
| #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_LBN 0 |
| #define MC_CMD_DBIRDOP_TYPEDEF_ADDRESS_WIDTH 32 |
| #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_OFST 4 |
| #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_LBN 16 |
| #define MC_CMD_DBIRDOP_TYPEDEF_VF_NUM_WIDTH 16 |
| #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_LBN 15 |
| #define MC_CMD_DBIRDOP_TYPEDEF_VF_ACTIVE_WIDTH 1 |
| #define MC_CMD_DBIRDOP_TYPEDEF_CS2_LBN 14 |
| #define MC_CMD_DBIRDOP_TYPEDEF_CS2_WIDTH 1 |
| #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_LBN 32 |
| #define MC_CMD_DBIRDOP_TYPEDEF_PARMS_WIDTH 32 |
| |
| |
| /***********************************/ |
| /* MC_CMD_SET_RAND_SEED |
| * Set the 16byte seed for the MC pseudo-random generator. |
| */ |
| #define MC_CMD_SET_RAND_SEED 0x1a |
| |
| /* MC_CMD_SET_RAND_SEED_IN msgrequest */ |
| #define MC_CMD_SET_RAND_SEED_IN_LEN 16 |
| /* Seed value. */ |
| #define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 |
| #define MC_CMD_SET_RAND_SEED_IN_SEED_LEN 16 |
| |
| /* MC_CMD_SET_RAND_SEED_OUT msgresponse */ |
| #define MC_CMD_SET_RAND_SEED_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_LTSSM_HIST |
| * Retrieve the history of the LTSSM, if the build supports it. |
| */ |
| #define MC_CMD_LTSSM_HIST 0x1b |
| |
| /* MC_CMD_LTSSM_HIST_IN msgrequest */ |
| #define MC_CMD_LTSSM_HIST_IN_LEN 0 |
| |
| /* MC_CMD_LTSSM_HIST_OUT msgresponse */ |
| #define MC_CMD_LTSSM_HIST_OUT_LENMIN 0 |
| #define MC_CMD_LTSSM_HIST_OUT_LENMAX 252 |
| #define MC_CMD_LTSSM_HIST_OUT_LEN(num) (0+4*(num)) |
| /* variable number of LTSSM values, as bytes. The history is read-to-clear. */ |
| #define MC_CMD_LTSSM_HIST_OUT_DATA_OFST 0 |
| #define MC_CMD_LTSSM_HIST_OUT_DATA_LEN 4 |
| #define MC_CMD_LTSSM_HIST_OUT_DATA_MINNUM 0 |
| #define MC_CMD_LTSSM_HIST_OUT_DATA_MAXNUM 63 |
| |
| |
| /***********************************/ |
| /* MC_CMD_DRV_ATTACH |
| * Inform MCPU that this port is managed on the host (i.e. driver active). For |
| * Huntington, also request the preferred datapath firmware to use if possible |
| * (it may not be possible for this request to be fulfilled; the driver must |
| * issue a subsequent MC_CMD_GET_CAPABILITIES command to determine which |
| * features are actually available). The FIRMWARE_ID field is ignored by older |
| * platforms. |
| */ |
| #define MC_CMD_DRV_ATTACH 0x1c |
| |
| /* MC_CMD_DRV_ATTACH_IN msgrequest */ |
| #define MC_CMD_DRV_ATTACH_IN_LEN 12 |
| /* new state (0=detached, 1=attached) to set if UPDATE=1 */ |
| #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 |
| /* 1 to set new state, or 0 to just report the existing state */ |
| #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 |
| /* preferred datapath firmware (for Huntington; ignored for Siena) */ |
| #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_OFST 8 |
| /* enum: Prefer to use full featured firmware */ |
| #define MC_CMD_FW_FULL_FEATURED 0x0 |
| /* enum: Prefer to use firmware with fewer features but lower latency */ |
| #define MC_CMD_FW_LOW_LATENCY 0x1 |
| |
| /* MC_CMD_DRV_ATTACH_OUT msgresponse */ |
| #define MC_CMD_DRV_ATTACH_OUT_LEN 4 |
| /* previous or existing state (0=detached, 1=attached) */ |
| #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 |
| |
| /* MC_CMD_DRV_ATTACH_EXT_OUT msgresponse */ |
| #define MC_CMD_DRV_ATTACH_EXT_OUT_LEN 8 |
| /* previous or existing state (0=detached, 1=attached) */ |
| #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0 |
| /* Flags associated with this function */ |
| #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4 |
| /* enum: Labels the lowest-numbered function visible to the OS */ |
| #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0 |
| /* enum: The function can control the link state of the physical port it is |
| * bound to. |
| */ |
| #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1 |
| /* enum: The function can perform privileged operations */ |
| #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2 |
| |
| |
| /***********************************/ |
| /* MC_CMD_SHMUART |
| * Route UART output to circular buffer in shared memory instead. |
| */ |
| #define MC_CMD_SHMUART 0x1f |
| |
| /* MC_CMD_SHMUART_IN msgrequest */ |
| #define MC_CMD_SHMUART_IN_LEN 4 |
| /* ??? */ |
| #define MC_CMD_SHMUART_IN_FLAG_OFST 0 |
| |
| /* MC_CMD_SHMUART_OUT msgresponse */ |
| #define MC_CMD_SHMUART_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_PORT_RESET |
| * Generic per-port reset. There is no equivalent for per-board reset. Locks |
| * required: None; Return code: 0, ETIME. NOTE: This command is deprecated - |
| * use MC_CMD_ENTITY_RESET instead. |
| */ |
| #define MC_CMD_PORT_RESET 0x20 |
| |
| /* MC_CMD_PORT_RESET_IN msgrequest */ |
| #define MC_CMD_PORT_RESET_IN_LEN 0 |
| |
| /* MC_CMD_PORT_RESET_OUT msgresponse */ |
| #define MC_CMD_PORT_RESET_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_ENTITY_RESET |
| * Generic per-resource reset. There is no equivalent for per-board reset. |
| * Locks required: None; Return code: 0, ETIME. NOTE: This command is an |
| * extended version of the deprecated MC_CMD_PORT_RESET with added fields. |
| */ |
| #define MC_CMD_ENTITY_RESET 0x20 |
| |
| /* MC_CMD_ENTITY_RESET_IN msgrequest */ |
| #define MC_CMD_ENTITY_RESET_IN_LEN 4 |
| /* Optional flags field. Omitting this will perform a "legacy" reset action |
| * (TBD). |
| */ |
| #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0 |
| #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0 |
| #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_WIDTH 1 |
| |
| /* MC_CMD_ENTITY_RESET_OUT msgresponse */ |
| #define MC_CMD_ENTITY_RESET_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_PCIE_CREDITS |
| * Read instantaneous and minimum flow control thresholds. |
| */ |
| #define MC_CMD_PCIE_CREDITS 0x21 |
| |
| /* MC_CMD_PCIE_CREDITS_IN msgrequest */ |
| #define MC_CMD_PCIE_CREDITS_IN_LEN 8 |
| /* poll period. 0 is disabled */ |
| #define MC_CMD_PCIE_CREDITS_IN_POLL_PERIOD_OFST 0 |
| /* wipe statistics */ |
| #define MC_CMD_PCIE_CREDITS_IN_WIPE_OFST 4 |
| |
| /* MC_CMD_PCIE_CREDITS_OUT msgresponse */ |
| #define MC_CMD_PCIE_CREDITS_OUT_LEN 16 |
| #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_OFST 0 |
| #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_HDR_LEN 2 |
| #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_OFST 2 |
| #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_P_DATA_LEN 2 |
| #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_OFST 4 |
| #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_HDR_LEN 2 |
| #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_OFST 6 |
| #define MC_CMD_PCIE_CREDITS_OUT_CURRENT_NP_DATA_LEN 2 |
| #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_OFST 8 |
| #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_HDR_LEN 2 |
| #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_OFST 10 |
| #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_P_DATA_LEN 2 |
| #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_OFST 12 |
| #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_HDR_LEN 2 |
| #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_OFST 14 |
| #define MC_CMD_PCIE_CREDITS_OUT_MINIMUM_NP_DATA_LEN 2 |
| |
| |
| /***********************************/ |
| /* MC_CMD_RXD_MONITOR |
| * Get histogram of RX queue fill level. |
| */ |
| #define MC_CMD_RXD_MONITOR 0x22 |
| |
| /* MC_CMD_RXD_MONITOR_IN msgrequest */ |
| #define MC_CMD_RXD_MONITOR_IN_LEN 12 |
| #define MC_CMD_RXD_MONITOR_IN_QID_OFST 0 |
| #define MC_CMD_RXD_MONITOR_IN_POLL_PERIOD_OFST 4 |
| #define MC_CMD_RXD_MONITOR_IN_WIPE_OFST 8 |
| |
| /* MC_CMD_RXD_MONITOR_OUT msgresponse */ |
| #define MC_CMD_RXD_MONITOR_OUT_LEN 80 |
| #define MC_CMD_RXD_MONITOR_OUT_QID_OFST 0 |
| #define MC_CMD_RXD_MONITOR_OUT_RING_FILL_OFST 4 |
| #define MC_CMD_RXD_MONITOR_OUT_CACHE_FILL_OFST 8 |
| #define MC_CMD_RXD_MONITOR_OUT_RING_LT_1_OFST 12 |
| #define MC_CMD_RXD_MONITOR_OUT_RING_LT_2_OFST 16 |
| #define MC_CMD_RXD_MONITOR_OUT_RING_LT_4_OFST 20 |
| #define MC_CMD_RXD_MONITOR_OUT_RING_LT_8_OFST 24 |
| #define MC_CMD_RXD_MONITOR_OUT_RING_LT_16_OFST 28 |
| #define MC_CMD_RXD_MONITOR_OUT_RING_LT_32_OFST 32 |
| #define MC_CMD_RXD_MONITOR_OUT_RING_LT_64_OFST 36 |
| #define MC_CMD_RXD_MONITOR_OUT_RING_LT_128_OFST 40 |
| #define MC_CMD_RXD_MONITOR_OUT_RING_LT_256_OFST 44 |
| #define MC_CMD_RXD_MONITOR_OUT_RING_GE_256_OFST 48 |
| #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_1_OFST 52 |
| #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_2_OFST 56 |
| #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_4_OFST 60 |
| #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_8_OFST 64 |
| #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_16_OFST 68 |
| #define MC_CMD_RXD_MONITOR_OUT_CACHE_LT_32_OFST 72 |
| #define MC_CMD_RXD_MONITOR_OUT_CACHE_GE_32_OFST 76 |
| |
| |
| /***********************************/ |
| /* MC_CMD_PUTS |
| * Copy the given ASCII string out onto UART and/or out of the network port. |
| */ |
| #define MC_CMD_PUTS 0x23 |
| |
| /* MC_CMD_PUTS_IN msgrequest */ |
| #define MC_CMD_PUTS_IN_LENMIN 13 |
| #define MC_CMD_PUTS_IN_LENMAX 252 |
| #define MC_CMD_PUTS_IN_LEN(num) (12+1*(num)) |
| #define MC_CMD_PUTS_IN_DEST_OFST 0 |
| #define MC_CMD_PUTS_IN_UART_LBN 0 |
| #define MC_CMD_PUTS_IN_UART_WIDTH 1 |
| #define MC_CMD_PUTS_IN_PORT_LBN 1 |
| #define MC_CMD_PUTS_IN_PORT_WIDTH 1 |
| #define MC_CMD_PUTS_IN_DHOST_OFST 4 |
| #define MC_CMD_PUTS_IN_DHOST_LEN 6 |
| #define MC_CMD_PUTS_IN_STRING_OFST 12 |
| #define MC_CMD_PUTS_IN_STRING_LEN 1 |
| #define MC_CMD_PUTS_IN_STRING_MINNUM 1 |
| #define MC_CMD_PUTS_IN_STRING_MAXNUM 240 |
| |
| /* MC_CMD_PUTS_OUT msgresponse */ |
| #define MC_CMD_PUTS_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_GET_PHY_CFG |
| * Report PHY configuration. This guarantees to succeed even if the PHY is in a |
| * 'zombie' state. Locks required: None |
| */ |
| #define MC_CMD_GET_PHY_CFG 0x24 |
| |
| /* MC_CMD_GET_PHY_CFG_IN msgrequest */ |
| #define MC_CMD_GET_PHY_CFG_IN_LEN 0 |
| |
| /* MC_CMD_GET_PHY_CFG_OUT msgresponse */ |
| #define MC_CMD_GET_PHY_CFG_OUT_LEN 72 |
| /* flags */ |
| #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 |
| #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0 |
| #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_WIDTH 1 |
| #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_LBN 1 |
| #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_WIDTH 1 |
| #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_LBN 2 |
| #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_WIDTH 1 |
| #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_LBN 3 |
| #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_WIDTH 1 |
| #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4 |
| #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_WIDTH 1 |
| #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_LBN 5 |
| #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_WIDTH 1 |
| #define MC_CMD_GET_PHY_CFG_OUT_BIST_LBN 6 |
| #define MC_CMD_GET_PHY_CFG_OUT_BIST_WIDTH 1 |
| /* ?? */ |
| #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 |
| /* Bitmask of supported capabilities */ |
| #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 |
| #define MC_CMD_PHY_CAP_10HDX_LBN 1 |
| #define MC_CMD_PHY_CAP_10HDX_WIDTH 1 |
| #define MC_CMD_PHY_CAP_10FDX_LBN 2 |
| #define MC_CMD_PHY_CAP_10FDX_WIDTH 1 |
| #define MC_CMD_PHY_CAP_100HDX_LBN 3 |
| #define MC_CMD_PHY_CAP_100HDX_WIDTH 1 |
| #define MC_CMD_PHY_CAP_100FDX_LBN 4 |
| #define MC_CMD_PHY_CAP_100FDX_WIDTH 1 |
| #define MC_CMD_PHY_CAP_1000HDX_LBN 5 |
| #define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 |
| #define MC_CMD_PHY_CAP_1000FDX_LBN 6 |
| #define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 |
| #define MC_CMD_PHY_CAP_10000FDX_LBN 7 |
| #define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 |
| #define MC_CMD_PHY_CAP_PAUSE_LBN 8 |
| #define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 |
| #define MC_CMD_PHY_CAP_ASYM_LBN 9 |
| #define MC_CMD_PHY_CAP_ASYM_WIDTH 1 |
| #define MC_CMD_PHY_CAP_AN_LBN 10 |
| #define MC_CMD_PHY_CAP_AN_WIDTH 1 |
| #define MC_CMD_PHY_CAP_40000FDX_LBN 11 |
| #define MC_CMD_PHY_CAP_40000FDX_WIDTH 1 |
| #define MC_CMD_PHY_CAP_DDM_LBN 12 |
| #define MC_CMD_PHY_CAP_DDM_WIDTH 1 |
| /* ?? */ |
| #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 |
| /* ?? */ |
| #define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 |
| /* ?? */ |
| #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 |
| /* ?? */ |
| #define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 |
| #define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 |
| /* ?? */ |
| #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 |
| /* enum: Xaui. */ |
| #define MC_CMD_MEDIA_XAUI 0x1 |
| /* enum: CX4. */ |
| #define MC_CMD_MEDIA_CX4 0x2 |
| /* enum: KX4. */ |
| #define MC_CMD_MEDIA_KX4 0x3 |
| /* enum: XFP Far. */ |
| #define MC_CMD_MEDIA_XFP 0x4 |
| /* enum: SFP+. */ |
| #define MC_CMD_MEDIA_SFP_PLUS 0x5 |
| /* enum: 10GBaseT. */ |
| #define MC_CMD_MEDIA_BASE_T 0x6 |
| /* enum: QSFP+. */ |
| #define MC_CMD_MEDIA_QSFP_PLUS 0x7 |
| #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 |
| /* enum: Native clause 22 */ |
| #define MC_CMD_MMD_CLAUSE22 0x0 |
| #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */ |
| #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */ |
| #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */ |
| #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */ |
| #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */ |
| #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */ |
| #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */ |
| /* enum: Clause22 proxied over clause45 by PHY. */ |
| #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d |
| #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */ |
| #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */ |
| #define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 |
| #define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 |
| |
| |
| /***********************************/ |
| /* MC_CMD_START_BIST |
| * Start a BIST test on the PHY. Locks required: PHY_LOCK if doing a PHY BIST |
| * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) |
| */ |
| #define MC_CMD_START_BIST 0x25 |
| |
| /* MC_CMD_START_BIST_IN msgrequest */ |
| #define MC_CMD_START_BIST_IN_LEN 4 |
| /* Type of test. */ |
| #define MC_CMD_START_BIST_IN_TYPE_OFST 0 |
| /* enum: Run the PHY's short cable BIST. */ |
| #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1 |
| /* enum: Run the PHY's long cable BIST. */ |
| #define MC_CMD_PHY_BIST_CABLE_LONG 0x2 |
| /* enum: Run BIST on the currently selected BPX Serdes (XAUI or XFI) . */ |
| #define MC_CMD_BPX_SERDES_BIST 0x3 |
| /* enum: Run the MC loopback tests. */ |
| #define MC_CMD_MC_LOOPBACK_BIST 0x4 |
| /* enum: Run the PHY's standard BIST. */ |
| #define MC_CMD_PHY_BIST 0x5 |
| /* enum: Run MC RAM test. */ |
| #define MC_CMD_MC_MEM_BIST 0x6 |
| /* enum: Run Port RAM test. */ |
| #define MC_CMD_PORT_MEM_BIST 0x7 |
| /* enum: Run register test. */ |
| #define MC_CMD_REG_BIST 0x8 |
| |
| /* MC_CMD_START_BIST_OUT msgresponse */ |
| #define MC_CMD_START_BIST_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_POLL_BIST |
| * Poll for BIST completion. Returns a single status code, and optionally some |
| * PHY specific bist output. The driver should only consume the BIST output |
| * after validating OUTLEN and MC_CMD_GET_PHY_CFG.TYPE. If a driver can't |
| * successfully parse the BIST output, it should still respect the pass/Fail in |
| * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0, |
| * EACCES (if PHY_LOCK is not held). |
| */ |
| #define MC_CMD_POLL_BIST 0x26 |
| |
| /* MC_CMD_POLL_BIST_IN msgrequest */ |
| #define MC_CMD_POLL_BIST_IN_LEN 0 |
| |
| /* MC_CMD_POLL_BIST_OUT msgresponse */ |
| #define MC_CMD_POLL_BIST_OUT_LEN 8 |
| /* result */ |
| #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 |
| /* enum: Running. */ |
| #define MC_CMD_POLL_BIST_RUNNING 0x1 |
| /* enum: Passed. */ |
| #define MC_CMD_POLL_BIST_PASSED 0x2 |
| /* enum: Failed. */ |
| #define MC_CMD_POLL_BIST_FAILED 0x3 |
| /* enum: Timed-out. */ |
| #define MC_CMD_POLL_BIST_TIMEOUT 0x4 |
| #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 |
| |
| /* MC_CMD_POLL_BIST_OUT_SFT9001 msgresponse */ |
| #define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 |
| /* result */ |
| /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ |
| /* Enum values, see field(s): */ |
| /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ |
| #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 |
| #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 |
| #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 |
| #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 |
| /* Status of each channel A */ |
| #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 |
| /* enum: Ok. */ |
| #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1 |
| /* enum: Open. */ |
| #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2 |
| /* enum: Intra-pair short. */ |
| #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3 |
| /* enum: Inter-pair short. */ |
| #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4 |
| /* enum: Busy. */ |
| #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9 |
| /* Status of each channel B */ |
| #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 |
| /* Enum values, see field(s): */ |
| /* CABLE_STATUS_A */ |
| /* Status of each channel C */ |
| #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 |
| /* Enum values, see field(s): */ |
| /* CABLE_STATUS_A */ |
| /* Status of each channel D */ |
| #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 |
| /* Enum values, see field(s): */ |
| /* CABLE_STATUS_A */ |
| |
| /* MC_CMD_POLL_BIST_OUT_MRSFP msgresponse */ |
| #define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 |
| /* result */ |
| /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ |
| /* Enum values, see field(s): */ |
| /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ |
| #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 |
| /* enum: Complete. */ |
| #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0 |
| /* enum: Bus switch off I2C write. */ |
| #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1 |
| /* enum: Bus switch off I2C no access IO exp. */ |
| #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2 |
| /* enum: Bus switch off I2C no access module. */ |
| #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3 |
| /* enum: IO exp I2C configure. */ |
| #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4 |
| /* enum: Bus switch I2C no cross talk. */ |
| #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5 |
| /* enum: Module presence. */ |
| #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6 |
| /* enum: Module ID I2C access. */ |
| #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7 |
| /* enum: Module ID sane value. */ |
| #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8 |
| |
| /* MC_CMD_POLL_BIST_OUT_MEM msgresponse */ |
| #define MC_CMD_POLL_BIST_OUT_MEM_LEN 36 |
| /* result */ |
| /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */ |
| /* Enum values, see field(s): */ |
| /* MC_CMD_POLL_BIST_OUT/MC_CMD_POLL_BIST_OUT_RESULT */ |
| #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4 |
| /* enum: Test has completed. */ |
| #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0 |
| /* enum: RAM test - walk ones. */ |
| #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1 |
| /* enum: RAM test - walk zeros. */ |
| #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2 |
| /* enum: RAM test - walking inversions zeros/ones. */ |
| #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3 |
| /* enum: RAM test - walking inversions checkerboard. */ |
| #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4 |
| /* enum: Register test - set / clear individual bits. */ |
| #define MC_CMD_POLL_BIST_MEM_REG 0x5 |
| /* enum: ECC error detected. */ |
| #define MC_CMD_POLL_BIST_MEM_ECC 0x6 |
| /* Failure address, only valid if result is POLL_BIST_FAILED */ |
| #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_OFST 8 |
| /* Bus or address space to which the failure address corresponds */ |
| #define MC_CMD_POLL_BIST_OUT_MEM_BUS_OFST 12 |
| /* enum: MC MIPS bus. */ |
| #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0 |
| /* enum: CSR IREG bus. */ |
| #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1 |
| /* enum: RX DPCPU bus. */ |
| #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2 |
| /* enum: TX0 DPCPU bus. */ |
| #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3 |
| /* enum: TX1 DPCPU bus. */ |
| #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4 |
| /* enum: RX DICPU bus. */ |
| #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5 |
| /* enum: TX DICPU bus. */ |
| #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6 |
| /* Pattern written to RAM / register */ |
| #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_OFST 16 |
| /* Actual value read from RAM / register */ |
| #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_OFST 20 |
| /* ECC error mask */ |
| #define MC_CMD_POLL_BIST_OUT_MEM_ECC_OFST 24 |
| /* ECC parity error mask */ |
| #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_OFST 28 |
| /* ECC fatal error mask */ |
| #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_OFST 32 |
| |
| |
| /***********************************/ |
| /* MC_CMD_FLUSH_RX_QUEUES |
| * Flush receive queue(s). If SRIOV is enabled (via MC_CMD_SRIOV), then RXQ |
| * flushes should be initiated via this MCDI operation, rather than via |
| * directly writing FLUSH_CMD. |
| * |
| * The flush is completed (either done/fail) asynchronously (after this command |
| * returns). The driver must still wait for flush done/failure events as usual. |
| */ |
| #define MC_CMD_FLUSH_RX_QUEUES 0x27 |
| |
| /* MC_CMD_FLUSH_RX_QUEUES_IN msgrequest */ |
| #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMIN 4 |
| #define MC_CMD_FLUSH_RX_QUEUES_IN_LENMAX 252 |
| #define MC_CMD_FLUSH_RX_QUEUES_IN_LEN(num) (0+4*(num)) |
| #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_OFST 0 |
| #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_LEN 4 |
| #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MINNUM 1 |
| #define MC_CMD_FLUSH_RX_QUEUES_IN_QID_OFST_MAXNUM 63 |
| |
| /* MC_CMD_FLUSH_RX_QUEUES_OUT msgresponse */ |
| #define MC_CMD_FLUSH_RX_QUEUES_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_GET_LOOPBACK_MODES |
| * Returns a bitmask of loopback modes available at each speed. |
| */ |
| #define MC_CMD_GET_LOOPBACK_MODES 0x28 |
| |
| /* MC_CMD_GET_LOOPBACK_MODES_IN msgrequest */ |
| #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 |
| |
| /* MC_CMD_GET_LOOPBACK_MODES_OUT msgresponse */ |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 40 |
| /* Supported loopbacks. */ |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LEN 8 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4 |
| /* enum: None. */ |
| #define MC_CMD_LOOPBACK_NONE 0x0 |
| /* enum: Data. */ |
| #define MC_CMD_LOOPBACK_DATA 0x1 |
| /* enum: GMAC. */ |
| #define MC_CMD_LOOPBACK_GMAC 0x2 |
| /* enum: XGMII. */ |
| #define MC_CMD_LOOPBACK_XGMII 0x3 |
| /* enum: XGXS. */ |
| #define MC_CMD_LOOPBACK_XGXS 0x4 |
| /* enum: XAUI. */ |
| #define MC_CMD_LOOPBACK_XAUI 0x5 |
| /* enum: GMII. */ |
| #define MC_CMD_LOOPBACK_GMII 0x6 |
| /* enum: SGMII. */ |
| #define MC_CMD_LOOPBACK_SGMII 0x7 |
| /* enum: XGBR. */ |
| #define MC_CMD_LOOPBACK_XGBR 0x8 |
| /* enum: XFI. */ |
| #define MC_CMD_LOOPBACK_XFI 0x9 |
| /* enum: XAUI Far. */ |
| #define MC_CMD_LOOPBACK_XAUI_FAR 0xa |
| /* enum: GMII Far. */ |
| #define MC_CMD_LOOPBACK_GMII_FAR 0xb |
| /* enum: SGMII Far. */ |
| #define MC_CMD_LOOPBACK_SGMII_FAR 0xc |
| /* enum: XFI Far. */ |
| #define MC_CMD_LOOPBACK_XFI_FAR 0xd |
| /* enum: GPhy. */ |
| #define MC_CMD_LOOPBACK_GPHY 0xe |
| /* enum: PhyXS. */ |
| #define MC_CMD_LOOPBACK_PHYXS 0xf |
| /* enum: PCS. */ |
| #define MC_CMD_LOOPBACK_PCS 0x10 |
| /* enum: PMA-PMD. */ |
| #define MC_CMD_LOOPBACK_PMAPMD 0x11 |
| /* enum: Cross-Port. */ |
| #define MC_CMD_LOOPBACK_XPORT 0x12 |
| /* enum: XGMII-Wireside. */ |
| #define MC_CMD_LOOPBACK_XGMII_WS 0x13 |
| /* enum: XAUI Wireside. */ |
| #define MC_CMD_LOOPBACK_XAUI_WS 0x14 |
| /* enum: XAUI Wireside Far. */ |
| #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 |
| /* enum: XAUI Wireside near. */ |
| #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 |
| /* enum: GMII Wireside. */ |
| #define MC_CMD_LOOPBACK_GMII_WS 0x17 |
| /* enum: XFI Wireside. */ |
| #define MC_CMD_LOOPBACK_XFI_WS 0x18 |
| /* enum: XFI Wireside Far. */ |
| #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 |
| /* enum: PhyXS Wireside. */ |
| #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a |
| /* enum: PMA lanes MAC-Serdes. */ |
| #define MC_CMD_LOOPBACK_PMA_INT 0x1b |
| /* enum: KR Serdes Parallel (Encoder). */ |
| #define MC_CMD_LOOPBACK_SD_NEAR 0x1c |
| /* enum: KR Serdes Serial. */ |
| #define MC_CMD_LOOPBACK_SD_FAR 0x1d |
| /* enum: PMA lanes MAC-Serdes Wireside. */ |
| #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e |
| /* enum: KR Serdes Parallel Wireside (Full PCS). */ |
| #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f |
| /* enum: KR Serdes Parallel Wireside (Sym Aligner to TX). */ |
| #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 |
| /* enum: KR Serdes Parallel Wireside (Deserializer to Serializer). */ |
| #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21 |
| /* enum: KR Serdes Serial Wireside. */ |
| #define MC_CMD_LOOPBACK_SD_FES_WS 0x22 |
| /* enum: Near side of AOE Siena side port */ |
| #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 |
| /* Supported loopbacks. */ |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_OFST 8 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LEN 8 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_OFST 8 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_OFST 12 |
| /* Enum values, see field(s): */ |
| /* 100M */ |
| /* Supported loopbacks. */ |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_OFST 16 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LEN 8 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_OFST 16 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_OFST 20 |
| /* Enum values, see field(s): */ |
| /* 100M */ |
| /* Supported loopbacks. */ |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_OFST 24 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LEN 8 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_OFST 24 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_OFST 28 |
| /* Enum values, see field(s): */ |
| /* 100M */ |
| /* Supported loopbacks. */ |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_OFST 32 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LEN 8 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_OFST 32 |
| #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_OFST 36 |
| /* Enum values, see field(s): */ |
| /* 100M */ |
| |
| |
| /***********************************/ |
| /* MC_CMD_GET_LINK |
| * Read the unified MAC/PHY link state. Locks required: None Return code: 0, |
| * ETIME. |
| */ |
| #define MC_CMD_GET_LINK 0x29 |
| |
| /* MC_CMD_GET_LINK_IN msgrequest */ |
| #define MC_CMD_GET_LINK_IN_LEN 0 |
| |
| /* MC_CMD_GET_LINK_OUT msgresponse */ |
| #define MC_CMD_GET_LINK_OUT_LEN 28 |
| /* near-side advertised capabilities */ |
| #define MC_CMD_GET_LINK_OUT_CAP_OFST 0 |
| /* link-partner advertised capabilities */ |
| #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 |
| /* Autonegotiated speed in mbit/s. The link may still be down even if this |
| * reads non-zero. |
| */ |
| #define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 |
| /* Current loopback setting. */ |
| #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 |
| /* Enum values, see field(s): */ |
| /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ |
| #define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 |
| #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0 |
| #define MC_CMD_GET_LINK_OUT_LINK_UP_WIDTH 1 |
| #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_LBN 1 |
| #define MC_CMD_GET_LINK_OUT_FULL_DUPLEX_WIDTH 1 |
| #define MC_CMD_GET_LINK_OUT_BPX_LINK_LBN 2 |
| #define MC_CMD_GET_LINK_OUT_BPX_LINK_WIDTH 1 |
| #define MC_CMD_GET_LINK_OUT_PHY_LINK_LBN 3 |
| #define MC_CMD_GET_LINK_OUT_PHY_LINK_WIDTH 1 |
| #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_LBN 6 |
| #define MC_CMD_GET_LINK_OUT_LINK_FAULT_RX_WIDTH 1 |
| #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_LBN 7 |
| #define MC_CMD_GET_LINK_OUT_LINK_FAULT_TX_WIDTH 1 |
| /* This returns the negotiated flow control value. */ |
| #define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 |
| /* enum: Flow control is off. */ |
| #define MC_CMD_FCNTL_OFF 0x0 |
| /* enum: Respond to flow control. */ |
| #define MC_CMD_FCNTL_RESPOND 0x1 |
| /* enum: Respond to and Issue flow control. */ |
| #define MC_CMD_FCNTL_BIDIR 0x2 |
| #define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 |
| #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 |
| #define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 |
| #define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 |
| #define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 |
| #define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 |
| #define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 |
| #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_LBN 3 |
| #define MC_CMD_MAC_FAULT_PENDING_RECONFIG_WIDTH 1 |
| |
| |
| /***********************************/ |
| /* MC_CMD_SET_LINK |
| * Write the unified MAC/PHY link configuration. Locks required: None. Return |
| * code: 0, EINVAL, ETIME |
| */ |
| #define MC_CMD_SET_LINK 0x2a |
| |
| /* MC_CMD_SET_LINK_IN msgrequest */ |
| #define MC_CMD_SET_LINK_IN_LEN 16 |
| /* ??? */ |
| #define MC_CMD_SET_LINK_IN_CAP_OFST 0 |
| /* Flags */ |
| #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 |
| #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0 |
| #define MC_CMD_SET_LINK_IN_LOWPOWER_WIDTH 1 |
| #define MC_CMD_SET_LINK_IN_POWEROFF_LBN 1 |
| #define MC_CMD_SET_LINK_IN_POWEROFF_WIDTH 1 |
| #define MC_CMD_SET_LINK_IN_TXDIS_LBN 2 |
| #define MC_CMD_SET_LINK_IN_TXDIS_WIDTH 1 |
| /* Loopback mode. */ |
| #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 |
| /* Enum values, see field(s): */ |
| /* MC_CMD_GET_LOOPBACK_MODES/MC_CMD_GET_LOOPBACK_MODES_OUT/100M */ |
| /* A loopback speed of "0" is supported, and means (choose any available |
| * speed). |
| */ |
| #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 |
| |
| /* MC_CMD_SET_LINK_OUT msgresponse */ |
| #define MC_CMD_SET_LINK_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_SET_ID_LED |
| * Set identification LED state. Locks required: None. Return code: 0, EINVAL |
| */ |
| #define MC_CMD_SET_ID_LED 0x2b |
| |
| /* MC_CMD_SET_ID_LED_IN msgrequest */ |
| #define MC_CMD_SET_ID_LED_IN_LEN 4 |
| /* Set LED state. */ |
| #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 |
| #define MC_CMD_LED_OFF 0x0 /* enum */ |
| #define MC_CMD_LED_ON 0x1 /* enum */ |
| #define MC_CMD_LED_DEFAULT 0x2 /* enum */ |
| |
| /* MC_CMD_SET_ID_LED_OUT msgresponse */ |
| #define MC_CMD_SET_ID_LED_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_SET_MAC |
| * Set MAC configuration. Locks required: None. Return code: 0, EINVAL |
| */ |
| #define MC_CMD_SET_MAC 0x2c |
| |
| /* MC_CMD_SET_MAC_IN msgrequest */ |
| #define MC_CMD_SET_MAC_IN_LEN 24 |
| /* The MTU is the MTU programmed directly into the XMAC/GMAC (inclusive of |
| * EtherII, VLAN, bug16011 padding). |
| */ |
| #define MC_CMD_SET_MAC_IN_MTU_OFST 0 |
| #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 |
| #define MC_CMD_SET_MAC_IN_ADDR_OFST 8 |
| #define MC_CMD_SET_MAC_IN_ADDR_LEN 8 |
| #define MC_CMD_SET_MAC_IN_ADDR_LO_OFST 8 |
| #define MC_CMD_SET_MAC_IN_ADDR_HI_OFST 12 |
| #define MC_CMD_SET_MAC_IN_REJECT_OFST 16 |
| #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 |
| #define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 |
| #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 |
| #define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 |
| #define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 |
| /* enum: Flow control is off. */ |
| /* MC_CMD_FCNTL_OFF 0x0 */ |
| /* enum: Respond to flow control. */ |
| /* MC_CMD_FCNTL_RESPOND 0x1 */ |
| /* enum: Respond to and Issue flow control. */ |
| /* MC_CMD_FCNTL_BIDIR 0x2 */ |
| /* enum: Auto neg flow control. */ |
| #define MC_CMD_FCNTL_AUTO 0x3 |
| |
| /* MC_CMD_SET_MAC_OUT msgresponse */ |
| #define MC_CMD_SET_MAC_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_PHY_STATS |
| * Get generic PHY statistics. This call returns the statistics for a generic |
| * PHY in a sparse array (indexed by the enumerate). Each value is represented |
| * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the |
| * statistics may be read from the message response. If DMA_ADDR != 0, then the |
| * statistics are dmad to that (page-aligned location). Locks required: None. |
| * Returns: 0, ETIME |
| */ |
| #define MC_CMD_PHY_STATS 0x2d |
| |
| /* MC_CMD_PHY_STATS_IN msgrequest */ |
| #define MC_CMD_PHY_STATS_IN_LEN 8 |
| /* ??? */ |
| #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0 |
| #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LEN 8 |
| #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 |
| #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 |
| |
| /* MC_CMD_PHY_STATS_OUT_DMA msgresponse */ |
| #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 |
| |
| /* MC_CMD_PHY_STATS_OUT_NO_DMA msgresponse */ |
| #define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (((MC_CMD_PHY_NSTATS*32))>>3) |
| #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0 |
| #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4 |
| #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_PHY_NSTATS |
| /* enum: OUI. */ |
| #define MC_CMD_OUI 0x0 |
| /* enum: PMA-PMD Link Up. */ |
| #define MC_CMD_PMA_PMD_LINK_UP 0x1 |
| /* enum: PMA-PMD RX Fault. */ |
| #define MC_CMD_PMA_PMD_RX_FAULT 0x2 |
| /* enum: PMA-PMD TX Fault. */ |
| #define MC_CMD_PMA_PMD_TX_FAULT 0x3 |
| /* enum: PMA-PMD Signal */ |
| #define MC_CMD_PMA_PMD_SIGNAL 0x4 |
| /* enum: PMA-PMD SNR A. */ |
| #define MC_CMD_PMA_PMD_SNR_A 0x5 |
| /* enum: PMA-PMD SNR B. */ |
| #define MC_CMD_PMA_PMD_SNR_B 0x6 |
| /* enum: PMA-PMD SNR C. */ |
| #define MC_CMD_PMA_PMD_SNR_C 0x7 |
| /* enum: PMA-PMD SNR D. */ |
| #define MC_CMD_PMA_PMD_SNR_D 0x8 |
| /* enum: PCS Link Up. */ |
| #define MC_CMD_PCS_LINK_UP 0x9 |
| /* enum: PCS RX Fault. */ |
| #define MC_CMD_PCS_RX_FAULT 0xa |
| /* enum: PCS TX Fault. */ |
| #define MC_CMD_PCS_TX_FAULT 0xb |
| /* enum: PCS BER. */ |
| #define MC_CMD_PCS_BER 0xc |
| /* enum: PCS Block Errors. */ |
| #define MC_CMD_PCS_BLOCK_ERRORS 0xd |
| /* enum: PhyXS Link Up. */ |
| #define MC_CMD_PHYXS_LINK_UP 0xe |
| /* enum: PhyXS RX Fault. */ |
| #define MC_CMD_PHYXS_RX_FAULT 0xf |
| /* enum: PhyXS TX Fault. */ |
| #define MC_CMD_PHYXS_TX_FAULT 0x10 |
| /* enum: PhyXS Align. */ |
| #define MC_CMD_PHYXS_ALIGN 0x11 |
| /* enum: PhyXS Sync. */ |
| #define MC_CMD_PHYXS_SYNC 0x12 |
| /* enum: AN link-up. */ |
| #define MC_CMD_AN_LINK_UP 0x13 |
| /* enum: AN Complete. */ |
| #define MC_CMD_AN_COMPLETE 0x14 |
| /* enum: AN 10GBaseT Status. */ |
| #define MC_CMD_AN_10GBT_STATUS 0x15 |
| /* enum: Clause 22 Link-Up. */ |
| #define MC_CMD_CL22_LINK_UP 0x16 |
| /* enum: (Last entry) */ |
| #define MC_CMD_PHY_NSTATS 0x17 |
| |
| |
| /***********************************/ |
| /* MC_CMD_MAC_STATS |
| * Get generic MAC statistics. This call returns unified statistics maintained |
| * by the MC as it switches between the GMAC and XMAC. The MC will write out |
| * all supported stats. The driver should zero initialise the buffer to |
| * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is |
| * performed, and the statistics may be read from the message response. If |
| * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location). |
| * Locks required: None. Returns: 0, ETIME |
| */ |
| #define MC_CMD_MAC_STATS 0x2e |
| |
| /* MC_CMD_MAC_STATS_IN msgrequest */ |
| #define MC_CMD_MAC_STATS_IN_LEN 16 |
| /* ??? */ |
| #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0 |
| #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LEN 8 |
| #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 |
| #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 |
| #define MC_CMD_MAC_STATS_IN_CMD_OFST 8 |
| #define MC_CMD_MAC_STATS_IN_DMA_LBN 0 |
| #define MC_CMD_MAC_STATS_IN_DMA_WIDTH 1 |
| #define MC_CMD_MAC_STATS_IN_CLEAR_LBN 1 |
| #define MC_CMD_MAC_STATS_IN_CLEAR_WIDTH 1 |
| #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_LBN 2 |
| #define MC_CMD_MAC_STATS_IN_PERIODIC_CHANGE_WIDTH 1 |
| #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_LBN 3 |
| #define MC_CMD_MAC_STATS_IN_PERIODIC_ENABLE_WIDTH 1 |
| #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4 |
| #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_WIDTH 1 |
| #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_LBN 5 |
| #define MC_CMD_MAC_STATS_IN_PERIODIC_NOEVENT_WIDTH 1 |
| #define MC_CMD_MAC_STATS_IN_PERIOD_MS_LBN 16 |
| #define MC_CMD_MAC_STATS_IN_PERIOD_MS_WIDTH 16 |
| #define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 |
| |
| /* MC_CMD_MAC_STATS_OUT_DMA msgresponse */ |
| #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0 |
| |
| /* MC_CMD_MAC_STATS_OUT_NO_DMA msgresponse */ |
| #define MC_CMD_MAC_STATS_OUT_NO_DMA_LEN (((MC_CMD_MAC_NSTATS*64))>>3) |
| #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0 |
| #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LEN 8 |
| #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0 |
| #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4 |
| #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_NUM MC_CMD_MAC_NSTATS |
| #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */ |
| #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */ |
| #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */ |
| #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */ |
| #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */ |
| #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */ |
| #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */ |
| #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */ |
| #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */ |
| #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */ |
| #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */ |
| #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */ |
| #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */ |
| #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */ |
| #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */ |
| #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */ |
| #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */ |
| #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */ |
| #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */ |
| #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */ |
| #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */ |
| #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */ |
| #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */ |
| #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */ |
| #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */ |
| #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */ |
| #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */ |
| #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */ |
| #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */ |
| #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */ |
| #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */ |
| #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */ |
| #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */ |
| #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */ |
| #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */ |
| #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */ |
| #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */ |
| #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */ |
| #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */ |
| #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */ |
| #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */ |
| #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */ |
| #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */ |
| #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */ |
| #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */ |
| #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */ |
| #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */ |
| #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */ |
| #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */ |
| #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */ |
| #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */ |
| #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */ |
| #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */ |
| #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */ |
| #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */ |
| #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */ |
| #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */ |
| #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */ |
| #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */ |
| #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */ |
| /* enum: PM trunc_bb_overflow counter. Valid for EF10 with PM_AND_RXDP_COUNTERS |
| * capability only. |
| */ |
| #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c |
| /* enum: PM discard_bb_overflow counter. Valid for EF10 with |
| * PM_AND_RXDP_COUNTERS capability only. |
| */ |
| #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d |
| /* enum: PM trunc_vfifo_full counter. Valid for EF10 with PM_AND_RXDP_COUNTERS |
| * capability only. |
| */ |
| #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e |
| /* enum: PM discard_vfifo_full counter. Valid for EF10 with |
| * PM_AND_RXDP_COUNTERS capability only. |
| */ |
| #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f |
| /* enum: PM trunc_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS |
| * capability only. |
| */ |
| #define MC_CMD_MAC_PM_TRUNC_QBB 0x40 |
| /* enum: PM discard_qbb counter. Valid for EF10 with PM_AND_RXDP_COUNTERS |
| * capability only. |
| */ |
| #define MC_CMD_MAC_PM_DISCARD_QBB 0x41 |
| /* enum: PM discard_mapping counter. Valid for EF10 with PM_AND_RXDP_COUNTERS |
| * capability only. |
| */ |
| #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42 |
| /* enum: RXDP counter: Number of packets dropped due to the queue being |
| * disabled. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. |
| */ |
| #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43 |
| /* enum: RXDP counter: Number of packets dropped by the DICPU. Valid for EF10 |
| * with PM_AND_RXDP_COUNTERS capability only. |
| */ |
| #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45 |
| /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with |
| * PM_AND_RXDP_COUNTERS capability only. |
| */ |
| #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46 |
| /* enum: RXDP counter: Number of times an emergency descriptor fetch was |
| * performed. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. |
| */ |
| #define MC_CMD_MAC_RXDP_EMERGENCY_FETCH_CONDITIONS 0x47 |
| /* enum: RXDP counter: Number of times the DPCPU waited for an existing |
| * descriptor fetch. Valid for EF10 with PM_AND_RXDP_COUNTERS capability only. |
| */ |
| #define MC_CMD_MAC_RXDP_EMERGENCY_WAIT_CONDITIONS 0x48 |
| /* enum: Start of GMAC stats buffer space, for Siena only. */ |
| #define MC_CMD_GMAC_DMABUF_START 0x40 |
| /* enum: End of GMAC stats buffer space, for Siena only. */ |
| #define MC_CMD_GMAC_DMABUF_END 0x5f |
| #define MC_CMD_MAC_GENERATION_END 0x60 /* enum */ |
| #define MC_CMD_MAC_NSTATS 0x61 /* enum */ |
| |
| |
| /***********************************/ |
| /* MC_CMD_SRIOV |
| * to be documented |
| */ |
| #define MC_CMD_SRIOV 0x30 |
| |
| /* MC_CMD_SRIOV_IN msgrequest */ |
| #define MC_CMD_SRIOV_IN_LEN 12 |
| #define MC_CMD_SRIOV_IN_ENABLE_OFST 0 |
| #define MC_CMD_SRIOV_IN_VI_BASE_OFST 4 |
| #define MC_CMD_SRIOV_IN_VF_COUNT_OFST 8 |
| |
| /* MC_CMD_SRIOV_OUT msgresponse */ |
| #define MC_CMD_SRIOV_OUT_LEN 8 |
| #define MC_CMD_SRIOV_OUT_VI_SCALE_OFST 0 |
| #define MC_CMD_SRIOV_OUT_VF_TOTAL_OFST 4 |
| |
| /* MC_CMD_MEMCPY_RECORD_TYPEDEF structuredef */ |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LEN 32 |
| /* this is only used for the first record */ |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_OFST 0 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_LBN 0 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_NUM_RECORDS_WIDTH 32 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_OFST 4 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_LBN 32 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_RID_WIDTH 32 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_OFST 8 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LEN 8 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LO_OFST 8 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_HI_OFST 12 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_LBN 64 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_TO_ADDR_WIDTH 64 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_OFST 16 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_RID_INLINE 0x100 /* enum */ |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_LBN 128 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_RID_WIDTH 32 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_OFST 20 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LEN 8 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LO_OFST 20 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_HI_OFST 24 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_LBN 160 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_FROM_ADDR_WIDTH 64 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_OFST 28 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_LBN 224 |
| #define MC_CMD_MEMCPY_RECORD_TYPEDEF_LENGTH_WIDTH 32 |
| |
| |
| /***********************************/ |
| /* MC_CMD_MEMCPY |
| * DMA write data into (Rid,Addr), either by dma reading (Rid,Addr), or by data |
| * embedded directly in the command. |
| * |
| * A common pattern is for a client to use generation counts to signal a dma |
| * update of a datastructure. To facilitate this, this MCDI operation can |
| * contain multiple requests which are executed in strict order. Requests take |
| * the form of duplicating the entire MCDI request continuously (including the |
| * requests record, which is ignored in all but the first structure) |
| * |
| * The source data can either come from a DMA from the host, or it can be |
| * embedded within the request directly, thereby eliminating a DMA read. To |
| * indicate this, the client sets FROM_RID=%RID_INLINE, ADDR_HI=0, and |
| * ADDR_LO=offset, and inserts the data at %offset from the start of the |
| * payload. It's the callers responsibility to ensure that the embedded data |
| * doesn't overlap the records. |
| * |
| * Returns: 0, EINVAL (invalid RID) |
| */ |
| #define MC_CMD_MEMCPY 0x31 |
| |
| /* MC_CMD_MEMCPY_IN msgrequest */ |
| #define MC_CMD_MEMCPY_IN_LENMIN 32 |
| #define MC_CMD_MEMCPY_IN_LENMAX 224 |
| #define MC_CMD_MEMCPY_IN_LEN(num) (0+32*(num)) |
| /* see MC_CMD_MEMCPY_RECORD_TYPEDEF */ |
| #define MC_CMD_MEMCPY_IN_RECORD_OFST 0 |
| #define MC_CMD_MEMCPY_IN_RECORD_LEN 32 |
| #define MC_CMD_MEMCPY_IN_RECORD_MINNUM 1 |
| #define MC_CMD_MEMCPY_IN_RECORD_MAXNUM 7 |
| |
| /* MC_CMD_MEMCPY_OUT msgresponse */ |
| #define MC_CMD_MEMCPY_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_WOL_FILTER_SET |
| * Set a WoL filter. |
| */ |
| #define MC_CMD_WOL_FILTER_SET 0x32 |
| |
| /* MC_CMD_WOL_FILTER_SET_IN msgrequest */ |
| #define MC_CMD_WOL_FILTER_SET_IN_LEN 192 |
| #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 |
| #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */ |
| #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */ |
| /* A type value of 1 is unused. */ |
| #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 |
| /* enum: Magic */ |
| #define MC_CMD_WOL_TYPE_MAGIC 0x0 |
| /* enum: MS Windows Magic */ |
| #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 |
| /* enum: IPv4 Syn */ |
| #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 |
| /* enum: IPv6 Syn */ |
| #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 |
| /* enum: Bitmap */ |
| #define MC_CMD_WOL_TYPE_BITMAP 0x5 |
| /* enum: Link */ |
| #define MC_CMD_WOL_TYPE_LINK 0x6 |
| /* enum: (Above this for future use) */ |
| #define MC_CMD_WOL_TYPE_MAX 0x7 |
| #define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 |
| #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4 |
| #define MC_CMD_WOL_FILTER_SET_IN_DATA_NUM 46 |
| |
| /* MC_CMD_WOL_FILTER_SET_IN_MAGIC msgrequest */ |
| #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_LEN 16 |
| /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ |
| /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ |
| #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST 8 |
| #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LEN 8 |
| #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_OFST 8 |
| #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_OFST 12 |
| |
| /* MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN msgrequest */ |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_LEN 20 |
| /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ |
| /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST 8 |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST 12 |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST 16 |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_LEN 2 |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST 18 |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_LEN 2 |
| |
| /* MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN msgrequest */ |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_LEN 44 |
| /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ |
| /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST 8 |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_LEN 16 |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST 24 |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_LEN 16 |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST 40 |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_LEN 2 |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST 42 |
| #define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_LEN 2 |
| |
| /* MC_CMD_WOL_FILTER_SET_IN_BITMAP msgrequest */ |
| #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN 187 |
| /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ |
| /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ |
| #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST 8 |
| #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_LEN 48 |
| #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_OFST 56 |
| #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_BITMAP_LEN 128 |
| #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST 184 |
| #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_LEN 1 |
| #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST 185 |
| #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_LEN 1 |
| #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST 186 |
| #define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_LEN 1 |
| |
| /* MC_CMD_WOL_FILTER_SET_IN_LINK msgrequest */ |
| #define MC_CMD_WOL_FILTER_SET_IN_LINK_LEN 12 |
| /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */ |
| /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */ |
| #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST 8 |
| #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 |
| #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 |
| #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 |
| #define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 |
| |
| /* MC_CMD_WOL_FILTER_SET_OUT msgresponse */ |
| #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 |
| #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_WOL_FILTER_REMOVE |
| * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS |
| */ |
| #define MC_CMD_WOL_FILTER_REMOVE 0x33 |
| |
| /* MC_CMD_WOL_FILTER_REMOVE_IN msgrequest */ |
| #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 |
| #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 |
| |
| /* MC_CMD_WOL_FILTER_REMOVE_OUT msgresponse */ |
| #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_WOL_FILTER_RESET |
| * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0, |
| * ENOSYS |
| */ |
| #define MC_CMD_WOL_FILTER_RESET 0x34 |
| |
| /* MC_CMD_WOL_FILTER_RESET_IN msgrequest */ |
| #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4 |
| #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0 |
| #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */ |
| #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */ |
| |
| /* MC_CMD_WOL_FILTER_RESET_OUT msgresponse */ |
| #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_SET_MCAST_HASH |
| * Set the MCAST hash value without otherwise reconfiguring the MAC |
| */ |
| #define MC_CMD_SET_MCAST_HASH 0x35 |
| |
| /* MC_CMD_SET_MCAST_HASH_IN msgrequest */ |
| #define MC_CMD_SET_MCAST_HASH_IN_LEN 32 |
| #define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 |
| #define MC_CMD_SET_MCAST_HASH_IN_HASH0_LEN 16 |
| #define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 |
| #define MC_CMD_SET_MCAST_HASH_IN_HASH1_LEN 16 |
| |
| /* MC_CMD_SET_MCAST_HASH_OUT msgresponse */ |
| #define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_NVRAM_TYPES |
| * Return bitfield indicating available types of virtual NVRAM partitions. |
| * Locks required: none. Returns: 0 |
| */ |
| #define MC_CMD_NVRAM_TYPES 0x36 |
| |
| /* MC_CMD_NVRAM_TYPES_IN msgrequest */ |
| #define MC_CMD_NVRAM_TYPES_IN_LEN 0 |
| |
| /* MC_CMD_NVRAM_TYPES_OUT msgresponse */ |
| #define MC_CMD_NVRAM_TYPES_OUT_LEN 4 |
| /* Bit mask of supported types. */ |
| #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 |
| /* enum: Disabled callisto. */ |
| #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0 |
| /* enum: MC firmware. */ |
| #define MC_CMD_NVRAM_TYPE_MC_FW 0x1 |
| /* enum: MC backup firmware. */ |
| #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2 |
| /* enum: Static configuration Port0. */ |
| #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3 |
| /* enum: Static configuration Port1. */ |
| #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4 |
| /* enum: Dynamic configuration Port0. */ |
| #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5 |
| /* enum: Dynamic configuration Port1. */ |
| #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6 |
| /* enum: Expansion Rom. */ |
| #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7 |
| /* enum: Expansion Rom Configuration Port0. */ |
| #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8 |
| /* enum: Expansion Rom Configuration Port1. */ |
| #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9 |
| /* enum: Phy Configuration Port0. */ |
| #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa |
| /* enum: Phy Configuration Port1. */ |
| #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb |
| /* enum: Log. */ |
| #define MC_CMD_NVRAM_TYPE_LOG 0xc |
| /* enum: FPGA image. */ |
| #define MC_CMD_NVRAM_TYPE_FPGA 0xd |
| /* enum: FPGA backup image */ |
| #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe |
| /* enum: FC firmware. */ |
| #define MC_CMD_NVRAM_TYPE_FC_FW 0xf |
| /* enum: FC backup firmware. */ |
| #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10 |
| /* enum: CPLD image. */ |
| #define MC_CMD_NVRAM_TYPE_CPLD 0x11 |
| /* enum: Licensing information. */ |
| #define MC_CMD_NVRAM_TYPE_LICENSE 0x12 |
| /* enum: FC Log. */ |
| #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13 |
| |
| |
| /***********************************/ |
| /* MC_CMD_NVRAM_INFO |
| * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0, |
| * EINVAL (bad type). |
| */ |
| #define MC_CMD_NVRAM_INFO 0x37 |
| |
| /* MC_CMD_NVRAM_INFO_IN msgrequest */ |
| #define MC_CMD_NVRAM_INFO_IN_LEN 4 |
| #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 |
| /* Enum values, see field(s): */ |
| /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ |
| |
| /* MC_CMD_NVRAM_INFO_OUT msgresponse */ |
| #define MC_CMD_NVRAM_INFO_OUT_LEN 24 |
| #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 |
| /* Enum values, see field(s): */ |
| /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ |
| #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 |
| #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 |
| #define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 |
| #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0 |
| #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_WIDTH 1 |
| #define MC_CMD_NVRAM_INFO_OUT_TLV_LBN 1 |
| #define MC_CMD_NVRAM_INFO_OUT_TLV_WIDTH 1 |
| #define MC_CMD_NVRAM_INFO_OUT_A_B_LBN 7 |
| #define MC_CMD_NVRAM_INFO_OUT_A_B_WIDTH 1 |
| #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 |
| #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 |
| |
| |
| /***********************************/ |
| /* MC_CMD_NVRAM_UPDATE_START |
| * Start a group of update operations on a virtual NVRAM partition. Locks |
| * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if |
| * PHY_LOCK required and not held). |
| */ |
| #define MC_CMD_NVRAM_UPDATE_START 0x38 |
| |
| /* MC_CMD_NVRAM_UPDATE_START_IN msgrequest */ |
| #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 |
| #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 |
| /* Enum values, see field(s): */ |
| /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ |
| |
| /* MC_CMD_NVRAM_UPDATE_START_OUT msgresponse */ |
| #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_NVRAM_READ |
| * Read data from a virtual NVRAM partition. Locks required: PHY_LOCK if |
| * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if |
| * PHY_LOCK required and not held) |
| */ |
| #define MC_CMD_NVRAM_READ 0x39 |
| |
| /* MC_CMD_NVRAM_READ_IN msgrequest */ |
| #define MC_CMD_NVRAM_READ_IN_LEN 12 |
| #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 |
| /* Enum values, see field(s): */ |
| /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ |
| #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 |
| /* amount to read in bytes */ |
| #define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 |
| |
| /* MC_CMD_NVRAM_READ_OUT msgresponse */ |
| #define MC_CMD_NVRAM_READ_OUT_LENMIN 1 |
| #define MC_CMD_NVRAM_READ_OUT_LENMAX 252 |
| #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num)) |
| #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 |
| #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_LEN 1 |
| #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MINNUM 1 |
| #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_MAXNUM 252 |
| |
| |
| /***********************************/ |
| /* MC_CMD_NVRAM_WRITE |
| * Write data to a virtual NVRAM partition. Locks required: PHY_LOCK if |
| * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if |
| * PHY_LOCK required and not held) |
| */ |
| #define MC_CMD_NVRAM_WRITE 0x3a |
| |
| /* MC_CMD_NVRAM_WRITE_IN msgrequest */ |
| #define MC_CMD_NVRAM_WRITE_IN_LENMIN 13 |
| #define MC_CMD_NVRAM_WRITE_IN_LENMAX 252 |
| #define MC_CMD_NVRAM_WRITE_IN_LEN(num) (12+1*(num)) |
| #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 |
| /* Enum values, see field(s): */ |
| /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ |
| #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 |
| #define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 |
| #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 |
| #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_LEN 1 |
| #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MINNUM 1 |
| #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_MAXNUM 240 |
| |
| /* MC_CMD_NVRAM_WRITE_OUT msgresponse */ |
| #define MC_CMD_NVRAM_WRITE_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_NVRAM_ERASE |
| * Erase sector(s) from a virtual NVRAM partition. Locks required: PHY_LOCK if |
| * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if |
| * PHY_LOCK required and not held) |
| */ |
| #define MC_CMD_NVRAM_ERASE 0x3b |
| |
| /* MC_CMD_NVRAM_ERASE_IN msgrequest */ |
| #define MC_CMD_NVRAM_ERASE_IN_LEN 12 |
| #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 |
| /* Enum values, see field(s): */ |
| /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ |
| #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 |
| #define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 |
| |
| /* MC_CMD_NVRAM_ERASE_OUT msgresponse */ |
| #define MC_CMD_NVRAM_ERASE_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_NVRAM_UPDATE_FINISH |
| * Finish a group of update operations on a virtual NVRAM partition. Locks |
| * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad |
| * type/offset/length), EACCES (if PHY_LOCK required and not held) |
| */ |
| #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c |
| |
| /* MC_CMD_NVRAM_UPDATE_FINISH_IN msgrequest */ |
| #define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 |
| #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 |
| /* Enum values, see field(s): */ |
| /* MC_CMD_NVRAM_TYPES/MC_CMD_NVRAM_TYPES_OUT/TYPES */ |
| #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 |
| |
| /* MC_CMD_NVRAM_UPDATE_FINISH_OUT msgresponse */ |
| #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_REBOOT |
| * Reboot the MC. |
| * |
| * The AFTER_ASSERTION flag is intended to be used when the driver notices an |
| * assertion failure (at which point it is expected to perform a complete tear |
| * down and reinitialise), to allow both ports to reset the MC once in an |
| * atomic fashion. |
| * |
| * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, |
| * which means that they will automatically reboot out of the assertion |
| * handler, so this is in practise an optional operation. It is still |
| * recommended that drivers execute this to support custom firmwares with |
| * REBOOT_ON_ASSERT=0. |
| * |
| * Locks required: NONE Returns: Nothing. You get back a response with ERR=1, |
| * DATALEN=0 |
| */ |
| #define MC_CMD_REBOOT 0x3d |
| |
| /* MC_CMD_REBOOT_IN msgrequest */ |
| #define MC_CMD_REBOOT_IN_LEN 4 |
| #define MC_CMD_REBOOT_IN_FLAGS_OFST 0 |
| #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */ |
| |
| /* MC_CMD_REBOOT_OUT msgresponse */ |
| #define MC_CMD_REBOOT_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_SCHEDINFO |
| * Request scheduler info. Locks required: NONE. Returns: An array of |
| * (timeslice,maximum overrun), one for each thread, in ascending order of |
| * thread address. |
| */ |
| #define MC_CMD_SCHEDINFO 0x3e |
| |
| /* MC_CMD_SCHEDINFO_IN msgrequest */ |
| #define MC_CMD_SCHEDINFO_IN_LEN 0 |
| |
| /* MC_CMD_SCHEDINFO_OUT msgresponse */ |
| #define MC_CMD_SCHEDINFO_OUT_LENMIN 4 |
| #define MC_CMD_SCHEDINFO_OUT_LENMAX 252 |
| #define MC_CMD_SCHEDINFO_OUT_LEN(num) (0+4*(num)) |
| #define MC_CMD_SCHEDINFO_OUT_DATA_OFST 0 |
| #define MC_CMD_SCHEDINFO_OUT_DATA_LEN 4 |
| #define MC_CMD_SCHEDINFO_OUT_DATA_MINNUM 1 |
| #define MC_CMD_SCHEDINFO_OUT_DATA_MAXNUM 63 |
| |
| |
| /***********************************/ |
| /* MC_CMD_REBOOT_MODE |
| * Set the mode for the next MC reboot. Locks required: NONE. Sets the reboot |
| * mode to the specified value. Returns the old mode. |
| */ |
| #define MC_CMD_REBOOT_MODE 0x3f |
| |
| /* MC_CMD_REBOOT_MODE_IN msgrequest */ |
| #define MC_CMD_REBOOT_MODE_IN_LEN 4 |
| #define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 |
| /* enum: Normal. */ |
| #define MC_CMD_REBOOT_MODE_NORMAL 0x0 |
| /* enum: Power-on Reset. */ |
| #define MC_CMD_REBOOT_MODE_POR 0x2 |
| /* enum: Snapper. */ |
| #define MC_CMD_REBOOT_MODE_SNAPPER 0x3 |
| /* enum: snapper fake POR */ |
| #define MC_CMD_REBOOT_MODE_SNAPPER_POR 0x4 |
| #define MC_CMD_REBOOT_MODE_IN_FAKE_LBN 7 |
| #define MC_CMD_REBOOT_MODE_IN_FAKE_WIDTH 1 |
| |
| /* MC_CMD_REBOOT_MODE_OUT msgresponse */ |
| #define MC_CMD_REBOOT_MODE_OUT_LEN 4 |
| #define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_SENSOR_INFO |
| * Returns information about every available sensor. |
| * |
| * Each sensor has a single (16bit) value, and a corresponding state. The |
| * mapping between value and state is nominally determined by the MC, but may |
| * be implemented using up to 2 ranges per sensor. |
| * |
| * This call returns a mask (32bit) of the sensors that are supported by this |
| * platform, then an array of sensor information structures, in order of sensor |
| * type (but without gaps for unimplemented sensors). Each structure defines |
| * the ranges for the corresponding sensor. An unused range is indicated by |
| * equal limit values. If one range is used, a value outside that range results |
| * in STATE_FATAL. If two ranges are used, a value outside the second range |
| * results in STATE_FATAL while a value outside the first and inside the second |
| * range results in STATE_WARNING. |
| * |
| * Sensor masks and sensor information arrays are organised into pages. For |
| * backward compatibility, older host software can only use sensors in page 0. |
| * Bit 32 in the sensor mask was previously unused, and is no reserved for use |
| * as the next page flag. |
| * |
| * If the request does not contain a PAGE value then firmware will only return |
| * page 0 of sensor information, with bit 31 in the sensor mask cleared. |
| * |
| * If the request contains a PAGE value then firmware responds with the sensor |
| * mask and sensor information array for that page of sensors. In this case bit |
| * 31 in the mask is set if another page exists. |
| * |
| * Locks required: None Returns: 0 |
| */ |
| #define MC_CMD_SENSOR_INFO 0x41 |
| |
| /* MC_CMD_SENSOR_INFO_IN msgrequest */ |
| #define MC_CMD_SENSOR_INFO_IN_LEN 0 |
| |
| /* MC_CMD_SENSOR_INFO_EXT_IN msgrequest */ |
| #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4 |
| /* Which page of sensors to report. |
| * |
| * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit). |
| * |
| * Page 1 contains sensors 32 to 62 (sensor 63 is the next page bit). etc. |
| */ |
| #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0 |
| |
| /* MC_CMD_SENSOR_INFO_OUT msgresponse */ |
| #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4 |
| #define MC_CMD_SENSOR_INFO_OUT_LENMAX 252 |
| #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num)) |
| #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 |
| /* enum: Controller temperature: degC */ |
| #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0 |
| /* enum: Phy common temperature: degC */ |
| #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1 |
| /* enum: Controller cooling: bool */ |
| #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2 |
| /* enum: Phy 0 temperature: degC */ |
| #define MC_CMD_SENSOR_PHY0_TEMP 0x3 |
| /* enum: Phy 0 cooling: bool */ |
| #define MC_CMD_SENSOR_PHY0_COOLING 0x4 |
| /* enum: Phy 1 temperature: degC */ |
| #define MC_CMD_SENSOR_PHY1_TEMP 0x5 |
| /* enum: Phy 1 cooling: bool */ |
| #define MC_CMD_SENSOR_PHY1_COOLING 0x6 |
| /* enum: 1.0v power: mV */ |
| #define MC_CMD_SENSOR_IN_1V0 0x7 |
| /* enum: 1.2v power: mV */ |
| #define MC_CMD_SENSOR_IN_1V2 0x8 |
| /* enum: 1.8v power: mV */ |
| #define MC_CMD_SENSOR_IN_1V8 0x9 |
| /* enum: 2.5v power: mV */ |
| #define MC_CMD_SENSOR_IN_2V5 0xa |
| /* enum: 3.3v power: mV */ |
| #define MC_CMD_SENSOR_IN_3V3 0xb |
| /* enum: 12v power: mV */ |
| #define MC_CMD_SENSOR_IN_12V0 0xc |
| /* enum: 1.2v analogue power: mV */ |
| #define MC_CMD_SENSOR_IN_1V2A 0xd |
| /* enum: reference voltage: mV */ |
| #define MC_CMD_SENSOR_IN_VREF 0xe |
| /* enum: AOE FPGA power: mV */ |
| #define MC_CMD_SENSOR_OUT_VAOE 0xf |
| /* enum: AOE FPGA temperature: degC */ |
| #define MC_CMD_SENSOR_AOE_TEMP 0x10 |
| /* enum: AOE FPGA PSU temperature: degC */ |
| #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11 |
| /* enum: AOE PSU temperature: degC */ |
| #define MC_CMD_SENSOR_PSU_TEMP 0x12 |
| /* enum: Fan 0 speed: RPM */ |
| #define MC_CMD_SENSOR_FAN_0 0x13 |
| /* enum: Fan 1 speed: RPM */ |
| #define MC_CMD_SENSOR_FAN_1 0x14 |
| /* enum: Fan 2 speed: RPM */ |
| #define MC_CMD_SENSOR_FAN_2 0x15 |
| /* enum: Fan 3 speed: RPM */ |
| #define MC_CMD_SENSOR_FAN_3 0x16 |
| /* enum: Fan 4 speed: RPM */ |
| #define MC_CMD_SENSOR_FAN_4 0x17 |
| /* enum: AOE FPGA input power: mV */ |
| #define MC_CMD_SENSOR_IN_VAOE 0x18 |
| /* enum: AOE FPGA current: mA */ |
| #define MC_CMD_SENSOR_OUT_IAOE 0x19 |
| /* enum: AOE FPGA input current: mA */ |
| #define MC_CMD_SENSOR_IN_IAOE 0x1a |
| /* enum: NIC power consumption: W */ |
| #define MC_CMD_SENSOR_NIC_POWER 0x1b |
| /* enum: 0.9v power voltage: mV */ |
| #define MC_CMD_SENSOR_IN_0V9 0x1c |
| /* enum: 0.9v power current: mA */ |
| #define MC_CMD_SENSOR_IN_I0V9 0x1d |
| /* enum: 1.2v power current: mA */ |
| #define MC_CMD_SENSOR_IN_I1V2 0x1e |
| /* enum: Not a sensor: reserved for the next page flag */ |
| #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f |
| /* enum: 0.9v power voltage (at ADC): mV */ |
| #define MC_CMD_SENSOR_IN_0V9_ADC 0x20 |
| /* enum: Controller temperature 2: degC */ |
| #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21 |
| /* enum: Voltage regulator internal temperature: degC */ |
| #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22 |
| /* enum: 0.9V voltage regulator temperature: degC */ |
| #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23 |
| /* enum: 1.2V voltage regulator temperature: degC */ |
| #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24 |
| /* enum: controller internal temperature sensor voltage (internal ADC): mV */ |
| #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25 |
| /* enum: controller internal temperature (internal ADC): degC */ |
| #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26 |
| /* enum: controller internal temperature sensor voltage (external ADC): mV */ |
| #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27 |
| /* enum: controller internal temperature (external ADC): degC */ |
| #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28 |
| /* enum: ambient temperature: degC */ |
| #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29 |
| /* enum: air flow: bool */ |
| #define MC_CMD_SENSOR_AIRFLOW 0x2a |
| /* enum: voltage between VSS08D and VSS08D at CSR: mV */ |
| #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b |
| /* enum: voltage between VSS08D and VSS08D at CSR (external ADC): mV */ |
| #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c |
| /* enum: Hotpoint temperature: degC */ |
| #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d |
| /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ |
| #define MC_CMD_SENSOR_ENTRY_OFST 4 |
| #define MC_CMD_SENSOR_ENTRY_LEN 8 |
| #define MC_CMD_SENSOR_ENTRY_LO_OFST 4 |
| #define MC_CMD_SENSOR_ENTRY_HI_OFST 8 |
| #define MC_CMD_SENSOR_ENTRY_MINNUM 0 |
| #define MC_CMD_SENSOR_ENTRY_MAXNUM 31 |
| |
| /* MC_CMD_SENSOR_INFO_EXT_OUT msgresponse */ |
| #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4 |
| #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMAX 252 |
| #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num)) |
| #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0 |
| /* Enum values, see field(s): */ |
| /* MC_CMD_SENSOR_INFO_OUT */ |
| #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_LBN 31 |
| #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_WIDTH 1 |
| /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF */ |
| /* MC_CMD_SENSOR_ENTRY_OFST 4 */ |
| /* MC_CMD_SENSOR_ENTRY_LEN 8 */ |
| /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */ |
| /* MC_CMD_SENSOR_ENTRY_HI_OFST 8 */ |
| /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */ |
| /* MC_CMD_SENSOR_ENTRY_MAXNUM 31 */ |
| |
| /* MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF structuredef */ |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_LEN 8 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LEN 2 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_WIDTH 16 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_OFST 2 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LEN 2 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_LBN 16 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX1_WIDTH 16 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LEN 2 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_LBN 32 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_WIDTH 16 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_OFST 6 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LEN 2 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_LBN 48 |
| #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MAX2_WIDTH 16 |
| |
| |
| /***********************************/ |
| /* MC_CMD_READ_SENSORS |
| * Returns the current reading from each sensor. DMAs an array of sensor |
| * readings, in order of sensor type (but without gaps for unimplemented |
| * sensors), into host memory. Each array element is a |
| * MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF dword. |
| * |
| * If the request does not contain the LENGTH field then only sensors 0 to 30 |
| * are reported, to avoid DMA buffer overflow in older host software. If the |
| * sensor reading require more space than the LENGTH allows, then return |
| * EINVAL. |
| * |
| * The MC will send a SENSOREVT event every time any sensor changes state. The |
| * driver is responsible for ensuring that it doesn't miss any events. The |
| * board will function normally if all sensors are in STATE_OK or |
| * STATE_WARNING. Otherwise the board should not be expected to function. |
| */ |
| #define MC_CMD_READ_SENSORS 0x42 |
| |
| /* MC_CMD_READ_SENSORS_IN msgrequest */ |
| #define MC_CMD_READ_SENSORS_IN_LEN 8 |
| /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned). */ |
| #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0 |
| #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LEN 8 |
| #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 |
| #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 |
| |
| /* MC_CMD_READ_SENSORS_EXT_IN msgrequest */ |
| #define MC_CMD_READ_SENSORS_EXT_IN_LEN 12 |
| /* DMA address of host buffer for sensor readings */ |
| #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0 |
| #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LEN 8 |
| #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0 |
| #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4 |
| /* Size in bytes of host buffer. */ |
| #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_OFST 8 |
| |
| /* MC_CMD_READ_SENSORS_OUT msgresponse */ |
| #define MC_CMD_READ_SENSORS_OUT_LEN 0 |
| |
| /* MC_CMD_READ_SENSORS_EXT_OUT msgresponse */ |
| #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0 |
| |
| /* MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF structuredef */ |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4 |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0 |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LEN 2 |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0 |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_WIDTH 16 |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_OFST 2 |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LEN 1 |
| /* enum: Ok. */ |
| #define MC_CMD_SENSOR_STATE_OK 0x0 |
| /* enum: Breached warning threshold. */ |
| #define MC_CMD_SENSOR_STATE_WARNING 0x1 |
| /* enum: Breached fatal threshold. */ |
| #define MC_CMD_SENSOR_STATE_FATAL 0x2 |
| /* enum: Fault with sensor. */ |
| #define MC_CMD_SENSOR_STATE_BROKEN 0x3 |
| /* enum: Sensor is working but does not currently have a reading. */ |
| #define MC_CMD_SENSOR_STATE_NO_READING 0x4 |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_LBN 16 |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_STATE_WIDTH 8 |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_OFST 3 |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LEN 1 |
| /* Enum values, see field(s): */ |
| /* MC_CMD_SENSOR_INFO/MC_CMD_SENSOR_INFO_OUT/MASK */ |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_LBN 24 |
| #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_TYPE_WIDTH 8 |
| |
| |
| /***********************************/ |
| /* MC_CMD_GET_PHY_STATE |
| * Report current state of PHY. A 'zombie' PHY is a PHY that has failed to boot |
| * (e.g. due to missing or corrupted firmware). Locks required: None. Return |
| * code: 0 |
| */ |
| #define MC_CMD_GET_PHY_STATE 0x43 |
| |
| /* MC_CMD_GET_PHY_STATE_IN msgrequest */ |
| #define MC_CMD_GET_PHY_STATE_IN_LEN 0 |
| |
| /* MC_CMD_GET_PHY_STATE_OUT msgresponse */ |
| #define MC_CMD_GET_PHY_STATE_OUT_LEN 4 |
| #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0 |
| /* enum: Ok. */ |
| #define MC_CMD_PHY_STATE_OK 0x1 |
| /* enum: Faulty. */ |
| #define MC_CMD_PHY_STATE_ZOMBIE 0x2 |
| |
| |
| /***********************************/ |
| /* MC_CMD_SETUP_8021QBB |
| * 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to |
| * disable 802.Qbb for a given priority. |
| */ |
| #define MC_CMD_SETUP_8021QBB 0x44 |
| |
| /* MC_CMD_SETUP_8021QBB_IN msgrequest */ |
| #define MC_CMD_SETUP_8021QBB_IN_LEN 32 |
| #define MC_CMD_SETUP_8021QBB_IN_TXQS_OFST 0 |
| #define MC_CMD_SETUP_8021QBB_IN_TXQS_LEN 32 |
| |
| /* MC_CMD_SETUP_8021QBB_OUT msgresponse */ |
| #define MC_CMD_SETUP_8021QBB_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_WOL_FILTER_GET |
| * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS |
| */ |
| #define MC_CMD_WOL_FILTER_GET 0x45 |
| |
| /* MC_CMD_WOL_FILTER_GET_IN msgrequest */ |
| #define MC_CMD_WOL_FILTER_GET_IN_LEN 0 |
| |
| /* MC_CMD_WOL_FILTER_GET_OUT msgresponse */ |
| #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 |
| #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD |
| * Add a protocol offload to NIC for lights-out state. Locks required: None. |
| * Returns: 0, ENOSYS |
| */ |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 |
| |
| /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN msgrequest */ |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMIN 8 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LENMAX 252 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN(num) (4+4*(num)) |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 |
| #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 /* enum */ |
| #define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 /* enum */ |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_LEN 4 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MINNUM 1 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_MAXNUM 62 |
| |
| /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP msgrequest */ |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_LEN 14 |
| /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_OFST 4 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_MAC_LEN 6 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARP_IP_OFST 10 |
| |
| /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS msgrequest */ |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_LEN 42 |
| /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 */ |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_OFST 4 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_MAC_LEN 6 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_OFST 10 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_SNIPV6_LEN 16 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_OFST 26 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NS_IPV6_LEN 16 |
| |
| /* MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT msgresponse */ |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 |
| #define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD |
| * Remove a protocol offload from NIC for lights-out state. Locks required: |
| * None. Returns: 0, ENOSYS |
| */ |
| #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 |
| |
| /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN msgrequest */ |
| #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 |
| #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 |
| #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 |
| |
| /* MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT msgresponse */ |
| #define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_MAC_RESET_RESTORE |
| * Restore MAC after block reset. Locks required: None. Returns: 0. |
| */ |
| #define MC_CMD_MAC_RESET_RESTORE 0x48 |
| |
| /* MC_CMD_MAC_RESET_RESTORE_IN msgrequest */ |
| #define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 |
| |
| /* MC_CMD_MAC_RESET_RESTORE_OUT msgresponse */ |
| #define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_TESTASSERT |
| * Deliberately trigger an assert-detonation in the firmware for testing |
| * purposes (i.e. to allow tests that the driver copes gracefully). Locks |
| * required: None Returns: 0 |
| */ |
| #define MC_CMD_TESTASSERT 0x49 |
| |
| /* MC_CMD_TESTASSERT_IN msgrequest */ |
| #define MC_CMD_TESTASSERT_IN_LEN 0 |
| |
| /* MC_CMD_TESTASSERT_OUT msgresponse */ |
| #define MC_CMD_TESTASSERT_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_WORKAROUND |
| * Enable/Disable a given workaround. The mcfw will return EINVAL if it doesn't |
| * understand the given workaround number - which should not be treated as a |
| * hard error by client code. This op does not imply any semantics about each |
| * workaround, that's between the driver and the mcfw on a per-workaround |
| * basis. Locks required: None. Returns: 0, EINVAL . |
| */ |
| #define MC_CMD_WORKAROUND 0x4a |
| |
| /* MC_CMD_WORKAROUND_IN msgrequest */ |
| #define MC_CMD_WORKAROUND_IN_LEN 8 |
| #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 |
| /* enum: Bug 17230 work around. */ |
| #define MC_CMD_WORKAROUND_BUG17230 0x1 |
| /* enum: Bug 35388 work around (unsafe EVQ writes). */ |
| #define MC_CMD_WORKAROUND_BUG35388 0x2 |
| /* enum: Bug35017 workaround (A64 tables must be identity map) */ |
| #define MC_CMD_WORKAROUND_BUG35017 0x3 |
| #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 |
| |
| /* MC_CMD_WORKAROUND_OUT msgresponse */ |
| #define MC_CMD_WORKAROUND_OUT_LEN 0 |
| |
| |
| /***********************************/ |
| /* MC_CMD_GET_PHY_MEDIA_INFO |
| * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for |
| * SFP+ PHYs). The 'media type' can be found via GET_PHY_CFG |
| * (GET_PHY_CFG_OUT_MEDIA_TYPE); the valid 'page number' input values, and the |
| * output data, are interpreted on a per-type basis. For SFP+: PAGE=0 or 1 |
| * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80. |
| * Anything else: currently undefined. Locks required: None. Return code: 0. |
| */ |
| #define MC_CMD_GET_PHY_MEDIA_INFO |