/***************************************************************************
 *     Copyright (c) 1999-2014, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: $
 * $brcm_Revision: $
 * $brcm_Date: $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on              Tue Dec  2 03:18:47 2014
 *                 Full Compile MD5 Checksum 3461841ff250f7118305e1f1650424cf
 *                   (minus title and desc)  
 *                 MD5 Checksum              92044aba65695bbffdeefc8d096b8587
 *
 * Compiled with:  RDB Utility               combo_header.pl
 *                 RDB Parser                3.0
 *                 unknown                   unknown
 *                 Perl Interpreter          5.008008
 *                 Operating System          linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_XPT_BUS_IF_H__
#define BCHP_XPT_BUS_IF_H__

/***************************************************************************
 *XPT_BUS_IF - Data Transport Configuration Registers
 ***************************************************************************/
#define BCHP_XPT_BUS_IF_MISC_CTRL0               0x00a00080 /* Data Transport Misc Control 0 Register */
#define BCHP_XPT_BUS_IF_TEST_MODE                0x00a00084 /* Data transport test register */
#define BCHP_XPT_BUS_IF_REVISION                 0x00a00088 /* Data Transport Revision Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG          0x00a0008c /* Interrupt Status Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN       0x00a00090 /* Interrupt Status Enable Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG         0x00a00094 /* Interrupt Status2 Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN      0x00a00098 /* Interrupt Status2 Enable Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG         0x00a0009c /* Interrupt Status3 Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN      0x00a000a0 /* Interrupt Status3 Enable Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG         0x00a000a4 /* Interrupt Status4 Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN      0x00a000a8 /* Interrupt Status4 Enable Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG         0x00a000ac /* Interrupt Status5 Register */
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN      0x00a000b0 /* Interrupt Status5 Enable Register */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET 0x00a000b4 /* Software initialization control for XPT sub-blocks */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR 0x00a000b8 /* Software initialization control for XPT sub-blocks */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS 0x00a000bc /* Software initialization control for XPT sub-blocks */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT 0x00a000c0 /* Software initialization control for XPT sub-blocks */
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0 0x00a000cc /* LCIF to XMEMIF Debug Registers */
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG   0x00a000d0 /* LCIF to XMEMIF Debug Registers */
#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS            0x00a000d4 /* Data Transport max number of playbacks supported */
#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS          0x00a000d8 /* Data Transport max number of PID parsers supported */
#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS         0x00a000dc /* Data Transport max number of PID channels supported excluding MEMDMA */
#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS  0x00a000e0 /* Data Transport max number of PID channels supported for MEMDMA */
#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS          0x00a000e4 /* Data Transport max number of input bands supported */
#define BCHP_XPT_BUS_IF_MAX_PCRS                 0x00a000e8 /* Data Transport max number of PCRs supported */
#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS        0x00a000ec /* Data Transport max number of TPIT channels supported */
#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS        0x00a000f0 /* Data Transport max number of RAVE contexts supported */
#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS         0x00a000f4 /* Data Transport max number of RMX channels supported */
#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS          0x00a000f8 /* Data Transport max number of MSG buffers supported */
#define BCHP_XPT_BUS_IF_MAX_SCDS                 0x00a000fc /* Data Transport max number of SCDs supported */

/***************************************************************************
 *MISC_CTRL0 - Data Transport Misc Control 0 Register
 ***************************************************************************/
/* XPT_BUS_IF :: MISC_CTRL0 :: reserved0 [31:07] */
#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_MASK                  0xffffff80
#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_SHIFT                 7

/* XPT_BUS_IF :: MISC_CTRL0 :: XPT_COUNTER_SCF [06:05] */
#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_MASK            0x00000060
#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_SHIFT           5
#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_DEFAULT         0x00000003
#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_108MHz          0
#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_216MHz          1
#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_270MHz          2
#define BCHP_XPT_BUS_IF_MISC_CTRL0_XPT_COUNTER_SCF_324MHz          3

/* XPT_BUS_IF :: MISC_CTRL0 :: reserved1 [04:03] */
#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_MASK                  0x00000018
#define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_SHIFT                 3

/* XPT_BUS_IF :: MISC_CTRL0 :: ERROR_INT_TEST_MODE [02:02] */
#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_MASK        0x00000004
#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_SHIFT       2
#define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_DEFAULT     0x00000000

/* XPT_BUS_IF :: MISC_CTRL0 :: MPOD_INT_TEST_MODE [01:01] */
#define BCHP_XPT_BUS_IF_MISC_CTRL0_MPOD_INT_TEST_MODE_MASK         0x00000002
#define BCHP_XPT_BUS_IF_MISC_CTRL0_MPOD_INT_TEST_MODE_SHIFT        1
#define BCHP_XPT_BUS_IF_MISC_CTRL0_MPOD_INT_TEST_MODE_DEFAULT      0x00000000

/* XPT_BUS_IF :: MISC_CTRL0 :: LINK_LIST_DESC_ENDIAN_CTRL [00:00] */
#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_MASK 0x00000001
#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_SHIFT 0
#define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_DEFAULT 0x00000000

/***************************************************************************
 *TEST_MODE - Data transport test register
 ***************************************************************************/
/* XPT_BUS_IF :: TEST_MODE :: reserved0 [31:01] */
#define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_MASK                   0xfffffffe
#define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_SHIFT                  1

/* XPT_BUS_IF :: TEST_MODE :: PSG_SECRET_ENBLE [00:00] */
#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_MASK            0x00000001
#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_SHIFT           0
#define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_DEFAULT         0x00000000

/***************************************************************************
 *REVISION - Data Transport Revision Register
 ***************************************************************************/
/* XPT_BUS_IF :: REVISION :: reserved0 [31:16] */
#define BCHP_XPT_BUS_IF_REVISION_reserved0_MASK                    0xffff0000
#define BCHP_XPT_BUS_IF_REVISION_reserved0_SHIFT                   16

/* XPT_BUS_IF :: REVISION :: MAJOR_REV_NUMBER [15:08] */
#define BCHP_XPT_BUS_IF_REVISION_MAJOR_REV_NUMBER_MASK             0x0000ff00
#define BCHP_XPT_BUS_IF_REVISION_MAJOR_REV_NUMBER_SHIFT            8
#define BCHP_XPT_BUS_IF_REVISION_MAJOR_REV_NUMBER_DEFAULT          0x00000040

/* XPT_BUS_IF :: REVISION :: MINOR_REV_NUMBER [07:00] */
#define BCHP_XPT_BUS_IF_REVISION_MINOR_REV_NUMBER_MASK             0x000000ff
#define BCHP_XPT_BUS_IF_REVISION_MINOR_REV_NUMBER_SHIFT            0

/***************************************************************************
 *INTR_STATUS_REG - Interrupt Status Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS_REG :: reserved0 [31:28] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved0_MASK             0xf0000000
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved0_SHIFT            28

/* XPT_BUS_IF :: INTR_STATUS_REG :: RSBUFF_TB_ERR_INTR [27:27] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_TB_ERR_INTR_MASK    0x08000000
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_TB_ERR_INTR_SHIFT   27
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_TB_ERR_INTR_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS_REG :: RSBUFF_PTR_OOR_INTR [26:26] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_PTR_OOR_INTR_MASK   0x04000000
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_PTR_OOR_INTR_SHIFT  26
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_PTR_OOR_INTR_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS_REG :: XCBUFF_PTR_OOR_INTR [25:25] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_PTR_OOR_INTR_MASK   0x02000000
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_PTR_OOR_INTR_SHIFT  25
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_PTR_OOR_INTR_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS_REG :: RSBUFF_OVERFLFLOW_INTR [24:24] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_OVERFLFLOW_INTR_MASK 0x01000000
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_OVERFLFLOW_INTR_SHIFT 24
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_RSBUFF_OVERFLFLOW_INTR_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS_REG :: XCBUFF_OVERFLOW_INTR [23:23] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_OVERFLOW_INTR_MASK  0x00800000
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_OVERFLOW_INTR_SHIFT 23
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_XCBUFF_OVERFLOW_INTR_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS_REG :: reserved1 [22:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved1_MASK             0x007fffff
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_reserved1_SHIFT            0

/***************************************************************************
 *INTR_STATUS_REG_EN - Interrupt Status Enable Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: reserved0 [31:28] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved0_MASK          0xf0000000
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved0_SHIFT         28

/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: RSBUFF_TB_ERR_INTR_EN [27:27] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_TB_ERR_INTR_EN_MASK 0x08000000
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_TB_ERR_INTR_EN_SHIFT 27
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_TB_ERR_INTR_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: RSBUFF_PTR_OOR_INTR_EN [26:26] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_PTR_OOR_INTR_EN_MASK 0x04000000
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_PTR_OOR_INTR_EN_SHIFT 26
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_PTR_OOR_INTR_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: XCBUFF_PTR_OOR_INTR_EN [25:25] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_PTR_OOR_INTR_EN_MASK 0x02000000
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_PTR_OOR_INTR_EN_SHIFT 25
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_PTR_OOR_INTR_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: RSBUFF_OVERFLFLOW_INTR_EN [24:24] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_OVERFLFLOW_INTR_EN_MASK 0x01000000
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_OVERFLFLOW_INTR_EN_SHIFT 24
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_RSBUFF_OVERFLFLOW_INTR_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: XCBUFF_OVERFLOW_INTR_EN [23:23] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_OVERFLOW_INTR_EN_MASK 0x00800000
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_OVERFLOW_INTR_EN_SHIFT 23
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_XCBUFF_OVERFLOW_INTR_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS_REG_EN :: reserved1 [22:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved1_MASK          0x007fffff
#define BCHP_XPT_BUS_IF_INTR_STATUS_REG_EN_reserved1_SHIFT         0

/***************************************************************************
 *INTR_STATUS2_REG - Interrupt Status2 Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS2_REG :: reserved0 [31:03] */
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_reserved0_MASK            0xfffffff8
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_reserved0_SHIFT           3

/* XPT_BUS_IF :: INTR_STATUS2_REG :: CA_ERR_INT [02:02] */
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CA_ERR_INT_MASK           0x00000004
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CA_ERR_INT_SHIFT          2
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CA_ERR_INT_DEFAULT        0x00000000

/* XPT_BUS_IF :: INTR_STATUS2_REG :: CP_DEC_ERR_INT [01:01] */
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_DEC_ERR_INT_MASK       0x00000002
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_DEC_ERR_INT_SHIFT      1
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_DEC_ERR_INT_DEFAULT    0x00000000

/* XPT_BUS_IF :: INTR_STATUS2_REG :: CP_ENC_ERR_INT [00:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_ENC_ERR_INT_MASK       0x00000001
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_ENC_ERR_INT_SHIFT      0
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_CP_ENC_ERR_INT_DEFAULT    0x00000000

/***************************************************************************
 *INTR_STATUS2_REG_EN - Interrupt Status2 Enable Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: reserved0 [31:03] */
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_reserved0_MASK         0xfffffff8
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_reserved0_SHIFT        3

/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: CA_ERR_INT_EN [02:02] */
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CA_ERR_INT_EN_MASK     0x00000004
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CA_ERR_INT_EN_SHIFT    2
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CA_ERR_INT_EN_DEFAULT  0x00000000

/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: CP_DEC_ERR_INT_EN [01:01] */
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_DEC_ERR_INT_EN_MASK 0x00000002
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_DEC_ERR_INT_EN_SHIFT 1
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_DEC_ERR_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS2_REG_EN :: CP_ENC_ERR_INT_EN [00:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_ENC_ERR_INT_EN_MASK 0x00000001
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_ENC_ERR_INT_EN_SHIFT 0
#define BCHP_XPT_BUS_IF_INTR_STATUS2_REG_EN_CP_ENC_ERR_INT_EN_DEFAULT 0x00000000

/***************************************************************************
 *INTR_STATUS3_REG - Interrupt Status3 Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS3_REG :: reserved0 [31:01] */
#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_reserved0_MASK            0xfffffffe
#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_reserved0_SHIFT           1

/* XPT_BUS_IF :: INTR_STATUS3_REG :: MPOD_EXTRACTOR_CRC_ERROR [00:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_MPOD_EXTRACTOR_CRC_ERROR_MASK 0x00000001
#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_MPOD_EXTRACTOR_CRC_ERROR_SHIFT 0
#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_MPOD_EXTRACTOR_CRC_ERROR_DEFAULT 0x00000000

/***************************************************************************
 *INTR_STATUS3_REG_EN - Interrupt Status3 Enable Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS3_REG_EN :: reserved0 [31:01] */
#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_reserved0_MASK         0xfffffffe
#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_reserved0_SHIFT        1

/* XPT_BUS_IF :: INTR_STATUS3_REG_EN :: MPOD_EXTRACTOR_CRC_ERROR_EN [00:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_MPOD_EXTRACTOR_CRC_ERROR_EN_MASK 0x00000001
#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_MPOD_EXTRACTOR_CRC_ERROR_EN_SHIFT 0
#define BCHP_XPT_BUS_IF_INTR_STATUS3_REG_EN_MPOD_EXTRACTOR_CRC_ERROR_EN_DEFAULT 0x00000000

/***************************************************************************
 *INTR_STATUS4_REG - Interrupt Status4 Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved0 [31:28] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_MASK            0xf0000000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_SHIFT           28

/* XPT_BUS_IF :: INTR_STATUS4_REG :: GISB_BRIDGE [27:27] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_MASK          0x08000000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_SHIFT         27
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_DEFAULT       0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved1 [26:16] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_MASK            0x07ff0000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_SHIFT           16

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB15_EOB_INT [15:15] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB15_EOB_INT_MASK       0x00008000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB15_EOB_INT_SHIFT      15
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB15_EOB_INT_DEFAULT    0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB14_EOB_INT [14:14] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB14_EOB_INT_MASK       0x00004000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB14_EOB_INT_SHIFT      14
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB14_EOB_INT_DEFAULT    0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB13_EOB_INT [13:13] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB13_EOB_INT_MASK       0x00002000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB13_EOB_INT_SHIFT      13
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB13_EOB_INT_DEFAULT    0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB12_EOB_INT [12:12] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB12_EOB_INT_MASK       0x00001000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB12_EOB_INT_SHIFT      12
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB12_EOB_INT_DEFAULT    0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB11_EOB_INT [11:11] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB11_EOB_INT_MASK       0x00000800
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB11_EOB_INT_SHIFT      11
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB11_EOB_INT_DEFAULT    0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB10_EOB_INT [10:10] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB10_EOB_INT_MASK       0x00000400
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB10_EOB_INT_SHIFT      10
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB10_EOB_INT_DEFAULT    0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB9_EOB_INT [09:09] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB9_EOB_INT_MASK        0x00000200
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB9_EOB_INT_SHIFT       9
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB9_EOB_INT_DEFAULT     0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB8_EOB_INT [08:08] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB8_EOB_INT_MASK        0x00000100
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB8_EOB_INT_SHIFT       8
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB8_EOB_INT_DEFAULT     0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB7_EOB_INT [07:07] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB7_EOB_INT_MASK        0x00000080
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB7_EOB_INT_SHIFT       7
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB7_EOB_INT_DEFAULT     0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB6_EOB_INT [06:06] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB6_EOB_INT_MASK        0x00000040
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB6_EOB_INT_SHIFT       6
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB6_EOB_INT_DEFAULT     0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB5_EOB_INT [05:05] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB5_EOB_INT_MASK        0x00000020
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB5_EOB_INT_SHIFT       5
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB5_EOB_INT_DEFAULT     0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB4_EOB_INT [04:04] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB4_EOB_INT_MASK        0x00000010
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB4_EOB_INT_SHIFT       4
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB4_EOB_INT_DEFAULT     0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB3_EOB_INT [03:03] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB3_EOB_INT_MASK        0x00000008
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB3_EOB_INT_SHIFT       3
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB3_EOB_INT_DEFAULT     0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB2_EOB_INT [02:02] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB2_EOB_INT_MASK        0x00000004
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB2_EOB_INT_SHIFT       2
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB2_EOB_INT_DEFAULT     0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB1_EOB_INT [01:01] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB1_EOB_INT_MASK        0x00000002
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB1_EOB_INT_SHIFT       1
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB1_EOB_INT_DEFAULT     0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG :: PSUB0_EOB_INT [00:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB0_EOB_INT_MASK        0x00000001
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB0_EOB_INT_SHIFT       0
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_PSUB0_EOB_INT_DEFAULT     0x00000000

/***************************************************************************
 *INTR_STATUS4_REG_EN - Interrupt Status4 Enable Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved0 [31:28] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_MASK         0xf0000000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_SHIFT        28

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: GISB_BRIDGE_EN [27:27] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_GISB_BRIDGE_EN_MASK    0x08000000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_GISB_BRIDGE_EN_SHIFT   27
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_GISB_BRIDGE_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved1 [26:16] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_MASK         0x07ff0000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_SHIFT        16

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB15_EOB_INT_EN [15:15] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB15_EOB_INT_EN_MASK 0x00008000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB15_EOB_INT_EN_SHIFT 15
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB15_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB14_EOB_INT_EN [14:14] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB14_EOB_INT_EN_MASK 0x00004000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB14_EOB_INT_EN_SHIFT 14
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB14_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB13_EOB_INT_EN [13:13] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB13_EOB_INT_EN_MASK 0x00002000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB13_EOB_INT_EN_SHIFT 13
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB13_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB12_EOB_INT_EN [12:12] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB12_EOB_INT_EN_MASK 0x00001000
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB12_EOB_INT_EN_SHIFT 12
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB12_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB11_EOB_INT_EN [11:11] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB11_EOB_INT_EN_MASK 0x00000800
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB11_EOB_INT_EN_SHIFT 11
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB11_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB10_EOB_INT_EN [10:10] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB10_EOB_INT_EN_MASK 0x00000400
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB10_EOB_INT_EN_SHIFT 10
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB10_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB9_EOB_INT_EN [09:09] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB9_EOB_INT_EN_MASK  0x00000200
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB9_EOB_INT_EN_SHIFT 9
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB9_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB8_EOB_INT_EN [08:08] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB8_EOB_INT_EN_MASK  0x00000100
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB8_EOB_INT_EN_SHIFT 8
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB8_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB7_EOB_INT_EN [07:07] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB7_EOB_INT_EN_MASK  0x00000080
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB7_EOB_INT_EN_SHIFT 7
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB7_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB6_EOB_INT_EN [06:06] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB6_EOB_INT_EN_MASK  0x00000040
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB6_EOB_INT_EN_SHIFT 6
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB6_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB5_EOB_INT_EN [05:05] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB5_EOB_INT_EN_MASK  0x00000020
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB5_EOB_INT_EN_SHIFT 5
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB5_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB4_EOB_INT_EN [04:04] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB4_EOB_INT_EN_MASK  0x00000010
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB4_EOB_INT_EN_SHIFT 4
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB4_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB3_EOB_INT_EN [03:03] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB3_EOB_INT_EN_MASK  0x00000008
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB3_EOB_INT_EN_SHIFT 3
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB3_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB2_EOB_INT_EN [02:02] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB2_EOB_INT_EN_MASK  0x00000004
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB2_EOB_INT_EN_SHIFT 2
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB2_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB1_EOB_INT_EN [01:01] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB1_EOB_INT_EN_MASK  0x00000002
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB1_EOB_INT_EN_SHIFT 1
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB1_EOB_INT_EN_DEFAULT 0x00000000

/* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: PSUB0_EOB_INT_EN [00:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB0_EOB_INT_EN_MASK  0x00000001
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB0_EOB_INT_EN_SHIFT 0
#define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_PSUB0_EOB_INT_EN_DEFAULT 0x00000000

/***************************************************************************
 *INTR_STATUS5_REG - Interrupt Status5 Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS5_REG :: reserved0 [31:01] */
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_MASK            0xfffffffe
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_SHIFT           1

/* XPT_BUS_IF :: INTR_STATUS5_REG :: WRCHECKER_INT [00:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_MASK        0x00000001
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_SHIFT       0
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_DEFAULT     0x00000000

/***************************************************************************
 *INTR_STATUS5_REG_EN - Interrupt Status5 Enable Register
 ***************************************************************************/
/* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: reserved0 [31:01] */
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_MASK         0xfffffffe
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_SHIFT        1

/* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: WRCHECKER_INT [00:00] */
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_WRCHECKER_INT_MASK     0x00000001
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_WRCHECKER_INT_SHIFT    0
#define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_WRCHECKER_INT_DEFAULT  0x00000000

/***************************************************************************
 *SUB_MODULE_SOFT_INIT_SET - Software initialization control for XPT sub-blocks
 ***************************************************************************/
/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_SET :: reserved0 [31:02] */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_reserved0_MASK    0xfffffffc
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_reserved0_SHIFT   2

/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_SET :: MEMDMA_MCPB_SOFT_INIT_SET [01:01] */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_MEMDMA_MCPB_SOFT_INIT_SET_MASK 0x00000002
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_MEMDMA_MCPB_SOFT_INIT_SET_SHIFT 1
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_MEMDMA_MCPB_SOFT_INIT_SET_DEFAULT 0x00000000

/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_SET :: XPT_MCPB_SOFT_INIT_SET [00:00] */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_XPT_MCPB_SOFT_INIT_SET_MASK 0x00000001
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_XPT_MCPB_SOFT_INIT_SET_SHIFT 0
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_SET_XPT_MCPB_SOFT_INIT_SET_DEFAULT 0x00000000

/***************************************************************************
 *SUB_MODULE_SOFT_INIT_CLEAR - Software initialization control for XPT sub-blocks
 ***************************************************************************/
/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_CLEAR :: reserved0 [31:02] */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_reserved0_MASK  0xfffffffc
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_reserved0_SHIFT 2

/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_CLEAR :: MEMDMA_MCPB_SOFT_INIT_CLEAR [01:01] */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_MEMDMA_MCPB_SOFT_INIT_CLEAR_MASK 0x00000002
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_MEMDMA_MCPB_SOFT_INIT_CLEAR_SHIFT 1
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_MEMDMA_MCPB_SOFT_INIT_CLEAR_DEFAULT 0x00000000

/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_CLEAR :: XPT_MCPB_SOFT_INIT_CLEAR [00:00] */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_XPT_MCPB_SOFT_INIT_CLEAR_MASK 0x00000001
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_XPT_MCPB_SOFT_INIT_CLEAR_SHIFT 0
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_CLEAR_XPT_MCPB_SOFT_INIT_CLEAR_DEFAULT 0x00000000

/***************************************************************************
 *SUB_MODULE_SOFT_INIT_STATUS - Software initialization control for XPT sub-blocks
 ***************************************************************************/
/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_STATUS :: reserved0 [31:02] */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_reserved0_SHIFT 2

/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_STATUS :: MEMDMA_MCPB_SOFT_INIT_STATUS [01:01] */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_MEMDMA_MCPB_SOFT_INIT_STATUS_MASK 0x00000002
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_MEMDMA_MCPB_SOFT_INIT_STATUS_SHIFT 1
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_MEMDMA_MCPB_SOFT_INIT_STATUS_DEFAULT 0x00000000

/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_STATUS :: XPT_MCPB_SOFT_INIT_STATUS [00:00] */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_XPT_MCPB_SOFT_INIT_STATUS_MASK 0x00000001
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_XPT_MCPB_SOFT_INIT_STATUS_SHIFT 0
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_STATUS_XPT_MCPB_SOFT_INIT_STATUS_DEFAULT 0x00000000

/***************************************************************************
 *SUB_MODULE_SOFT_INIT_DO_MEM_INIT - Software initialization control for XPT sub-blocks
 ***************************************************************************/
/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_DO_MEM_INIT :: reserved0 [31:02] */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_reserved0_MASK 0xfffffffc
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_reserved0_SHIFT 2

/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_DO_MEM_INIT :: MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT [01:01] */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT_MASK 0x00000002
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT_SHIFT 1
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_MEMDMA_MCPB_SOFT_INIT_DO_MEM_INIT_DEFAULT 0x00000001

/* XPT_BUS_IF :: SUB_MODULE_SOFT_INIT_DO_MEM_INIT :: XPT_MCPB_SOFT_INIT_DO_MEM_INIT [00:00] */
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_XPT_MCPB_SOFT_INIT_DO_MEM_INIT_MASK 0x00000001
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_XPT_MCPB_SOFT_INIT_DO_MEM_INIT_SHIFT 0
#define BCHP_XPT_BUS_IF_SUB_MODULE_SOFT_INIT_DO_MEM_INIT_XPT_MCPB_SOFT_INIT_DO_MEM_INIT_DEFAULT 0x00000001

/***************************************************************************
 *XMEMIF_RD_LC_DEBUG_REG_0 - LCIF to XMEMIF Debug Registers
 ***************************************************************************/
/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG_0 :: reserved0 [31:16] */
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_reserved0_MASK    0xffff0000
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_reserved0_SHIFT   16

/* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG_0 :: PSUB_DEBUG_REG [15:00] */
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_PSUB_DEBUG_REG_MASK 0x0000ffff
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_PSUB_DEBUG_REG_SHIFT 0
#define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_0_PSUB_DEBUG_REG_DEFAULT 0x00000000

/***************************************************************************
 *XMEMIF_WR_LC_DEBUG_REG - LCIF to XMEMIF Debug Registers
 ***************************************************************************/
/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: reserved0 [31:05] */
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_MASK      0xffffffe0
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_SHIFT     5

/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: RSBUFF_WR_DEBUG_REG [04:04] */
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RSBUFF_WR_DEBUG_REG_MASK 0x00000010
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RSBUFF_WR_DEBUG_REG_SHIFT 4
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RSBUFF_WR_DEBUG_REG_DEFAULT 0x00000000

/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: XCBUFF_WR_DEBUG_REG [03:03] */
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_XCBUFF_WR_DEBUG_REG_MASK 0x00000008
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_XCBUFF_WR_DEBUG_REG_SHIFT 3
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_XCBUFF_WR_DEBUG_REG_DEFAULT 0x00000000

/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: MSG_DEBUG_REG [02:02] */
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_MSG_DEBUG_REG_MASK  0x00000004
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_MSG_DEBUG_REG_SHIFT 2
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_MSG_DEBUG_REG_DEFAULT 0x00000000

/* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: RAVE_DEBUG_REG [01:00] */
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_MASK 0x00000003
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_SHIFT 0
#define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_DEFAULT 0x00000000

/***************************************************************************
 *MAX_PLAYBACKS - Data Transport max number of playbacks supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_PLAYBACKS :: reserved0 [31:06] */
#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_MASK               0xffffffc0
#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_SHIFT              6

/* XPT_BUS_IF :: MAX_PLAYBACKS :: MAX_PLAYBACKS [05:00] */
#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_MASK           0x0000003f
#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_SHIFT          0
#define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_DEFAULT        0x00000020

/***************************************************************************
 *MAX_PID_PARSERS - Data Transport max number of PID parsers supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_PID_PARSERS :: reserved0 [31:06] */
#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_reserved0_MASK             0xffffffc0
#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_reserved0_SHIFT            6

/* XPT_BUS_IF :: MAX_PID_PARSERS :: MAX_PID_PARSERS [05:00] */
#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_MAX_PID_PARSERS_MASK       0x0000003f
#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_MAX_PID_PARSERS_SHIFT      0
#define BCHP_XPT_BUS_IF_MAX_PID_PARSERS_MAX_PID_PARSERS_DEFAULT    0x00000018

/***************************************************************************
 *MAX_PID_CHANNELS - Data Transport max number of PID channels supported excluding MEMDMA
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_PID_CHANNELS :: reserved0 [31:12] */
#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_MASK            0xfffff000
#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_SHIFT           12

/* XPT_BUS_IF :: MAX_PID_CHANNELS :: MAX_PID_CHANNELS [11:00] */
#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_MASK     0x00000fff
#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_SHIFT    0
#define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_DEFAULT  0x00000300

/***************************************************************************
 *MEMDMA_MAX_PID_CHANNELS - Data Transport max number of PID channels supported for MEMDMA
 ***************************************************************************/
/* XPT_BUS_IF :: MEMDMA_MAX_PID_CHANNELS :: reserved0 [31:12] */
#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_reserved0_MASK     0xfffff000
#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_reserved0_SHIFT    12

/* XPT_BUS_IF :: MEMDMA_MAX_PID_CHANNELS :: MAX_PID_CHANNELS [11:00] */
#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_MAX_PID_CHANNELS_MASK 0x00000fff
#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_MAX_PID_CHANNELS_SHIFT 0
#define BCHP_XPT_BUS_IF_MEMDMA_MAX_PID_CHANNELS_MAX_PID_CHANNELS_DEFAULT 0x00000400

/***************************************************************************
 *MAX_INPUT_BANDS - Data Transport max number of input bands supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_INPUT_BANDS :: reserved0 [31:05] */
#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_reserved0_MASK             0xffffffe0
#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_reserved0_SHIFT            5

/* XPT_BUS_IF :: MAX_INPUT_BANDS :: MAX_INPUT_BANDS [04:00] */
#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_MAX_INPUT_BANDS_MASK       0x0000001f
#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_MAX_INPUT_BANDS_SHIFT      0
#define BCHP_XPT_BUS_IF_MAX_INPUT_BANDS_MAX_INPUT_BANDS_DEFAULT    0x0000000d

/***************************************************************************
 *MAX_PCRS - Data Transport max number of PCRs supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_PCRS :: reserved0 [31:04] */
#define BCHP_XPT_BUS_IF_MAX_PCRS_reserved0_MASK                    0xfffffff0
#define BCHP_XPT_BUS_IF_MAX_PCRS_reserved0_SHIFT                   4

/* XPT_BUS_IF :: MAX_PCRS :: MAX_PCRS [03:00] */
#define BCHP_XPT_BUS_IF_MAX_PCRS_MAX_PCRS_MASK                     0x0000000f
#define BCHP_XPT_BUS_IF_MAX_PCRS_MAX_PCRS_SHIFT                    0
#define BCHP_XPT_BUS_IF_MAX_PCRS_MAX_PCRS_DEFAULT                  0x0000000e

/***************************************************************************
 *MAX_TPIT_CHANNELS - Data Transport max number of TPIT channels supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: reserved0 [31:05] */
#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_MASK           0xffffffe0
#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_SHIFT          5

/* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: MAX_TPIT_CHANNELS [04:00] */
#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_MASK   0x0000001f
#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_SHIFT  0
#define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_DEFAULT 0x00000010

/***************************************************************************
 *MAX_RAVE_CONTEXTS - Data Transport max number of RAVE contexts supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: reserved0 [31:08] */
#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_MASK           0xffffff00
#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_SHIFT          8

/* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: MAX_RAVE_CONTEXTS [07:00] */
#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_MASK   0x000000ff
#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_SHIFT  0
#define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_DEFAULT 0x00000030

/***************************************************************************
 *MAX_RMX_CHANNELS - Data Transport max number of RMX channels supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_RMX_CHANNELS :: reserved0 [31:04] */
#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_reserved0_MASK            0xfffffff0
#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_reserved0_SHIFT           4

/* XPT_BUS_IF :: MAX_RMX_CHANNELS :: MAX_RMX_CHANNELS [03:00] */
#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_MAX_RMX_CHANNELS_MASK     0x0000000f
#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_MAX_RMX_CHANNELS_SHIFT    0
#define BCHP_XPT_BUS_IF_MAX_RMX_CHANNELS_MAX_RMX_CHANNELS_DEFAULT  0x00000002

/***************************************************************************
 *MAX_MSG_BUFFERS - Data Transport max number of MSG buffers supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_MSG_BUFFERS :: reserved0 [31:09] */
#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_reserved0_MASK             0xfffffe00
#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_reserved0_SHIFT            9

/* XPT_BUS_IF :: MAX_MSG_BUFFERS :: MAX_MSG_BUFFERS [08:00] */
#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_MAX_MSG_BUFFERS_MASK       0x000001ff
#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_MAX_MSG_BUFFERS_SHIFT      0
#define BCHP_XPT_BUS_IF_MAX_MSG_BUFFERS_MAX_MSG_BUFFERS_DEFAULT    0x00000100

/***************************************************************************
 *MAX_SCDS - Data Transport max number of SCDs supported
 ***************************************************************************/
/* XPT_BUS_IF :: MAX_SCDS :: reserved0 [31:09] */
#define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_MASK                    0xfffffe00
#define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_SHIFT                   9

/* XPT_BUS_IF :: MAX_SCDS :: MAX_SCDS [08:00] */
#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_MASK                     0x000001ff
#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_SHIFT                    0
#define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_DEFAULT                  0x00000040

#endif /* #ifndef BCHP_XPT_BUS_IF_H__ */

/* End of File */