/***************************************************************************
 *     Copyright (c) 1999-2014, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: $
 * $brcm_Revision: $
 * $brcm_Date: $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on              Tue Dec  2 03:18:45 2014
 *                 Full Compile MD5 Checksum 3461841ff250f7118305e1f1650424cf
 *                   (minus title and desc)  
 *                 MD5 Checksum              92044aba65695bbffdeefc8d096b8587
 *
 * Compiled with:  RDB Utility               combo_header.pl
 *                 RDB Parser                3.0
 *                 unknown                   unknown
 *                 Perl Interpreter          5.008008
 *                 Operating System          linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_HIF_INTR2_H__
#define BCHP_HIF_INTR2_H__

/***************************************************************************
 *HIF_INTR2 - HIF Level 2 Interrupt Controller Registers
 ***************************************************************************/
#define BCHP_HIF_INTR2_CPU_STATUS                0x00441000 /* CPU interrupt Status Register */
#define BCHP_HIF_INTR2_CPU_SET                   0x00441004 /* CPU interrupt Set Register */
#define BCHP_HIF_INTR2_CPU_CLEAR                 0x00441008 /* CPU interrupt Clear Register */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS           0x0044100c /* CPU interrupt Mask Status Register */
#define BCHP_HIF_INTR2_CPU_MASK_SET              0x00441010 /* CPU interrupt Mask Set Register */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR            0x00441014 /* CPU interrupt Mask Clear Register */
#define BCHP_HIF_INTR2_PCI_STATUS                0x00441018 /* PCI interrupt Status Register */
#define BCHP_HIF_INTR2_PCI_SET                   0x0044101c /* PCI interrupt Set Register */
#define BCHP_HIF_INTR2_PCI_CLEAR                 0x00441020 /* PCI interrupt Clear Register */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS           0x00441024 /* PCI interrupt Mask Status Register */
#define BCHP_HIF_INTR2_PCI_MASK_SET              0x00441028 /* PCI interrupt Mask Set Register */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR            0x0044102c /* PCI interrupt Mask Clear Register */

/***************************************************************************
 *CPU_STATUS - CPU interrupt Status Register
 ***************************************************************************/
/* HIF_INTR2 :: CPU_STATUS :: PCIE_0_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_LINKDOWN_INTR_MASK        0x80000000
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_LINKDOWN_INTR_SHIFT       31
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_LINKDOWN_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: CPU_STATUS :: PCIE_0_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_LINKUP_INTR_MASK          0x40000000
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_LINKUP_INTR_SHIFT         30
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_LINKUP_INTR_DEFAULT       0x00000000

/* HIF_INTR2 :: CPU_STATUS :: PCIE_1_LINKDOWN_INTR [29:29] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_LINKDOWN_INTR_MASK        0x20000000
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_LINKDOWN_INTR_SHIFT       29
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_LINKDOWN_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: CPU_STATUS :: PCIE_1_LINKUP_INTR [28:28] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_LINKUP_INTR_MASK          0x10000000
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_LINKUP_INTR_SHIFT         28
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_LINKUP_INTR_DEFAULT       0x00000000

/* HIF_INTR2 :: CPU_STATUS :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_MASK              0x08000000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_SHIFT             27
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000

/* HIF_INTR2 :: CPU_STATUS :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_MASK               0x04000000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_SHIFT              26
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000

/* HIF_INTR2 :: CPU_STATUS :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_SHIFT            25
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: CPU_STATUS :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_SHIFT           24
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000

/* HIF_INTR2 :: CPU_STATUS :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_SHIFT            23
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: CPU_STATUS :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_SHIFT            22
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: CPU_STATUS :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_SHIFT           21
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000

/* HIF_INTR2 :: CPU_STATUS :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_SHIFT          20
#define BCHP_HIF_INTR2_CPU_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000

/* HIF_INTR2 :: CPU_STATUS :: reserved0 [19:16] */
#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_MASK                   0x000f0000
#define BCHP_HIF_INTR2_CPU_STATUS_reserved0_SHIFT                  16

/* HIF_INTR2 :: CPU_STATUS :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_MASK               0x00008000
#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_SHIFT              15
#define BCHP_HIF_INTR2_CPU_STATUS_ITCH0_RD_INTR_DEFAULT            0x00000000

/* HIF_INTR2 :: CPU_STATUS :: reserved1 [14:14] */
#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_MASK                   0x00004000
#define BCHP_HIF_INTR2_CPU_STATUS_reserved1_SHIFT                  14

/* HIF_INTR2 :: CPU_STATUS :: PCIE_0_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_RG_BRIDGE_INTR_MASK       0x00002000
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_RG_BRIDGE_INTR_SHIFT      13
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_RG_BRIDGE_INTR_DEFAULT    0x00000000

/* HIF_INTR2 :: CPU_STATUS :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_RGR_BRIDGE_INTR_MASK      0x00001000
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_RGR_BRIDGE_INTR_SHIFT     12
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_0_RGR_BRIDGE_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: CPU_STATUS :: PCIE_1_RG_BRIDGE_INTR [11:11] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_RG_BRIDGE_INTR_MASK       0x00000800
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_RG_BRIDGE_INTR_SHIFT      11
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_RG_BRIDGE_INTR_DEFAULT    0x00000000

/* HIF_INTR2 :: CPU_STATUS :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_RGR_BRIDGE_INTR_MASK      0x00000400
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_RGR_BRIDGE_INTR_SHIFT     10
#define BCHP_HIF_INTR2_CPU_STATUS_PCIE_1_RGR_BRIDGE_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: CPU_STATUS :: reserved2 [09:06] */
#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_MASK                   0x000003c0
#define BCHP_HIF_INTR2_CPU_STATUS_reserved2_SHIFT                  6

/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_MASK          0x00000020
#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_SHIFT         5
#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_ERR_INTR_DEFAULT       0x00000000

/* HIF_INTR2 :: CPU_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_MASK         0x00000010
#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_SHIFT        4
#define BCHP_HIF_INTR2_CPU_STATUS_FLASH_DMA_DONE_INTR_DEFAULT      0x00000000

/* HIF_INTR2 :: CPU_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK      0x00000008
#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT     3
#define BCHP_HIF_INTR2_CPU_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: CPU_STATUS :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_MASK                   0x00000004
#define BCHP_HIF_INTR2_CPU_STATUS_reserved3_SHIFT                  2

/* HIF_INTR2 :: CPU_STATUS :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_MASK               0x00000002
#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_SHIFT              1
#define BCHP_HIF_INTR2_CPU_STATUS_ITCH1_RD_INTR_DEFAULT            0x00000000

/* HIF_INTR2 :: CPU_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
#define BCHP_HIF_INTR2_CPU_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000

/***************************************************************************
 *CPU_SET - CPU interrupt Set Register
 ***************************************************************************/
/* HIF_INTR2 :: CPU_SET :: PCIE_0_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_LINKDOWN_INTR_MASK           0x80000000
#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_LINKDOWN_INTR_SHIFT          31
#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_LINKDOWN_INTR_DEFAULT        0x00000000

/* HIF_INTR2 :: CPU_SET :: PCIE_0_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_LINKUP_INTR_MASK             0x40000000
#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_LINKUP_INTR_SHIFT            30
#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_LINKUP_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: CPU_SET :: PCIE_1_LINKDOWN_INTR [29:29] */
#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_LINKDOWN_INTR_MASK           0x20000000
#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_LINKDOWN_INTR_SHIFT          29
#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_LINKDOWN_INTR_DEFAULT        0x00000000

/* HIF_INTR2 :: CPU_SET :: PCIE_1_LINKUP_INTR [28:28] */
#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_LINKUP_INTR_MASK             0x10000000
#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_LINKUP_INTR_SHIFT            28
#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_LINKUP_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: CPU_SET :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_MASK                 0x08000000
#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_SHIFT                27
#define BCHP_HIF_INTR2_CPU_SET_NAND_CORR_INTR_DEFAULT              0x00000000

/* HIF_INTR2 :: CPU_SET :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_MASK                  0x04000000
#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_SHIFT                 26
#define BCHP_HIF_INTR2_CPU_SET_NAND_UNC_INTR_DEFAULT               0x00000000

/* HIF_INTR2 :: CPU_SET :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_MASK                0x02000000
#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_SHIFT               25
#define BCHP_HIF_INTR2_CPU_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000

/* HIF_INTR2 :: CPU_SET :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_MASK               0x01000000
#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_SHIFT              24
#define BCHP_HIF_INTR2_CPU_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000

/* HIF_INTR2 :: CPU_SET :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_MASK                0x00800000
#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_SHIFT               23
#define BCHP_HIF_INTR2_CPU_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000

/* HIF_INTR2 :: CPU_SET :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_MASK                0x00400000
#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_SHIFT               22
#define BCHP_HIF_INTR2_CPU_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000

/* HIF_INTR2 :: CPU_SET :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_MASK               0x00200000
#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_SHIFT              21
#define BCHP_HIF_INTR2_CPU_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000

/* HIF_INTR2 :: CPU_SET :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_MASK              0x00100000
#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_SHIFT             20
#define BCHP_HIF_INTR2_CPU_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000

/* HIF_INTR2 :: CPU_SET :: reserved0 [19:16] */
#define BCHP_HIF_INTR2_CPU_SET_reserved0_MASK                      0x000f0000
#define BCHP_HIF_INTR2_CPU_SET_reserved0_SHIFT                     16

/* HIF_INTR2 :: CPU_SET :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_MASK                  0x00008000
#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_SHIFT                 15
#define BCHP_HIF_INTR2_CPU_SET_ITCH0_RD_INTR_DEFAULT               0x00000000

/* HIF_INTR2 :: CPU_SET :: reserved1 [14:14] */
#define BCHP_HIF_INTR2_CPU_SET_reserved1_MASK                      0x00004000
#define BCHP_HIF_INTR2_CPU_SET_reserved1_SHIFT                     14

/* HIF_INTR2 :: CPU_SET :: PCIE_0_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_RG_BRIDGE_INTR_MASK          0x00002000
#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_RG_BRIDGE_INTR_SHIFT         13
#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_RG_BRIDGE_INTR_DEFAULT       0x00000000

/* HIF_INTR2 :: CPU_SET :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_RGR_BRIDGE_INTR_MASK         0x00001000
#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_RGR_BRIDGE_INTR_SHIFT        12
#define BCHP_HIF_INTR2_CPU_SET_PCIE_0_RGR_BRIDGE_INTR_DEFAULT      0x00000000

/* HIF_INTR2 :: CPU_SET :: PCIE_1_RG_BRIDGE_INTR [11:11] */
#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_RG_BRIDGE_INTR_MASK          0x00000800
#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_RG_BRIDGE_INTR_SHIFT         11
#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_RG_BRIDGE_INTR_DEFAULT       0x00000000

/* HIF_INTR2 :: CPU_SET :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_RGR_BRIDGE_INTR_MASK         0x00000400
#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_RGR_BRIDGE_INTR_SHIFT        10
#define BCHP_HIF_INTR2_CPU_SET_PCIE_1_RGR_BRIDGE_INTR_DEFAULT      0x00000000

/* HIF_INTR2 :: CPU_SET :: reserved2 [09:06] */
#define BCHP_HIF_INTR2_CPU_SET_reserved2_MASK                      0x000003c0
#define BCHP_HIF_INTR2_CPU_SET_reserved2_SHIFT                     6

/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_MASK             0x00000020
#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_SHIFT            5
#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_ERR_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: CPU_SET :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_MASK            0x00000010
#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_SHIFT           4
#define BCHP_HIF_INTR2_CPU_SET_FLASH_DMA_DONE_INTR_DEFAULT         0x00000000

/* HIF_INTR2 :: CPU_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_MASK         0x00000008
#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT        3
#define BCHP_HIF_INTR2_CPU_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT      0x00000000

/* HIF_INTR2 :: CPU_SET :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_CPU_SET_reserved3_MASK                      0x00000004
#define BCHP_HIF_INTR2_CPU_SET_reserved3_SHIFT                     2

/* HIF_INTR2 :: CPU_SET :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_MASK                  0x00000002
#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_SHIFT                 1
#define BCHP_HIF_INTR2_CPU_SET_ITCH1_RD_INTR_DEFAULT               0x00000000

/* HIF_INTR2 :: CPU_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
#define BCHP_HIF_INTR2_CPU_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000

/***************************************************************************
 *CPU_CLEAR - CPU interrupt Clear Register
 ***************************************************************************/
/* HIF_INTR2 :: CPU_CLEAR :: PCIE_0_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_LINKDOWN_INTR_MASK         0x80000000
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_LINKDOWN_INTR_SHIFT        31
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_LINKDOWN_INTR_DEFAULT      0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: PCIE_0_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_LINKUP_INTR_MASK           0x40000000
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_LINKUP_INTR_SHIFT          30
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_LINKUP_INTR_DEFAULT        0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: PCIE_1_LINKDOWN_INTR [29:29] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_LINKDOWN_INTR_MASK         0x20000000
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_LINKDOWN_INTR_SHIFT        29
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_LINKDOWN_INTR_DEFAULT      0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: PCIE_1_LINKUP_INTR [28:28] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_LINKUP_INTR_MASK           0x10000000
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_LINKUP_INTR_SHIFT          28
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_LINKUP_INTR_DEFAULT        0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_MASK               0x08000000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_SHIFT              27
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_MASK                0x04000000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_SHIFT               26
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_SHIFT             25
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_SHIFT             23
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_SHIFT             22
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_SHIFT            21
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_SHIFT           20
#define BCHP_HIF_INTR2_CPU_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: reserved0 [19:16] */
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_MASK                    0x000f0000
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved0_SHIFT                   16

/* HIF_INTR2 :: CPU_CLEAR :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_MASK                0x00008000
#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_SHIFT               15
#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH0_RD_INTR_DEFAULT             0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: reserved1 [14:14] */
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_MASK                    0x00004000
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved1_SHIFT                   14

/* HIF_INTR2 :: CPU_CLEAR :: PCIE_0_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_RG_BRIDGE_INTR_MASK        0x00002000
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_RG_BRIDGE_INTR_SHIFT       13
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_RG_BRIDGE_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_RGR_BRIDGE_INTR_MASK       0x00001000
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_RGR_BRIDGE_INTR_SHIFT      12
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_0_RGR_BRIDGE_INTR_DEFAULT    0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: PCIE_1_RG_BRIDGE_INTR [11:11] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_RG_BRIDGE_INTR_MASK        0x00000800
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_RG_BRIDGE_INTR_SHIFT       11
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_RG_BRIDGE_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_RGR_BRIDGE_INTR_MASK       0x00000400
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_RGR_BRIDGE_INTR_SHIFT      10
#define BCHP_HIF_INTR2_CPU_CLEAR_PCIE_1_RGR_BRIDGE_INTR_DEFAULT    0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: reserved2 [09:06] */
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_MASK                    0x000003c0
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved2_SHIFT                   6

/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_MASK           0x00000020
#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_SHIFT          5
#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT        0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_MASK          0x00000010
#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_SHIFT         4
#define BCHP_HIF_INTR2_CPU_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT       0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK       0x00000008
#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT      3
#define BCHP_HIF_INTR2_CPU_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT    0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_MASK                    0x00000004
#define BCHP_HIF_INTR2_CPU_CLEAR_reserved3_SHIFT                   2

/* HIF_INTR2 :: CPU_CLEAR :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_MASK                0x00000002
#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_SHIFT               1
#define BCHP_HIF_INTR2_CPU_CLEAR_ITCH1_RD_INTR_DEFAULT             0x00000000

/* HIF_INTR2 :: CPU_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
#define BCHP_HIF_INTR2_CPU_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000

/***************************************************************************
 *CPU_MASK_STATUS - CPU interrupt Mask Status Register
 ***************************************************************************/
/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_0_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_LINKDOWN_INTR_MASK   0x80000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_LINKDOWN_INTR_SHIFT  31
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_0_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_LINKUP_INTR_MASK     0x40000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_LINKUP_INTR_SHIFT    30
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_LINKUP_INTR_DEFAULT  0x00000000

/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_1_LINKDOWN_INTR [29:29] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_LINKDOWN_INTR_MASK   0x20000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_LINKDOWN_INTR_SHIFT  29
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_1_LINKUP_INTR [28:28] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_LINKUP_INTR_MASK     0x10000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_LINKUP_INTR_SHIFT    28
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_LINKUP_INTR_DEFAULT  0x00000000

/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved0 [19:16] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_MASK              0x000f0000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved0_SHIFT             16

/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_MASK          0x00008000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_SHIFT         15
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH0_RD_INTR_DEFAULT       0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved1 [14:14] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_MASK              0x00004000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved1_SHIFT             14

/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_0_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_RG_BRIDGE_INTR_MASK  0x00002000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_1_RG_BRIDGE_INTR [11:11] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_RG_BRIDGE_INTR_MASK  0x00000800
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved2 [09:06] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_MASK              0x000003c0
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved2_SHIFT             6

/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK     0x00000020
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT    5
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT  0x00000000

/* HIF_INTR2 :: CPU_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK    0x00000010
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT   4
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: CPU_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: CPU_MASK_STATUS :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_MASK              0x00000004
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_reserved3_SHIFT             2

/* HIF_INTR2 :: CPU_MASK_STATUS :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_MASK          0x00000002
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_SHIFT         1
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_ITCH1_RD_INTR_DEFAULT       0x00000001

/* HIF_INTR2 :: CPU_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
#define BCHP_HIF_INTR2_CPU_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001

/***************************************************************************
 *CPU_MASK_SET - CPU interrupt Mask Set Register
 ***************************************************************************/
/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_0_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_LINKDOWN_INTR_MASK      0x80000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_LINKDOWN_INTR_SHIFT     31
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_LINKDOWN_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_0_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_LINKUP_INTR_MASK        0x40000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_LINKUP_INTR_SHIFT       30
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_LINKUP_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_1_LINKDOWN_INTR [29:29] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_LINKDOWN_INTR_MASK      0x20000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_LINKDOWN_INTR_SHIFT     29
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_LINKDOWN_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_1_LINKUP_INTR [28:28] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_LINKUP_INTR_MASK        0x10000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_LINKUP_INTR_SHIFT       28
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_LINKUP_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_SHIFT           27
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_SHIFT            26
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
#define BCHP_HIF_INTR2_CPU_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: reserved0 [19:16] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_MASK                 0x000f0000
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved0_SHIFT                16

/* HIF_INTR2 :: CPU_MASK_SET :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_MASK             0x00008000
#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_SHIFT            15
#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH0_RD_INTR_DEFAULT          0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: reserved1 [14:14] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_MASK                 0x00004000
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved1_SHIFT                14

/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_0_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_RG_BRIDGE_INTR_MASK     0x00002000
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_RG_BRIDGE_INTR_SHIFT    13
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_RG_BRIDGE_INTR_DEFAULT  0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_RGR_BRIDGE_INTR_MASK    0x00001000
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_RGR_BRIDGE_INTR_SHIFT   12
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_1_RG_BRIDGE_INTR [11:11] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_RG_BRIDGE_INTR_MASK     0x00000800
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_RG_BRIDGE_INTR_SHIFT    11
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_RG_BRIDGE_INTR_DEFAULT  0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_RGR_BRIDGE_INTR_MASK    0x00000400
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_RGR_BRIDGE_INTR_SHIFT   10
#define BCHP_HIF_INTR2_CPU_MASK_SET_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: reserved2 [09:06] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_MASK                 0x000003c0
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved2_SHIFT                6

/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_MASK        0x00000020
#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT       5
#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: CPU_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_MASK       0x00000010
#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT      4
#define BCHP_HIF_INTR2_CPU_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT    0x00000000

/* HIF_INTR2 :: CPU_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK    0x00000008
#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT   3
#define BCHP_HIF_INTR2_CPU_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: CPU_MASK_SET :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_MASK                 0x00000004
#define BCHP_HIF_INTR2_CPU_MASK_SET_reserved3_SHIFT                2

/* HIF_INTR2 :: CPU_MASK_SET :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_MASK             0x00000002
#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_SHIFT            1
#define BCHP_HIF_INTR2_CPU_MASK_SET_ITCH1_RD_INTR_DEFAULT          0x00000001

/* HIF_INTR2 :: CPU_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
#define BCHP_HIF_INTR2_CPU_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001

/***************************************************************************
 *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
 ***************************************************************************/
/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_0_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_LINKDOWN_INTR_MASK    0x80000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_LINKDOWN_INTR_SHIFT   31
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_0_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_LINKUP_INTR_MASK      0x40000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_LINKUP_INTR_SHIFT     30
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_LINKUP_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_1_LINKDOWN_INTR [29:29] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_LINKDOWN_INTR_MASK    0x20000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_LINKDOWN_INTR_SHIFT   29
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_1_LINKUP_INTR [28:28] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_LINKUP_INTR_MASK      0x10000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_LINKUP_INTR_SHIFT     28
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_LINKUP_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved0 [19:16] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_MASK               0x000f0000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT              16

/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_MASK           0x00008000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_SHIFT          15
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT        0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved1 [14:14] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_MASK               0x00004000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved1_SHIFT              14

/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_0_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_RG_BRIDGE_INTR_MASK   0x00002000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_RG_BRIDGE_INTR_SHIFT  13
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_RGR_BRIDGE_INTR_MASK  0x00001000
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_1_RG_BRIDGE_INTR [11:11] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_RG_BRIDGE_INTR_MASK   0x00000800
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_RG_BRIDGE_INTR_SHIFT  11
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_RGR_BRIDGE_INTR_MASK  0x00000400
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved2 [09:06] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_MASK               0x000003c0
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved2_SHIFT              6

/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK      0x00000020
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT     5
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: CPU_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK     0x00000010
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT    4
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT  0x00000000

/* HIF_INTR2 :: CPU_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK  0x00000008
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: CPU_MASK_CLEAR :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_MASK               0x00000004
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_reserved3_SHIFT              2

/* HIF_INTR2 :: CPU_MASK_CLEAR :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_MASK           0x00000002
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_SHIFT          1
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_ITCH1_RD_INTR_DEFAULT        0x00000001

/* HIF_INTR2 :: CPU_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
#define BCHP_HIF_INTR2_CPU_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001

/***************************************************************************
 *PCI_STATUS - PCI interrupt Status Register
 ***************************************************************************/
/* HIF_INTR2 :: PCI_STATUS :: PCIE_0_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_LINKDOWN_INTR_MASK        0x80000000
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_LINKDOWN_INTR_SHIFT       31
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_LINKDOWN_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: PCI_STATUS :: PCIE_0_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_LINKUP_INTR_MASK          0x40000000
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_LINKUP_INTR_SHIFT         30
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_LINKUP_INTR_DEFAULT       0x00000000

/* HIF_INTR2 :: PCI_STATUS :: PCIE_1_LINKDOWN_INTR [29:29] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_LINKDOWN_INTR_MASK        0x20000000
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_LINKDOWN_INTR_SHIFT       29
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_LINKDOWN_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: PCI_STATUS :: PCIE_1_LINKUP_INTR [28:28] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_LINKUP_INTR_MASK          0x10000000
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_LINKUP_INTR_SHIFT         28
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_LINKUP_INTR_DEFAULT       0x00000000

/* HIF_INTR2 :: PCI_STATUS :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_MASK              0x08000000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_SHIFT             27
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CORR_INTR_DEFAULT           0x00000000

/* HIF_INTR2 :: PCI_STATUS :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_MASK               0x04000000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_SHIFT              26
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_UNC_INTR_DEFAULT            0x00000000

/* HIF_INTR2 :: PCI_STATUS :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_MASK             0x02000000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_SHIFT            25
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_RBPIN_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: PCI_STATUS :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_MASK            0x01000000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_SHIFT           24
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CTLRDY_INTR_DEFAULT         0x00000000

/* HIF_INTR2 :: PCI_STATUS :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_MASK             0x00800000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_SHIFT            23
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_PGMPG_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: PCI_STATUS :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_MASK             0x00400000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_SHIFT            22
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_CPYBK_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: PCI_STATUS :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_MASK            0x00200000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_SHIFT           21
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_BLKERA_INTR_DEFAULT         0x00000000

/* HIF_INTR2 :: PCI_STATUS :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_MASK           0x00100000
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_SHIFT          20
#define BCHP_HIF_INTR2_PCI_STATUS_NAND_NP_READ_INTR_DEFAULT        0x00000000

/* HIF_INTR2 :: PCI_STATUS :: reserved0 [19:16] */
#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_MASK                   0x000f0000
#define BCHP_HIF_INTR2_PCI_STATUS_reserved0_SHIFT                  16

/* HIF_INTR2 :: PCI_STATUS :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_MASK               0x00008000
#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_SHIFT              15
#define BCHP_HIF_INTR2_PCI_STATUS_ITCH0_RD_INTR_DEFAULT            0x00000000

/* HIF_INTR2 :: PCI_STATUS :: reserved1 [14:14] */
#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_MASK                   0x00004000
#define BCHP_HIF_INTR2_PCI_STATUS_reserved1_SHIFT                  14

/* HIF_INTR2 :: PCI_STATUS :: PCIE_0_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_RG_BRIDGE_INTR_MASK       0x00002000
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_RG_BRIDGE_INTR_SHIFT      13
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_RG_BRIDGE_INTR_DEFAULT    0x00000000

/* HIF_INTR2 :: PCI_STATUS :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_RGR_BRIDGE_INTR_MASK      0x00001000
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_RGR_BRIDGE_INTR_SHIFT     12
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_0_RGR_BRIDGE_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: PCI_STATUS :: PCIE_1_RG_BRIDGE_INTR [11:11] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_RG_BRIDGE_INTR_MASK       0x00000800
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_RG_BRIDGE_INTR_SHIFT      11
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_RG_BRIDGE_INTR_DEFAULT    0x00000000

/* HIF_INTR2 :: PCI_STATUS :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_RGR_BRIDGE_INTR_MASK      0x00000400
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_RGR_BRIDGE_INTR_SHIFT     10
#define BCHP_HIF_INTR2_PCI_STATUS_PCIE_1_RGR_BRIDGE_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: PCI_STATUS :: reserved2 [09:06] */
#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_MASK                   0x000003c0
#define BCHP_HIF_INTR2_PCI_STATUS_reserved2_SHIFT                  6

/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_MASK          0x00000020
#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_SHIFT         5
#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_ERR_INTR_DEFAULT       0x00000000

/* HIF_INTR2 :: PCI_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_MASK         0x00000010
#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_SHIFT        4
#define BCHP_HIF_INTR2_PCI_STATUS_FLASH_DMA_DONE_INTR_DEFAULT      0x00000000

/* HIF_INTR2 :: PCI_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK      0x00000008
#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT     3
#define BCHP_HIF_INTR2_PCI_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: PCI_STATUS :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_MASK                   0x00000004
#define BCHP_HIF_INTR2_PCI_STATUS_reserved3_SHIFT                  2

/* HIF_INTR2 :: PCI_STATUS :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_MASK               0x00000002
#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_SHIFT              1
#define BCHP_HIF_INTR2_PCI_STATUS_ITCH1_RD_INTR_DEFAULT            0x00000000

/* HIF_INTR2 :: PCI_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_MASK        0x00000001
#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT       0
#define BCHP_HIF_INTR2_PCI_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT     0x00000000

/***************************************************************************
 *PCI_SET - PCI interrupt Set Register
 ***************************************************************************/
/* HIF_INTR2 :: PCI_SET :: PCIE_0_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_LINKDOWN_INTR_MASK           0x80000000
#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_LINKDOWN_INTR_SHIFT          31
#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_LINKDOWN_INTR_DEFAULT        0x00000000

/* HIF_INTR2 :: PCI_SET :: PCIE_0_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_LINKUP_INTR_MASK             0x40000000
#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_LINKUP_INTR_SHIFT            30
#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_LINKUP_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: PCI_SET :: PCIE_1_LINKDOWN_INTR [29:29] */
#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_LINKDOWN_INTR_MASK           0x20000000
#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_LINKDOWN_INTR_SHIFT          29
#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_LINKDOWN_INTR_DEFAULT        0x00000000

/* HIF_INTR2 :: PCI_SET :: PCIE_1_LINKUP_INTR [28:28] */
#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_LINKUP_INTR_MASK             0x10000000
#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_LINKUP_INTR_SHIFT            28
#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_LINKUP_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: PCI_SET :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_MASK                 0x08000000
#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_SHIFT                27
#define BCHP_HIF_INTR2_PCI_SET_NAND_CORR_INTR_DEFAULT              0x00000000

/* HIF_INTR2 :: PCI_SET :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_MASK                  0x04000000
#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_SHIFT                 26
#define BCHP_HIF_INTR2_PCI_SET_NAND_UNC_INTR_DEFAULT               0x00000000

/* HIF_INTR2 :: PCI_SET :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_MASK                0x02000000
#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_SHIFT               25
#define BCHP_HIF_INTR2_PCI_SET_NAND_RBPIN_INTR_DEFAULT             0x00000000

/* HIF_INTR2 :: PCI_SET :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_MASK               0x01000000
#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_SHIFT              24
#define BCHP_HIF_INTR2_PCI_SET_NAND_CTLRDY_INTR_DEFAULT            0x00000000

/* HIF_INTR2 :: PCI_SET :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_MASK                0x00800000
#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_SHIFT               23
#define BCHP_HIF_INTR2_PCI_SET_NAND_PGMPG_INTR_DEFAULT             0x00000000

/* HIF_INTR2 :: PCI_SET :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_MASK                0x00400000
#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_SHIFT               22
#define BCHP_HIF_INTR2_PCI_SET_NAND_CPYBK_INTR_DEFAULT             0x00000000

/* HIF_INTR2 :: PCI_SET :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_MASK               0x00200000
#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_SHIFT              21
#define BCHP_HIF_INTR2_PCI_SET_NAND_BLKERA_INTR_DEFAULT            0x00000000

/* HIF_INTR2 :: PCI_SET :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_MASK              0x00100000
#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_SHIFT             20
#define BCHP_HIF_INTR2_PCI_SET_NAND_NP_READ_INTR_DEFAULT           0x00000000

/* HIF_INTR2 :: PCI_SET :: reserved0 [19:16] */
#define BCHP_HIF_INTR2_PCI_SET_reserved0_MASK                      0x000f0000
#define BCHP_HIF_INTR2_PCI_SET_reserved0_SHIFT                     16

/* HIF_INTR2 :: PCI_SET :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_MASK                  0x00008000
#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_SHIFT                 15
#define BCHP_HIF_INTR2_PCI_SET_ITCH0_RD_INTR_DEFAULT               0x00000000

/* HIF_INTR2 :: PCI_SET :: reserved1 [14:14] */
#define BCHP_HIF_INTR2_PCI_SET_reserved1_MASK                      0x00004000
#define BCHP_HIF_INTR2_PCI_SET_reserved1_SHIFT                     14

/* HIF_INTR2 :: PCI_SET :: PCIE_0_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_RG_BRIDGE_INTR_MASK          0x00002000
#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_RG_BRIDGE_INTR_SHIFT         13
#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_RG_BRIDGE_INTR_DEFAULT       0x00000000

/* HIF_INTR2 :: PCI_SET :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_RGR_BRIDGE_INTR_MASK         0x00001000
#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_RGR_BRIDGE_INTR_SHIFT        12
#define BCHP_HIF_INTR2_PCI_SET_PCIE_0_RGR_BRIDGE_INTR_DEFAULT      0x00000000

/* HIF_INTR2 :: PCI_SET :: PCIE_1_RG_BRIDGE_INTR [11:11] */
#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_RG_BRIDGE_INTR_MASK          0x00000800
#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_RG_BRIDGE_INTR_SHIFT         11
#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_RG_BRIDGE_INTR_DEFAULT       0x00000000

/* HIF_INTR2 :: PCI_SET :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_RGR_BRIDGE_INTR_MASK         0x00000400
#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_RGR_BRIDGE_INTR_SHIFT        10
#define BCHP_HIF_INTR2_PCI_SET_PCIE_1_RGR_BRIDGE_INTR_DEFAULT      0x00000000

/* HIF_INTR2 :: PCI_SET :: reserved2 [09:06] */
#define BCHP_HIF_INTR2_PCI_SET_reserved2_MASK                      0x000003c0
#define BCHP_HIF_INTR2_PCI_SET_reserved2_SHIFT                     6

/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_MASK             0x00000020
#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_SHIFT            5
#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_ERR_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: PCI_SET :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_MASK            0x00000010
#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_SHIFT           4
#define BCHP_HIF_INTR2_PCI_SET_FLASH_DMA_DONE_INTR_DEFAULT         0x00000000

/* HIF_INTR2 :: PCI_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_MASK         0x00000008
#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT        3
#define BCHP_HIF_INTR2_PCI_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT      0x00000000

/* HIF_INTR2 :: PCI_SET :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_PCI_SET_reserved3_MASK                      0x00000004
#define BCHP_HIF_INTR2_PCI_SET_reserved3_SHIFT                     2

/* HIF_INTR2 :: PCI_SET :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_MASK                  0x00000002
#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_SHIFT                 1
#define BCHP_HIF_INTR2_PCI_SET_ITCH1_RD_INTR_DEFAULT               0x00000000

/* HIF_INTR2 :: PCI_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_MASK           0x00000001
#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_SHIFT          0
#define BCHP_HIF_INTR2_PCI_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT        0x00000000

/***************************************************************************
 *PCI_CLEAR - PCI interrupt Clear Register
 ***************************************************************************/
/* HIF_INTR2 :: PCI_CLEAR :: PCIE_0_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_LINKDOWN_INTR_MASK         0x80000000
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_LINKDOWN_INTR_SHIFT        31
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_LINKDOWN_INTR_DEFAULT      0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: PCIE_0_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_LINKUP_INTR_MASK           0x40000000
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_LINKUP_INTR_SHIFT          30
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_LINKUP_INTR_DEFAULT        0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: PCIE_1_LINKDOWN_INTR [29:29] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_LINKDOWN_INTR_MASK         0x20000000
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_LINKDOWN_INTR_SHIFT        29
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_LINKDOWN_INTR_DEFAULT      0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: PCIE_1_LINKUP_INTR [28:28] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_LINKUP_INTR_MASK           0x10000000
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_LINKUP_INTR_SHIFT          28
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_LINKUP_INTR_DEFAULT        0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_MASK               0x08000000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_SHIFT              27
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CORR_INTR_DEFAULT            0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_MASK                0x04000000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_SHIFT               26
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_UNC_INTR_DEFAULT             0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_MASK              0x02000000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_SHIFT             25
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_RBPIN_INTR_DEFAULT           0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_MASK             0x01000000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_SHIFT            24
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CTLRDY_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_MASK              0x00800000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_SHIFT             23
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_PGMPG_INTR_DEFAULT           0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_MASK              0x00400000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_SHIFT             22
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_CPYBK_INTR_DEFAULT           0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_MASK             0x00200000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_SHIFT            21
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_BLKERA_INTR_DEFAULT          0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_MASK            0x00100000
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_SHIFT           20
#define BCHP_HIF_INTR2_PCI_CLEAR_NAND_NP_READ_INTR_DEFAULT         0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: reserved0 [19:16] */
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_MASK                    0x000f0000
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved0_SHIFT                   16

/* HIF_INTR2 :: PCI_CLEAR :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_MASK                0x00008000
#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_SHIFT               15
#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH0_RD_INTR_DEFAULT             0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: reserved1 [14:14] */
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_MASK                    0x00004000
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved1_SHIFT                   14

/* HIF_INTR2 :: PCI_CLEAR :: PCIE_0_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_RG_BRIDGE_INTR_MASK        0x00002000
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_RG_BRIDGE_INTR_SHIFT       13
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_RG_BRIDGE_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_RGR_BRIDGE_INTR_MASK       0x00001000
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_RGR_BRIDGE_INTR_SHIFT      12
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_0_RGR_BRIDGE_INTR_DEFAULT    0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: PCIE_1_RG_BRIDGE_INTR [11:11] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_RG_BRIDGE_INTR_MASK        0x00000800
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_RG_BRIDGE_INTR_SHIFT       11
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_RG_BRIDGE_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_RGR_BRIDGE_INTR_MASK       0x00000400
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_RGR_BRIDGE_INTR_SHIFT      10
#define BCHP_HIF_INTR2_PCI_CLEAR_PCIE_1_RGR_BRIDGE_INTR_DEFAULT    0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: reserved2 [09:06] */
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_MASK                    0x000003c0
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved2_SHIFT                   6

/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_MASK           0x00000020
#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_SHIFT          5
#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT        0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_MASK          0x00000010
#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_SHIFT         4
#define BCHP_HIF_INTR2_PCI_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT       0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK       0x00000008
#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT      3
#define BCHP_HIF_INTR2_PCI_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT    0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_MASK                    0x00000004
#define BCHP_HIF_INTR2_PCI_CLEAR_reserved3_SHIFT                   2

/* HIF_INTR2 :: PCI_CLEAR :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_MASK                0x00000002
#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_SHIFT               1
#define BCHP_HIF_INTR2_PCI_CLEAR_ITCH1_RD_INTR_DEFAULT             0x00000000

/* HIF_INTR2 :: PCI_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK         0x00000001
#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT        0
#define BCHP_HIF_INTR2_PCI_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT      0x00000000

/***************************************************************************
 *PCI_MASK_STATUS - PCI interrupt Mask Status Register
 ***************************************************************************/
/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_0_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_LINKDOWN_INTR_MASK   0x80000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_LINKDOWN_INTR_SHIFT  31
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_0_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_LINKUP_INTR_MASK     0x40000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_LINKUP_INTR_SHIFT    30
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_LINKUP_INTR_DEFAULT  0x00000000

/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_1_LINKDOWN_INTR [29:29] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_LINKDOWN_INTR_MASK   0x20000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_LINKDOWN_INTR_SHIFT  29
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_1_LINKUP_INTR [28:28] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_LINKUP_INTR_MASK     0x10000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_LINKUP_INTR_SHIFT    28
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_LINKUP_INTR_DEFAULT  0x00000000

/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_MASK         0x08000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_SHIFT        27
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CORR_INTR_DEFAULT      0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_MASK          0x04000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_SHIFT         26
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_UNC_INTR_DEFAULT       0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_MASK        0x02000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_SHIFT       25
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_RBPIN_INTR_DEFAULT     0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_MASK       0x01000000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_SHIFT      24
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CTLRDY_INTR_DEFAULT    0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_MASK        0x00800000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_SHIFT       23
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_PGMPG_INTR_DEFAULT     0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_MASK        0x00400000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_SHIFT       22
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_CPYBK_INTR_DEFAULT     0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_MASK       0x00200000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_SHIFT      21
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_BLKERA_INTR_DEFAULT    0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_MASK      0x00100000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_SHIFT     20
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_NAND_NP_READ_INTR_DEFAULT   0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved0 [19:16] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_MASK              0x000f0000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved0_SHIFT             16

/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_MASK          0x00008000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_SHIFT         15
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH0_RD_INTR_DEFAULT       0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved1 [14:14] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_MASK              0x00004000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved1_SHIFT             14

/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_0_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_RG_BRIDGE_INTR_MASK  0x00002000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_RG_BRIDGE_INTR_SHIFT 13
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_RGR_BRIDGE_INTR_MASK 0x00001000
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_1_RG_BRIDGE_INTR [11:11] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_RG_BRIDGE_INTR_MASK  0x00000800
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_RG_BRIDGE_INTR_SHIFT 11
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_RGR_BRIDGE_INTR_MASK 0x00000400
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved2 [09:06] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_MASK              0x000003c0
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved2_SHIFT             6

/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_MASK     0x00000020
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_SHIFT    5
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_ERR_INTR_DEFAULT  0x00000000

/* HIF_INTR2 :: PCI_MASK_STATUS :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_MASK    0x00000010
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_SHIFT   4
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_FLASH_DMA_DONE_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: PCI_MASK_STATUS :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_MASK 0x00000008
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: PCI_MASK_STATUS :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_MASK              0x00000004
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_reserved3_SHIFT             2

/* HIF_INTR2 :: PCI_MASK_STATUS :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_MASK          0x00000002
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_SHIFT         1
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_ITCH1_RD_INTR_DEFAULT       0x00000001

/* HIF_INTR2 :: PCI_MASK_STATUS :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_MASK   0x00000001
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_SHIFT  0
#define BCHP_HIF_INTR2_PCI_MASK_STATUS_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001

/***************************************************************************
 *PCI_MASK_SET - PCI interrupt Mask Set Register
 ***************************************************************************/
/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_0_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_LINKDOWN_INTR_MASK      0x80000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_LINKDOWN_INTR_SHIFT     31
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_LINKDOWN_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_0_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_LINKUP_INTR_MASK        0x40000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_LINKUP_INTR_SHIFT       30
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_LINKUP_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_1_LINKDOWN_INTR [29:29] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_LINKDOWN_INTR_MASK      0x20000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_LINKDOWN_INTR_SHIFT     29
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_LINKDOWN_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_1_LINKUP_INTR [28:28] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_LINKUP_INTR_MASK        0x10000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_LINKUP_INTR_SHIFT       28
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_LINKUP_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_MASK            0x08000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_SHIFT           27
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CORR_INTR_DEFAULT         0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_MASK             0x04000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_SHIFT            26
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_UNC_INTR_DEFAULT          0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_MASK           0x02000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_SHIFT          25
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_RBPIN_INTR_DEFAULT        0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_MASK          0x01000000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_SHIFT         24
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CTLRDY_INTR_DEFAULT       0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_MASK           0x00800000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_SHIFT          23
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_PGMPG_INTR_DEFAULT        0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_MASK           0x00400000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_SHIFT          22
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_CPYBK_INTR_DEFAULT        0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_MASK          0x00200000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_SHIFT         21
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_BLKERA_INTR_DEFAULT       0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_MASK         0x00100000
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_SHIFT        20
#define BCHP_HIF_INTR2_PCI_MASK_SET_NAND_NP_READ_INTR_DEFAULT      0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: reserved0 [19:16] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_MASK                 0x000f0000
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved0_SHIFT                16

/* HIF_INTR2 :: PCI_MASK_SET :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_MASK             0x00008000
#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_SHIFT            15
#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH0_RD_INTR_DEFAULT          0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: reserved1 [14:14] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_MASK                 0x00004000
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved1_SHIFT                14

/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_0_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_RG_BRIDGE_INTR_MASK     0x00002000
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_RG_BRIDGE_INTR_SHIFT    13
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_RG_BRIDGE_INTR_DEFAULT  0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_RGR_BRIDGE_INTR_MASK    0x00001000
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_RGR_BRIDGE_INTR_SHIFT   12
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_1_RG_BRIDGE_INTR [11:11] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_RG_BRIDGE_INTR_MASK     0x00000800
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_RG_BRIDGE_INTR_SHIFT    11
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_RG_BRIDGE_INTR_DEFAULT  0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_RGR_BRIDGE_INTR_MASK    0x00000400
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_RGR_BRIDGE_INTR_SHIFT   10
#define BCHP_HIF_INTR2_PCI_MASK_SET_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: reserved2 [09:06] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_MASK                 0x000003c0
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved2_SHIFT                6

/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_MASK        0x00000020
#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_SHIFT       5
#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_ERR_INTR_DEFAULT     0x00000000

/* HIF_INTR2 :: PCI_MASK_SET :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_MASK       0x00000010
#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_SHIFT      4
#define BCHP_HIF_INTR2_PCI_MASK_SET_FLASH_DMA_DONE_INTR_DEFAULT    0x00000000

/* HIF_INTR2 :: PCI_MASK_SET :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_MASK    0x00000008
#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_SHIFT   3
#define BCHP_HIF_INTR2_PCI_MASK_SET_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: PCI_MASK_SET :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_MASK                 0x00000004
#define BCHP_HIF_INTR2_PCI_MASK_SET_reserved3_SHIFT                2

/* HIF_INTR2 :: PCI_MASK_SET :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_MASK             0x00000002
#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_SHIFT            1
#define BCHP_HIF_INTR2_PCI_MASK_SET_ITCH1_RD_INTR_DEFAULT          0x00000001

/* HIF_INTR2 :: PCI_MASK_SET :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_MASK      0x00000001
#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_SHIFT     0
#define BCHP_HIF_INTR2_PCI_MASK_SET_HIF_RGR2_BRIDGE_INTR_DEFAULT   0x00000001

/***************************************************************************
 *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
 ***************************************************************************/
/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_0_LINKDOWN_INTR [31:31] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_LINKDOWN_INTR_MASK    0x80000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_LINKDOWN_INTR_SHIFT   31
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_LINKDOWN_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_0_LINKUP_INTR [30:30] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_LINKUP_INTR_MASK      0x40000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_LINKUP_INTR_SHIFT     30
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_LINKUP_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_1_LINKDOWN_INTR [29:29] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_LINKDOWN_INTR_MASK    0x20000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_LINKDOWN_INTR_SHIFT   29
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_LINKDOWN_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_1_LINKUP_INTR [28:28] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_LINKUP_INTR_MASK      0x10000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_LINKUP_INTR_SHIFT     28
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_LINKUP_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CORR_INTR [27:27] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_MASK          0x08000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_SHIFT         27
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CORR_INTR_DEFAULT       0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_UNC_INTR [26:26] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_MASK           0x04000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_SHIFT          26
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_UNC_INTR_DEFAULT        0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_RBPIN_INTR [25:25] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_MASK         0x02000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_SHIFT        25
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_RBPIN_INTR_DEFAULT      0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CTLRDY_INTR [24:24] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_MASK        0x01000000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_SHIFT       24
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CTLRDY_INTR_DEFAULT     0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_PGMPG_INTR [23:23] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_MASK         0x00800000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_SHIFT        23
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_PGMPG_INTR_DEFAULT      0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_CPYBK_INTR [22:22] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_MASK         0x00400000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_SHIFT        22
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_CPYBK_INTR_DEFAULT      0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_BLKERA_INTR [21:21] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_MASK        0x00200000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_SHIFT       21
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_BLKERA_INTR_DEFAULT     0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: NAND_NP_READ_INTR [20:20] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_MASK       0x00100000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_SHIFT      20
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_NAND_NP_READ_INTR_DEFAULT    0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved0 [19:16] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_MASK               0x000f0000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT              16

/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH0_RD_INTR [15:15] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_MASK           0x00008000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_SHIFT          15
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH0_RD_INTR_DEFAULT        0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved1 [14:14] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_MASK               0x00004000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved1_SHIFT              14

/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_0_RG_BRIDGE_INTR [13:13] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_RG_BRIDGE_INTR_MASK   0x00002000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_RG_BRIDGE_INTR_SHIFT  13
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_RG_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_0_RGR_BRIDGE_INTR [12:12] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_RGR_BRIDGE_INTR_MASK  0x00001000
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_RGR_BRIDGE_INTR_SHIFT 12
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_0_RGR_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_1_RG_BRIDGE_INTR [11:11] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_RG_BRIDGE_INTR_MASK   0x00000800
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_RG_BRIDGE_INTR_SHIFT  11
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_RG_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: PCIE_1_RGR_BRIDGE_INTR [10:10] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_RGR_BRIDGE_INTR_MASK  0x00000400
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_RGR_BRIDGE_INTR_SHIFT 10
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_PCIE_1_RGR_BRIDGE_INTR_DEFAULT 0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved2 [09:06] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_MASK               0x000003c0
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved2_SHIFT              6

/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_ERR_INTR [05:05] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_MASK      0x00000020
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_SHIFT     5
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_ERR_INTR_DEFAULT   0x00000000

/* HIF_INTR2 :: PCI_MASK_CLEAR :: FLASH_DMA_DONE_INTR [04:04] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_MASK     0x00000010
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_SHIFT    4
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_FLASH_DMA_DONE_INTR_DEFAULT  0x00000000

/* HIF_INTR2 :: PCI_MASK_CLEAR :: WEBHIF_WD_TIMEOUT_INTR [03:03] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_MASK  0x00000008
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_SHIFT 3
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_WEBHIF_WD_TIMEOUT_INTR_DEFAULT 0x00000000

/* HIF_INTR2 :: PCI_MASK_CLEAR :: reserved3 [02:02] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_MASK               0x00000004
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_reserved3_SHIFT              2

/* HIF_INTR2 :: PCI_MASK_CLEAR :: ITCH1_RD_INTR [01:01] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_MASK           0x00000002
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_SHIFT          1
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_ITCH1_RD_INTR_DEFAULT        0x00000001

/* HIF_INTR2 :: PCI_MASK_CLEAR :: HIF_RGR2_BRIDGE_INTR [00:00] */
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_MASK    0x00000001
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_SHIFT   0
#define BCHP_HIF_INTR2_PCI_MASK_CLEAR_HIF_RGR2_BRIDGE_INTR_DEFAULT 0x00000001

#endif /* #ifndef BCHP_HIF_INTR2_H__ */

/* End of File */