/****************************************************************************
 *     Copyright (c) 1999-2014, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on               Wed Feb 18 03:13:18 2015
 *                 Full Compile MD5 Checksum  e2f31009bf32b83eddf082e72de66fc9
 *                     (minus title and desc)
 *                 MD5 Checksum               5d3a169247e37ce28e4167f85d3a548a
 *
 * Compiled with:  RDB Utility                combo_header.pl
 *                 RDB.pm                     15517
 *                 unknown                    unknown
 *                 Perl Interpreter           5.008008
 *                 Operating System           linux
 *
 *
 ***************************************************************************/

#ifndef BCHP_USB_CTRL_H__
#define BCHP_USB_CTRL_H__

/***************************************************************************
 *USB_CTRL - USB Control Registers
 ***************************************************************************/
#define BCHP_USB_CTRL_SETUP                      0x00480200 /* [RW] Setup Register */
#define BCHP_USB_CTRL_PLL_CTL                    0x00480204 /* [RW] PLL Control Register */
#define BCHP_USB_CTRL_FLADJ_VALUE                0x00480208 /* [RW] Frame Adjust Value */
#define BCHP_USB_CTRL_EBRIDGE                    0x0048020c /* [RW] Control Register for EHCI Bridge */
#define BCHP_USB_CTRL_OBRIDGE                    0x00480210 /* [RW] Control Register for OHCI Bridge */
#define BCHP_USB_CTRL_MDIO                       0x00480214 /* [RW] MDIO Interface Programming Register */
#define BCHP_USB_CTRL_MDIO2                      0x00480218 /* [RO] MDIO Interface Read Register */
#define BCHP_USB_CTRL_TEST_PORT_CTL              0x0048021c /* [RW] Test Port Control Register */
#define BCHP_USB_CTRL_USB_SIMCTL                 0x00480220 /* [RW] Simulation Register */
#define BCHP_USB_CTRL_USB_TESTCTL                0x00480224 /* [RW] Throutput Test Control */
#define BCHP_USB_CTRL_USB_TESTMON                0x00480228 /* [RO] Throughput Test Monitor */
#define BCHP_USB_CTRL_UTMI_CTL_1                 0x0048022c /* [RW] UTMI Control Register */
#define BCHP_USB_CTRL_UTMI_CTL_2                 0x00480230 /* [RW] UTMI Control 2 Register */
#define BCHP_USB_CTRL_USB_PM                     0x00480234 /* [RW] Power Management Register */
#define BCHP_USB_CTRL_USB_PM_STATUS              0x00480238 /* [RW] usb20 Power Management Status Register */
#define BCHP_USB_CTRL_OHCI_ADDR_EXT              0x0048023c /* [RW] OHCI ADDRESS Extension */
#define BCHP_USB_CTRL_PLL_LDO_CTL                0x00480240 /* [RW] 28NM USBPHY LDO Control */
#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS            0x00480244 /* [RW] 28NM USBPHY PLLBIAS Control */
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL            0x00480248 /* [RW] 28NM USBPHY AFE Bandgap Control */
#define BCHP_USB_CTRL_AFE_USBIO_TST              0x0048024c /* [RW] 28NM USBPHY AFE Bandgap Control */
#define BCHP_USB_CTRL_PLL_NDIV_FRAC              0x00480250 /* [RW] PLL Feedback Divider Control Register */
#define BCHP_USB_CTRL_TP_DIAG                    0x00480254 /* [RW] diagnostic for tp bus */
#define BCHP_USB_CTRL_SPARE3                     0x00480258 /* [RW] Spare1 Register for future use */
#define BCHP_USB_CTRL_SPARE4                     0x0048025c /* [RW] Spare1 Register for future use */
#define BCHP_USB_CTRL_USB30_CTL1                 0x00480260 /* [RW] USB30 CONTROL Register 1 */
#define BCHP_USB_CTRL_USB30_CTL2                 0x00480264 /* [RW] USB30 CONTROL Register 2 */
#define BCHP_USB_CTRL_USB30_CTL3                 0x00480268 /* [RW] USB30 CONTROL Register 3 */
#define BCHP_USB_CTRL_USB30_CTL4                 0x0048026c /* [RW] USB30 CONTROL Register 4 */
#define BCHP_USB_CTRL_USB30_PCTL                 0x00480270 /* [RW] USB30 PORT CONTROL Register */
#define BCHP_USB_CTRL_USB30_CTL5                 0x00480274 /* [RW] USB30 CONTROL Register 5 */
#define BCHP_USB_CTRL_SPARE5                     0x00480278 /* [RW] Spare1 Register for future use */
#define BCHP_USB_CTRL_SPARE6                     0x0048027c /* [RW] Spare2 Register for future use */
#define BCHP_USB_CTRL_SCB0_BASE_RANGE            0x004802a0 /* [RW] SCB0 base start and end address */
#define BCHP_USB_CTRL_SCB1_BASE_RANGE            0x004802a4 /* [RW] SCB1 base start and end address */
#define BCHP_USB_CTRL_SCB2_BASE_RANGE            0x004802a8 /* [RW] SCB2 base start and end address */
#define BCHP_USB_CTRL_SCB0_EXTN_RANGE            0x004802ac /* [RW] SCB0 extn start and end address */
#define BCHP_USB_CTRL_SCB1_EXTN_RANGE            0x004802b0 /* [RW] SCB1 extn start and end address */
#define BCHP_USB_CTRL_SCB2_EXTN_RANGE            0x004802b4 /* [RW] SCB2 extn start and end address */
#define BCHP_USB_CTRL_USB_REVID                  0x004802fc /* [RO] USB REVID */

/***************************************************************************
 *SETUP - Setup Register
 ***************************************************************************/
/* USB_CTRL :: SETUP :: OC3_DISABLE [31:30] */
#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_MASK                       0xc0000000
#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_SHIFT                      30
#define BCHP_USB_CTRL_SETUP_OC3_DISABLE_DEFAULT                    0x00000000

/* USB_CTRL :: SETUP :: OC_DISABLE [29:28] */
#define BCHP_USB_CTRL_SETUP_OC_DISABLE_MASK                        0x30000000
#define BCHP_USB_CTRL_SETUP_OC_DISABLE_SHIFT                       28
#define BCHP_USB_CTRL_SETUP_OC_DISABLE_DEFAULT                     0x00000000

/* USB_CTRL :: SETUP :: usb_pwron_force [27:27] */
#define BCHP_USB_CTRL_SETUP_usb_pwron_force_MASK                   0x08000000
#define BCHP_USB_CTRL_SETUP_usb_pwron_force_SHIFT                  27
#define BCHP_USB_CTRL_SETUP_usb_pwron_force_DEFAULT                0x00000000

/* USB_CTRL :: SETUP :: usb_pwron_val [26:26] */
#define BCHP_USB_CTRL_SETUP_usb_pwron_val_MASK                     0x04000000
#define BCHP_USB_CTRL_SETUP_usb_pwron_val_SHIFT                    26
#define BCHP_USB_CTRL_SETUP_usb_pwron_val_DEFAULT                  0x00000000

/* USB_CTRL :: SETUP :: SETUP_SPARE [25:20] */
#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_MASK                       0x03f00000
#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_SHIFT                      20
#define BCHP_USB_CTRL_SETUP_SETUP_SPARE_DEFAULT                    0x00000000

/* USB_CTRL :: SETUP :: ohci_susp_lgcy [19:19] */
#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_MASK                    0x00080000
#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_SHIFT                   19
#define BCHP_USB_CTRL_SETUP_ohci_susp_lgcy_DEFAULT                 0x00000000

/* USB_CTRL :: SETUP :: ss_ulpi_pp2vbus [18:18] */
#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_MASK                   0x00040000
#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_SHIFT                  18
#define BCHP_USB_CTRL_SETUP_ss_ulpi_pp2vbus_DEFAULT                0x00000000

/* USB_CTRL :: SETUP :: ss_ehci64bit_en [17:17] */
#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_MASK                   0x00020000
#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_SHIFT                  17
#define BCHP_USB_CTRL_SETUP_ss_ehci64bit_en_DEFAULT                0x00000001

/* USB_CTRL :: SETUP :: async_expire_dis [16:16] */
#define BCHP_USB_CTRL_SETUP_async_expire_dis_MASK                  0x00010000
#define BCHP_USB_CTRL_SETUP_async_expire_dis_SHIFT                 16
#define BCHP_USB_CTRL_SETUP_async_expire_dis_DEFAULT               0x00000000

/* USB_CTRL :: SETUP :: scb2_en [15:15] */
#define BCHP_USB_CTRL_SETUP_scb2_en_MASK                           0x00008000
#define BCHP_USB_CTRL_SETUP_scb2_en_SHIFT                          15
#define BCHP_USB_CTRL_SETUP_scb2_en_DEFAULT                        0x00000000

/* USB_CTRL :: SETUP :: scb1_en [14:14] */
#define BCHP_USB_CTRL_SETUP_scb1_en_MASK                           0x00004000
#define BCHP_USB_CTRL_SETUP_scb1_en_SHIFT                          14
#define BCHP_USB_CTRL_SETUP_scb1_en_DEFAULT                        0x00000001

/* USB_CTRL :: SETUP :: scb0_en [13:13] */
#define BCHP_USB_CTRL_SETUP_scb0_en_MASK                           0x00002000
#define BCHP_USB_CTRL_SETUP_scb0_en_SHIFT                          13
#define BCHP_USB_CTRL_SETUP_scb0_en_DEFAULT                        0x00000001

/* USB_CTRL :: SETUP :: scb_client_swap [12:12] */
#define BCHP_USB_CTRL_SETUP_scb_client_swap_MASK                   0x00001000
#define BCHP_USB_CTRL_SETUP_scb_client_swap_SHIFT                  12
#define BCHP_USB_CTRL_SETUP_scb_client_swap_DEFAULT                0x00000000

/* USB_CTRL :: SETUP :: setup_spare1 [11:10] */
#define BCHP_USB_CTRL_SETUP_setup_spare1_MASK                      0x00000c00
#define BCHP_USB_CTRL_SETUP_setup_spare1_SHIFT                     10
#define BCHP_USB_CTRL_SETUP_setup_spare1_DEFAULT                   0x00000000

/* USB_CTRL :: SETUP :: soft_shutdown [09:09] */
#define BCHP_USB_CTRL_SETUP_soft_shutdown_MASK                     0x00000200
#define BCHP_USB_CTRL_SETUP_soft_shutdown_SHIFT                    9
#define BCHP_USB_CTRL_SETUP_soft_shutdown_DEFAULT                  0x00000000

/* USB_CTRL :: SETUP :: utmi_bkward_en [08:08] */
#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_MASK                    0x00000100
#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_SHIFT                   8
#define BCHP_USB_CTRL_SETUP_utmi_bkward_en_DEFAULT                 0x00000000

/* USB_CTRL :: SETUP :: utmi_pls_en [07:07] */
#define BCHP_USB_CTRL_SETUP_utmi_pls_en_MASK                       0x00000080
#define BCHP_USB_CTRL_SETUP_utmi_pls_en_SHIFT                      7
#define BCHP_USB_CTRL_SETUP_utmi_pls_en_DEFAULT                    0x00000000

/* USB_CTRL :: SETUP :: soft_reset [06:06] */
#define BCHP_USB_CTRL_SETUP_soft_reset_MASK                        0x00000040
#define BCHP_USB_CTRL_SETUP_soft_reset_SHIFT                       6
#define BCHP_USB_CTRL_SETUP_soft_reset_DEFAULT                     0x00000000

/* USB_CTRL :: SETUP :: IPP [05:05] */
#define BCHP_USB_CTRL_SETUP_IPP_MASK                               0x00000020
#define BCHP_USB_CTRL_SETUP_IPP_SHIFT                              5
#define BCHP_USB_CTRL_SETUP_IPP_DEFAULT                            0x00000000

/* USB_CTRL :: SETUP :: IOC [04:04] */
#define BCHP_USB_CTRL_SETUP_IOC_MASK                               0x00000010
#define BCHP_USB_CTRL_SETUP_IOC_SHIFT                              4
#define BCHP_USB_CTRL_SETUP_IOC_DEFAULT                            0x00000000

/* USB_CTRL :: SETUP :: WABO [03:03] */
#define BCHP_USB_CTRL_SETUP_WABO_MASK                              0x00000008
#define BCHP_USB_CTRL_SETUP_WABO_SHIFT                             3
#define BCHP_USB_CTRL_SETUP_WABO_DEFAULT                           0x00000000

/* USB_CTRL :: SETUP :: FNBO [02:02] */
#define BCHP_USB_CTRL_SETUP_FNBO_MASK                              0x00000004
#define BCHP_USB_CTRL_SETUP_FNBO_SHIFT                             2
#define BCHP_USB_CTRL_SETUP_FNBO_DEFAULT                           0x00000000

/* USB_CTRL :: SETUP :: FNHW [01:01] */
#define BCHP_USB_CTRL_SETUP_FNHW_MASK                              0x00000002
#define BCHP_USB_CTRL_SETUP_FNHW_SHIFT                             1
#define BCHP_USB_CTRL_SETUP_FNHW_DEFAULT                           0x00000000

/* USB_CTRL :: SETUP :: BABO [00:00] */
#define BCHP_USB_CTRL_SETUP_BABO_MASK                              0x00000001
#define BCHP_USB_CTRL_SETUP_BABO_SHIFT                             0
#define BCHP_USB_CTRL_SETUP_BABO_DEFAULT                           0x00000000

/***************************************************************************
 *PLL_CTL - PLL Control Register
 ***************************************************************************/
/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE [31:31] */
#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE_MASK                    0x80000000
#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE_SHIFT                   31
#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE_DEFAULT                 0x00000000

/* USB_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_MASK                      0x40000000
#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_SHIFT                     30
#define BCHP_USB_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                   0x00000001

/* USB_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_MASK                      0x20000000
#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                     29
#define BCHP_USB_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                   0x00000000

/* USB_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                     0x10000000
#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                    28
#define BCHP_USB_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                  0x00000001

/* USB_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                  0x08000000
#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                 27
#define BCHP_USB_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT               0x00000000

/* USB_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_MASK                          0x07000000
#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_SHIFT                         24
#define BCHP_USB_CTRL_PLL_CTL_PLL_Ka_DEFAULT                       0x00000000

/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                   0x00800000
#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                  23
#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT                0x00000000

/* USB_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_MASK                          0x00700000
#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_SHIFT                         20
#define BCHP_USB_CTRL_PLL_CTL_PLL_Ki_DEFAULT                       0x00000004

/* USB_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_MASK                          0x000f0000
#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_SHIFT                         16
#define BCHP_USB_CTRL_PLL_CTL_PLL_Kp_DEFAULT                       0x0000000a

/* USB_CTRL :: PLL_CTL :: PLL_pdiv [15:12] */
#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_MASK                        0x0000f000
#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_SHIFT                       12
#define BCHP_USB_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                     0x00000001

/* USB_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                   0x00000c00
#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                  10
#define BCHP_USB_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT                0x00000000

/* USB_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_MASK                        0x000003ff
#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_SHIFT                       0
#define BCHP_USB_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                     0x00000020

/***************************************************************************
 *FLADJ_VALUE - Frame Adjust Value
 ***************************************************************************/
/* USB_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                   0xffffffff
#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                  0
#define BCHP_USB_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT                0x000c0020

/***************************************************************************
 *EBRIDGE - Control Register for EHCI Bridge
 ***************************************************************************/
/* USB_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                  0x80000000
#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                 31
#define BCHP_USB_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT               0x00000000

/* USB_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_MASK                     0x40000000
#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_SHIFT                    30
#define BCHP_USB_CTRL_EBRIDGE_ebrff_reset_DEFAULT                  0x00000000

/* USB_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK              0x20000000
#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT             29
#define BCHP_USB_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT           0x00000000

/* USB_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_MASK                    0x10000000
#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_SHIFT                   28
#define BCHP_USB_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                 0x00000000

/* USB_CTRL :: EBRIDGE :: EBR_SPARE [27:18] */
#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_MASK                       0x0ffc0000
#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_SHIFT                      18
#define BCHP_USB_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                    0x00000000

/* USB_CTRL :: EBRIDGE :: ESTOP_SCB_REQ [17:17] */
#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_MASK                   0x00020000
#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_SHIFT                  17
#define BCHP_USB_CTRL_EBRIDGE_ESTOP_SCB_REQ_DEFAULT                0x00000000

/* USB_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                   0x0001f000
#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                  12
#define BCHP_USB_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT                0x00000002

/* USB_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                    0x00000f80
#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                   7
#define BCHP_USB_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                 0x00000004

/* USB_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_MASK                        0x0000007e
#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_SHIFT                       1
#define BCHP_USB_CTRL_EBRIDGE_EBR_MISC_DEFAULT                     0x00000000

/* USB_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                      0x00000001
#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                     0
#define BCHP_USB_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                   0x00000000

/***************************************************************************
 *OBRIDGE - Control Register for OHCI Bridge
 ***************************************************************************/
/* USB_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                  0x80000000
#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                 31
#define BCHP_USB_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT               0x00000000

/* USB_CTRL :: OBRIDGE :: obrff_reset [30:30] */
#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_MASK                     0x40000000
#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_SHIFT                    30
#define BCHP_USB_CTRL_OBRIDGE_obrff_reset_DEFAULT                  0x00000000

/* USB_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK              0x20000000
#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT             29
#define BCHP_USB_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT           0x00000000

/* USB_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_MASK                    0x10000000
#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_SHIFT                   28
#define BCHP_USB_CTRL_OBRIDGE_obr_size_sel_DEFAULT                 0x00000000

/* USB_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_MASK                       0x0ffe0000
#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_SHIFT                      17
#define BCHP_USB_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                    0x00000000

/* USB_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                   0x0001f000
#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                  12
#define BCHP_USB_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT                0x00000002

/* USB_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                    0x00000f80
#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                   7
#define BCHP_USB_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                 0x00000004

/* USB_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_MASK                        0x0000007e
#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_SHIFT                       1
#define BCHP_USB_CTRL_OBRIDGE_OBR_MISC_DEFAULT                     0x00000000

/* USB_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                      0x00000001
#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                     0
#define BCHP_USB_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                   0x00000000

/***************************************************************************
 *MDIO - MDIO Interface Programming Register
 ***************************************************************************/
/* USB_CTRL :: MDIO :: MDIO_PHY_SEL [31:31] */
#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_MASK                       0x80000000
#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_SHIFT                      31
#define BCHP_USB_CTRL_MDIO_MDIO_PHY_SEL_DEFAULT                    0x00000000

/* USB_CTRL :: MDIO :: MDIO_SPARE [30:26] */
#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_MASK                         0x7c000000
#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_SHIFT                        26
#define BCHP_USB_CTRL_MDIO_MDIO_SPARE_DEFAULT                      0x00000000

/* USB_CTRL :: MDIO :: WR_START [25:25] */
#define BCHP_USB_CTRL_MDIO_WR_START_MASK                           0x02000000
#define BCHP_USB_CTRL_MDIO_WR_START_SHIFT                          25
#define BCHP_USB_CTRL_MDIO_WR_START_DEFAULT                        0x00000000

/* USB_CTRL :: MDIO :: RD_START [24:24] */
#define BCHP_USB_CTRL_MDIO_RD_START_MASK                           0x01000000
#define BCHP_USB_CTRL_MDIO_RD_START_SHIFT                          24
#define BCHP_USB_CTRL_MDIO_RD_START_DEFAULT                        0x00000000

/* USB_CTRL :: MDIO :: MDIO_ADDR [23:16] */
#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_MASK                          0x00ff0000
#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_SHIFT                         16
#define BCHP_USB_CTRL_MDIO_MDIO_ADDR_DEFAULT                       0x00000000

/* USB_CTRL :: MDIO :: MDIO_DATA [15:00] */
#define BCHP_USB_CTRL_MDIO_MDIO_DATA_MASK                          0x0000ffff
#define BCHP_USB_CTRL_MDIO_MDIO_DATA_SHIFT                         0
#define BCHP_USB_CTRL_MDIO_MDIO_DATA_DEFAULT                       0x00000000

/***************************************************************************
 *MDIO2 - MDIO Interface Read Register
 ***************************************************************************/
/* USB_CTRL :: MDIO2 :: SYNOPSYS_CORE_ID [31:16] */
#define BCHP_USB_CTRL_MDIO2_SYNOPSYS_CORE_ID_MASK                  0xffff0000
#define BCHP_USB_CTRL_MDIO2_SYNOPSYS_CORE_ID_SHIFT                 16
#define BCHP_USB_CTRL_MDIO2_SYNOPSYS_CORE_ID_DEFAULT               0x0000298a

/* USB_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_MASK                      0x0000ffff
#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                     0
#define BCHP_USB_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                   0x00000000

/***************************************************************************
 *TEST_PORT_CTL - Test Port Control Register
 ***************************************************************************/
/* USB_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [31:28] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK               0xf0000000
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT              28
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT            0x00000000

/* USB_CTRL :: TEST_PORT_CTL :: scb2_wr_data_sel [27:27] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_MASK          0x08000000
#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_SHIFT         27
#define BCHP_USB_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_DEFAULT       0x00000000

/* USB_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK          0x04000000
#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT         26
#define BCHP_USB_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT       0x00000000

/* USB_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK          0x02000000
#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT         25
#define BCHP_USB_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT       0x00000000

/* USB_CTRL :: TEST_PORT_CTL :: testclk_sel [24:23] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_MASK               0x01800000
#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_SHIFT              23
#define BCHP_USB_CTRL_TEST_PORT_CTL_testclk_sel_DEFAULT            0x00000000

/* USB_CTRL :: TEST_PORT_CTL :: pwrflt_testsel [22:21] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_MASK            0x00600000
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_SHIFT           21
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt_testsel_DEFAULT         0x00000000

/* USB_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [20:20] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK                0x00100000
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT               20
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT             0x00000000

/* USB_CTRL :: TEST_PORT_CTL :: pwrflt0_oe [19:19] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_MASK                0x00080000
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_SHIFT               19
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwrflt0_oe_DEFAULT             0x00000000

/* USB_CTRL :: TEST_PORT_CTL :: pwron1_testsel [18:18] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_MASK            0x00040000
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_SHIFT           18
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron1_testsel_DEFAULT         0x00000000

/* USB_CTRL :: TEST_PORT_CTL :: pwron0_testsel [17:17] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_MASK            0x00020000
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_SHIFT           17
#define BCHP_USB_CTRL_TEST_PORT_CTL_pwron0_testsel_DEFAULT         0x00000000

/* USB_CTRL :: TEST_PORT_CTL :: tpin_sel [16:16] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_MASK                  0x00010000
#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_SHIFT                 16
#define BCHP_USB_CTRL_TEST_PORT_CTL_tpin_sel_DEFAULT               0x00000000

/* USB_CTRL :: TEST_PORT_CTL :: UTMI_TP_SEL [15:08] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_MASK               0x0000ff00
#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_SHIFT              8
#define BCHP_USB_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_DEFAULT            0x00000000

/* USB_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                 0x000000ff
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT                0
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT              0x00000000
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag0             0
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag1             1
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag2             2
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag3             3
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag4             4
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag5             5
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag6             6
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag7             7
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag8             8
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag9             9
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag10            10
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag11            11
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag12            12
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag13            13
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag14            14
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag15            15
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag16            16
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag17            17
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag18            18
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag19            19
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag20            20
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag21            21
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag22            22
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag23            23
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag24            24
#define BCHP_USB_CTRL_TEST_PORT_CTL_TPOUT_SEL_hc_diag25            25

/***************************************************************************
 *USB_SIMCTL - Simulation Register
 ***************************************************************************/
/* USB_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_MASK                  0x80000000
#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                 31
#define BCHP_USB_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT               0x00000000

/* USB_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_MASK                0x40000000
#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_SHIFT               30
#define BCHP_USB_CTRL_USB_SIMCTL_scale_down_en_DEFAULT             0x00000000

/* USB_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_MASK            0x30000000
#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT           28
#define BCHP_USB_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT         0x00000000

/* USB_CTRL :: USB_SIMCTL :: intr_test [27:27] */
#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_MASK                    0x08000000
#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_SHIFT                   27
#define BCHP_USB_CTRL_USB_SIMCTL_intr_test_DEFAULT                 0x00000000

/* USB_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK        0x04000000
#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT       26
#define BCHP_USB_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT     0x00000000

/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:10] */
#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                 0x03fffc00
#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT                10
#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT              0x00000000

/* USB_CTRL :: USB_SIMCTL :: ss_hubsetup_min [09:09] */
#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_MASK              0x00000200
#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_SHIFT             9
#define BCHP_USB_CTRL_USB_SIMCTL_ss_hubsetup_min_DEFAULT           0x00000000

/* USB_CTRL :: USB_SIMCTL :: ohci_memreq_disable [08:08] */
#define BCHP_USB_CTRL_USB_SIMCTL_ohci_memreq_disable_MASK          0x00000100
#define BCHP_USB_CTRL_USB_SIMCTL_ohci_memreq_disable_SHIFT         8
#define BCHP_USB_CTRL_USB_SIMCTL_ohci_memreq_disable_DEFAULT       0x00000000

/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE2 [07:07] */
#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_MASK                0x00000080
#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_SHIFT               7
#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE2_DEFAULT             0x00000000

/* USB_CTRL :: USB_SIMCTL :: usb_cap_dis [06:06] */
#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_MASK                  0x00000040
#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_SHIFT                 6
#define BCHP_USB_CTRL_USB_SIMCTL_usb_cap_dis_DEFAULT               0x00000000

/* USB_CTRL :: USB_SIMCTL :: scb_req_lgcy [05:05] */
#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_MASK                 0x00000020
#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_SHIFT                5
#define BCHP_USB_CTRL_USB_SIMCTL_scb_req_lgcy_DEFAULT              0x00000000

/* USB_CTRL :: USB_SIMCTL :: rel_270a_comp [04:04] */
#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_MASK                0x00000010
#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_SHIFT               4
#define BCHP_USB_CTRL_USB_SIMCTL_rel_270a_comp_DEFAULT             0x00000000

/* USB_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [03:00] */
#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK                0x0000000f
#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT               0
#define BCHP_USB_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT             0x00000000

/***************************************************************************
 *USB_TESTCTL - Throutput Test Control
 ***************************************************************************/
/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK              0xff800000
#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT             23
#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT           0x00000000

/* USB_CTRL :: USB_TESTCTL :: CONTROLLER_SEL [22:21] */
#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_MASK              0x00600000
#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_SHIFT             21
#define BCHP_USB_CTRL_USB_TESTCTL_CONTROLLER_SEL_DEFAULT           0x00000000

/* USB_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_MASK                     0x00100000
#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                    20
#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                  0x00000000

/* USB_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_MASK                   0x00080000
#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                  19
#define BCHP_USB_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT                0x00000000

/* USB_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_MASK                    0x00070000
#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                   16
#define BCHP_USB_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                 0x00000000

/* USB_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK              0x0000fc00
#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT             10
#define BCHP_USB_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT           0x00000000

/* USB_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK              0x000003ff
#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT             0
#define BCHP_USB_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT           0x00000000

/***************************************************************************
 *USB_TESTMON - Throughput Test Monitor
 ***************************************************************************/
/* USB_CTRL :: USB_TESTMON :: PLL_SS_LOCK [31:31] */
#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_MASK                 0x80000000
#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_SHIFT                31
#define BCHP_USB_CTRL_USB_TESTMON_PLL_SS_LOCK_DEFAULT              0x00000000

/* USB_CTRL :: USB_TESTMON :: PLL_HS_LOCK [30:30] */
#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_MASK                 0x40000000
#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_SHIFT                30
#define BCHP_USB_CTRL_USB_TESTMON_PLL_HS_LOCK_DEFAULT              0x00000000

/* USB_CTRL :: USB_TESTMON :: LDO_FLAG_ON [29:29] */
#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_MASK                 0x20000000
#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_SHIFT                29
#define BCHP_USB_CTRL_USB_TESTMON_LDO_FLAG_ON_DEFAULT              0x00000000

/* USB_CTRL :: USB_TESTMON :: TESTMON_STAT [28:00] */
#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_MASK                0x1fffffff
#define BCHP_USB_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT               0

/***************************************************************************
 *UTMI_CTL_1 - UTMI Control Register
 ***************************************************************************/
/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK              0x80000000
#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT             31
#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT           0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK             0x70000000
#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT            28
#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT          0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN_P1 [27:27] */
#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_MASK           0x08000000
#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_SHIFT          27
#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_P1_DEFAULT        0x00000001

/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB_P1 [26:26] */
#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_MASK              0x04000000
#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_SHIFT             26
#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_P1_DEFAULT           0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU_P1 [25:25] */
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_MASK       0x02000000
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_SHIFT      25
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_P1_DEFAULT    0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED_P1 [24:24] */
#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_MASK        0x01000000
#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_SHIFT       24
#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_P1_DEFAULT     0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK                0x00800000
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT               23
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT             0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK                0x00400000
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT               22
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT             0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK                0x00200000
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT               21
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT             0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK                0x00100000
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT               20
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT             0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                  0x000c0000
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                 18
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT               0x00000000
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_Host                  0
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_Device                1
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_OTG                   2
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_P1_BC10                  3

/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK          0x00020000
#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT         17
#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT       0x00000001

/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK           0x00010000
#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT          16
#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT        0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                 0x00008000
#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT                15
#define BCHP_USB_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT              0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK                0x00007000
#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT               12
#define BCHP_USB_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT             0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_EN [11:11] */
#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_MASK              0x00000800
#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_SHIFT             11
#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_EN_DEFAULT           0x00000001

/* USB_CTRL :: UTMI_CTL_1 :: NO_R45_CALIB [10:10] */
#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_MASK                 0x00000400
#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_SHIFT                10
#define BCHP_USB_CTRL_UTMI_CTL_1_NO_R45_CALIB_DEFAULT              0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: BC10_ACTIVE_IDLE_PU [09:09] */
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_MASK          0x00000200
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_SHIFT         9
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_ACTIVE_IDLE_PU_DEFAULT       0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: POWER_UP_FSM_SPEED [08:08] */
#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_MASK           0x00000100
#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_SHIFT          8
#define BCHP_USB_CTRL_UTMI_CTL_1_POWER_UP_FSM_SPEED_DEFAULT        0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                   0x00000080
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                  7
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT                0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                   0x00000040
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                  6
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT                0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                   0x00000020
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                  5
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT                0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                   0x00000010
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                  4
#define BCHP_USB_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT                0x00000000

/* USB_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_MASK                     0x0000000c
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                    2
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                  0x00000000
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_Host                     0
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_Device                   1
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_OTG                      2
#define BCHP_USB_CTRL_UTMI_CTL_1_PHY_MODE_BC10                     3

/* USB_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK             0x00000002
#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT            1
#define BCHP_USB_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT          0x00000001

/* USB_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK              0x00000001
#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT             0
#define BCHP_USB_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT           0x00000000

/***************************************************************************
 *UTMI_CTL_2 - UTMI Control 2 Register
 ***************************************************************************/
/* USB_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK               0xffffffff
#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT              0
#define BCHP_USB_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT            0x00000000

/***************************************************************************
 *USB_PM - Power Management Register
 ***************************************************************************/
/* USB_CTRL :: USB_PM :: USB_PWRDN [31:31] */
#define BCHP_USB_CTRL_USB_PM_USB_PWRDN_MASK                        0x80000000
#define BCHP_USB_CTRL_USB_PM_USB_PWRDN_SHIFT                       31
#define BCHP_USB_CTRL_USB_PM_USB_PWRDN_DEFAULT                     0x00000001

/* USB_CTRL :: USB_PM :: xhc_soft_resetb [30:30] */
#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_MASK                  0x40000000
#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_SHIFT                 30
#define BCHP_USB_CTRL_USB_PM_xhc_soft_resetb_DEFAULT               0x00000000

/* USB_CTRL :: USB_PM :: usb20_hc1_resetb [29:29] */
#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_MASK                 0x20000000
#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_SHIFT                29
#define BCHP_USB_CTRL_USB_PM_usb20_hc1_resetb_DEFAULT              0x00000001

/* USB_CTRL :: USB_PM :: usb20_hc0_resetb [28:28] */
#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_MASK                 0x10000000
#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_SHIFT                28
#define BCHP_USB_CTRL_USB_PM_usb20_hc0_resetb_DEFAULT              0x00000001

/* USB_CTRL :: USB_PM :: USB_PM_SPARE1 [27:16] */
#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_MASK                    0x0fff0000
#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_SHIFT                   16
#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE1_DEFAULT                 0x00000000

/* USB_CTRL :: USB_PM :: ehci_rmtwkup_override [15:15] */
#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_MASK            0x00008000
#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_SHIFT           15
#define BCHP_USB_CTRL_USB_PM_ehci_rmtwkup_override_DEFAULT         0x00000000

/* USB_CTRL :: USB_PM :: ohci_rmtwkup_override [14:14] */
#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_MASK            0x00004000
#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_SHIFT           14
#define BCHP_USB_CTRL_USB_PM_ohci_rmtwkup_override_DEFAULT         0x00000000

/* USB_CTRL :: USB_PM :: USB_PM_SPARE [13:05] */
#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_MASK                     0x00003fe0
#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_SHIFT                    5
#define BCHP_USB_CTRL_USB_PM_USB_PM_SPARE_DEFAULT                  0x00000000

/* USB_CTRL :: USB_PM :: xhc_pme_en [04:04] */
#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_MASK                       0x00000010
#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_SHIFT                      4
#define BCHP_USB_CTRL_USB_PM_xhc_pme_en_DEFAULT                    0x00000000

/* USB_CTRL :: USB_PM :: S2_discon_intr_en [03:03] */
#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_MASK                0x00000008
#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_SHIFT               3
#define BCHP_USB_CTRL_USB_PM_S2_discon_intr_en_DEFAULT             0x00000000

/* USB_CTRL :: USB_PM :: S0_discon_intr_en [02:02] */
#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_MASK                0x00000004
#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_SHIFT               2
#define BCHP_USB_CTRL_USB_PM_S0_discon_intr_en_DEFAULT             0x00000000

/* USB_CTRL :: USB_PM :: con_intr_en [01:01] */
#define BCHP_USB_CTRL_USB_PM_con_intr_en_MASK                      0x00000002
#define BCHP_USB_CTRL_USB_PM_con_intr_en_SHIFT                     1
#define BCHP_USB_CTRL_USB_PM_con_intr_en_DEFAULT                   0x00000000

/* USB_CTRL :: USB_PM :: rmtwkup_en [00:00] */
#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_MASK                       0x00000001
#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_SHIFT                      0
#define BCHP_USB_CTRL_USB_PM_rmtwkup_en_DEFAULT                    0x00000000

/***************************************************************************
 *USB_PM_STATUS - usb20 Power Management Status Register
 ***************************************************************************/
/* USB_CTRL :: USB_PM_STATUS :: SPARE1_BITS [31:16] */
#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_MASK               0xffff0000
#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_SHIFT              16
#define BCHP_USB_CTRL_USB_PM_STATUS_SPARE1_BITS_DEFAULT            0x00000000

/* USB_CTRL :: USB_PM_STATUS :: PM_STATUS [15:00] */
#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_MASK                 0x0000ffff
#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_SHIFT                0
#define BCHP_USB_CTRL_USB_PM_STATUS_PM_STATUS_DEFAULT              0x00000000

/***************************************************************************
 *OHCI_ADDR_EXT - OHCI ADDRESS Extension
 ***************************************************************************/
/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_SPARE [31:08] */
#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_MASK           0xffffff00
#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_SHIFT          8
#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_DEFAULT        0x00000000

/* USB_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_EXT [07:00] */
#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_MASK             0x000000ff
#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_SHIFT            0
#define BCHP_USB_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_DEFAULT          0x00000000

/***************************************************************************
 *PLL_LDO_CTL - 28NM USBPHY LDO Control
 ***************************************************************************/
/* USB_CTRL :: PLL_LDO_CTL :: AFE_PLL_LDO_CNTL [31:16] */
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_MASK            0xffff0000
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_SHIFT           16
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_DEFAULT         0x00000000

/* USB_CTRL :: PLL_LDO_CTL :: DFE_LDO_CNTL [15:12] */
#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_MASK                0x0000f000
#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_SHIFT               12
#define BCHP_USB_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_DEFAULT             0x00000000

/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_CNTL [11:08] */
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_MASK                0x00000f00
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_SHIFT               8
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_DEFAULT             0x00000000

/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_SPARE [07:03] */
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_MASK               0x000000f8
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_SHIFT              3
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_DEFAULT            0x00000000

/* USB_CTRL :: PLL_LDO_CTL :: AFE_CORERDY_VDDC [02:02] */
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_MASK            0x00000004
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_SHIFT           2
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_DEFAULT         0x00000001

/* USB_CTRL :: PLL_LDO_CTL :: AFE_LDO_PWRDWNB [01:01] */
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK             0x00000002
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_SHIFT            1
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_DEFAULT          0x00000001

/* USB_CTRL :: PLL_LDO_CTL :: AFE_BG_PWRDWNB [00:00] */
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK              0x00000001
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_SHIFT             0
#define BCHP_USB_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_DEFAULT           0x00000001

/***************************************************************************
 *PLL_LDO_PLLBIAS - 28NM USBPHY PLLBIAS Control
 ***************************************************************************/
/* USB_CTRL :: PLL_LDO_PLLBIAS :: PLLBIAS_SPARE [31:18] */
#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_MASK           0xfffc0000
#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_SHIFT          18
#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_DEFAULT        0x00000000

/* USB_CTRL :: PLL_LDO_PLLBIAS :: AFE_PLLBIAS_TESTMODE [17:00] */
#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_MASK    0x0003ffff
#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_SHIFT   0
#define BCHP_USB_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AFE_BG_CNTL - 28NM USBPHY AFE Bandgap Control
 ***************************************************************************/
/* USB_CTRL :: PLL_AFE_BG_CNTL :: PLL_AFE_BG_SPARE [31:17] */
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_MASK        0xfffe0000
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_SHIFT       17
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_DEFAULT     0x00000000

/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_PRGM [16:12] */
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_MASK             0x0001f000
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_SHIFT            12
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_DEFAULT          0x00000000

/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_AFE_PRGM [11:08] */
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_MASK 0x00000f00
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_SHIFT 8
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_DEFAULT 0x00000000

/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_DFE_PRGM [07:04] */
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_MASK 0x000000f0
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_SHIFT 4
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_DEFAULT 0x00000000

/* USB_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF1P0_TRIM [03:00] */
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_MASK     0x0000000f
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_SHIFT    0
#define BCHP_USB_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_DEFAULT  0x00000000

/***************************************************************************
 *AFE_USBIO_TST - 28NM USBPHY AFE Bandgap Control
 ***************************************************************************/
/* USB_CTRL :: AFE_USBIO_TST :: ANALOG_TESTMODE [31:31] */
#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_MASK           0x80000000
#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_SHIFT          31
#define BCHP_USB_CTRL_AFE_USBIO_TST_ANALOG_TESTMODE_DEFAULT        0x00000000

/* USB_CTRL :: AFE_USBIO_TST :: PHY_ISO [30:30] */
#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_MASK                   0x40000000
#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_SHIFT                  30
#define BCHP_USB_CTRL_AFE_USBIO_TST_PHY_ISO_DEFAULT                0x00000000

/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_SPARE [29:16] */
#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_MASK       0x3fff0000
#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_SHIFT      16
#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_DEFAULT    0x00000000

/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P2 [15:08] */
#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_MASK          0x0000ff00
#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_SHIFT         8
#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_DEFAULT       0x00000000

/* USB_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P1 [07:00] */
#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_MASK          0x000000ff
#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_SHIFT         0
#define BCHP_USB_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_DEFAULT       0x00000000

/***************************************************************************
 *PLL_NDIV_FRAC - PLL Feedback Divider Control Register
 ***************************************************************************/
/* USB_CTRL :: PLL_NDIV_FRAC :: PLL_NDIV_FRAC_SPARE2 [31:20] */
#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_MASK      0xfff00000
#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_SHIFT     20
#define BCHP_USB_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_DEFAULT   0x00000000

/* USB_CTRL :: PLL_NDIV_FRAC :: pll_ndiv_frac [19:00] */
#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_MASK             0x000fffff
#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_SHIFT            0
#define BCHP_USB_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_DEFAULT          0x00000000

/***************************************************************************
 *TP_DIAG - diagnostic for tp bus
 ***************************************************************************/
/* USB_CTRL :: TP_DIAG :: TP_DIAG_BITS [31:00] */
#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_MASK                    0xffffffff
#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_SHIFT                   0
#define BCHP_USB_CTRL_TP_DIAG_TP_DIAG_BITS_DEFAULT                 0x00000000

/***************************************************************************
 *SPARE3 - Spare1 Register for future use
 ***************************************************************************/
/* USB_CTRL :: SPARE3 :: SPARE3_BITS [31:00] */
#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_MASK                      0xffffffff
#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_SHIFT                     0
#define BCHP_USB_CTRL_SPARE3_SPARE3_BITS_DEFAULT                   0x00000000

/***************************************************************************
 *SPARE4 - Spare1 Register for future use
 ***************************************************************************/
/* USB_CTRL :: SPARE4 :: SPARE4_BITS [31:00] */
#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_MASK                      0xffffffff
#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_SHIFT                     0
#define BCHP_USB_CTRL_SPARE4_SPARE4_BITS_DEFAULT                   0x00000000

/***************************************************************************
 *USB30_CTL1 - USB30 CONTROL Register 1
 ***************************************************************************/
/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare2 [31:22] */
#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_MASK            0xffc00000
#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_SHIFT           22
#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare2_DEFAULT         0x00000000

/* USB_CTRL :: USB30_CTL1 :: usb30_sspll_suspend_en [21:21] */
#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_MASK       0x00200000
#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_SHIFT      21
#define BCHP_USB_CTRL_USB30_CTL1_usb30_sspll_suspend_en_DEFAULT    0x00000000

/* USB_CTRL :: USB30_CTL1 :: usb30_pipe_resetb [20:20] */
#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_MASK            0x00100000
#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_SHIFT           20
#define BCHP_USB_CTRL_USB30_CTL1_usb30_pipe_resetb_DEFAULT         0x00000001

/* USB_CTRL :: USB30_CTL1 :: mdio_resetb [19:19] */
#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_MASK                  0x00080000
#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_SHIFT                 19
#define BCHP_USB_CTRL_USB30_CTL1_mdio_resetb_DEFAULT               0x00000001

/* USB_CTRL :: USB30_CTL1 :: aux_resetb [18:18] */
#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_MASK                   0x00040000
#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_SHIFT                  18
#define BCHP_USB_CTRL_USB30_CTL1_aux_resetb_DEFAULT                0x00000000

/* USB_CTRL :: USB30_CTL1 :: cdr_reset [17:17] */
#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_MASK                    0x00020000
#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_SHIFT                   17
#define BCHP_USB_CTRL_USB30_CTL1_cdr_reset_DEFAULT                 0x00000000

/* USB_CTRL :: USB30_CTL1 :: phy3_resetb [16:16] */
#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_MASK                  0x00010000
#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_SHIFT                 16
#define BCHP_USB_CTRL_USB30_CTL1_phy3_resetb_DEFAULT               0x00000001

/* USB_CTRL :: USB30_CTL1 :: usb30_ctl1_spare1 [15:07] */
#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_MASK            0x0000ff80
#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_SHIFT           7
#define BCHP_USB_CTRL_USB30_CTL1_usb30_ctl1_spare1_DEFAULT         0x00000000

/* USB_CTRL :: USB30_CTL1 :: phy3_standalonemode [06:06] */
#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_MASK          0x00000040
#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_SHIFT         6
#define BCHP_USB_CTRL_USB30_CTL1_phy3_standalonemode_DEFAULT       0x00000000

/* USB_CTRL :: USB30_CTL1 :: phy3_phy_iso [05:05] */
#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_MASK                 0x00000020
#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_SHIFT                5
#define BCHP_USB_CTRL_USB30_CTL1_phy3_phy_iso_DEFAULT              0x00000000

/* USB_CTRL :: USB30_CTL1 :: phy3_pll_seq_start [04:04] */
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_MASK           0x00000010
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_SHIFT          4
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_seq_start_DEFAULT        0x00000000

/* USB_CTRL :: USB30_CTL1 :: phy3_pll_refclk_sel [03:01] */
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_MASK          0x0000000e
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_SHIFT         1
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_DEFAULT       0x00000004
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_CML_Refclk    0
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_XTAL          1
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_REFCLKP_N     2
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_REFCLKP_N_with_Termination 3
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_refclk_sel_Cmos_Refclk   4

/* USB_CTRL :: USB30_CTL1 :: phy3_pll_auxclk_sel [00:00] */
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_MASK          0x00000001
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_SHIFT         0
#define BCHP_USB_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_DEFAULT       0x00000000

/***************************************************************************
 *USB30_CTL2 - USB30 CONTROL Register 2
 ***************************************************************************/
/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare2 [31:30] */
#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_MASK            0xc0000000
#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_SHIFT           30
#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare2_DEFAULT         0x00000000

/* USB_CTRL :: USB30_CTL2 :: xhci_max_scb_size [29:24] */
#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_MASK            0x3f000000
#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_SHIFT           24
#define BCHP_USB_CTRL_USB30_CTL2_xhci_max_scb_size_DEFAULT         0x00000020

/* USB_CTRL :: USB30_CTL2 :: xhci_wrfifo_thrshld [23:16] */
#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_MASK          0x00ff0000
#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_SHIFT         16
#define BCHP_USB_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_DEFAULT       0x00000000

/* USB_CTRL :: USB30_CTL2 :: xhci_rdfifo_thrshld [15:08] */
#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_MASK          0x0000ff00
#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_SHIFT         8
#define BCHP_USB_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_DEFAULT       0x00000000

/* USB_CTRL :: USB30_CTL2 :: usb30_ctl2_spare1 [07:03] */
#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_MASK            0x000000f8
#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_SHIFT           3
#define BCHP_USB_CTRL_USB30_CTL2_usb30_ctl2_spare1_DEFAULT         0x00000000

/* USB_CTRL :: USB30_CTL2 :: xhci_cntl_client_en [02:02] */
#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_MASK          0x00000004
#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_SHIFT         2
#define BCHP_USB_CTRL_USB30_CTL2_xhci_cntl_client_en_DEFAULT       0x00000001

/* USB_CTRL :: USB30_CTL2 :: xhci_swap_mode [01:00] */
#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_MASK               0x00000003
#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_SHIFT              0
#define BCHP_USB_CTRL_USB30_CTL2_xhci_swap_mode_DEFAULT            0x00000000

/***************************************************************************
 *USB30_CTL3 - USB30 CONTROL Register 3
 ***************************************************************************/
/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare2 [31:30] */
#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_MASK            0xc0000000
#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_SHIFT           30
#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare2_DEFAULT         0x00000000

/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en_p1 [29:29] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_MASK     0x20000000
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_SHIFT    29
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_DEFAULT  0x00000000

/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_p1 [28:24] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_MASK        0x1f000000
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_SHIFT       24
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_DEFAULT     0x00000009

/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_p1 [23:20] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_MASK        0x00f00000
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_SHIFT       20
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_DEFAULT     0x00000007

/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode_p1 [19:19] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_MASK           0x00080000
#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_SHIFT          19
#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_p1_DEFAULT        0x00000000

/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en_p1 [18:18] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_MASK     0x00040000
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_SHIFT    18
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_DEFAULT  0x00000000

/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing_p1 [17:17] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_MASK         0x00020000
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_SHIFT        17
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_DEFAULT      0x00000000

/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_mode_p1 [16:16] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_MASK            0x00010000
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_SHIFT           16
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_p1_DEFAULT         0x00000001

/* USB_CTRL :: USB30_CTL3 :: usb30_ctl3_spare1 [15:14] */
#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_MASK            0x0000c000
#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_SHIFT           14
#define BCHP_USB_CTRL_USB30_CTL3_usb30_ctl3_spare1_DEFAULT         0x00000000

/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en [13:13] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_MASK        0x00002000
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_SHIFT       13
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_DEFAULT     0x00000000

/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph [12:08] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_MASK           0x00001f00
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_SHIFT          8
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txdeemph_DEFAULT        0x00000009

/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin [07:04] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_MASK           0x000000f0
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_SHIFT          4
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_DEFAULT        0x00000007

/* USB_CTRL :: USB30_CTL3 :: phy3_rxebufmode [03:03] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_MASK              0x00000008
#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_SHIFT             3
#define BCHP_USB_CTRL_USB30_CTL3_phy3_rxebufmode_DEFAULT           0x00000000

/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en [02:02] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_MASK        0x00000004
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_SHIFT       2
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_DEFAULT     0x00000000

/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_txswing [01:01] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_MASK            0x00000002
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_SHIFT           1
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_txswing_DEFAULT         0x00000000

/* USB_CTRL :: USB30_CTL3 :: phy3_pipe_mode [00:00] */
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_MASK               0x00000001
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_SHIFT              0
#define BCHP_USB_CTRL_USB30_CTL3_phy3_pipe_mode_DEFAULT            0x00000001

/***************************************************************************
 *USB30_CTL4 - USB30 CONTROL Register 4
 ***************************************************************************/
/* USB_CTRL :: USB30_CTL4 :: usb30_ctl4_spare1 [31:24] */
#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_MASK            0xff000000
#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_SHIFT           24
#define BCHP_USB_CTRL_USB30_CTL4_usb30_ctl4_spare1_DEFAULT         0x00000000

/* USB_CTRL :: USB30_CTL4 :: phy3_tpout_sel [23:16] */
#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_MASK               0x00ff0000
#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_SHIFT              16
#define BCHP_USB_CTRL_USB30_CTL4_phy3_tpout_sel_DEFAULT            0x00000000

/* USB_CTRL :: USB30_CTL4 :: xhci_tpout_sel [15:00] */
#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_MASK               0x0000ffff
#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_SHIFT              0
#define BCHP_USB_CTRL_USB30_CTL4_xhci_tpout_sel_DEFAULT            0x00000000

/***************************************************************************
 *USB30_PCTL - USB30 PORT CONTROL Register
 ***************************************************************************/
/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE2 [31:29] */
#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_MASK             0xe0000000
#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_SHIFT            29
#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE2_DEFAULT          0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX_P1 [28:28] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_MASK           0x10000000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_SHIFT          28
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_P1_DEFAULT        0x00000001

/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1 [27:27] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_MASK 0x08000000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_SHIFT 27
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_P1_DEFAULT 0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1 [26:25] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_MASK 0x06000000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_SHIFT 25
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_P1_DEFAULT 0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE_P1 [24:24] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_MASK 0x01000000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_SHIFT 24
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_P1_DEFAULT 0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE_P1 [23:23] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_MASK 0x00800000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_SHIFT 23
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_P1_DEFAULT 0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE_P1 [22:22] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_MASK 0x00400000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_SHIFT 22
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_P1_DEFAULT 0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE_P1 [21:21] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_MASK       0x00200000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_SHIFT      21
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_P1_DEFAULT    0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE_P1 [20:20] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_MASK       0x00100000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_SHIFT      20
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_P1_DEFAULT    0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_MODE_P1 [19:18] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_MASK                 0x000c0000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_SHIFT                18
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_P1_DEFAULT              0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB_P1 [17:17] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_MASK          0x00020000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_SHIFT         17
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_P1_DEFAULT       0x00000001

/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING_P1 [16:16] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_MASK      0x00010000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_SHIFT     16
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_P1_DEFAULT   0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_IDDQ_OVERRIDE [15:15] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_MASK           0x00008000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_SHIFT          15
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_IDDQ_OVERRIDE_DEFAULT        0x00000000

/* USB_CTRL :: USB30_PCTL :: USB3_PCTL_SPARE1 [14:13] */
#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_MASK             0x00006000
#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_SHIFT            13
#define BCHP_USB_CTRL_USB30_PCTL_USB3_PCTL_SPARE1_DEFAULT          0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_BYP_CLKMUX [12:12] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_MASK              0x00001000
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_SHIFT             12
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_BYP_CLKMUX_DEFAULT           0x00000001

/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_EN [11:11] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_MASK 0x00000800
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_SHIFT 11
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_EN_DEFAULT 0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_PIPE_PWRDWN_OVERRIDE_VALUE [10:09] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_MASK 0x00000600
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_SHIFT 9
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_PIPE_PWRDWN_OVERRIDE_VALUE_DEFAULT 0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetOut_OVERRIDE [08:08] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_MASK    0x00000100
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_SHIFT   8
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetOut_OVERRIDE_DEFAULT 0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_TX_ElecIdle_OVERRIDE [07:07] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_MASK    0x00000080
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_SHIFT   7
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_ElecIdle_OVERRIDE_DEFAULT 0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_TX_RxDetReq_OVERRIDE [06:06] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_MASK    0x00000040
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_SHIFT   6
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_RxDetReq_OVERRIDE_DEFAULT 0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_TX_PD_OVERRIDE [05:05] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_MASK          0x00000020
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_SHIFT         5
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_TX_PD_OVERRIDE_DEFAULT       0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_RX_PD_OVERRIDE [04:04] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_MASK          0x00000010
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_SHIFT         4
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_RX_PD_OVERRIDE_DEFAULT       0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_MODE [03:02] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_MASK                    0x0000000c
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_SHIFT                   2
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_MODE_DEFAULT                 0x00000000

/* USB_CTRL :: USB30_PCTL :: PHY3_SOFT_RESETB [01:01] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_MASK             0x00000002
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_SHIFT            1
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_SOFT_RESETB_DEFAULT          0x00000001

/* USB_CTRL :: USB30_PCTL :: PHY3_AFE_NON_DRIVING [00:00] */
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_MASK         0x00000001
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_SHIFT        0
#define BCHP_USB_CTRL_USB30_PCTL_PHY3_AFE_NON_DRIVING_DEFAULT      0x00000000

/***************************************************************************
 *USB30_CTL5 - USB30 CONTROL Register 5
 ***************************************************************************/
/* USB_CTRL :: USB30_CTL5 :: USB30_CTL5 [31:00] */
#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_MASK                   0xffffffff
#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_SHIFT                  0
#define BCHP_USB_CTRL_USB30_CTL5_USB30_CTL5_DEFAULT                0x00000000

/***************************************************************************
 *SPARE5 - Spare1 Register for future use
 ***************************************************************************/
/* USB_CTRL :: SPARE5 :: SPARE5_BITS [31:00] */
#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_MASK                      0xffffffff
#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_SHIFT                     0
#define BCHP_USB_CTRL_SPARE5_SPARE5_BITS_DEFAULT                   0x00000000

/***************************************************************************
 *SPARE6 - Spare2 Register for future use
 ***************************************************************************/
/* USB_CTRL :: SPARE6 :: SPARE6_BITS [31:00] */
#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_MASK                      0xffffffff
#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_SHIFT                     0
#define BCHP_USB_CTRL_SPARE6_SPARE6_BITS_DEFAULT                   0x00000000

/***************************************************************************
 *SCB0_BASE_RANGE - SCB0 base start and end address
 ***************************************************************************/
/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_SPARE_BITS [31:24] */
#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_MASK    0xff000000
#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_SHIFT   24
#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_SPARE_BITS_DEFAULT 0x00000000

/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_END_ADDR [23:12] */
#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_MASK      0x00fff000
#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_SHIFT     12
#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_END_ADDR_DEFAULT   0x00000007

/* USB_CTRL :: SCB0_BASE_RANGE :: SCB0_BASE_START_ADDR [11:00] */
#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_MASK    0x00000fff
#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_SHIFT   0
#define BCHP_USB_CTRL_SCB0_BASE_RANGE_SCB0_BASE_START_ADDR_DEFAULT 0x00000000

/***************************************************************************
 *SCB1_BASE_RANGE - SCB1 base start and end address
 ***************************************************************************/
/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_SPARE_BITS [31:24] */
#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_MASK    0xff000000
#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_SHIFT   24
#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_SPARE_BITS_DEFAULT 0x00000000

/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_END_ADDR [23:12] */
#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_MASK      0x00fff000
#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_SHIFT     12
#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_END_ADDR_DEFAULT   0x0000000b

/* USB_CTRL :: SCB1_BASE_RANGE :: SCB1_BASE_START_ADDR [11:00] */
#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_MASK    0x00000fff
#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_SHIFT   0
#define BCHP_USB_CTRL_SCB1_BASE_RANGE_SCB1_BASE_START_ADDR_DEFAULT 0x00000008

/***************************************************************************
 *SCB2_BASE_RANGE - SCB2 base start and end address
 ***************************************************************************/
/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_SPARE_BITS [31:24] */
#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_MASK    0xff000000
#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_SHIFT   24
#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_SPARE_BITS_DEFAULT 0x00000000

/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_END_ADDR [23:12] */
#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_MASK      0x00fff000
#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_SHIFT     12
#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_END_ADDR_DEFAULT   0x0000000b

/* USB_CTRL :: SCB2_BASE_RANGE :: SCB2_BASE_START_ADDR [11:00] */
#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_MASK    0x00000fff
#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_SHIFT   0
#define BCHP_USB_CTRL_SCB2_BASE_RANGE_SCB2_BASE_START_ADDR_DEFAULT 0x00000008

/***************************************************************************
 *SCB0_EXTN_RANGE - SCB0 extn start and end address
 ***************************************************************************/
/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_SPARE_BITS [31:24] */
#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_MASK    0xff000000
#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_SHIFT   24
#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_SPARE_BITS_DEFAULT 0x00000000

/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_END_ADDR [23:12] */
#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_MASK      0x00fff000
#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_SHIFT     12
#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_END_ADDR_DEFAULT   0x00000017

/* USB_CTRL :: SCB0_EXTN_RANGE :: SCB0_EXTN_START_ADDR [11:00] */
#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_MASK    0x00000fff
#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_SHIFT   0
#define BCHP_USB_CTRL_SCB0_EXTN_RANGE_SCB0_EXTN_START_ADDR_DEFAULT 0x00000010

/***************************************************************************
 *SCB1_EXTN_RANGE - SCB1 extn start and end address
 ***************************************************************************/
/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_SPARE_BITS [31:24] */
#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_MASK    0xff000000
#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_SHIFT   24
#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_SPARE_BITS_DEFAULT 0x00000000

/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_END_ADDR [23:12] */
#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_MASK      0x00fff000
#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_SHIFT     12
#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_END_ADDR_DEFAULT   0x0000003b

/* USB_CTRL :: SCB1_EXTN_RANGE :: SCB1_EXTN_START_ADDR [11:00] */
#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_MASK    0x00000fff
#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_SHIFT   0
#define BCHP_USB_CTRL_SCB1_EXTN_RANGE_SCB1_EXTN_START_ADDR_DEFAULT 0x00000030

/***************************************************************************
 *SCB2_EXTN_RANGE - SCB2 extn start and end address
 ***************************************************************************/
/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_SPARE_BITS [31:24] */
#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_MASK    0xff000000
#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_SHIFT   24
#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_SPARE_BITS_DEFAULT 0x00000000

/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_END_ADDR [23:12] */
#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_MASK      0x00fff000
#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_SHIFT     12
#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_END_ADDR_DEFAULT   0x000000cb

/* USB_CTRL :: SCB2_EXTN_RANGE :: SCB2_EXTN_START_ADDR [11:00] */
#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_MASK    0x00000fff
#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_SHIFT   0
#define BCHP_USB_CTRL_SCB2_EXTN_RANGE_SCB2_EXTN_START_ADDR_DEFAULT 0x000000c0

/***************************************************************************
 *USB_REVID - USB REVID
 ***************************************************************************/
/* USB_CTRL :: USB_REVID :: USB_REVID [31:00] */
#define BCHP_USB_CTRL_USB_REVID_USB_REVID_MASK                     0xffffffff
#define BCHP_USB_CTRL_USB_REVID_USB_REVID_SHIFT                    0
#define BCHP_USB_CTRL_USB_REVID_USB_REVID_DEFAULT                  0x00000001

#endif /* #ifndef BCHP_USB_CTRL_H__ */

/* End of File */