| /*************************************************************************** |
| * Copyright (c) 1999-2014, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Wed Jul 2 03:12:38 2014 |
| * Full Compile MD5 Checksum 7dc2787604a7d66ecd88cf44bdf8b9f2 |
| * (minus title and desc) |
| * MD5 Checksum fac21eb3a5c0bbaa870b50b1cab81ef9 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_SUN_TOP_CTRL_H__ |
| #define BCHP_SUN_TOP_CTRL_H__ |
| |
| /*************************************************************************** |
| *SUN_TOP_CTRL - Top Control registers |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID 0x00404000 /* Chip family ID */ |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID 0x00404004 /* Product Revision ID */ |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0 0x0040401c /* Strapping values */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1 0x00404020 /* Strapping values */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS 0x00404024 /* Bond option value register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0 0x00404028 /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1 0x0040402c /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0 0x00404030 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1 0x00404034 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0 0x00404038 /* Semaphore channel 0 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1 0x0040403c /* Semaphore channel 1 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2 0x00404040 /* Semaphore channel 2 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3 0x00404044 /* Semaphore channel 3 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4 0x00404048 /* Semaphore channel 4 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5 0x0040404c /* Semaphore channel 5 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6 0x00404050 /* Semaphore channel 6 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7 0x00404054 /* Semaphore channel 7 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8 0x00404058 /* Semaphore channel 8 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9 0x0040405c /* Semaphore channel 9 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10 0x00404060 /* Semaphore channel 10 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11 0x00404064 /* Semaphore channel 11 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12 0x00404068 /* Semaphore channel 12 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13 0x0040406c /* Semaphore channel 13 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14 0x00404070 /* Semaphore channel 14 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15 0x00404074 /* Semaphore channel 15 */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0 0x00404078 /* General watchdog timer 0 */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1 0x0040407c /* General watchdog timer 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 0x00404080 /* General control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1 0x00404084 /* General control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2 0x00404088 /* General control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3 0x0040408c /* General control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4 0x00404090 /* General control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5 0x00404094 /* General control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0 0x00404098 /* General status register 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1 0x0040409c /* General status register 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2 0x004040a0 /* General status register 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3 0x004040bc /* General status register 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4 0x004040c0 /* General status register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x00404100 /* Pinmux control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1 0x00404104 /* Pinmux control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2 0x00404108 /* Pinmux control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3 0x0040410c /* Pinmux control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4 0x00404110 /* Pinmux control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5 0x00404114 /* Pinmux control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6 0x00404118 /* Pinmux control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7 0x0040411c /* Pinmux control register 7 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8 0x00404120 /* Pinmux control register 8 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9 0x00404124 /* Pinmux control register 9 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10 0x00404128 /* Pinmux control register 10 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11 0x0040412c /* Pinmux control register 11 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12 0x00404130 /* Pinmux control register 12 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13 0x00404134 /* Pinmux control register 13 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14 0x00404138 /* Pinmux control register 14 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15 0x0040413c /* Pinmux control register 15 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16 0x00404140 /* Pinmux control register 16 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17 0x00404144 /* Pinmux control register 17 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18 0x00404148 /* Pinmux control register 18 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19 0x0040414c /* Pinmux control register 19 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20 0x00404150 /* Pinmux control register 20 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21 0x00404154 /* Pinmux control register 21 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0 0x00404158 /* Pad pull-up/pull-down control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1 0x0040415c /* Pad pull-up/pull-down control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2 0x00404160 /* Pad pull-up/pull-down control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3 0x00404164 /* Pad pull-up/pull-down control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4 0x00404168 /* Pad pull-up/pull-down control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5 0x0040416c /* Pad pull-up/pull-down control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6 0x00404170 /* Pad pull-up/pull-down control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7 0x00404174 /* Pad pull-up/pull-down control register 7 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8 0x00404178 /* Pad pull-up/pull-down control register 8 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9 0x0040417c /* Pad pull-up/pull-down control register 9 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10 0x00404180 /* Pad pull-up/pull-down control register 10 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11 0x00404184 /* Pad pull-up/pull-down control register 11 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12 0x00404188 /* Pad pull-up/pull-down control register 12 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13 0x0040418c /* Pad pull-up/pull-down control register 13 */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0 0x00404190 /* Bypass clock unselect register 0 */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL 0x00404300 /* Reset control */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE 0x00404304 /* Reset source enable */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET 0x00404308 /* Software master reset */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION 0x0040430c /* Hardware reset extension */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR 0x00404310 /* Reset Monitor */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY 0x00404314 /* Reset history */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET 0x00404318 /* Software init 0 set */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR 0x0040431c /* Software init 0 clear */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS 0x00404320 /* Software init 0 status */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR 0x00404324 /* Security software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET 0x00404330 /* Software init 1 set */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR 0x00404334 /* Software init 1 clear */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS 0x00404338 /* Software init 1 status */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR 0x0040433c /* Security software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */ |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH 0x00404364 /* Scratch register */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL 0x00404368 /* Spare control bits reserved for future use */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL 0x00404380 /* Test port control */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK 0x00404384 /* Testport peek register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE 0x00404388 /* Testport poke register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK 0x0040438c /* Testport peek register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE 0x00404390 /* Testport poke register */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN 0x00404394 /* EJTAG input bus enables */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL 0x00404398 /* EJTAG output select */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL 0x004043a0 /* VTRAP Control */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS 0x004043a4 /* VTRAP Status */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0 0x004043a8 /* UART Router select 0 */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1 0x004043ac /* UART Router select 1 */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG 0x00404400 /* Serial Slave Port configuration register */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV 0x00404420 /* SERS Revision Register */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG 0x00404424 /* SERS Configuration Register */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL 0x00404514 /* Block select for RO testmode */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION 0x00404518 /* Test configuration */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2 0x0040451c /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2 0x00404520 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6 0x00404528 /* General control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7 0x0040452c /* General control register 7 */ |
| |
| /*************************************************************************** |
| *CHIP_FAMILY_ID - Chip family ID |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT 0x73660010 |
| |
| /*************************************************************************** |
| *PRODUCT_ID - Product Revision ID |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT 0x73660010 |
| |
| /*************************************************************************** |
| *BSP_FEATURE_TABLE_ADDR - BSP feature table address |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STRAP_VALUE_0 - Strapping values |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:10] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK 0xfffffc00 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [08:04] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK 0x000001f0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie_rc_ep [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_rc_ep_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_rc_ep_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_rc_ep_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pcie_sata_combo_sel [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_sata_combo_sel_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_sata_combo_sel_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pcie_sata_combo_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STRAP_VALUE_1 - Strapping values |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:05] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK 0xffffffe0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_DEFAULT 0x00000004 |
| |
| /*************************************************************************** |
| *BOND_STATUS - Bond option value register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_0 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pcie0_disable [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pcie0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_4kx2k_disable [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_4kx2k_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_pass_thru_disable [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_pass_thru_disable_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_pass_thru_disable_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_pass_thru_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdmi_rx_disable [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdmi_rx_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rv9_disable [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rv9_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [20:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK 0x001f0000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_memsys_1_disable [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memsys_1_disable_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memsys_1_disable_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_memsys_1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved1 [14:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_MASK 0x00006000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved1_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hvd0_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hvd0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved2 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved2_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved2_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vice2_0_disable [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_0_disable_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_0_disable_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vice2_0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK 0x00000060 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_1 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_capsense_disable [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_capsense_disable_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_capsense_disable_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_capsense_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_moca2_disable [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_moca2_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_directv_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_directv_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_directv_disable_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_directv_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_ldpc_disable [28:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_ldpc_disable_MASK 0x1fe00000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_ldpc_disable_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_ldpc_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_cpus_to_use [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_cpus_to_use_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_cpus_to_use_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_cpus_to_use_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_tfec_disable [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tfec_disable_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tfec_disable_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tfec_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb30_disable [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb30_disable_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb30_disable_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb30_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_audio_1_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_audio_0_disable [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_audio_0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_tuner_disable [10:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tuner_disable_MASK 0x00000700 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tuner_disable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_tuner_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hdcp22_disable [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdcp22_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_pcie1_disable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_pcie1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rfm_disable [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rfm_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb3_disable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb3_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb2_disable [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb2_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb1_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_usb0_disable [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_usb0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_hdmi_tx1_disable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdmi_tx1_disable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdmi_tx1_disable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_hdmi_tx1_disable_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_0 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pcie0_disable [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie0_disable_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pcie0_disable_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_4kx2k_disable [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_4kx2k_disable_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_pass_thru_disable [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_pass_thru_disable_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_pass_thru_disable_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdmi_rx_disable [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdmi_rx_disable_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rv9_disable [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rv9_disable_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [20:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK 0x001f0000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_memsys_1_disable [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_memsys_1_disable_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_memsys_1_disable_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved1 [14:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_MASK 0x00006000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved1_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hvd0_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hvd0_disable_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved2 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved2_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved2_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vice2_0_disable [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vice2_0_disable_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vice2_0_disable_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_1 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_capsense_disable [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_capsense_disable_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_capsense_disable_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_moca2_disable [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca2_disable_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_moca2_disable_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_directv_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_directv_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_directv_disable_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_ldpc_disable [28:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_ldpc_disable_MASK 0x1fe00000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_ldpc_disable_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_cpus_to_use [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_cpus_to_use_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_cpus_to_use_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_tfec_disable [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tfec_disable_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tfec_disable_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb30_disable [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb30_disable_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb30_disable_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_audio_1_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_1_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_1_disable_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_audio_0_disable [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_0_disable_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_audio_0_disable_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_tuner_disable [10:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tuner_disable_MASK 0x00000700 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_tuner_disable_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hdcp22_disable [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdcp22_disable_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_pcie1_disable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie1_disable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_pcie1_disable_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rfm_disable [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rfm_disable_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb3_disable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb3_disable_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb2_disable [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb2_disable_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb1_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb1_disable_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_usb0_disable [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_usb0_disable_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_hdmi_tx1_disable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdmi_tx1_disable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_hdmi_tx1_disable_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_0 - Semaphore channel 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_1 - Semaphore channel 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_2 - Semaphore channel 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_3 - Semaphore channel 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_4 - Semaphore channel 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_5 - Semaphore channel 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_6 - Semaphore channel 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_7 - Semaphore channel 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_8 - Semaphore channel 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_9 - Semaphore channel 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_10 - Semaphore channel 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_11 - Semaphore channel 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_12 - Semaphore channel 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_13 - Semaphore channel 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_14 - Semaphore channel 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_15 - Semaphore channel 15 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GEN_WATCHDOG_0 - General watchdog timer 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GEN_WATCHDOG_1 - General watchdog timer 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_0 - General control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: bert_pinmux_ctrl [08:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_bert_pinmux_ctrl_MASK 0x000001c0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_bert_pinmux_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_bert_pinmux_ctrl_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_1_pd [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_1_pd_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: ana_detect_sdio_0_pd [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_ana_detect_sdio_0_pd_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_1_pad_modehv_override [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_1_pad_modehv_override_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: sdio_0_pad_modehv_override [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_sdio_0_pad_modehv_override_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: mii_genet_mac_select [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_genet_mac_select_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_1 - General control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: fsk_test_dac_edge_sel [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_edge_sel_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_edge_sel_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_edge_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: fsk_test_dac_en [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_en_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_en_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_fsk_test_dac_en_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_2 - General control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_3 - General control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_4 - General control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_5 - General control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_0 - General status register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: ebi_pad_config [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_ebi_pad_config_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_1 - General status register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_1_pad_vddo [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_1_pad_vddo_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: sdio_0_pad_vddo [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_sdio_0_pad_vddo_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_2 - General status register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK 0xfffc0000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_amp_en [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_amp_en_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel_gmii [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_gmii_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_gmii_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_gmii_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_modehv [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_modehv_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_modehv_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_modehv_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_0_pad_sel [14:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_MASK 0x00007000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_0_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_1_pad_amp_en [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_amp_en_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_amp_en_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_amp_en_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_1_pad_sel_gmii [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_gmii_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_gmii_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_gmii_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_1_pad_modehv [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_modehv_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_modehv_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_modehv_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: mtsif_1_pad_sel [08:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_MASK 0x000001c0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_mtsif_1_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_amp_en [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_amp_en_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel_gmii [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_gmii_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_modehv [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_modehv_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_sel_DRIVE_16MA 7 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_057 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_057_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_056 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_056_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_055 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_055_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_054 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_054_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_053 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_053_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_052 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_052_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_051 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_051_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_050 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_050_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_049 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_049_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_048 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_048_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_047 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_047_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_046 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_046_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_045 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_045_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_044 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_044_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_043 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_043_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_042 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_042_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_041 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_041_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_040 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_040_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_039 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_039_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_038 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_038_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_037 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_037_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_036 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_036_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_035 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_035_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_034 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_034_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_033 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_033_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_032 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_032_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_031 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_031_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: pad_mode_gpio_030 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_pad_mode_gpio_030_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: sdio_1_pad_slew [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_1_pad_slew_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_1_pad_slew_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_1_pad_slew_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: sdio_0_pad_slew [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_0_pad_slew_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_0_pad_slew_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_sdio_0_pad_slew_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_slew [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_slew_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: emmc_pad_sel [26:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_MASK 0x07000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_emmc_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_src [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: bspi_pad_sel [22:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_MASK 0x00700000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_bspi_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_src [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_4_pad_sel [18:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_MASK 0x00070000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_4_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_src [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_3_pad_sel [14:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_MASK 0x00007000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_3_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_src [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_2_pad_sel [10:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_MASK 0x00000700 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_2_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_src [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_1_pad_sel [06:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_MASK 0x00000070 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_1_pad_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_src [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: ebi_0_pad_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_ebi_0_pad_sel_DRIVE_16MA 7 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: egphy_test_pin_mux_sel [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_egphy_test_pin_mux_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_3 - General status register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: cpu_system_counter [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_cpu_system_counter_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_4 - General status register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: cpu_system_counter [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_cpu_system_counter_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_0 - Pinmux control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TSPI_S0_MOSI 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_ALT_TP_IN_12 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_137 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_137_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_137_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_137_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_137_GPIO_137 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_137_SC0_SPU 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_136 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_136_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_136_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_136_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_136_GPIO_136 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_136_SC0_AUX2 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_135 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_135_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_135_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_135_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_135_GPIO_135 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_135_SC0_AUX1 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_134 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_134_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_134_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_134_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_134_GPIO_134 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_134_SC0_IO 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_133 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_133_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_133_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_133_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_133_GPIO_133 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_133_SC0_CLK 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_132 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_132_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_132_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_132_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_132_GPIO_132 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_132_SC0_RST 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_131 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_131_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_131_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_131_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_131_GPIO_131 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_131_SC0_PRES 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_1 - Pinmux control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_06 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_06_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_06_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_06_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_06_EBI_DATA_06 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_06_TP_IN_06 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_05 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_05_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_05_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_05_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_05_EBI_DATA_05 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_05_TP_IN_05 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_04 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_04_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_04_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_04_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_04_EBI_DATA_04 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_04_TP_IN_04 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_03 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_03_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_03_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_03_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_03_EBI_DATA_03 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_03_TP_IN_03 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_02 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_02_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_02_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_02_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_02_EBI_DATA_02 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_02_TP_IN_02 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_01 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_01_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_01_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_01_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_01_EBI_DATA_01 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_01_TP_IN_01 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ebi_data_00 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_00_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_00_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_00_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_00_EBI_DATA_00 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ebi_data_00_TP_IN_00 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: ir_out [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ir_out_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ir_out_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ir_out_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ir_out_IR_OUT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ir_out_TSPI_S0_SCK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_ir_out_ALT_TP_OUT_18 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_2 - Pinmux control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_rwb [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rwb_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rwb_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rwb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rwb_EBI_RWB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_rwb_TP_IN_16 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_cs5b [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs5b_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs5b_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs5b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs5b_EBI_CS5B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs5b_EBI_ADDR_14 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs5b_TP_IN_15 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_cs4b [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs4b_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs4b_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs4b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs4b_EBI_CS4B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs4b_EBI_ADDR_13 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs4b_TP_IN_14 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_cs3b [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs3b_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs3b_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs3b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs3b_EBI_CS3B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs3b_TP_IN_13 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_cs2b [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs2b_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs2b_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs2b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs2b_EBI_CS2B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs2b_TP_IN_11 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_cs1b [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs1b_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs1b_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs1b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs1b_EBI_CS1B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs1b_TP_IN_09 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_cs0b [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs0b_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs0b_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs0b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs0b_EBI_CS0B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_cs0b_TP_IN_08 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: ebi_data_07 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data_07_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data_07_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data_07_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data_07_EBI_DATA_07 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_ebi_data_07_TP_IN_07 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_3 - Pinmux control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_nand_dqs [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_dqs_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_dqs_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_dqs_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_dqs_EBI_NAND_DQS 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_dqs_TSPI_S3_MOSI 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_nand_wpb [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_wpb_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_wpb_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_wpb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_wpb_EBI_NAND_WPB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_wpb_TSPI_S3_SS0B 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_nand_rbb [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_rbb_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_rbb_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_rbb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_rbb_EBI_NAND_RBB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_nand_rbb_TP_IN_22 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_dsb [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_dsb_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_dsb_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_dsb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_dsb_EBI_DSB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_dsb_TP_IN_21 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_tsb [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_tsb_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_tsb_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_tsb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_tsb_EBI_TSB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_tsb_TP_IN_20 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_rdb [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_rdb_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_rdb_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_rdb_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_rdb_EBI_RDB 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_rdb_TP_IN_19 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_we1b [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we1b_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we1b_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we1b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we1b_EBI_WE1B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we1b_TP_IN_18 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: ebi_we0b [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we0b_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we0b_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we0b_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we0b_EBI_WE0B 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_ebi_we0b_TP_IN_17 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_4 - Pinmux control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_007 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_GPIO_007 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_EBI_DATA_15 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_SD_CARD1_CLK_IN 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_SPI_M_MISO 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_LED_LD_15 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_CPU_TRACE_DATA11 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_TP_IN_27 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_007_PM_GPIO_007 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_006 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_GPIO_006 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_EBI_DATA_14 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_SD_CARD1_PRES 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_SPI_M_SCK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_LED_LD_14 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_CPU_TRACE_DATA10 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_TP_IN_26 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_006_PM_GPIO_006 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_005 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_GPIO_005 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_EBI_DATA_13 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_SD_CARD1_DAT3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_UART_TXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_LED_LD_13 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_CPU_TRACE_DATA9 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_VEC_VSYNC 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_TSPI_S1_MOSI 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_ALT_TP_OUT_04 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_005_PM_GPIO_005 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_004 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_GPIO_004 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_EBI_DATA_12 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_SD_CARD1_DAT2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_UART_RXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_LED_LD_12 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_CPU_TRACE_DATA8 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_VEC_HSYNC 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_TP_IN_25 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_004_PM_GPIO_004 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_003 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_GPIO_003 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_EBI_DATA_11 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_SD_CARD1_DAT1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_UART_TXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_LED_LD_11 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_CPU_TRACE_DATA7 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_IR_IN1 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_TSPI_S1_SS0B 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_ALT_TP_OUT_03 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_003_PM_GPIO_003 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_002 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_GPIO_002 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_EBI_DATA_10 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_SD_CARD1_DAT0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_UART_RXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_LED_LD_10 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_CPU_TRACE_DATA6 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_IR_INT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_TP_IN_24 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_002_PM_GPIO_002 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_001 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_GPIO_001 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_EBI_DATA_09 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_SD_CARD1_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_UART_TXD_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_LED_LD_9 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_CPU_TRACE_DATA5 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_RGMII_A_RX_OK 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_TSPI_S1_SCK 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_ALT_TP_OUT_02 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_001_PM_GPIO_001 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_000 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_GPIO_000 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_EBI_DATA_08 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_SD_CARD1_CMD 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_UART_RXD_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_LED_LD_8 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_CPU_TRACE_DATA4 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_RGMII_A_START_STOP 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_TP_IN_23 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_000_PM_GPIO_000 8 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_5 - Pinmux control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_015 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_GPIO_015 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_EBI_ADDR_09 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_PKT_ERROR0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_CHIP2POD_SCTL1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_RMX_SYNC0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_ENET1_ACTIVITY 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_TP_OUT_31 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_015_PM_GPIO_015 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_014 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_GPIO_014 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_EBI_ADDR_08 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_PKT_SYNC0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_CHIP2POD_SDO1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_RMX_DATA0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_ENET1_LINK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_TP_OUT_30 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_014_PM_GPIO_014 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_013 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_GPIO_013 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_EBI_ADDR_07 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_PKT_DATA0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_POD2CHIP_SDI1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_RMX_CLK0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_ENET0_ACTIVITY 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_TSPI_S2_SS0B 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_ALT_TP_IN_02 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_013_PM_GPIO_013 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_012 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_GPIO_012 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_EBI_ADDR_06 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_PKT_CLK0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_CHIP2POD_SCLK1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_ENET0_LINK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_TSPI_S2_SCK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_ALT_TP_IN_01 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_012_PM_GPIO_012 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_011 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_GPIO_011 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_EBI_ADDR_05 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_SD_CARD1_VOLT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_PWM2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_CPU_TRACE_DATA15 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_TSPI_S1_MISO 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_011_ALT_TP_OUT_10 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_010 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_GPIO_010 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_EBI_ADDR_04 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_SD_CARD1_LED 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_SPI_M_SS1B 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_PWM3 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_CPU_TRACE_DATA14 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_TSPI_S2_MOSI 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_ALT_TP_IN_00 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_010_PM_GPIO_010 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_009 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_GPIO_009 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_EBI_ADDR_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_SD_CARD1_PWR0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_SPI_M_SS0B 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_PWM0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_CPU_TRACE_DATA13 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_TP_IN_31 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_009_PM_GPIO_009 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_008 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_GPIO_008 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_EBI_WAITB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_SD_CARD1_WPROT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_SPI_M_MOSI 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_PWM1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_CPU_TRACE_DATA12 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_TP_IN_28 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_008_PM_GPIO_008 7 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_6 - Pinmux control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_023 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_GPIO_023 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_MTSIF1_RX_DATA2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_MTSIF1_TX_DATA2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_PKT_CLK1_ALT2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_023_PM_GPIO_023 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_022 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_GPIO_022 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_PKT_VALID0_ALT2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_ENET2_ACTIVITY 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_ENET0_ACTIVITY 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_022_PM_GPIO_022 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_021 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_GPIO_021 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_MTSIF1_RX_DATA1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_MTSIF1_TX_DATA1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_PKT_ERROR0_ALT2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_021_PM_GPIO_021 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_020 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_GPIO_020 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_MTSIF1_RX_SYNC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_MTSIF1_TX_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_PKT_SYNC0_ALT2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_020_PM_GPIO_020 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_019 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_GPIO_019 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_MTSIF1_RX_DATA0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_MTSIF1_TX_DATA0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_PKT_DATA0_ALT2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_019_PM_GPIO_019 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_018 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_GPIO_018 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_MTSIF1_RX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_MTSIF1_TX_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_PKT_CLK0_ALT2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_018_PM_GPIO_018 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_017 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_GPIO_017 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_EBI_ADDR_11 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_MTSIF_ATS_INC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_TSIO_VCTRL 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_RMX_PAUSE0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_ENET2_ACTIVITY 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_DEMOD_MTSIF_ATS_INC 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_ALT_TP_IN_16 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_017_PM_GPIO_017 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_016 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_GPIO_016 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_EBI_ADDR_10 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_PKT_VALID0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_MTSIF_ATS_RST 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_RMX_VALID0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_ENET2_LINK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_DEMOD_MTSIF_ATS_RST 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_TP_OUT_27 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_016_PM_GPIO_016 8 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_7 - Pinmux control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_031 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_GPIO_031 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_CHIP2POD_MCLKO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_RMXP_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_EBI_ADDR_15 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_ALT_TP_IN_03 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_031_PM_GPIO_031 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_030 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_GPIO_030 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_POD2CHIP_MCLKI 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_PPKT_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_EBI_ADDR_14 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_ALT_TP_OUT_17 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_030_PM_GPIO_030 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_029 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_GPIO_029 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_PWM0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_ENET0_ACTIVITY 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_IR_IN1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_029_PM_GPIO_029 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_028 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_GPIO_028 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_MTSIF1_RX_DATA7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_MTSIF1_TX_DATA7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_ENET0_LINK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_028_PM_GPIO_028 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_027 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_GPIO_027 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_MTSIF1_RX_DATA6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_MTSIF1_TX_DATA6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_PKT_VALID1_ALT2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_027_PM_GPIO_027 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_026 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_GPIO_026 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_MTSIF1_RX_DATA5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_MTSIF1_TX_DATA5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_PKT_ERROR1_ALT2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_026_PM_GPIO_026 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_025 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_GPIO_025 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_MTSIF1_RX_DATA4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_MTSIF1_TX_DATA4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_PKT_SYNC1_ALT2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_025_PM_GPIO_025 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_024 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_GPIO_024 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_MTSIF1_RX_DATA3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_MTSIF1_TX_DATA3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_PKT_DATA1_ALT2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_024_PM_GPIO_024 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_8 - Pinmux control register 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_039 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_GPIO_039 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_POD2CHIP_MDI1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_PPKT_DATA1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_UART_RXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_ALT_TP_IN_10 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_039_PM_GPIO_039 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_038 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_GPIO_038 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_POD2CHIP_MDI0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_PPKT_DATA0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_UART_TXD_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_ALT_TP_OUT_11 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_038_PM_GPIO_038 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_037 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_GPIO_037 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_POD2CHIP_MIVAL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_PPKT_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_UART_RXD_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_ALT_TP_IN_09 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_037_PM_GPIO_037 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_036 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_GPIO_036 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_POD2CHIP_MISTRT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_PPKT_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_ALT_TP_IN_08 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_036_PM_GPIO_036 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_035 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_GPIO_035 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_CHIP2POD_SCTL0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_SPI_M_SS0B 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_EBI_ADDR_02 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_VEC_VSYNC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_ALT_TP_IN_07 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_035_PM_GPIO_035 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_034 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_GPIO_034 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_CHIP2POD_SDO0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_SPI_M_MOSI 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_EBI_ADDR_00 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_VEC_HSYNC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_ALT_TP_IN_06 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_034_PM_GPIO_034 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_033 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_GPIO_033 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_POD2CHIP_SDI0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_SPI_M_MISO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_ALT_TP_IN_05 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_033_PM_GPIO_033 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_032 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_GPIO_032 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_CHIP2POD_SCLK0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_SPI_M_SCK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_EBI_ADDR_01 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_ALT_TP_IN_04 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_032_PM_GPIO_032 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_9 - Pinmux control register 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_047 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_GPIO_047 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_CHIP2POD_MOVAL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_RMXP_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_EBI_ADDR_16 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_SC1_VCC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_ALT_TP_IN_22 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_047_PM_GPIO_047 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_046 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_GPIO_046 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_POD2CHIP_MICLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_PPKT_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_EBI_ADDR_13 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_POD2CHIP_MCLKI 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_ALT_TP_IN_21 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_046_PM_GPIO_046 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_045 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_GPIO_045 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_POD2CHIP_MDI7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_PPKT_DATA7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_ALT_TP_IN_20 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_045_PM_GPIO_045 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_044 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_GPIO_044 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_POD2CHIP_MDI6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_PPKT_DATA6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_ALT_TP_IN_19 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_044_PM_GPIO_044 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_043 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_GPIO_043 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_POD2CHIP_MDI5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_PPKT_DATA5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_ALT_TP_IN_18 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_043_PM_GPIO_043 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_042 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_GPIO_042 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_POD2CHIP_MDI4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_PPKT_DATA4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_UART_TXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_ALT_TP_OUT_13 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_042_PM_GPIO_042 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_041 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_GPIO_041 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_POD2CHIP_MDI3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_PPKT_DATA3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_UART_RXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_ALT_TP_IN_11 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_041_PM_GPIO_041 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_040 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_GPIO_040 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_POD2CHIP_MDI2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_PPKT_DATA2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_UART_TXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_ALT_TP_OUT_12 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_040_PM_GPIO_040 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_10 - Pinmux control register 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_055 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_GPIO_055 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_CHIP2POD_MDO6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_RMXP_DATA6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_EBI_ADDR_24 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_ALT_TP_IN_30 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_055_PM_GPIO_055 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_054 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_GPIO_054 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_CHIP2POD_MDO5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_RMXP_DATA5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_EBI_ADDR_23 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_SC1_VPP 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_ALT_TP_IN_29 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_054_PM_GPIO_054 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_053 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_GPIO_053 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_CHIP2POD_MDO4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_RMXP_DATA4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_EBI_ADDR_22 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_SC1_AUX2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_ALT_TP_IN_28 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_053_PM_GPIO_053 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_052 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_GPIO_052 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_CHIP2POD_MDO3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_RMXP_DATA3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_EBI_ADDR_21 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_SC1_AUX1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_EXT_IRQB_7 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_ALT_TP_IN_27 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_052_PM_GPIO_052 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_051 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_GPIO_051 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_CHIP2POD_MDO2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_RMXP_DATA2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_EBI_ADDR_20 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_SC1_PRES 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_EXT_IRQB_6 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_ALT_TP_IN_26 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_051_PM_GPIO_051 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_050 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_GPIO_050 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_CHIP2POD_MDO1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_RMXP_DATA1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_EBI_ADDR_19 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_SC1_IO 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_EXT_IRQB_5 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_ALT_TP_IN_25 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_050_PM_GPIO_050 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_049 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_GPIO_049 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_CHIP2POD_MDO0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_RMXP_DATA0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_EBI_ADDR_18 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_SC1_RST 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_EXT_IRQB_4 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_ALT_TP_IN_24 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_049_PM_GPIO_049 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_048 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_GPIO_048 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_CHIP2POD_MOSTRT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_RMXP_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_EBI_ADDR_17 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_SC1_CLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_ALT_TP_IN_23 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_048_PM_GPIO_048 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_11 - Pinmux control register 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_063 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_GPIO_063 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_SC0_AUX1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_I2S_CLK0_OUT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_I2S_CLK0_IN 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_TP_OUT_22 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_063_PM_GPIO_063 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_062 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_GPIO_062 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_SC0_PRES 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_TP_OUT_21 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_062_PM_GPIO_062 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_061 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_GPIO_061 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_SC0_IO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_IR_IN1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_TP_OUT_20 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_061_PM_GPIO_061 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_060 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_GPIO_060 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_SC0_RST 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_IR_INT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_TP_OUT_19 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_060_PM_GPIO_060 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_059 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_GPIO_059 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_SC0_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_TP_OUT_18 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_059_PM_GPIO_059 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_058 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_GPIO_058 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_SC0_VCC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_TEST_THP 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_TP_OUT_17 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_058_PM_GPIO_058 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_057 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_GPIO_057 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_CHIP2POD_MOCLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_RMXP_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_EBI_ADDR_12 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_CHIP2POD_MCLKO 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_ALT_TP_OUT_16 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_057_PM_GPIO_057 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_056 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_GPIO_056 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_CHIP2POD_MDO7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_RMXP_DATA7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_EBI_ADDR_25 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_ALT_TP_IN_15 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_056_PM_GPIO_056 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_12 - Pinmux control register 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_071 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_GPIO_071 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_MTSIF0_RX_DATA2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_PKT_CLK3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_UART_RTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_EXT_IRQB_4 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_ALT_TP_OUT_26 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_071_PM_GPIO_071 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_070 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_GPIO_070 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_PKT_VALID2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_UART_CTS_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_EXT_IRQB_3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_ENET2_LINK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_ENET0_LINK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_ALT_TP_OUT_25 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_070_PM_GPIO_070 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_069 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_GPIO_069 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_MTSIF0_RX_DATA1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_PKT_ERROR2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_UART_TXD_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_IR_IN1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_ALT_TP_OUT_19 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_069_PM_GPIO_069 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_068 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_GPIO_068 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_MTSIF0_RX_SYNC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_PKT_SYNC2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_UART_RXD_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_EXT_IRQB_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_ALT_TP_IN_17 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_068_PM_GPIO_068 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_067 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_GPIO_067 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_MTSIF0_RX_DATA0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_PKT_DATA2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_UART_RTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_EXT_IRQB_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_ALT_TP_OUT_24 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_067_PM_GPIO_067 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_066 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_GPIO_066 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_MTSIF0_RX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_PKT_CLK2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_UART_CTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_EXT_IRQB_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_ALT_TP_OUT_23 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_066_PM_GPIO_066 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_065 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_GPIO_065 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_SC0_VPP 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_I2S_LR0_OUT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_I2S_LR0_IN 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_TP_OUT_24 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_065_PM_GPIO_065 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_064 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_GPIO_064 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_SC0_AUX2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_I2S_DATA0_OUT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_I2S_DATA0_IN 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_TP_OUT_23 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_064_PM_GPIO_064 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_13 - Pinmux control register 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_079 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_GPIO_079 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_RGMII_A_RX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_PKT_CLK0_ALT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_VO0_656_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_IR_IN1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_079_PM_GPIO_079 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_078 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_GPIO_078 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_MTSIF_ATS_RST 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_DEMOD_MTSIF_ATS_RST 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_ALT_TP_OUT_22 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_078_PM_GPIO_078 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_077 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_GPIO_077 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_MTSIF_ATS_INC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_DEMOD_MTSIF_ATS_INC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_UART_RTS_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_ALT_TP_OUT_21 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_077_PM_GPIO_077 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_076 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_GPIO_076 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_MTSIF0_RX_DATA7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_PKT_VALID2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_UART_CTS_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_ALT_TP_OUT_20 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_076_PM_GPIO_076 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_075 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_GPIO_075 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_MTSIF0_RX_DATA6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_PKT_VALID3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_UART_TXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_ALT_TP_OUT_15 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_075_PM_GPIO_075 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_074 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_GPIO_074 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_MTSIF0_RX_DATA5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_PKT_ERROR3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_UART_RXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_ALT_TP_IN_14 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_074_PM_GPIO_074 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_073 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_GPIO_073 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_MTSIF0_RX_DATA4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_PKT_SYNC3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_UART_TXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_ALT_TP_OUT_14 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_073_PM_GPIO_073 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_072 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_GPIO_072 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_MTSIF0_RX_DATA3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_PKT_DATA3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_UART_RXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_EXT_IRQB_5 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_ALT_TP_IN_13 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_072_PM_GPIO_072 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_14 - Pinmux control register 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_087 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_GPIO_087 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_RGMII_A_TXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_PKT_ERROR1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_VO0_656_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_UART_RXD_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_087_PM_GPIO_087 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_086 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_GPIO_086 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_RGMII_A_TX_EN_CTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_PKT_SYNC1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_VO0_656_7 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_UART_RTS_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_086_PM_GPIO_086 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_085 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_GPIO_085 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_RGMII_A_TX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_PKT_DATA1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_VO0_656_6 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_UART_CTS_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_085_PM_GPIO_085 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_084 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_GPIO_084 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_RGMII_A_RXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_PKT_CLK1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_VO0_656_5 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_UART_TXD_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_084_PM_GPIO_084 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_083 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_GPIO_083 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_RGMII_A_RXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_PKT_VALID0_ALT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_VO0_656_4 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_UART_RXD_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_083_PM_GPIO_083 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_082 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_GPIO_082 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_RGMII_A_RXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_PKT_ERROR0_ALT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_VO0_656_3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_UART_RTS_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_082_PM_GPIO_082 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_081 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_GPIO_081 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_RGMII_A_RXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_PKT_SYNC0_ALT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_VO0_656_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_UART_CTS_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_081_PM_GPIO_081 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_080 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_GPIO_080 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_RGMII_A_RX_EN_CTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_PKT_DATA0_ALT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_VO0_656_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_080_PM_GPIO_080 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_15 - Pinmux control register 15 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_095 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_GPIO_095 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_RGMIIA_IRQ 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_SPI_M_SCK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_I2S_LR0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_RMX_SYNC0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_ALT_TP_OUT_29 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_095_PM_GPIO_095 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_094 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_GPIO_094 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_MII_A_TX_ERR 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_SPI_M_SS0B 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_I2S_DATA0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_RMX_DATA0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_ENET0_ACTIVITY 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_SDS_BERT_DATA 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_ALT_TP_OUT_28 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_094_PM_GPIO_094 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_093 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_GPIO_093 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_MII_A_RX_ERR 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_SPI_M_MOSI 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_I2S_CLK0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_RMX_CLK0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_ENET0_LINK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_SDS_BERT_CLK 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_ALT_TP_OUT_27 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_093_PM_GPIO_093 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_092 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_GPIO_092 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_RGMII_A_MDC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_UART_TXD_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_092_PM_GPIO_092 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_091 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_GPIO_091 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_RGMII_A_MDIO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_UART_RXD_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_091_PM_GPIO_091 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_090 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_GPIO_090 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_RGMII_A_TXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_VEC_VSYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_UART_RTS_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_090_PM_GPIO_090 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_089 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_GPIO_089 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_RGMII_A_TXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_VEC_HSYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_TTX0_REQ 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_UART_CTS_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_089_PM_GPIO_089 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_088 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_GPIO_088 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_RGMII_A_TXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_PKT_VALID1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_TTX0_DATA 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_UART_TXD_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_088_PM_GPIO_088 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_16 - Pinmux control register 16 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_103 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_GPIO_103 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_SD_CARD0_DAT3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_UART_RTS_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_EXT_IRQB_4 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_CPU_TRACE_DATA3 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_TP_OUT_29 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_103_PM_GPIO_103 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_102 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_GPIO_102 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_SD_CARD0_DAT2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_PKT_VALID1_ALT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_UART_CTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_EXT_IRQB_3 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_CPU_TRACE_DATA2 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_TP_OUT_28 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_102_PM_GPIO_102 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_101 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_GPIO_101 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_SD_CARD0_DAT1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_PKT_ERROR1_ALT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_UART_TXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_EXT_IRQB_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_CPU_TRACE_DATA1 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_TSPI_S3_SCK 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_ALT_TP_OUT_05 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_101_PM_GPIO_101 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_100 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_GPIO_100 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_SD_CARD0_DAT0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_PKT_SYNC1_ALT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_UART_RXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_EXT_IRQB_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_CPU_TRACE_DATA0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_TP_IN_30 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_100_PM_GPIO_100 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_099 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_GPIO_099 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_SD_CARD0_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_PKT_DATA1_ALT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_UART_RTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_EXT_IRQB_0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_CPU_TRACE_CLK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_TP_OUT_26 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_099_PM_GPIO_099 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_098 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_GPIO_098 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_SD_CARD0_CMD 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_PKT_CLK1_ALT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_UART_CTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_EXT_IRQB_5 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_TP_OUT_25 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_098_PM_GPIO_098 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_097 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_GPIO_097 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_MII_A_COL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_EXT_SC_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_SPI_M_SS1B 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_ENET1_ACTIVITY 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_RMX_PAUSE0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_MTSIF_ATS_RST 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_DEMOD_MTSIF_ATS_RST 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_ALT_TP_OUT_31 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_097_PM_GPIO_097 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: gpio_096 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_GPIO_096 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_MII_A_CRS 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_SC_CLK_OUT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_SPI_M_MISO 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_ENET1_LINK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_RMX_VALID0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_MTSIF_ATS_INC 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_DEMOD_MTSIF_ATS_INC 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_ALT_TP_OUT_30 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_gpio_096_PM_GPIO_096 9 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_17 - Pinmux control register 17 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_111 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_GPIO_111 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_UART_RXD_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_EXT_SC_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_AUD_FS_CLK0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_SPI_S_SS0B 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_ALT_TP_IN_31 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_111_PM_GPIO_111 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_110 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_GPIO_110 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_UART_TXD_0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_SC_CLK_OUT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_IR_INT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_SPI_S_MISO 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_110_ALT_TP_OUT_07 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_109 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_GPIO_109 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_SD_CARD0_VOLT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_TSPI_S3_MISO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_109_ALT_TP_OUT_09 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_108 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_GPIO_108 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_SD_CARD0_PWR0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_RMX_VALID1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_PWM2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_TSPI_S2_MISO 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_108_ALT_TP_OUT_08 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_107 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_GPIO_107 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_SD_CARD0_WPROT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_RMX_PAUSE1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_UART_RTS_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_PWM3 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_TP_OUT_05 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_107_PM_GPIO_107 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_106 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_GPIO_106 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_SD_CARD0_CLK_IN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_RMX_SYNC1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_UART_CTS_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_PWM0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_SATA_MDIO 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_TP_OUT_04 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_106_PM_GPIO_106 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_105 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_GPIO_105 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_SD_CARD0_LED 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_RMX_DATA1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_UART_TXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_PWM1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_AUD_FS_CLK0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_SC_CLK_OUT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_SATA_MDCLK 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_ALT_TP_OUT_06 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_105_PM_GPIO_105 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: gpio_104 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_GPIO_104 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_SD_CARD0_PRES 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_RMX_CLK1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_UART_RXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_IR_IN1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_TP_IN_29 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_gpio_104_PM_GPIO_104 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_18 - Pinmux control register 18 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_119 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_GPIO_119 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_RGMII_A_TX_EN_CTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_VO0_656_7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_UART_RTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_119_PM_GPIO_119 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_118 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_GPIO_118 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_RGMII_A_TX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_VO0_656_6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_UART_CTS_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_118_PM_GPIO_118 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_117 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_GPIO_117 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_RGMII_A_RXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_VO0_656_5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_UART_TXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_117_PM_GPIO_117 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_116 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_GPIO_116 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_RGMII_A_RXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_VO0_656_4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_UART_RXD_1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_116_PM_GPIO_116 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_115 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_GPIO_115 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_RGMII_A_RXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_VO0_656_3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_UART_RTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_115_PM_GPIO_115 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_114 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_GPIO_114 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_RGMII_A_RXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_VO0_656_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_UART_CTS_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_114_PM_GPIO_114 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_113 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_GPIO_113 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_RGMII_A_RX_EN_CTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_VO0_656_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_113_PM_GPIO_113 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: gpio_112 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_GPIO_112 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_RGMII_A_RX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_VO0_656_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_IR_IN1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_gpio_112_PM_GPIO_112 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_19 - Pinmux control register 19 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_127 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_GPIO_127 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_MII_A_TX_ERR 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_SPI_M_SS0B 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_I2S_DATA0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_ENET0_ACTIVITY 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_127_PM_GPIO_127 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_126 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_GPIO_126 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_MII_A_RX_ERR 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_SPI_M_MOSI 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_I2S_CLK0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_ENET0_LINK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_126_PM_GPIO_126 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_125 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_GPIO_125 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_RGMII_A_MDC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_SPI_S_SS0B 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_UART_TXD_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_125_PM_GPIO_125 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_124 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_GPIO_124 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_RGMII_A_MDIO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_SPI_S_MISO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_UART_RXD_0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_124_PM_GPIO_124 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_123 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_GPIO_123 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_RGMII_A_TXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_VEC_VSYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_UART_RTS_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_123_PM_GPIO_123 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_122 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_GPIO_122 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_RGMII_A_TXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_VEC_HSYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_UART_CTS_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_TTX0_REQ 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_122_PM_GPIO_122 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_121 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_GPIO_121 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_RGMII_A_TXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_UART_TXD_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_TTX0_DATA 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_121_PM_GPIO_121 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_19 :: gpio_120 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_GPIO_120 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_RGMII_A_TXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_VO0_656_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_UART_RXD_2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_19_gpio_120_PM_GPIO_120 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_20 - Pinmux control register 20 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: sgpio_04 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_04_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_04_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_04_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_04_SGPIO_04 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_04_MOCA_BSC_SCL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_04_BSC_M6_SCL 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: sgpio_03 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_03_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_03_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_03_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_03_SGPIO_03 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_03_BSC_M5_SDA 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: sgpio_02 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_02_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_02_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_02_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_02_SGPIO_02 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_02_BSC_M5_SCL 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: sgpio_01 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_01_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_01_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_01_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_01_SGPIO_01 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_01_BSC_M4_SDA 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: sgpio_00 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_00_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_00_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_00_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_00_SGPIO_00 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_sgpio_00_BSC_M4_SCL 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_130 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_GPIO_130 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_MII_A_COL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_SPI_M_SS1B 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_MTSIF_ATS_RST 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_DEMOD_MTSIF_ATS_RST 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_ENET1_ACTIVITY 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_130_PM_GPIO_130 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_129 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_GPIO_129 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_MII_A_CRS 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_SPI_M_MISO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_MTSIF_ATS_INC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_DEMOD_MTSIF_ATS_INC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_ENET1_LINK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_129_PM_GPIO_129 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_20 :: gpio_128 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_GPIO_128 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_RGMIIA_IRQ 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_SPI_M_SCK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_I2S_LR0_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_20_gpio_128_PM_GPIO_128 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_21 - Pinmux control register 21 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: reserved0 [31:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_reserved0_MASK 0xfffff000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_reserved0_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: byp_clk_1 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_1_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_1_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_1_BYP_CLK_1 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_1_OBSRV_CLK_1 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: byp_clk_0 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_0_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_0_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_0_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_0_BYP_CLK_0 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_byp_clk_0_OBSRV_CLK_0 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_21 :: sgpio_05 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_SGPIO_05 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_MOCA_BSC_SDA 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_21_sgpio_05_BSC_M6_SDA 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: pcie_clkreqb_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_clkreqb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: pcie_rstb_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_pcie_rstb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved1 [23:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_MASK 0x00ffffff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: emmc_cmd_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_cmd_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_cmd_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_cmd_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_cmd_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_cmd_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_emmc_cmd_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_wpb_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_wpb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_holdb_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_holdb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_mosi_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_miso_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_sck_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [17:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK 0x0003fc00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: pcie1_clkreqb_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_clkreqb_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_clkreqb_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_clkreqb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_clkreqb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_clkreqb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_clkreqb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: pcie1_rstb_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pcie1_rstb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved1 [05:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_MASK 0x0000003f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_cs5b_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs5b_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs5b_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs5b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs5b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs5b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs5b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_cs4b_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs4b_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs4b_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs4b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs4b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs4b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs4b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_cs3b_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs3b_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs3b_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs3b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs3b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs3b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs3b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_cs2b_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs2b_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs2b_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs2b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs2b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs2b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs2b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_cs1b_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs1b_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs1b_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs1b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs1b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs1b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs1b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_cs0b_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs0b_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs0b_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs0b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs0b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs0b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_cs0b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_07_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_07_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_07_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_07_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_07_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_07_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_07_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_06_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_06_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_06_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_06_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_06_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_06_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_06_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_05_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_05_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_05_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_05_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_05_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_05_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_05_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_04_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_04_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_04_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_04_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_04_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_04_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_04_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_03_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_03_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_03_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_03_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_03_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_03_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_03_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_02_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_02_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_02_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_02_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_02_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_02_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_02_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_01_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_01_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_01_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_01_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_01_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_01_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_01_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: ebi_data_00_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_00_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_00_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_00_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_00_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_00_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_ebi_data_00_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: emmc_clk_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_emmc_clk_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_emmc_clk_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_emmc_clk_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_emmc_clk_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_emmc_clk_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_emmc_clk_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_005_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_005_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_005_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_005_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_005_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_005_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_005_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_004_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_004_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_004_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_004_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_004_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_004_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_004_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_003_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_003_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_003_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_003_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_003_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_003_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_003_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_002_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_002_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_002_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_002_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_002_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_002_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_002_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_001_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_001_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_001_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_001_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_001_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_001_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_001_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_000_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_000_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_000_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_000_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_000_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_000_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_000_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_nand_dqs_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_dqs_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_dqs_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_dqs_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_dqs_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_dqs_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_dqs_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_nand_wpb_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_wpb_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_wpb_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_wpb_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_wpb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_wpb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_wpb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_nand_rbb_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_nand_rbb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_dsb_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_dsb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_tsb_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_tsb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_rdb_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rdb_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_we1b_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we1b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_we0b_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_we0b_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: ebi_rwb_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_ebi_rwb_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_020_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_020_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_020_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_020_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_020_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_020_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_020_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_019_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_019_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_019_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_019_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_019_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_019_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_019_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_018_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_018_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_018_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_018_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_018_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_018_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_018_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_017_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_017_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_017_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_017_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_017_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_017_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_017_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_016_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_016_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_016_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_016_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_016_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_016_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_016_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_015_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_015_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_015_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_015_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_015_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_015_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_015_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_014_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_014_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_014_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_014_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_014_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_014_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_014_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_013_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_013_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_013_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_013_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_013_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_013_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_013_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_012_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_012_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_012_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_012_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_012_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_012_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_012_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_010_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_010_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_010_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_010_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_010_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_010_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_010_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_009_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_009_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_009_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_009_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_009_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_009_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_009_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_008_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_008_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_008_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_008_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_008_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_008_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_008_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_007_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_007_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_007_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_007_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_007_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_007_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_007_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_006_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_006_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_006_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_006_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_006_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_006_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_006_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_035_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_035_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_035_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_035_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_035_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_035_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_035_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_034_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_034_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_034_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_034_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_034_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_034_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_034_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_033_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_033_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_033_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_033_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_033_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_033_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_033_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_032_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_032_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_032_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_032_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_032_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_032_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_032_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_031_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_031_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_031_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_031_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_031_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_031_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_031_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_030_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_030_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_030_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_030_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_030_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_030_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_030_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_029_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_029_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_029_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_029_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_029_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_029_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_029_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_028_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_028_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_028_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_028_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_028_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_028_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_028_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_027_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_027_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_027_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_027_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_027_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_027_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_027_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_026_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_026_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_026_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_026_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_026_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_026_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_026_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_025_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_025_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_025_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_025_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_025_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_025_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_025_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_024_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_024_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_024_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_024_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_024_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_024_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_024_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_023_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_023_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_023_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_023_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_023_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_023_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_023_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_022_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_022_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_022_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_022_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_022_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_022_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_022_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_021_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_021_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_021_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_021_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_021_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_021_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_021_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_050_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_050_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_050_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_050_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_050_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_050_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_050_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_049_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_049_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_049_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_049_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_049_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_049_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_049_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_048_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_048_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_048_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_048_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_048_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_048_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_048_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_047_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_047_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_047_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_047_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_047_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_047_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_047_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_046_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_046_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_046_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_046_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_046_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_046_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_046_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_045_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_045_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_045_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_045_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_045_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_045_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_045_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_044_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_044_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_044_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_044_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_044_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_044_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_044_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_043_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_043_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_043_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_043_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_043_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_043_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_043_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_042_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_042_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_042_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_042_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_042_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_042_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_042_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_041_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_041_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_041_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_041_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_041_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_041_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_041_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_040_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_040_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_040_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_040_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_040_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_040_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_040_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_039_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_039_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_039_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_039_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_039_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_039_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_039_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_038_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_038_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_038_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_038_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_038_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_038_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_038_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_037_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_037_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_037_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_037_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_037_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_037_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_037_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_036_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_036_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_036_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_036_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_036_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_036_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_036_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_065_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_065_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_065_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_065_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_065_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_065_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_065_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_064_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_064_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_064_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_064_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_064_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_064_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_064_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_063_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_063_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_063_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_063_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_063_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_063_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_063_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_062_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_062_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_062_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_062_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_062_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_062_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_062_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_061_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_061_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_061_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_061_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_061_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_061_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_061_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_060_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_060_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_060_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_060_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_060_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_060_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_060_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_059_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_059_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_059_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_059_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_059_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_059_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_059_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_058_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_058_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_058_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_058_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_058_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_058_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_058_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_057_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_057_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_057_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_057_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_057_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_057_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_057_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_056_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_056_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_056_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_056_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_056_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_056_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_056_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_055_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_055_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_055_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_055_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_055_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_055_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_055_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_054_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_054_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_054_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_054_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_054_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_054_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_054_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_053_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_053_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_053_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_053_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_053_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_053_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_053_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_052_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_052_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_052_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_052_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_052_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_052_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_052_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_051_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_051_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_051_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_051_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_051_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_051_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_051_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_080_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_080_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_080_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_080_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_080_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_080_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_080_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_079_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_079_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_079_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_079_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_079_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_079_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_079_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_078_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_078_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_078_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_078_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_078_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_078_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_078_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_077_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_077_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_077_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_077_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_077_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_077_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_077_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_076_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_076_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_076_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_076_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_076_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_076_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_076_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_075_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_075_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_075_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_075_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_075_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_075_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_075_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_074_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_074_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_074_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_074_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_074_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_074_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_074_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_073_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_073_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_073_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_073_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_073_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_073_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_073_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_072_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_072_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_072_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_072_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_072_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_072_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_072_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_071_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_071_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_071_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_071_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_071_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_071_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_071_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_070_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_070_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_070_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_070_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_070_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_070_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_070_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_069_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_069_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_069_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_069_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_069_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_069_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_069_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_068_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_068_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_068_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_068_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_068_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_068_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_068_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_067_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_067_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_067_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_067_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_067_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_067_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_067_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_066_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_066_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_066_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_066_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_066_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_066_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_066_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_095_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_095_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_095_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_095_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_095_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_095_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_095_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_094_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_094_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_094_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_094_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_094_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_094_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_094_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_093_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_093_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_093_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_093_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_093_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_093_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_093_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_092_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_092_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_092_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_092_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_092_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_092_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_092_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_091_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_091_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_091_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_091_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_091_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_091_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_091_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_090_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_090_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_090_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_090_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_090_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_090_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_090_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_089_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_089_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_089_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_089_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_089_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_089_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_089_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_088_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_088_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_088_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_088_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_088_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_088_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_088_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_087_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_087_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_087_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_087_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_087_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_087_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_087_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_086_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_086_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_086_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_086_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_086_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_086_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_086_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_085_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_085_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_085_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_085_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_085_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_085_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_085_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_084_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_084_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_084_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_084_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_084_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_084_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_084_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_083_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_083_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_083_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_083_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_083_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_083_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_083_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_082_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_082_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_082_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_082_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_082_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_082_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_082_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_081_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_081_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_081_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_081_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_081_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_081_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_081_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: reserved0 [29:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_MASK 0x3f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_reserved0_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_107_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_107_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_107_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_107_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_107_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_107_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_107_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_106_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_106_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_106_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_106_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_106_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_106_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_106_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_105_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_105_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_105_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_105_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_105_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_105_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_105_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_104_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_104_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_104_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_104_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_104_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_104_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_104_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_103_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_103_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_103_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_103_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_103_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_103_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_103_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_102_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_102_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_102_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_102_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_102_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_102_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_102_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_101_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_101_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_101_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_101_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_101_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_101_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_101_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_100_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_100_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_100_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_100_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_100_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_100_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_100_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_099_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_099_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_099_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_099_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_099_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_099_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_099_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_098_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_098_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_098_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_098_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_098_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_098_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_098_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_097_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_097_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_097_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_097_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_097_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_097_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_097_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_096_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_096_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_096_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_096_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_096_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_096_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_096_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_125_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_125_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_125_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_125_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_125_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_125_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_125_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_124_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_124_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_124_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_124_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_124_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_124_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_124_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_123_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_123_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_123_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_123_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_123_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_123_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_123_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_122_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_122_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_122_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_122_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_122_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_122_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_122_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_121_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_121_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_121_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_121_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_121_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_121_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_121_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_120_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_120_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_120_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_120_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_120_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_120_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_120_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_119_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_119_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_119_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_119_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_119_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_119_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_119_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_118_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_118_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_118_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_118_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_118_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_118_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_118_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_117_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_117_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_117_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_117_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_117_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_117_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_117_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_116_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_116_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_116_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_116_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_116_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_116_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_116_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_115_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_115_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_115_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_115_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_115_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_115_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_115_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_114_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_114_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_114_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_114_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_114_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_114_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_114_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_113_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_113_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_113_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_113_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_113_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_113_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_113_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_112_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_112_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_112_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_112_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_112_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_112_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_112_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_111_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_111_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_111_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_111_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_111_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_111_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_111_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_12 - Pad pull-up/pull-down control register 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: spare_pad_ctrl_12 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: reserved0 [29:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_MASK 0x3ffffc00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_130_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_130_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_130_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_130_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_130_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_130_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_130_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_129_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_129_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_129_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_129_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_129_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_129_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_129_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_128_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_128_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_128_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_128_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_128_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_128_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_128_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_127_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_127_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_127_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_127_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_127_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_127_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_127_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: gpio_126_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_126_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_126_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_126_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_126_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_126_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_gpio_126_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_13 - Pad pull-up/pull-down control register 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: reserved0 [31:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved0_MASK 0xfc000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved0_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: spare_pad_ctrl_13 [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: reserved1 [23:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved1_MASK 0x00ffffff |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_9 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_9_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_9_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_8 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_8_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_8_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_6 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_6_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_6_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_2_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_clk_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_clk_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_CTRL - Reset control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_SOURCE_ENABLE - Reset source enable |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK 0xfffffc00 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_MASTER_RESET - Software master reset |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HW_RESET_EXTENSION - Hardware reset extension |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_MONITOR - Reset Monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0 |
| |
| /*************************************************************************** |
| *RESET_HISTORY - Reset history |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:20] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK 0xfff00000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: gen_watchdog_1_reset [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_gen_watchdog_1_reset_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_0_reset [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_0_reset_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_1_reset [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_1_reset_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_1_reset [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_1_reset_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_0_SET - Software init 0 set |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved_for_padding0 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved_for_padding0_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved_for_padding0_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_moca_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_hvd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: reserved_for_padding1 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved_for_padding1_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_reserved_for_padding1_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie1_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_pcie0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_start_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_webcpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_0_CLEAR - Software init 0 clear |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved_for_padding0 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved_for_padding0_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved_for_padding0_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_moca_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_hvd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: reserved_for_padding1 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved_for_padding1_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_reserved_for_padding1_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie1_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_pcie0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_start_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_webcpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_0_STATUS - Software init 0 status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved_for_padding0 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved_for_padding0_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved_for_padding0_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_moca_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_13_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_hvd0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: reserved_for_padding1 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved_for_padding1_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_reserved_for_padding1_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie1_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_pcie0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_start_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_webcpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved_for_padding0 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved_for_padding0_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved_for_padding0_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: reserved_for_padding1 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved_for_padding1_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_reserved_for_padding1_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht0_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie1_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved_for_padding0 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved_for_padding0_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved_for_padding0_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: reserved_for_padding1 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved_for_padding1_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_reserved_for_padding1_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht0_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie1_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved_for_padding0 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved_for_padding0_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved_for_padding0_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_moca_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb1_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr1_sw_init_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc1_sw_init_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga0_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_13_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_hvd0_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: reserved_for_padding1 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved_for_padding1_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_reserved_for_padding1_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht0_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie1_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_pcie0_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_start_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_webcpu_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_1_SET - Software init 1 set |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: demod_xpt_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_demod_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio1_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sdio0_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sdio0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: rf4ce_top_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_rf4ce_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: avs_top_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: hdmi_aon_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_hdmi_aon_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: stb_chan_top_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_stb_chan_top_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_stb_chan_top_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_stb_chan_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: aif_wb_stat_top1_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top1_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top1_sw_init_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: aif_wb_stat_top0_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top0_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top0_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: aif_mdac_cal_top_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_mdac_cal_top_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_mdac_cal_top_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds_afec3_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec3_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec3_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec3_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds_afec2_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec2_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec2_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds_afec1_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec1_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec1_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds_afec0_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec0_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec0_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds_afec0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_top3_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top3_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top3_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top3_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top3_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top3_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top3_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top3_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_top2_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top2_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top2_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top2_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top2_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top2_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_top1_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top1_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top1_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top1_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds1_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds1_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sds0_top0_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top0_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top0_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sds0_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: fsk_top_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_fsk_top_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_fsk_top_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_fsk_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: leap_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved_for_padding0 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved_for_padding0_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved_for_padding0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: gphy_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_gphy_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: genet2_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_genet2_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_genet2_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_genet2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: m2mc1_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_m2mc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: v3d_top_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_v3d_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_vice20_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_1_CLEAR - Software init 1 clear |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: demod_xpt_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_demod_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio1_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sdio0_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sdio0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: rf4ce_top_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_rf4ce_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: avs_top_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: hdmi_aon_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_hdmi_aon_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: stb_chan_top_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_stb_chan_top_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_stb_chan_top_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_stb_chan_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: aif_wb_stat_top1_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top1_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top1_sw_init_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: aif_wb_stat_top0_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top0_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top0_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: aif_mdac_cal_top_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_mdac_cal_top_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_mdac_cal_top_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds_afec3_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec3_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec3_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec3_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds_afec2_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec2_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec2_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds_afec1_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec1_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec1_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds_afec0_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec0_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec0_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds_afec0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_top3_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top3_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top3_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top3_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top3_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top3_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top3_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top3_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_top2_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top2_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top2_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top2_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top2_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top2_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_top1_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top1_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top1_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top1_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds1_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds1_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sds0_top0_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top0_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top0_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sds0_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: fsk_top_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_fsk_top_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_fsk_top_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_fsk_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: leap_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved_for_padding0 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved_for_padding0_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved_for_padding0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: gphy_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_gphy_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: genet2_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_genet2_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_genet2_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_genet2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: m2mc1_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_m2mc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: v3d_top_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_v3d_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_vice20_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_1_STATUS - Software init 1 status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: demod_xpt_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_demod_xpt_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio1_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sdio0_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sdio0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: rf4ce_top_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_rf4ce_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: avs_top_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: hdmi_aon_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_hdmi_aon_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: stb_chan_top_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_stb_chan_top_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_stb_chan_top_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_stb_chan_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: aif_wb_stat_top1_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top1_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top1_sw_init_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: aif_wb_stat_top0_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top0_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top0_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_wb_stat_top0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: aif_mdac_cal_top_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_mdac_cal_top_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_mdac_cal_top_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_aif_mdac_cal_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds_afec3_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec3_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec3_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec3_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds_afec2_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec2_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec2_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec2_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds_afec1_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec1_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec1_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds_afec0_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec0_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec0_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds_afec0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_top3_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top3_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top3_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top3_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top3_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top3_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top3_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top3_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_top2_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top2_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top2_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top2_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top2_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top2_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top2_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top2_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_top1_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top1_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top1_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top1_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds1_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds1_top0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sds0_top0_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top0_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top0_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sds0_top0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: fsk_top_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_fsk_top_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_fsk_top_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_fsk_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: leap_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved_for_padding0 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved_for_padding0_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved_for_padding0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: gphy_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_gphy_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: genet2_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_genet2_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_genet2_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_genet2_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: m2mc1_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_m2mc1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: v3d_top_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_v3d_top_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_vice20_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: demod_xpt_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio1_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sdio0_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: avs_top_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: stb_chan_top_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_stb_chan_top_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_stb_chan_top_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: aif_wb_stat_top1_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_wb_stat_top1_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_wb_stat_top1_sw_init_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: aif_wb_stat_top0_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: aif_mdac_cal_top_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds_afec3_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec3_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec3_sw_init_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds_afec2_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec2_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec2_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds_afec1_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec1_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec1_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds_afec0_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec0_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds_afec0_sw_init_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_top3_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top3_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top3_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top3_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top3_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top3_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_top2_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top2_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top2_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top2_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top2_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top2_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_top1_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top1_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top1_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top1_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds1_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds1_top0_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sds0_top0_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top0_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sds0_top0_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: fsk_top_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_fsk_top_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_fsk_top_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: leap_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved_for_padding0 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved_for_padding0_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved_for_padding0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: gphy_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: genet2_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_genet2_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_genet2_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: m2mc1_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: v3d_top_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: demod_xpt_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio1_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sdio0_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: avs_top_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: stb_chan_top_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_stb_chan_top_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_stb_chan_top_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: aif_wb_stat_top1_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_wb_stat_top1_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_wb_stat_top1_sw_init_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: aif_wb_stat_top0_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: aif_mdac_cal_top_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds_afec3_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec3_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec3_sw_init_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds_afec2_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec2_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec2_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds_afec1_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec1_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec1_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds_afec0_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec0_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds_afec0_sw_init_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_top3_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top3_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top3_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top3_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top3_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top3_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_top2_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top2_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top2_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top2_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top2_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top2_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_top1_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top1_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top1_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top1_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds1_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds1_top0_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sds0_top0_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top0_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sds0_top0_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: fsk_top_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_fsk_top_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_fsk_top_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: leap_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved_for_padding0 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved_for_padding0_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved_for_padding0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: gphy_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: genet2_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_genet2_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_genet2_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: m2mc1_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: v3d_top_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: demod_xpt_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_demod_xpt_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_demod_xpt_sw_init_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio1_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio1_sw_init_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sdio0_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sdio0_sw_init_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: rf4ce_top_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_rf4ce_top_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_rf4ce_top_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: avs_top_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_avs_top_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: hdmi_aon_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_hdmi_aon_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_hdmi_aon_sw_init_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: stb_chan_top_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_stb_chan_top_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_stb_chan_top_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: aif_wb_stat_top1_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_wb_stat_top1_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_wb_stat_top1_sw_init_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: aif_wb_stat_top0_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_wb_stat_top0_sw_init_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: aif_mdac_cal_top_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_aif_mdac_cal_top_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds_afec3_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec3_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec3_sw_init_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds_afec2_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec2_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec2_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds_afec1_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec1_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec1_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds_afec0_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec0_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds_afec0_sw_init_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_top3_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top3_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top3_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top3_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top3_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top3_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_top2_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top2_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top2_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top2_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top2_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top2_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_top1_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top1_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top1_sw_init_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top1_sw_init_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds1_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds1_top0_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sds0_top0_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top0_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sds0_top0_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: fsk_top_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_fsk_top_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_fsk_top_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: leap_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved_for_padding0 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved_for_padding0_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved_for_padding0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: gphy_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_gphy_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: genet2_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_genet2_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_genet2_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: m2mc1_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_m2mc1_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_m2mc1_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: v3d_top_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_v3d_top_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_vice20_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved_for_padding0 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved_for_padding0_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved_for_padding0_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: reserved_for_padding1 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved_for_padding1_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_reserved_for_padding1_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie1_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_pcie0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_start_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_webcpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: demod_xpt_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_demod_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio1_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sdio0_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: rf4ce_top_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_rf4ce_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: avs_top_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: hdmi_aon_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_hdmi_aon_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: stb_chan_top_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_stb_chan_top_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_stb_chan_top_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_stb_chan_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: aif_wb_stat_top1_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top1_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top1_sw_init_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: aif_wb_stat_top0_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: aif_mdac_cal_top_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds_afec3_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec3_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec3_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec3_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds_afec2_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec2_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec2_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds_afec1_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec1_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec1_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds_afec0_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec0_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec0_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds_afec0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_top3_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top3_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top3_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top3_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top3_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top3_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top3_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top3_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_top2_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top2_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top2_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top2_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top2_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top2_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_top1_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top1_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top1_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top1_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds1_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds1_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sds0_top0_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top0_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top0_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sds0_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: fsk_top_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_fsk_top_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_fsk_top_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_fsk_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: leap_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved_for_padding0 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved_for_padding0_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved_for_padding0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: gphy_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: genet2_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_genet2_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_genet2_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_genet2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: m2mc1_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_m2mc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: v3d_top_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_vice20_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved_for_padding0 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved_for_padding0_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved_for_padding0_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: moca_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_moca_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb1_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr1_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc1_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga0_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: hvd0_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_hvd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: reserved_for_padding1 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved_for_padding1_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_reserved_for_padding1_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: pcie1_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie1_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie1_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: pcie0_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_pcie0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: webcpu_start_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_start_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: webcpu_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_webcpu_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: demod_xpt_sw_init [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_demod_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio1_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sdio0_sw_init [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sdio0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: rf4ce_top_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_rf4ce_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: avs_top_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_avs_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: hdmi_aon_sw_init [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_hdmi_aon_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: stb_chan_top_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_stb_chan_top_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_stb_chan_top_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_stb_chan_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: aif_wb_stat_top1_sw_init [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top1_sw_init_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top1_sw_init_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: aif_wb_stat_top0_sw_init [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_wb_stat_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: aif_mdac_cal_top_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_aif_mdac_cal_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds_afec3_sw_init [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec3_sw_init_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec3_sw_init_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec3_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds_afec2_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec2_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec2_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds_afec1_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec1_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec1_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds_afec0_sw_init [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec0_sw_init_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec0_sw_init_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds_afec0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_top3_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top3_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top3_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top3_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top3_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top3_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top3_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top3_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_top2_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top2_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top2_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top2_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top2_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top2_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_top1_sw_init [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top1_sw_init_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top1_sw_init_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top1_sw_init [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top1_sw_init_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top1_sw_init_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds1_top0_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top0_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top0_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds1_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sds0_top0_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top0_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top0_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sds0_top0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: fsk_top_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_fsk_top_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_fsk_top_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_fsk_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: leap_sw_init [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved_for_padding0 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved_for_padding0_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved_for_padding0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: gphy_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_gphy_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: genet2_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_genet2_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_genet2_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_genet2_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: m2mc1_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_m2mc1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: v3d_top_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_v3d_top_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: vice20_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_vice20_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UNCLEARED_SCRATCH - Scratch register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPARE_CTRL - Spare control bits reserved for future use |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TEST_PORT_CTRL - Test port control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK 0x0ffffc00 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK 0x00000180 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK 0x0000007f |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA 1 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RF4CE_TOP 2 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIF_MDAC_CAL_TOP 12 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIF_WB_SAT_TOP0 13 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIF_WB_SAT_TOP1 14 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_STB_CHAN_TOP 15 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS 16 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK 17 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON 18 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF 19 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVS 20 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP 21 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC 22 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO 23 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HVD0 25 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA0 28 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT 30 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0 31 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC1 32 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1 34 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET2 35 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_PCIE0 36 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_PCIE1 37 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0 38 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB1 39 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA 40 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_V3D_TOP 41 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM 42 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FSK_TOP 43 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R_0 44 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T_0 45 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_R_0 46 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_T_0 47 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R_1 48 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T_1 49 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_R_1 50 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_T_1 51 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R_2 52 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T_2 53 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_R_2 54 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_T_2 55 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R_3 56 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T_3 57 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_R_3 58 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS1_T_3 59 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS_AFEC0 60 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS_AFEC1 61 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS_AFEC2 62 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS_AFEC3 63 |
| |
| /*************************************************************************** |
| *TEST_PORT_OUT_PEEK - Testport peek register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_OUT_POKE - Testport poke register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TEST_PORT_IN_PEEK - Testport peek register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_IN_POKE - Testport poke register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EJTAG_INPUT_EN - EJTAG input bus enables |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:11] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK 0xfffff800 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [10:00] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK 0x000007ff |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_CPU_ONE_HOT 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA0_CPU_ONE_HOT 4 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA1_CPU_ONE_HOT 8 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE20_ARC0_CPU_ONE_HOT 16 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_VICE20_ARC1_CPU_ONE_HOT 32 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AVS_CPU_ONE_HOT 64 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_LEAP_CPU_ONE_HOT 128 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_RF4CE_CPU_ONE_HOT 256 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SCPU_CPU_ONE_HOT 512 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 1024 |
| |
| /*************************************************************************** |
| *EJTAG_OUTPUT_SEL - EJTAG output select |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_CPU 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA0_CPU 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA1_CPU 3 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE20_ARC0_CPU 4 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_VICE20_ARC1_CPU 5 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AVS_CPU 6 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_LEAP_CPU 7 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_RF4CE_CPU 8 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SCPU_CPU 9 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 10 |
| |
| /*************************************************************************** |
| *VTRAP_CTRL - VTRAP Control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:23] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK 0xff800000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_1_threshold [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_1_threshold_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_1_threshold [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_1_threshold_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_0_threshold [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_0_threshold_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_1_threshold [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_1_threshold_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_0_threshold [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_0_threshold_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [17:05] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x0003ffe0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_1_status_clear [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_1_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_0_status_clear [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_0_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_1_status_clear [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_1_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_0_status_clear [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_0_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_1_status_clear [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_1_status_clear_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VTRAP_STATUS - VTRAP Status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:05] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK 0xffffffe0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_1_status [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_1_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_0_status [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_0_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_1_status [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_1_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_0_status [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_0_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_1_status [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_1_status_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UART_ROUTER_SEL_0 - UART Router select 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: reserved0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_reserved0_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_5_cpu_sel [29:25] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_MASK 0x3e000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_HVD0_ILP2 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_VICE20_ARC0 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_VICE20_ARC1 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_AVS_TOP 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_LEAP 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_5_cpu_sel_SCPU 11 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_4_cpu_sel [24:20] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_MASK 0x01f00000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_HVD0_ILP2 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_VICE20_ARC0 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_VICE20_ARC1 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_AVS_TOP 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_LEAP 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_4_cpu_sel_SCPU 11 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_3_cpu_sel [19:15] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_MASK 0x000f8000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_HVD0_ILP2 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_VICE20_ARC0 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_VICE20_ARC1 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_AVS_TOP 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_LEAP 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_3_cpu_sel_SCPU 11 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_2_cpu_sel [14:10] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_MASK 0x00007c00 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_HVD0_ILP2 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_VICE20_ARC0 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_VICE20_ARC1 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_AVS_TOP 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_LEAP 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_2_cpu_sel_SCPU 11 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_1_cpu_sel [09:05] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_MASK 0x000003e0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_HVD0_ILP2 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_VICE20_ARC0 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_VICE20_ARC1 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_AVS_TOP 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_LEAP 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_1_cpu_sel_SCPU 11 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_0 :: port_0_cpu_sel [04:00] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_MASK 0x0000001f |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_HVD0_ILP2 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_VICE20_ARC0 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_VICE20_ARC1 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_AVS_TOP 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_LEAP 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_0_port_0_cpu_sel_SCPU 11 |
| |
| /*************************************************************************** |
| *UART_ROUTER_SEL_1 - UART Router select 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: reserved0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_reserved0_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_11_cpu_sel [29:25] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_MASK 0x3e000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_HVD0_ILP2 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_VICE20_ARC0 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_VICE20_ARC1 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_AVS_TOP 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_LEAP 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_11_cpu_sel_SCPU 11 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_10_cpu_sel [24:20] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_MASK 0x01f00000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_HVD0_ILP2 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_VICE20_ARC0 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_VICE20_ARC1 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_AVS_TOP 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_LEAP 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_10_cpu_sel_SCPU 11 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_9_cpu_sel [19:15] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_MASK 0x000f8000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_HVD0_ILP2 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_VICE20_ARC0 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_VICE20_ARC1 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_AVS_TOP 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_LEAP 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_9_cpu_sel_SCPU 11 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_8_cpu_sel [14:10] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_MASK 0x00007c00 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_HVD0_ILP2 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_VICE20_ARC0 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_VICE20_ARC1 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_AVS_TOP 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_LEAP 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_8_cpu_sel_SCPU 11 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_7_cpu_sel [09:05] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_MASK 0x000003e0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_HVD0_ILP2 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_VICE20_ARC0 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_VICE20_ARC1 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_AVS_TOP 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_LEAP 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_7_cpu_sel_SCPU 11 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL_1 :: port_6_cpu_sel [04:00] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_MASK 0x0000001f |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AUDIO_FP0 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_HVD0_ILP2 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SID 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_VICE20_ARC0 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_VICE20_ARC1 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_AVS_TOP 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_LEAP 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_RF4CE_TOP 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_1_port_6_cpu_sel_SCPU 11 |
| |
| /*************************************************************************** |
| *SSP_CONFIG - Serial Slave Port configuration register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK 0xfffff800 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK 0x00000780 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT 0x00000004 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK 0x00000078 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SERS_REV - SERS Revision Register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK 0x0000ff00 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SERS_CFG - SERS Configuration Register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode 1 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT 0x00000000 |
| |
| /* union - case mapped_buffer_mode [26:08] */ |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000 |
| |
| /* union - case cmd_fifo_mode [26:08] */ |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK 0x07c00000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK 0x003e0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK 0x000000fe |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SERS_CMD_BUF_%i - Host Serial Write Command Buffer |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE 0x00404428 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END 7 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *SERS_CMD_BUF_%i - Host Serial Write Command Buffer |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT 0 |
| |
| |
| /*************************************************************************** |
| *SERS_STAT_BUF_%i - Host Serial Read Status Buffer |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE 0x00404448 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END 1 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *SERS_STAT_BUF_%i - Host Serial Read Status Buffer |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT 0 |
| |
| |
| /*************************************************************************** |
| *RO_TEST_BLOCK_SEL - Block select for RO testmode |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:18] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK 0xfffc0000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [17:14] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0003c000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_CMOS 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_CMOS 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_CMOS 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_NMOS 3 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_NMOS 4 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_NMOS 5 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_STANDARD_VT_PMOS 6 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_HVT_PMOS 7 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SUPER_LVT_PMOS 8 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_CMOS 9 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_NMOS 10 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_IO_PMOS 11 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_en [13:02] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_MASK 0x00003ffc |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_DISABLE_RO 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_CMOS_ONE_HOT 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_CMOS_ONE_HOT 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_CMOS_ONE_HOT 4 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_NMOS_ONE_HOT 8 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_NMOS_ONE_HOT 16 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_NMOS_ONE_HOT 32 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_STANDARD_VT_PMOS_ONE_HOT 64 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_HVT_PMOS_ONE_HOT 128 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_SUPER_LVT_PMOS_ONE_HOT 256 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_CMOS_ONE_HOT 512 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_NMOS_ONE_HOT 1024 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_en_IO_PMOS_ONE_HOT 2048 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3 |
| |
| /*************************************************************************** |
| *TEST_CONFIGURATION - Test configuration |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_2 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_23 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_23_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_23_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_22 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_22_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_22_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_21 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_21_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_21_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_21_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_20 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_20_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_20_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_19 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_19_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_19_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_19_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_18 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_18_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_18_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_18_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_17 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_17_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_17_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_16 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_16_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_15 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_14 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_13 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_12 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_11 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_10 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_9 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_8 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_7 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_6 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_5 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_4 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_3 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_2 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_1 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_spare_0 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_spare_0_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_2 :: otp_option_sds_channel_disable [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_sds_channel_disable_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_sds_channel_disable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_2_otp_option_sds_channel_disable_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_2 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_23 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_23_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_23_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_22 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_22_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_22_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_21 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_21_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_21_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_21_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_20 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_20_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_20_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_19 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_19_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_19_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_19_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_18 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_18_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_18_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_18_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_17 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_17_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_17_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_16 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_16_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_15 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_14 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_13 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_12 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_11 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_10 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_9 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_8 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_7 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_6 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_5 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_4 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_3 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_2 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_1 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_spare_0 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_spare_0_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_2 :: otp_option_sds_channel_disable [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_sds_channel_disable_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_2_otp_option_sds_channel_disable_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_6 - General control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: demod_xpt_tb_disable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_demod_xpt_tb_disable_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_7 - General control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_7 :: demod_xpt_chip_signature [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_7_demod_xpt_chip_signature_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */ |
| |
| /* End of File */ |
