/***************************************************************************
 *     Copyright (c) 1999-2014, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on              Wed Sep  3 15:00:00 2014
 *                 Full Compile MD5 Checksum 10187d4079392bab2546025f43274d34
 *                   (minus title and desc)  
 *                 MD5 Checksum              c1587c5e16f21f52e852e7c7a65c7811
 *
 * Compiled with:  RDB Utility               combo_header.pl
 *                 RDB Parser                3.0
 *                 unknown                   unknown
 *                 Perl Interpreter          5.008005
 *                 Operating System          linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_SDIO_0_CFG_H__
#define BCHP_SDIO_0_CFG_H__

/***************************************************************************
 *SDIO_0_CFG - SDIO (CARD0) Configuration Registers
 ***************************************************************************/
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1          0x00440100 /* SDIO EMMC Control Register */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2          0x00440104 /* SDIO EMMC Control Register */
#define BCHP_SDIO_0_CFG_TP_OUT_SEL               0x00440108 /* SDIO TP_OUT Control Register */
#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE         0x0044010c /* SDIO CAPABILITIES override Register */
#define BCHP_SDIO_0_CFG_CAP_REG0                 0x00440110 /* SDIO CAPABILITIES override Register[31:0] */
#define BCHP_SDIO_0_CFG_CAP_REG1                 0x00440114 /* SDIO CAPABILITIES override Register[63:32] */
#define BCHP_SDIO_0_CFG_PRESET1                  0x00440118 /* SDIO PRESET_INIT/PRESET_DS override Register */
#define BCHP_SDIO_0_CFG_PRESET2                  0x0044011c /* SDIO PRESET_HS/PRESET_SDR12 override Register */
#define BCHP_SDIO_0_CFG_PRESET3                  0x00440120 /* SDIO PRESET_SDR25/PRESET_SDR50 override Register */
#define BCHP_SDIO_0_CFG_PRESET4                  0x00440124 /* SDIO PRESET_SDR104/PRESET_DDR50 override Register */
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY           0x00440128 /* SDIO Clock delay register */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV               0x0044012c /* SDIO Clock delay register */
#define BCHP_SDIO_0_CFG_IP_DLY                   0x00440130 /* SDIO Host input delay register */
#define BCHP_SDIO_0_CFG_OP_DLY                   0x00440134 /* SDIO Host output delay register */
#define BCHP_SDIO_0_CFG_TUNING                   0x00440138 /* SDIO Host tuning configuration register */
#define BCHP_SDIO_0_CFG_VOLT_CTRL                0x0044013c /* SDIO Host 1p8V control logic select register */
#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY            0x00440140 /* Debug TAP delay setting register */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS  0x00440144 /* Debug A2S Bridge Status */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR 0x00440148 /* Debug register to read AHB req start address (32b) */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR   0x0044014c /* Debug register to read AHB req end address (32b) */
#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT 0x00440150 /* Disable Client Init */
#define BCHP_SDIO_0_CFG_SD_PIN_SEL               0x00440154 /* SD Pin Select */
#define BCHP_SDIO_0_CFG_MAX_CURRENT              0x00440158 /* Max Current Override */
#define BCHP_SDIO_0_CFG_VERSION                  0x004401f0 /* SDIO VERSION Register */
#define BCHP_SDIO_0_CFG_SCRATCH                  0x004401fc /* SDIO Scratch Register */

/***************************************************************************
 *SDIO_EMMC_CTRL1 - SDIO EMMC Control Register
 ***************************************************************************/
/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_SEL_EN [31:31] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_MASK    0x80000000
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_SHIFT   31
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_SEL_EN_DEFAULT 0x00000000

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SDCD_N_TEST_LEV [30:30] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_MASK       0x40000000
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_SHIFT      30
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SDCD_N_TEST_LEV_DEFAULT    0x00000001

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved0 [29:29] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_MASK             0x20000000
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved0_SHIFT            29

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: RETUNING_REQ [28:28] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_MASK          0x10000000
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_SHIFT         28
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_RETUNING_REQ_DEFAULT       0x00000000

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved1 [27:18] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved1_MASK             0x0ffc0000
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved1_SHIFT            18

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FORCE_WR_FLUSH [17:17] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_MASK        0x00020000
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_SHIFT       17
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FORCE_WR_FLUSH_DEFAULT     0x00000000

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: MF_NUM_WR [16:16] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_MASK             0x00010000
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_SHIFT            16
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_MF_NUM_WR_DEFAULT          0x00000000

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: WORD_ABO [15:15] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_MASK              0x00008000
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_SHIFT             15
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_WORD_ABO_DEFAULT           0x00000000

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NBO [14:14] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_MASK             0x00004000
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_SHIFT            14
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NBO_DEFAULT          0x00000000

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: FRAME_NHW [13:13] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_MASK             0x00002000
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_SHIFT            13
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_FRAME_NHW_DEFAULT          0x00000001

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: BUFFER_ABO [12:12] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_MASK            0x00001000
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_SHIFT           12
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_BUFFER_ABO_DEFAULT         0x00000001

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_BUF_ACC [11:11] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_MASK           0x00000800
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_SHIFT          11
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_BUF_ACC_DEFAULT        0x00000001

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_SEQ_EN [10:10] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_MASK            0x00000400
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_SHIFT           10
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_SEQ_EN_DEFAULT         0x00000001

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: reserved2 [09:02] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved2_MASK             0x000003fc
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_reserved2_SHIFT            2

/* SDIO_0_CFG :: SDIO_EMMC_CTRL1 :: SCB_MAX_SIZE [01:00] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_MASK          0x00000003
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_SHIFT         0
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL1_SCB_MAX_SIZE_DEFAULT       0x00000003

/***************************************************************************
 *SDIO_EMMC_CTRL2 - SDIO EMMC Control Register
 ***************************************************************************/
/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved0 [31:08] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_MASK             0xffffff00
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved0_SHIFT            8

/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_BYTE [07:06] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_MASK     0x000000c0
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_SHIFT    6
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_BYTE_DEFAULT  0x00000000

/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: reserved1 [05:05] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_MASK             0x00000020
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_reserved1_SHIFT            5

/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_ADDR_MAP_HW [04:04] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_MASK       0x00000010
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_SHIFT      4
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_ADDR_MAP_HW_DEFAULT    0x00000000

/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_RD [03:02] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_MASK      0x0000000c
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_SHIFT     2
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_RD_DEFAULT   0x00000000

/* SDIO_0_CFG :: SDIO_EMMC_CTRL2 :: REG_DATA_SWAP_WR [01:00] */
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_MASK      0x00000003
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_SHIFT     0
#define BCHP_SDIO_0_CFG_SDIO_EMMC_CTRL2_REG_DATA_SWAP_WR_DEFAULT   0x00000000

/***************************************************************************
 *TP_OUT_SEL - SDIO TP_OUT Control Register
 ***************************************************************************/
/* SDIO_0_CFG :: TP_OUT_SEL :: reserved0 [31:02] */
#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_MASK                  0xfffffffc
#define BCHP_SDIO_0_CFG_TP_OUT_SEL_reserved0_SHIFT                 2

/* SDIO_0_CFG :: TP_OUT_SEL :: TP_OUT_SELECT [01:00] */
#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_MASK              0x00000003
#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_SHIFT             0
#define BCHP_SDIO_0_CFG_TP_OUT_SEL_TP_OUT_SELECT_DEFAULT           0x00000000

/***************************************************************************
 *CAP_REG_OVERRIDE - SDIO CAPABILITIES override Register
 ***************************************************************************/
/* SDIO_0_CFG :: CAP_REG_OVERRIDE :: reserved0 [31:01] */
#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_reserved0_MASK            0xfffffffe
#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_reserved0_SHIFT           1

/* SDIO_0_CFG :: CAP_REG_OVERRIDE :: CAP_REG_OVERRIDE [00:00] */
#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_MASK     0x00000001
#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_SHIFT    0
#define BCHP_SDIO_0_CFG_CAP_REG_OVERRIDE_CAP_REG_OVERRIDE_DEFAULT  0x00000000

/***************************************************************************
 *CAP_REG0 - SDIO CAPABILITIES override Register[31:0]
 ***************************************************************************/
/* SDIO_0_CFG :: CAP_REG0 :: SLOT_TYPE [31:30] */
#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_MASK                    0xc0000000
#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_SHIFT                   30
#define BCHP_SDIO_0_CFG_CAP_REG0_SLOT_TYPE_DEFAULT                 0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: INT_MODE [29:29] */
#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_MASK                     0x20000000
#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_SHIFT                    29
#define BCHP_SDIO_0_CFG_CAP_REG0_INT_MODE_DEFAULT                  0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: SYS_BUS_64BIT [28:28] */
#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_MASK                0x10000000
#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_SHIFT               28
#define BCHP_SDIO_0_CFG_CAP_REG0_SYS_BUS_64BIT_DEFAULT             0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: reserved0 [27:27] */
#define BCHP_SDIO_0_CFG_CAP_REG0_reserved0_MASK                    0x08000000
#define BCHP_SDIO_0_CFG_CAP_REG0_reserved0_SHIFT                   27

/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_1P8V [26:26] */
#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_MASK                 0x04000000
#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_SHIFT                26
#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_1P8V_DEFAULT              0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_3P0V [25:25] */
#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_MASK                 0x02000000
#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_SHIFT                25
#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P0V_DEFAULT              0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: VOLTAGE_3P3V [24:24] */
#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_MASK                 0x01000000
#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_SHIFT                24
#define BCHP_SDIO_0_CFG_CAP_REG0_VOLTAGE_3P3V_DEFAULT              0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: SUSPEND_RESUME [23:23] */
#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_MASK               0x00800000
#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_SHIFT              23
#define BCHP_SDIO_0_CFG_CAP_REG0_SUSPEND_RESUME_DEFAULT            0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: SDMA [22:22] */
#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_MASK                         0x00400000
#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_SHIFT                        22
#define BCHP_SDIO_0_CFG_CAP_REG0_SDMA_DEFAULT                      0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: HIGH_SPEED [21:21] */
#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_MASK                   0x00200000
#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_SHIFT                  21
#define BCHP_SDIO_0_CFG_CAP_REG0_HIGH_SPEED_DEFAULT                0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: reserved1 [20:20] */
#define BCHP_SDIO_0_CFG_CAP_REG0_reserved1_MASK                    0x00100000
#define BCHP_SDIO_0_CFG_CAP_REG0_reserved1_SHIFT                   20

/* SDIO_0_CFG :: CAP_REG0 :: ADMA2 [19:19] */
#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_MASK                        0x00080000
#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_SHIFT                       19
#define BCHP_SDIO_0_CFG_CAP_REG0_ADMA2_DEFAULT                     0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: EXTENDED_MEDIA [18:18] */
#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_MASK               0x00040000
#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_SHIFT              18
#define BCHP_SDIO_0_CFG_CAP_REG0_EXTENDED_MEDIA_DEFAULT            0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: MAX_BLOCK_LEN [17:16] */
#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_MASK                0x00030000
#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_SHIFT               16
#define BCHP_SDIO_0_CFG_CAP_REG0_MAX_BLOCK_LEN_DEFAULT             0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: BASE_CLK_FREQ [15:08] */
#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_MASK                0x0000ff00
#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_SHIFT               8
#define BCHP_SDIO_0_CFG_CAP_REG0_BASE_CLK_FREQ_DEFAULT             0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_UNIT [07:07] */
#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_MASK                 0x00000080
#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_SHIFT                7
#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_UNIT_DEFAULT              0x00000000

/* SDIO_0_CFG :: CAP_REG0 :: reserved2 [06:06] */
#define BCHP_SDIO_0_CFG_CAP_REG0_reserved2_MASK                    0x00000040
#define BCHP_SDIO_0_CFG_CAP_REG0_reserved2_SHIFT                   6

/* SDIO_0_CFG :: CAP_REG0 :: TIMEOUT_CLK_FREQ [05:00] */
#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_MASK             0x0000003f
#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_SHIFT            0
#define BCHP_SDIO_0_CFG_CAP_REG0_TIMEOUT_CLK_FREQ_DEFAULT          0x00000000

/***************************************************************************
 *CAP_REG1 - SDIO CAPABILITIES override Register[63:32]
 ***************************************************************************/
/* SDIO_0_CFG :: CAP_REG1 :: reserved0 [31:26] */
#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_MASK                    0xfc000000
#define BCHP_SDIO_0_CFG_CAP_REG1_reserved0_SHIFT                   26

/* SDIO_0_CFG :: CAP_REG1 :: SPI_BLOCK_MODE [25:25] */
#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_MASK               0x02000000
#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_SHIFT              25
#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_BLOCK_MODE_DEFAULT            0x00000000

/* SDIO_0_CFG :: CAP_REG1 :: SPI_MODE [24:24] */
#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_MASK                     0x01000000
#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_SHIFT                    24
#define BCHP_SDIO_0_CFG_CAP_REG1_SPI_MODE_DEFAULT                  0x00000000

/* SDIO_0_CFG :: CAP_REG1 :: CLK_MULT [23:16] */
#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_MASK                     0x00ff0000
#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_SHIFT                    16
#define BCHP_SDIO_0_CFG_CAP_REG1_CLK_MULT_DEFAULT                  0x00000000

/* SDIO_0_CFG :: CAP_REG1 :: RETUNING_MODE [15:14] */
#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_MASK                0x0000c000
#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_SHIFT               14
#define BCHP_SDIO_0_CFG_CAP_REG1_RETUNING_MODE_DEFAULT             0x00000000

/* SDIO_0_CFG :: CAP_REG1 :: TUNE_SDR50 [13:13] */
#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_MASK                   0x00002000
#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_SHIFT                  13
#define BCHP_SDIO_0_CFG_CAP_REG1_TUNE_SDR50_DEFAULT                0x00000000

/* SDIO_0_CFG :: CAP_REG1 :: reserved1 [12:12] */
#define BCHP_SDIO_0_CFG_CAP_REG1_reserved1_MASK                    0x00001000
#define BCHP_SDIO_0_CFG_CAP_REG1_reserved1_SHIFT                   12

/* SDIO_0_CFG :: CAP_REG1 :: TIME_RETUNE [11:08] */
#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_MASK                  0x00000f00
#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_SHIFT                 8
#define BCHP_SDIO_0_CFG_CAP_REG1_TIME_RETUNE_DEFAULT               0x00000000

/* SDIO_0_CFG :: CAP_REG1 :: reserved2 [07:07] */
#define BCHP_SDIO_0_CFG_CAP_REG1_reserved2_MASK                    0x00000080
#define BCHP_SDIO_0_CFG_CAP_REG1_reserved2_SHIFT                   7

/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_D [06:06] */
#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_MASK                     0x00000040
#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_SHIFT                    6
#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_D_DEFAULT                  0x00000000

/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_C [05:05] */
#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_MASK                     0x00000020
#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_SHIFT                    5
#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_C_DEFAULT                  0x00000000

/* SDIO_0_CFG :: CAP_REG1 :: DRIVER_A [04:04] */
#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_MASK                     0x00000010
#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_SHIFT                    4
#define BCHP_SDIO_0_CFG_CAP_REG1_DRIVER_A_DEFAULT                  0x00000000

/* SDIO_0_CFG :: CAP_REG1 :: reserved3 [03:03] */
#define BCHP_SDIO_0_CFG_CAP_REG1_reserved3_MASK                    0x00000008
#define BCHP_SDIO_0_CFG_CAP_REG1_reserved3_SHIFT                   3

/* SDIO_0_CFG :: CAP_REG1 :: DDR50 [02:02] */
#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_MASK                        0x00000004
#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_SHIFT                       2
#define BCHP_SDIO_0_CFG_CAP_REG1_DDR50_DEFAULT                     0x00000000

/* SDIO_0_CFG :: CAP_REG1 :: SDR104 [01:01] */
#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_MASK                       0x00000002
#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_SHIFT                      1
#define BCHP_SDIO_0_CFG_CAP_REG1_SDR104_DEFAULT                    0x00000000

/* SDIO_0_CFG :: CAP_REG1 :: SDR50 [00:00] */
#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_MASK                        0x00000001
#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_SHIFT                       0
#define BCHP_SDIO_0_CFG_CAP_REG1_SDR50_DEFAULT                     0x00000000

/***************************************************************************
 *PRESET1 - SDIO PRESET_INIT/PRESET_DS override Register
 ***************************************************************************/
/* SDIO_0_CFG :: PRESET1 :: PRESET1_OVERRIDE [31:31] */
#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_MASK              0x80000000
#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_SHIFT             31
#define BCHP_SDIO_0_CFG_PRESET1_PRESET1_OVERRIDE_DEFAULT           0x00000000

/* SDIO_0_CFG :: PRESET1 :: reserved0 [30:29] */
#define BCHP_SDIO_0_CFG_PRESET1_reserved0_MASK                     0x60000000
#define BCHP_SDIO_0_CFG_PRESET1_reserved0_SHIFT                    29

/* SDIO_0_CFG :: PRESET1 :: PRESET_INIT [28:16] */
#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_MASK                   0x1fff0000
#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_SHIFT                  16
#define BCHP_SDIO_0_CFG_PRESET1_PRESET_INIT_DEFAULT                0x00000000

/* SDIO_0_CFG :: PRESET1 :: reserved1 [15:13] */
#define BCHP_SDIO_0_CFG_PRESET1_reserved1_MASK                     0x0000e000
#define BCHP_SDIO_0_CFG_PRESET1_reserved1_SHIFT                    13

/* SDIO_0_CFG :: PRESET1 :: PRESET_DS [12:00] */
#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_MASK                     0x00001fff
#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_SHIFT                    0
#define BCHP_SDIO_0_CFG_PRESET1_PRESET_DS_DEFAULT                  0x00000001

/***************************************************************************
 *PRESET2 - SDIO PRESET_HS/PRESET_SDR12 override Register
 ***************************************************************************/
/* SDIO_0_CFG :: PRESET2 :: PRESET2_OVERRIDE [31:31] */
#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_MASK              0x80000000
#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_SHIFT             31
#define BCHP_SDIO_0_CFG_PRESET2_PRESET2_OVERRIDE_DEFAULT           0x00000000

/* SDIO_0_CFG :: PRESET2 :: reserved0 [30:29] */
#define BCHP_SDIO_0_CFG_PRESET2_reserved0_MASK                     0x60000000
#define BCHP_SDIO_0_CFG_PRESET2_reserved0_SHIFT                    29

/* SDIO_0_CFG :: PRESET2 :: PRESET_SDR12 [28:16] */
#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_MASK                  0x1fff0000
#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_SHIFT                 16
#define BCHP_SDIO_0_CFG_PRESET2_PRESET_SDR12_DEFAULT               0x00000002

/* SDIO_0_CFG :: PRESET2 :: reserved1 [15:13] */
#define BCHP_SDIO_0_CFG_PRESET2_reserved1_MASK                     0x0000e000
#define BCHP_SDIO_0_CFG_PRESET2_reserved1_SHIFT                    13

/* SDIO_0_CFG :: PRESET2 :: PRESET_HS [12:00] */
#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_MASK                     0x00001fff
#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_SHIFT                    0
#define BCHP_SDIO_0_CFG_PRESET2_PRESET_HS_DEFAULT                  0x00000003

/***************************************************************************
 *PRESET3 - SDIO PRESET_SDR25/PRESET_SDR50 override Register
 ***************************************************************************/
/* SDIO_0_CFG :: PRESET3 :: PRESET3_OVERRIDE [31:31] */
#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_MASK              0x80000000
#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_SHIFT             31
#define BCHP_SDIO_0_CFG_PRESET3_PRESET3_OVERRIDE_DEFAULT           0x00000000

/* SDIO_0_CFG :: PRESET3 :: reserved0 [30:29] */
#define BCHP_SDIO_0_CFG_PRESET3_reserved0_MASK                     0x60000000
#define BCHP_SDIO_0_CFG_PRESET3_reserved0_SHIFT                    29

/* SDIO_0_CFG :: PRESET3 :: PRESET_SDR50 [28:16] */
#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_MASK                  0x1fff0000
#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_SHIFT                 16
#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR50_DEFAULT               0x00000002

/* SDIO_0_CFG :: PRESET3 :: reserved1 [15:13] */
#define BCHP_SDIO_0_CFG_PRESET3_reserved1_MASK                     0x0000e000
#define BCHP_SDIO_0_CFG_PRESET3_reserved1_SHIFT                    13

/* SDIO_0_CFG :: PRESET3 :: PRESET_SDR25 [12:00] */
#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_MASK                  0x00001fff
#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_SHIFT                 0
#define BCHP_SDIO_0_CFG_PRESET3_PRESET_SDR25_DEFAULT               0x00000003

/***************************************************************************
 *PRESET4 - SDIO PRESET_SDR104/PRESET_DDR50 override Register
 ***************************************************************************/
/* SDIO_0_CFG :: PRESET4 :: PRESET4_OVERRIDE [31:31] */
#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_MASK              0x80000000
#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_SHIFT             31
#define BCHP_SDIO_0_CFG_PRESET4_PRESET4_OVERRIDE_DEFAULT           0x00000000

/* SDIO_0_CFG :: PRESET4 :: reserved0 [30:29] */
#define BCHP_SDIO_0_CFG_PRESET4_reserved0_MASK                     0x60000000
#define BCHP_SDIO_0_CFG_PRESET4_reserved0_SHIFT                    29

/* SDIO_0_CFG :: PRESET4 :: PRESET_DDR50 [28:16] */
#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_MASK                  0x1fff0000
#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_SHIFT                 16
#define BCHP_SDIO_0_CFG_PRESET4_PRESET_DDR50_DEFAULT               0x00000002

/* SDIO_0_CFG :: PRESET4 :: reserved1 [15:13] */
#define BCHP_SDIO_0_CFG_PRESET4_reserved1_MASK                     0x0000e000
#define BCHP_SDIO_0_CFG_PRESET4_reserved1_SHIFT                    13

/* SDIO_0_CFG :: PRESET4 :: PRESET_SDR104 [12:00] */
#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_MASK                 0x00001fff
#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_SHIFT                0
#define BCHP_SDIO_0_CFG_PRESET4_PRESET_SDR104_DEFAULT              0x00000003

/***************************************************************************
 *SD_CLOCK_DELAY - SDIO Clock delay register
 ***************************************************************************/
/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved0 [31:31] */
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_MASK              0x80000000
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved0_SHIFT             31

/* SDIO_0_CFG :: SD_CLOCK_DELAY :: CLOCK_DELAY_OVERRIDE [30:30] */
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_MASK   0x40000000
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_SHIFT  30
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_CLOCK_DELAY_OVERRIDE_DEFAULT 0x00000001

/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_SEL [29:29] */
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_MASK        0x20000000
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_SEL_SHIFT       29

/* SDIO_0_CFG :: SD_CLOCK_DELAY :: reserved1 [28:12] */
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_MASK              0x1ffff000
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_reserved1_SHIFT             12

/* SDIO_0_CFG :: SD_CLOCK_DELAY :: OUTPUT_CLOCK_DELAY [11:08] */
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_MASK     0x00000f00
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_SHIFT    8
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_OUTPUT_CLOCK_DELAY_DEFAULT  0x00000000

/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INTERNAL_CLOCK_DELAY [07:04] */
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_MASK   0x000000f0
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_SHIFT  4
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INTERNAL_CLOCK_DELAY_DEFAULT 0x0000000f

/* SDIO_0_CFG :: SD_CLOCK_DELAY :: INPUT_CLOCK_DELAY [03:00] */
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_MASK      0x0000000f
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_SHIFT     0
#define BCHP_SDIO_0_CFG_SD_CLOCK_DELAY_INPUT_CLOCK_DELAY_DEFAULT   0x0000000f

/***************************************************************************
 *SD_PAD_DRV - SDIO Clock delay register
 ***************************************************************************/
/* SDIO_0_CFG :: SD_PAD_DRV :: OVERRIDE_EN [31:31] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_MASK                0x80000000
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_SHIFT               31
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_OVERRIDE_EN_DEFAULT             0x00000000

/* SDIO_0_CFG :: SD_PAD_DRV :: reserved0 [30:23] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_MASK                  0x7f800000
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved0_SHIFT                 23

/* SDIO_0_CFG :: SD_PAD_DRV :: CLK_VAL [22:20] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_MASK                    0x00700000
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_SHIFT                   20
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CLK_VAL_DEFAULT                 0x00000005

/* SDIO_0_CFG :: SD_PAD_DRV :: reserved1 [19:19] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_MASK                  0x00080000
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved1_SHIFT                 19

/* SDIO_0_CFG :: SD_PAD_DRV :: CMD_VAL [18:16] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_MASK                    0x00070000
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_SHIFT                   16
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_CMD_VAL_DEFAULT                 0x00000005

/* SDIO_0_CFG :: SD_PAD_DRV :: reserved2 [15:15] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_MASK                  0x00008000
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved2_SHIFT                 15

/* SDIO_0_CFG :: SD_PAD_DRV :: DAT3_VAL [14:12] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_MASK                   0x00007000
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_SHIFT                  12
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT3_VAL_DEFAULT                0x00000005

/* SDIO_0_CFG :: SD_PAD_DRV :: reserved3 [11:11] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_MASK                  0x00000800
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved3_SHIFT                 11

/* SDIO_0_CFG :: SD_PAD_DRV :: DAT2_VAL [10:08] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_MASK                   0x00000700
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_SHIFT                  8
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT2_VAL_DEFAULT                0x00000005

/* SDIO_0_CFG :: SD_PAD_DRV :: reserved4 [07:07] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_MASK                  0x00000080
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved4_SHIFT                 7

/* SDIO_0_CFG :: SD_PAD_DRV :: DAT1_VAL [06:04] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_MASK                   0x00000070
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_SHIFT                  4
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT1_VAL_DEFAULT                0x00000005

/* SDIO_0_CFG :: SD_PAD_DRV :: reserved5 [03:03] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_MASK                  0x00000008
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_reserved5_SHIFT                 3

/* SDIO_0_CFG :: SD_PAD_DRV :: DAT0_VAL [02:00] */
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_MASK                   0x00000007
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_SHIFT                  0
#define BCHP_SDIO_0_CFG_SD_PAD_DRV_DAT0_VAL_DEFAULT                0x00000005

/***************************************************************************
 *IP_DLY - SDIO Host input delay register
 ***************************************************************************/
/* SDIO_0_CFG :: IP_DLY :: IP_TAP_EN [31:31] */
#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_MASK                      0x80000000
#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_EN_SHIFT                     31

/* SDIO_0_CFG :: IP_DLY :: FORCE_USE_IP_TUNE_CLK [30:30] */
#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_MASK          0x40000000
#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_SHIFT         30
#define BCHP_SDIO_0_CFG_IP_DLY_FORCE_USE_IP_TUNE_CLK_DEFAULT       0x00000000

/* SDIO_0_CFG :: IP_DLY :: reserved0 [29:18] */
#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_MASK                      0x3ffc0000
#define BCHP_SDIO_0_CFG_IP_DLY_reserved0_SHIFT                     18

/* SDIO_0_CFG :: IP_DLY :: IP_DELAY_CTRL [17:16] */
#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_MASK                  0x00030000
#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_SHIFT                 16
#define BCHP_SDIO_0_CFG_IP_DLY_IP_DELAY_CTRL_DEFAULT               0x00000000

/* SDIO_0_CFG :: IP_DLY :: reserved1 [15:06] */
#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_MASK                      0x0000ffc0
#define BCHP_SDIO_0_CFG_IP_DLY_reserved1_SHIFT                     6

/* SDIO_0_CFG :: IP_DLY :: reserved_for_padding2 [05:05] */
#define BCHP_SDIO_0_CFG_IP_DLY_reserved_for_padding2_MASK          0x00000020
#define BCHP_SDIO_0_CFG_IP_DLY_reserved_for_padding2_SHIFT         5

/* SDIO_0_CFG :: IP_DLY :: IP_TAP_DELAY [04:00] */
#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_MASK                   0x0000001f
#define BCHP_SDIO_0_CFG_IP_DLY_IP_TAP_DELAY_SHIFT                  0

/***************************************************************************
 *OP_DLY - SDIO Host output delay register
 ***************************************************************************/
/* SDIO_0_CFG :: OP_DLY :: OP_TAP_EN [31:31] */
#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_MASK                      0x80000000
#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_EN_SHIFT                     31

/* SDIO_0_CFG :: OP_DLY :: reserved0 [30:18] */
#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_MASK                      0x7ffc0000
#define BCHP_SDIO_0_CFG_OP_DLY_reserved0_SHIFT                     18

/* SDIO_0_CFG :: OP_DLY :: OP_DELAY_CTRL [17:16] */
#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_MASK                  0x00030000
#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_SHIFT                 16
#define BCHP_SDIO_0_CFG_OP_DLY_OP_DELAY_CTRL_DEFAULT               0x00000000

/* SDIO_0_CFG :: OP_DLY :: reserved1 [15:04] */
#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_MASK                      0x0000fff0
#define BCHP_SDIO_0_CFG_OP_DLY_reserved1_SHIFT                     4

/* SDIO_0_CFG :: OP_DLY :: OP_TAP_DELAY [03:00] */
#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_MASK                   0x0000000f
#define BCHP_SDIO_0_CFG_OP_DLY_OP_TAP_DELAY_SHIFT                  0

/***************************************************************************
 *TUNING - SDIO Host tuning configuration register
 ***************************************************************************/
/* SDIO_0_CFG :: TUNING :: reserved0 [31:06] */
#define BCHP_SDIO_0_CFG_TUNING_reserved0_MASK                      0xffffffc0
#define BCHP_SDIO_0_CFG_TUNING_reserved0_SHIFT                     6

/* SDIO_0_CFG :: TUNING :: TUNING_COUNT [05:00] */
#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_MASK                   0x0000003f
#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_SHIFT                  0
#define BCHP_SDIO_0_CFG_TUNING_TUNING_COUNT_DEFAULT                0x00000020

/***************************************************************************
 *VOLT_CTRL - SDIO Host 1p8V control logic select register
 ***************************************************************************/
/* SDIO_0_CFG :: VOLT_CTRL :: reserved0 [31:05] */
#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_MASK                   0xffffffe0
#define BCHP_SDIO_0_CFG_VOLT_CTRL_reserved0_SHIFT                  5

/* SDIO_0_CFG :: VOLT_CTRL :: POW_INV_EN [04:04] */
#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_MASK                  0x00000010
#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_SHIFT                 4
#define BCHP_SDIO_0_CFG_VOLT_CTRL_POW_INV_EN_DEFAULT               0x00000000

/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_VAL [03:03] */
#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_MASK                    0x00000008
#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_SHIFT                   3
#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_VAL_DEFAULT                 0x00000000

/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_INV_EN [02:02] */
#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_MASK                 0x00000004
#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_SHIFT                2
#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_INV_EN_DEFAULT              0x00000000

/* SDIO_0_CFG :: VOLT_CTRL :: 1P8V_CTRL_SEL [01:00] */
#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_MASK               0x00000003
#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_SHIFT              0
#define BCHP_SDIO_0_CFG_VOLT_CTRL_1P8V_CTRL_SEL_DEFAULT            0x00000000

/***************************************************************************
 *DEBUG_TAP_DLY - Debug TAP delay setting register
 ***************************************************************************/
/* SDIO_0_CFG :: DEBUG_TAP_DLY :: reserved0 [31:12] */
#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved0_MASK               0xfffff000
#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved0_SHIFT              12

/* SDIO_0_CFG :: DEBUG_TAP_DLY :: DEBUG_OP_TAP_DELAY [11:08] */
#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_OP_TAP_DELAY_MASK      0x00000f00
#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_OP_TAP_DELAY_SHIFT     8

/* SDIO_0_CFG :: DEBUG_TAP_DLY :: reserved1 [07:07] */
#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved1_MASK               0x00000080
#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_reserved1_SHIFT              7

/* SDIO_0_CFG :: DEBUG_TAP_DLY :: DEBUG_IP_TAP_DELAY [06:00] */
#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_IP_TAP_DELAY_MASK      0x0000007f
#define BCHP_SDIO_0_CFG_DEBUG_TAP_DLY_DEBUG_IP_TAP_DELAY_SHIFT     0

/***************************************************************************
 *DEBUG_A2S_BRIDGE_STATUS - Debug A2S Bridge Status
 ***************************************************************************/
/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: s2a_req_done_sync [31:31] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_s2a_req_done_sync_MASK 0x80000000
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_s2a_req_done_sync_SHIFT 31

/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved0 [30:29] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved0_MASK     0x60000000
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved0_SHIFT    29

/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_req_xfer [28:28] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_xfer_MASK  0x10000000
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_xfer_SHIFT 28

/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved1 [27:25] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved1_MASK     0x0e000000
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved1_SHIFT    25

/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_req_write [24:24] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_write_MASK 0x01000000
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_req_write_SHIFT 24

/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_first_bwe4 [23:20] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_first_bwe4_MASK 0x00f00000
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_first_bwe4_SHIFT 20

/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: a2s_last_bwe4 [19:16] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_last_bwe4_MASK 0x000f0000
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_a2s_last_bwe4_SHIFT 16

/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved2 [15:07] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved2_MASK     0x0000ff80
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved2_SHIFT    7

/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: scb_state [06:04] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_scb_state_MASK     0x00000070
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_scb_state_SHIFT    4

/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: reserved3 [03:03] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved3_MASK     0x00000008
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_reserved3_SHIFT    3

/* SDIO_0_CFG :: DEBUG_A2S_BRIDGE_STATUS :: ahb_state [02:00] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_ahb_state_MASK     0x00000007
#define BCHP_SDIO_0_CFG_DEBUG_A2S_BRIDGE_STATUS_ahb_state_SHIFT    0

/***************************************************************************
 *DEBUG_A2S_REQ_START_ADDR - Debug register to read AHB req start address (32b)
 ***************************************************************************/
/* SDIO_0_CFG :: DEBUG_A2S_REQ_START_ADDR :: START_ADDR [31:00] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR_START_ADDR_MASK   0xffffffff
#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_START_ADDR_START_ADDR_SHIFT  0

/***************************************************************************
 *DEBUG_A2S_REQ_END_ADDR - Debug register to read AHB req end address (32b)
 ***************************************************************************/
/* SDIO_0_CFG :: DEBUG_A2S_REQ_END_ADDR :: END_ADDR [31:00] */
#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR_END_ADDR_MASK       0xffffffff
#define BCHP_SDIO_0_CFG_DEBUG_A2S_REQ_END_ADDR_END_ADDR_SHIFT      0

/***************************************************************************
 *DEBUG_DISABLE_CLIENT_INIT - Disable Client Init
 ***************************************************************************/
/* SDIO_0_CFG :: DEBUG_DISABLE_CLIENT_INIT :: reserved0 [31:01] */
#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_reserved0_MASK   0xfffffffe
#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_reserved0_SHIFT  1

/* SDIO_0_CFG :: DEBUG_DISABLE_CLIENT_INIT :: diable_client_init [00:00] */
#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_MASK 0x00000001
#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_SHIFT 0
#define BCHP_SDIO_0_CFG_DEBUG_DISABLE_CLIENT_INIT_diable_client_init_DEFAULT 0x00000000

/***************************************************************************
 *SD_PIN_SEL - SD Pin Select
 ***************************************************************************/
/* SDIO_0_CFG :: SD_PIN_SEL :: reserved0 [31:02] */
#define BCHP_SDIO_0_CFG_SD_PIN_SEL_reserved0_MASK                  0xfffffffc
#define BCHP_SDIO_0_CFG_SD_PIN_SEL_reserved0_SHIFT                 2

/* SDIO_0_CFG :: SD_PIN_SEL :: PIN_SEL [01:00] */
#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_MASK                    0x00000003
#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_SHIFT                   0
#define BCHP_SDIO_0_CFG_SD_PIN_SEL_PIN_SEL_DEFAULT                 0x00000000

/***************************************************************************
 *MAX_CURRENT - Max Current Override
 ***************************************************************************/
/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE [31:31] */
#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_MASK                  0x80000000
#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_SHIFT                 31
#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_DEFAULT               0x00000000

/* SDIO_0_CFG :: MAX_CURRENT :: reserved0 [30:24] */
#define BCHP_SDIO_0_CFG_MAX_CURRENT_reserved0_MASK                 0x7f000000
#define BCHP_SDIO_0_CFG_MAX_CURRENT_reserved0_SHIFT                24

/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_1P8V [23:16] */
#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_MASK             0x00ff0000
#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_SHIFT            16
#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_1P8V_DEFAULT          0x00000000

/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_3P3V [15:08] */
#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_MASK             0x0000ff00
#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_SHIFT            8
#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P3V_DEFAULT          0x00000000

/* SDIO_0_CFG :: MAX_CURRENT :: OVERRIDE_3P0V [07:00] */
#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_MASK             0x000000ff
#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_SHIFT            0
#define BCHP_SDIO_0_CFG_MAX_CURRENT_OVERRIDE_3P0V_DEFAULT          0x00000000

/***************************************************************************
 *VERSION - SDIO VERSION Register
 ***************************************************************************/
/* SDIO_0_CFG :: VERSION :: reserved0 [31:24] */
#define BCHP_SDIO_0_CFG_VERSION_reserved0_MASK                     0xff000000
#define BCHP_SDIO_0_CFG_VERSION_reserved0_SHIFT                    24

/* SDIO_0_CFG :: VERSION :: MAJOR_ID [23:16] */
#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_MASK                      0x00ff0000
#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_SHIFT                     16
#define BCHP_SDIO_0_CFG_VERSION_MAJOR_ID_DEFAULT                   0x00000003

/* SDIO_0_CFG :: VERSION :: MINOR_VER [15:08] */
#define BCHP_SDIO_0_CFG_VERSION_MINOR_VER_MASK                     0x0000ff00
#define BCHP_SDIO_0_CFG_VERSION_MINOR_VER_SHIFT                    8
#define BCHP_SDIO_0_CFG_VERSION_MINOR_VER_DEFAULT                  0x00000002

/* SDIO_0_CFG :: VERSION :: reserved1 [07:04] */
#define BCHP_SDIO_0_CFG_VERSION_reserved1_MASK                     0x000000f0
#define BCHP_SDIO_0_CFG_VERSION_reserved1_SHIFT                    4

/* SDIO_0_CFG :: VERSION :: METAL_VER [03:00] */
#define BCHP_SDIO_0_CFG_VERSION_METAL_VER_MASK                     0x0000000f
#define BCHP_SDIO_0_CFG_VERSION_METAL_VER_SHIFT                    0
#define BCHP_SDIO_0_CFG_VERSION_METAL_VER_DEFAULT                  0x00000000

/***************************************************************************
 *SCRATCH - SDIO Scratch Register
 ***************************************************************************/
/* SDIO_0_CFG :: SCRATCH :: SCRATCH_BITS [31:00] */
#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_MASK                  0xffffffff
#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_SHIFT                 0
#define BCHP_SDIO_0_CFG_SCRATCH_SCRATCH_BITS_DEFAULT               0x00000000

#endif /* #ifndef BCHP_SDIO_0_CFG_H__ */

/* End of File */