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gfiber / kernel / lockdown / 393ffb914678ba13b8b2c6f65be683ea55b7d9ba / . / include / linux / brcmstb / 7366b0 / bchp_memc_ddr_0.h
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/***************************************************************************
* Copyright (c) 1999-2014, Broadcom Corporation
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*
* Module Description:
* DO NOT EDIT THIS FILE DIRECTLY
*
* This module was generated magically with RDB from a source description
* file. You must edit the source file for changes to be made to this file.
*
*
* Date: Generated on Thu Apr 24 03:08:53 2014
* Full Compile MD5 Checksum 1af2c2cf28828ece5496e1312aac0166
* (minus title and desc)
* MD5 Checksum 3203ffce85e3fc9a10f84123e54057b0
*
* Compiled with: RDB Utility combo_header.pl
* RDB Parser 3.0
* unknown unknown
* Perl Interpreter 5.008008
* Operating System linux
*
* Revision History:
*
* $brcm_Log: $
*
***************************************************************************/
#ifndef BCHP_MEMC_DDR_0_H__
#define BCHP_MEMC_DDR_0_H__
/***************************************************************************
*MEMC_DDR_0 - Sequencer DRAM Param and Control Registers
***************************************************************************/
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG 0x00502000 /* Memory Controller Configuration Register */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS 0x00502004 /* Memory Controller Configuration Status Register */
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL 0x00502008 /* Dram initialization control */
#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS 0x0050200c /* Dram initialization status */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0 0x00502010 /* Dram Mode Register 0 */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1 0x00502014 /* Dram Mode Register 1 */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2 0x00502018 /* Dram Mode Register 2 */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3 0x0050201c /* Dram Mode Register 3 */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4 0x00502020 /* Dram Mode Register 4 */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5 0x00502024 /* Dram Mode Register 5 */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6 0x00502028 /* Dram Mode Register 6 */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7 0x0050202c /* Dram Mode Register 7 */
#define BCHP_MEMC_DDR_0_DRAM_MODE_8 0x00502030 /* Dram Mode Register 8 */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15 0x00502034 /* Dram Mode Register 15 */
#define BCHP_MEMC_DDR_0_PPD_CONFIG 0x00502038 /* Precharge power down mode configuration register */
#define BCHP_MEMC_DDR_0_SRPD_CONFIG 0x0050203c /* Self-refresh power down mode configuration register */
#define BCHP_MEMC_DDR_0_SSPD_CMD 0x00502040 /* Software standby power down mode */
#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS 0x00502044 /* Power down status */
#define BCHP_MEMC_DDR_0_WARM_BOOT 0x00502048 /* Warm boot control registers */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0 0x0050204c /* DDR-SDRAM Timing Register 0 */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_1 0x00502050 /* DDR-SDRAM Timing Register 1 */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2 0x00502054 /* Read to Write & write to read timing register */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3 0x00502058 /* DDR-SDRAM Timing Register 3 */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_4 0x0050205c /* DDR-SDRAM Timing Register 4 */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_5 0x00502060 /* DDR-SDRAM Timing Register 5 */
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL 0x00502064 /* Minimum DQ Idle Time Control */
#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY 0x00502068 /* PHY Operational Access Penalty Count. */
#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT 0x0050206c /* Memory Controller , state machine timeout register. */
#define BCHP_MEMC_DDR_0_BANK_STATUS 0x00502070 /* Memory Controller, Bank Status Register */
#define BCHP_MEMC_DDR_0_TESTER_LATENCY 0x00502074 /* Memory Controller, Tester Latency Register. */
#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH 0x00502078 /* Sequencer Ring Buffer programmable depth. */
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO 0x0050207c /* Sequencer write data error info */
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO 0x00502080 /* Sequencer transaction ID mismatch error info */
#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS 0x00502084 /* Sequencer Violation Info register clear. */
#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD 0x00502088 /* Command Lookahead */
#define BCHP_MEMC_DDR_0_DFI_PHASE_ENABLE 0x0050208c /* Sequencer DFI Phase Enable */
#define BCHP_MEMC_DDR_0_STAT_CONTROL 0x00502300 /* Statistics Control register */
#define BCHP_MEMC_DDR_0_STAT_TIMER 0x00502304 /* Statistics Timer */
#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP 0x00502308 /* DRAM Idle_NOP Cycle Count Register. */
#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP 0x0050230c /* Maximum DRAM idle_NOP cycle count register. */
#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP 0x00502310 /* Minimum DRAM idle_NOP cycle count register. */
#define BCHP_MEMC_DDR_0_STAT_CAS_ALL 0x00502314 /* CAS Count Register. */
#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL 0x00502318 /* Maximum DRAM CAS cycle count register. */
#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL 0x0050231c /* Minimum DRAM CAS cycle count register. */
#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL 0x00502320 /* DRAM Penalty Cycle Count register. */
#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM 0x00502324 /* GDDR Write Mask Penalty Cycle Count register. */
#define BCHP_MEMC_DDR_0_STAT_PAGE_MERGE_ALL 0x00502328 /* Page Merge Event Count register. */
#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL 0x0050232c /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL 0x00502330 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL 0x00502334 /* Number of overall system memory read transactions. */
#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL 0x00502338 /* Number of overall system memory write transactions. */
#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL 0x0050233c /* Maximum Number of Overall System memory transactions. */
#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL 0x00502340 /* Minimum Number of Overall System memory transactions. */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS 0x00502344 /* Service CAS Cycle Count register. */
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS 0x00502348 /* Maximum service CAS cycle count register. */
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS 0x0050234c /* Minimum service CAS cycle count register. */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY 0x00502350 /* Service Intra DRAM Penalty Cycle Count register. */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY 0x00502354 /* Service Post DRAM Penalty Cycle Count register. */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY 0x00502358 /* Service GDDR Write Mask Penalty Cycle Count register. */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_PAGE_MERGES 0x0050235c /* Service Page Merge Event Count register. */
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES 0x00502360 /* Maximum service cycle count register. */
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES 0x00502364 /* Minimum service cycle count register. */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ 0x00502368 /* Service Read Transaction Count register. */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE 0x0050236c /* Service Write Transaction Count register. */
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS 0x00502370 /* Maximum service Transaction count register. */
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS 0x00502374 /* Minimum service cycle Transaction register. */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY 0x00502378 /* Service Latency Count register. */
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY 0x0050237c /* Maximum Service Latency count register. */
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY 0x00502380 /* Minimum Service Latency count register. */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x00502384 /* Absolute Minimum Service Latency count register. */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x00502388 /* Absolute Maximum Service Latency count register. */
#define BCHP_MEMC_DDR_0_STAT_REFRESH 0x0050238c /* Total number of refreshes issued. */
#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE 0x00502390 /* Min DQ Idle Write event counter */
#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ 0x00502394 /* Min DQ Idle Read event counter */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0 0x00502400 /* CAS or consumption cycle count register for client 0. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1 0x00502404 /* CAS or consumption cycle count register for client 1. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2 0x00502408 /* CAS or consumption cycle count register for client 2. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3 0x0050240c /* CAS or consumption cycle count register for client 3. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4 0x00502410 /* CAS or consumption cycle count register for client 4. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5 0x00502414 /* CAS or consumption cycle count register for client 5. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6 0x00502418 /* CAS or consumption cycle count register for client 6. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7 0x0050241c /* CAS or consumption cycle count register for client 7. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8 0x00502420 /* CAS or consumption cycle count register for client 8. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9 0x00502424 /* CAS or consumption cycle count register for client 9. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10 0x00502428 /* CAS or consumption cycle count register for client 10. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11 0x0050242c /* CAS or consumption cycle count register for client 11. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12 0x00502430 /* CAS or consumption cycle count register for client 12. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13 0x00502434 /* CAS or consumption cycle count register for client 13. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14 0x00502438 /* CAS or consumption cycle count register for client 14. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15 0x0050243c /* CAS or consumption cycle count register for client 15. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16 0x00502440 /* CAS or consumption cycle count register for client 16. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17 0x00502444 /* CAS or consumption cycle count register for client 17. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18 0x00502448 /* CAS or consumption cycle count register for client 18. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19 0x0050244c /* CAS or consumption cycle count register for client 19. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20 0x00502450 /* CAS or consumption cycle count register for client 20. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21 0x00502454 /* CAS or consumption cycle count register for client 21. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22 0x00502458 /* CAS or consumption cycle count register for client 22. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23 0x0050245c /* CAS or consumption cycle count register for client 23. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24 0x00502460 /* CAS or consumption cycle count register for client 24. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25 0x00502464 /* CAS or consumption cycle count register for client 25. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26 0x00502468 /* CAS or consumption cycle count register for client 26. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27 0x0050246c /* CAS or consumption cycle count register for client 27. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28 0x00502470 /* CAS or consumption cycle count register for client 28. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29 0x00502474 /* CAS or consumption cycle count register for client 29. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30 0x00502478 /* CAS or consumption cycle count register for client 30. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31 0x0050247c /* CAS or consumption cycle count register for client 31. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32 0x00502480 /* CAS or consumption cycle count register for client 32. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33 0x00502484 /* CAS or consumption cycle count register for client 33. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34 0x00502488 /* CAS or consumption cycle count register for client 34. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35 0x0050248c /* CAS or consumption cycle count register for client 35. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36 0x00502490 /* CAS or consumption cycle count register for client 36. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37 0x00502494 /* CAS or consumption cycle count register for client 37. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38 0x00502498 /* CAS or consumption cycle count register for client 38. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39 0x0050249c /* CAS or consumption cycle count register for client 39. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40 0x005024a0 /* CAS or consumption cycle count register for client 40. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41 0x005024a4 /* CAS or consumption cycle count register for client 41. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42 0x005024a8 /* CAS or consumption cycle count register for client 42. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43 0x005024ac /* CAS or consumption cycle count register for client 43. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44 0x005024b0 /* CAS or consumption cycle count register for client 44. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45 0x005024b4 /* CAS or consumption cycle count register for client 45. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46 0x005024b8 /* CAS or consumption cycle count register for client 46. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47 0x005024bc /* CAS or consumption cycle count register for client 47. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48 0x005024c0 /* CAS or consumption cycle count register for client 48. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49 0x005024c4 /* CAS or consumption cycle count register for client 49. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50 0x005024c8 /* CAS or consumption cycle count register for client 50. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51 0x005024cc /* CAS or consumption cycle count register for client 51. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52 0x005024d0 /* CAS or consumption cycle count register for client 52. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53 0x005024d4 /* CAS or consumption cycle count register for client 53. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54 0x005024d8 /* CAS or consumption cycle count register for client 54. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55 0x005024dc /* CAS or consumption cycle count register for client 55. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56 0x005024e0 /* CAS or consumption cycle count register for client 56. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57 0x005024e4 /* CAS or consumption cycle count register for client 57. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58 0x005024e8 /* CAS or consumption cycle count register for client 58. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59 0x005024ec /* CAS or consumption cycle count register for client 59. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60 0x005024f0 /* CAS or consumption cycle count register for client 60. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61 0x005024f4 /* CAS or consumption cycle count register for client 61. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62 0x005024f8 /* CAS or consumption cycle count register for client 62. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63 0x005024fc /* CAS or consumption cycle count register for client 63. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64 0x00502500 /* CAS or consumption cycle count register for client 64. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65 0x00502504 /* CAS or consumption cycle count register for client 65. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66 0x00502508 /* CAS or consumption cycle count register for client 66. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67 0x0050250c /* CAS or consumption cycle count register for client 67. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68 0x00502510 /* CAS or consumption cycle count register for client 68. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69 0x00502514 /* CAS or consumption cycle count register for client 69. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70 0x00502518 /* CAS or consumption cycle count register for client 70. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71 0x0050251c /* CAS or consumption cycle count register for client 71. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72 0x00502520 /* CAS or consumption cycle count register for client 72. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73 0x00502524 /* CAS or consumption cycle count register for client 73. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74 0x00502528 /* CAS or consumption cycle count register for client 74. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75 0x0050252c /* CAS or consumption cycle count register for client 75. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76 0x00502530 /* CAS or consumption cycle count register for client 76. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77 0x00502534 /* CAS or consumption cycle count register for client 77. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78 0x00502538 /* CAS or consumption cycle count register for client 78. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79 0x0050253c /* CAS or consumption cycle count register for client 79. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80 0x00502540 /* CAS or consumption cycle count register for client 80. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81 0x00502544 /* CAS or consumption cycle count register for client 81. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82 0x00502548 /* CAS or consumption cycle count register for client 82. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83 0x0050254c /* CAS or consumption cycle count register for client 83. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84 0x00502550 /* CAS or consumption cycle count register for client 84. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85 0x00502554 /* CAS or consumption cycle count register for client 85. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86 0x00502558 /* CAS or consumption cycle count register for client 86. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87 0x0050255c /* CAS or consumption cycle count register for client 87. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88 0x00502560 /* CAS or consumption cycle count register for client 88. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89 0x00502564 /* CAS or consumption cycle count register for client 89. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90 0x00502568 /* CAS or consumption cycle count register for client 90. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91 0x0050256c /* CAS or consumption cycle count register for client 91. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92 0x00502570 /* CAS or consumption cycle count register for client 92. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93 0x00502574 /* CAS or consumption cycle count register for client 93. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94 0x00502578 /* CAS or consumption cycle count register for client 94. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95 0x0050257c /* CAS or consumption cycle count register for client 95. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96 0x00502580 /* CAS or consumption cycle count register for client 96. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97 0x00502584 /* CAS or consumption cycle count register for client 97. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98 0x00502588 /* CAS or consumption cycle count register for client 98. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99 0x0050258c /* CAS or consumption cycle count register for client 99. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100 0x00502590 /* CAS or consumption cycle count register for client 100. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101 0x00502594 /* CAS or consumption cycle count register for client 101. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102 0x00502598 /* CAS or consumption cycle count register for client 102. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103 0x0050259c /* CAS or consumption cycle count register for client 103. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104 0x005025a0 /* CAS or consumption cycle count register for client 104. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105 0x005025a4 /* CAS or consumption cycle count register for client 105. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106 0x005025a8 /* CAS or consumption cycle count register for client 106. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107 0x005025ac /* CAS or consumption cycle count register for client 107. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108 0x005025b0 /* CAS or consumption cycle count register for client 108. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109 0x005025b4 /* CAS or consumption cycle count register for client 109. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110 0x005025b8 /* CAS or consumption cycle count register for client 110. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111 0x005025bc /* CAS or consumption cycle count register for client 111. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112 0x005025c0 /* CAS or consumption cycle count register for client 112. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113 0x005025c4 /* CAS or consumption cycle count register for client 113. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114 0x005025c8 /* CAS or consumption cycle count register for client 114. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115 0x005025cc /* CAS or consumption cycle count register for client 115. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116 0x005025d0 /* CAS or consumption cycle count register for client 116. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117 0x005025d4 /* CAS or consumption cycle count register for client 117. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118 0x005025d8 /* CAS or consumption cycle count register for client 118. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119 0x005025dc /* CAS or consumption cycle count register for client 119. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120 0x005025e0 /* CAS or consumption cycle count register for client 120. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121 0x005025e4 /* CAS or consumption cycle count register for client 121. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122 0x005025e8 /* CAS or consumption cycle count register for client 122. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123 0x005025ec /* CAS or consumption cycle count register for client 123. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124 0x005025f0 /* CAS or consumption cycle count register for client 124. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125 0x005025f4 /* CAS or consumption cycle count register for client 125. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126 0x005025f8 /* CAS or consumption cycle count register for client 126. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127 0x005025fc /* CAS or consumption cycle count register for client 127. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128 0x00502600 /* CAS or consumption cycle count register for client 128. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129 0x00502604 /* CAS or consumption cycle count register for client 129. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130 0x00502608 /* CAS or consumption cycle count register for client 130. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131 0x0050260c /* CAS or consumption cycle count register for client 131. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132 0x00502610 /* CAS or consumption cycle count register for client 132. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133 0x00502614 /* CAS or consumption cycle count register for client 133. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134 0x00502618 /* CAS or consumption cycle count register for client 134. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135 0x0050261c /* CAS or consumption cycle count register for client 135. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136 0x00502620 /* CAS or consumption cycle count register for client 136. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137 0x00502624 /* CAS or consumption cycle count register for client 137. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138 0x00502628 /* CAS or consumption cycle count register for client 138. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139 0x0050262c /* CAS or consumption cycle count register for client 139. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140 0x00502630 /* CAS or consumption cycle count register for client 140. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141 0x00502634 /* CAS or consumption cycle count register for client 141. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142 0x00502638 /* CAS or consumption cycle count register for client 142. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143 0x0050263c /* CAS or consumption cycle count register for client 143. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144 0x00502640 /* CAS or consumption cycle count register for client 144. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145 0x00502644 /* CAS or consumption cycle count register for client 145. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146 0x00502648 /* CAS or consumption cycle count register for client 146. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147 0x0050264c /* CAS or consumption cycle count register for client 147. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148 0x00502650 /* CAS or consumption cycle count register for client 148. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149 0x00502654 /* CAS or consumption cycle count register for client 149. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150 0x00502658 /* CAS or consumption cycle count register for client 150. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151 0x0050265c /* CAS or consumption cycle count register for client 151. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152 0x00502660 /* CAS or consumption cycle count register for client 152. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153 0x00502664 /* CAS or consumption cycle count register for client 153. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154 0x00502668 /* CAS or consumption cycle count register for client 154. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155 0x0050266c /* CAS or consumption cycle count register for client 155. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156 0x00502670 /* CAS or consumption cycle count register for client 156. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157 0x00502674 /* CAS or consumption cycle count register for client 157. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158 0x00502678 /* CAS or consumption cycle count register for client 158. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159 0x0050267c /* CAS or consumption cycle count register for client 159. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160 0x00502680 /* CAS or consumption cycle count register for client 160. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161 0x00502684 /* CAS or consumption cycle count register for client 161. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162 0x00502688 /* CAS or consumption cycle count register for client 162. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163 0x0050268c /* CAS or consumption cycle count register for client 163. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164 0x00502690 /* CAS or consumption cycle count register for client 164. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165 0x00502694 /* CAS or consumption cycle count register for client 165. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166 0x00502698 /* CAS or consumption cycle count register for client 166. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167 0x0050269c /* CAS or consumption cycle count register for client 167. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168 0x005026a0 /* CAS or consumption cycle count register for client 168. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169 0x005026a4 /* CAS or consumption cycle count register for client 169. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170 0x005026a8 /* CAS or consumption cycle count register for client 170. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171 0x005026ac /* CAS or consumption cycle count register for client 171. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172 0x005026b0 /* CAS or consumption cycle count register for client 172. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173 0x005026b4 /* CAS or consumption cycle count register for client 173. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174 0x005026b8 /* CAS or consumption cycle count register for client 174. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175 0x005026bc /* CAS or consumption cycle count register for client 175. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176 0x005026c0 /* CAS or consumption cycle count register for client 176. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177 0x005026c4 /* CAS or consumption cycle count register for client 177. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178 0x005026c8 /* CAS or consumption cycle count register for client 178. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179 0x005026cc /* CAS or consumption cycle count register for client 179. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180 0x005026d0 /* CAS or consumption cycle count register for client 180. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181 0x005026d4 /* CAS or consumption cycle count register for client 181. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182 0x005026d8 /* CAS or consumption cycle count register for client 182. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183 0x005026dc /* CAS or consumption cycle count register for client 183. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184 0x005026e0 /* CAS or consumption cycle count register for client 184. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185 0x005026e4 /* CAS or consumption cycle count register for client 185. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186 0x005026e8 /* CAS or consumption cycle count register for client 186. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187 0x005026ec /* CAS or consumption cycle count register for client 187. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188 0x005026f0 /* CAS or consumption cycle count register for client 188. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189 0x005026f4 /* CAS or consumption cycle count register for client 189. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190 0x005026f8 /* CAS or consumption cycle count register for client 190. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191 0x005026fc /* CAS or consumption cycle count register for client 191. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192 0x00502700 /* CAS or consumption cycle count register for client 192. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193 0x00502704 /* CAS or consumption cycle count register for client 193. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194 0x00502708 /* CAS or consumption cycle count register for client 194. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195 0x0050270c /* CAS or consumption cycle count register for client 195. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196 0x00502710 /* CAS or consumption cycle count register for client 196. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197 0x00502714 /* CAS or consumption cycle count register for client 197. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198 0x00502718 /* CAS or consumption cycle count register for client 198. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199 0x0050271c /* CAS or consumption cycle count register for client 199. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200 0x00502720 /* CAS or consumption cycle count register for client 200. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201 0x00502724 /* CAS or consumption cycle count register for client 201. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202 0x00502728 /* CAS or consumption cycle count register for client 202. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203 0x0050272c /* CAS or consumption cycle count register for client 203. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204 0x00502730 /* CAS or consumption cycle count register for client 204. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205 0x00502734 /* CAS or consumption cycle count register for client 205. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206 0x00502738 /* CAS or consumption cycle count register for client 206. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207 0x0050273c /* CAS or consumption cycle count register for client 207. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208 0x00502740 /* CAS or consumption cycle count register for client 208. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209 0x00502744 /* CAS or consumption cycle count register for client 209. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210 0x00502748 /* CAS or consumption cycle count register for client 210. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211 0x0050274c /* CAS or consumption cycle count register for client 211. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212 0x00502750 /* CAS or consumption cycle count register for client 212. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213 0x00502754 /* CAS or consumption cycle count register for client 213. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214 0x00502758 /* CAS or consumption cycle count register for client 214. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215 0x0050275c /* CAS or consumption cycle count register for client 215. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216 0x00502760 /* CAS or consumption cycle count register for client 216. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217 0x00502764 /* CAS or consumption cycle count register for client 217. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218 0x00502768 /* CAS or consumption cycle count register for client 218. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219 0x0050276c /* CAS or consumption cycle count register for client 219. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220 0x00502770 /* CAS or consumption cycle count register for client 220. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221 0x00502774 /* CAS or consumption cycle count register for client 221. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222 0x00502778 /* CAS or consumption cycle count register for client 222. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223 0x0050277c /* CAS or consumption cycle count register for client 223. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224 0x00502780 /* CAS or consumption cycle count register for client 224. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225 0x00502784 /* CAS or consumption cycle count register for client 225. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226 0x00502788 /* CAS or consumption cycle count register for client 226. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227 0x0050278c /* CAS or consumption cycle count register for client 227. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228 0x00502790 /* CAS or consumption cycle count register for client 228. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229 0x00502794 /* CAS or consumption cycle count register for client 229. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230 0x00502798 /* CAS or consumption cycle count register for client 230. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231 0x0050279c /* CAS or consumption cycle count register for client 231. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232 0x005027a0 /* CAS or consumption cycle count register for client 232. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233 0x005027a4 /* CAS or consumption cycle count register for client 233. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234 0x005027a8 /* CAS or consumption cycle count register for client 234. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235 0x005027ac /* CAS or consumption cycle count register for client 235. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236 0x005027b0 /* CAS or consumption cycle count register for client 236. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237 0x005027b4 /* CAS or consumption cycle count register for client 237. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238 0x005027b8 /* CAS or consumption cycle count register for client 238. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239 0x005027bc /* CAS or consumption cycle count register for client 239. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240 0x005027c0 /* CAS or consumption cycle count register for client 240. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241 0x005027c4 /* CAS or consumption cycle count register for client 241. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242 0x005027c8 /* CAS or consumption cycle count register for client 242. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243 0x005027cc /* CAS or consumption cycle count register for client 243. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244 0x005027d0 /* CAS or consumption cycle count register for client 244. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245 0x005027d4 /* CAS or consumption cycle count register for client 245. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246 0x005027d8 /* CAS or consumption cycle count register for client 246. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247 0x005027dc /* CAS or consumption cycle count register for client 247. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248 0x005027e0 /* CAS or consumption cycle count register for client 248. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249 0x005027e4 /* CAS or consumption cycle count register for client 249. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250 0x005027e8 /* CAS or consumption cycle count register for client 250. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251 0x005027ec /* CAS or consumption cycle count register for client 251. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252 0x005027f0 /* CAS or consumption cycle count register for client 252. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253 0x005027f4 /* CAS or consumption cycle count register for client 253. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254 0x005027f8 /* CAS or consumption cycle count register for client 254. */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255 0x005027fc /* CAS or consumption cycle count register for client 255. */
/***************************************************************************
*CNTRLR_CONFIG - Memory Controller Configuration Register
***************************************************************************/
/* MEMC_DDR_0 :: CNTRLR_CONFIG :: reserved0 [31:15] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_MASK 0xffff8000
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_reserved0_SHIFT 15
/* MEMC_DDR_0 :: CNTRLR_CONFIG :: GROUPAGE_ENABLE [14:14] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_GROUPAGE_ENABLE_MASK 0x00004000
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_GROUPAGE_ENABLE_SHIFT 14
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_GROUPAGE_ENABLE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: CNTRLR_CONFIG :: MODIFY_RASTER_ADDR [13:13] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_MASK 0x00002000
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_SHIFT 13
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_MODIFY_RASTER_ADDR_DEFAULT 0x00000001
/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_COMMANDS_2T [12:12] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_COMMANDS_2T_MASK 0x00001000
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_COMMANDS_2T_SHIFT 12
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_COMMANDS_2T_DEFAULT 0x00000000
/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_TOTAL_WIDTH [11:10] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_MASK 0x00000c00
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_SHIFT 10
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_DEFAULT 0x00000002
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_reserved_x8 0
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_x16 1
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_x32 2
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_TOTAL_WIDTH_reserved_x64 3
/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_DEVICE_WIDTH [09:08] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_MASK 0x00000300
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_SHIFT 8
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_DEFAULT 0x00000001
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_x8 0
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_x16 1
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_reserved_2 2
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_WIDTH_reserved_3 3
/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_DEVICE_SIZE [07:04] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_MASK 0x000000f0
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_SHIFT 4
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_DEFAULT 0x00000003
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_256_Mb 0
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_512_Mb 1
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_1_Gb 2
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_2_Gb 3
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_4_Gb 4
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_8_Gb 5
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_16_Gb 6
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_7 7
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_8 8
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_9 9
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_10 10
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_11 11
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_12 12
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_13 13
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_14 14
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_SIZE_reserved_15 15
/* MEMC_DDR_0 :: CNTRLR_CONFIG :: DRAM_DEVICE_TYPE [03:00] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_MASK 0x0000000f
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_SHIFT 0
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DEFAULT 0x00000001
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_DDR2 0
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DDR3 1
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_DDR4 2
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_GDDR5M 3
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_GDDR5 4
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_5 5
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_6 6
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_7 7
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_8 8
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_9 9
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_10 10
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_11 11
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_12 12
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_13 13
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_14 14
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_DRAM_DEVICE_TYPE_reserved_15 15
/***************************************************************************
*CNTRLR_CONFIG_STATUS - Memory Controller Configuration Status Register
***************************************************************************/
/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: reserved0 [31:15] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_reserved0_MASK 0xffff8000
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_reserved0_SHIFT 15
/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: GROUPAGE_ENABLE [14:14] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_GROUPAGE_ENABLE_MASK 0x00004000
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_GROUPAGE_ENABLE_SHIFT 14
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_GROUPAGE_ENABLE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: MODIFY_RASTER_ADDR [13:13] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_MODIFY_RASTER_ADDR_MASK 0x00002000
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_MODIFY_RASTER_ADDR_SHIFT 13
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_MODIFY_RASTER_ADDR_DEFAULT 0x00000001
/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_COMMANDS_2T [12:12] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_COMMANDS_2T_MASK 0x00001000
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_COMMANDS_2T_SHIFT 12
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_COMMANDS_2T_DEFAULT 0x00000000
/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_TOTAL_WIDTH [11:10] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_MASK 0x00000c00
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_SHIFT 10
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_DEFAULT 0x00000002
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_reserved_x8 0
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_x16 1
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_x32 2
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_TOTAL_WIDTH_reserved_x64 3
/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_DEVICE_WIDTH [09:08] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_MASK 0x00000300
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_SHIFT 8
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_DEFAULT 0x00000001
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_x8 0
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_x16 1
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_reserved_2 2
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_WIDTH_reserved_3 3
/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_DEVICE_SIZE [07:04] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_MASK 0x000000f0
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_SHIFT 4
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_DEFAULT 0x00000003
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_256_Mb 0
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_512_Mb 1
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_1_Gb 2
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_2_Gb 3
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_4_Gb 4
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_8_Gb 5
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_16_Gb 6
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_7 7
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_8 8
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_9 9
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_10 10
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_11 11
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_12 12
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_13 13
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_14 14
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_SIZE_reserved_15 15
/* MEMC_DDR_0 :: CNTRLR_CONFIG_STATUS :: DRAM_DEVICE_TYPE [03:00] */
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_MASK 0x0000000f
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_SHIFT 0
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_DEFAULT 0x00000001
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_DDR2 0
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_DDR3 1
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_DDR4 2
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_GDDR5M 3
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_GDDR5 4
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_5 5
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_6 6
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_7 7
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_8 8
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_9 9
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_10 10
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_11 11
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_12 12
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_13 13
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_14 14
#define BCHP_MEMC_DDR_0_CNTRLR_CONFIG_STATUS_DRAM_DEVICE_TYPE_reserved_15 15
/***************************************************************************
*DRAM_INIT_CNTRL - Dram initialization control
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: reserved0 [31:06] */
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_MASK 0xffffffc0
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_reserved0_SHIFT 6
/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: IGNORE_PHY_REQUEST_AT_RESET [05:05] */
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_MASK 0x00000020
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_SHIFT 5
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_IGNORE_PHY_REQUEST_AT_RESET_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: ENTER_PHY_OP_STATE [04:04] */
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_MASK 0x00000010
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENTER_PHY_OP_STATE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: ENABLE_AUTO_PHY_OP_ACCESS [03:03] */
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_MASK 0x00000008
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_ENABLE_AUTO_PHY_OP_ACCESS_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: OVERRIDE_PHY_INIT_COMPLETE [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_INIT_COMPLETE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: OVERRIDE_PHY_DFI_GRANT [01:01] */
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_MASK 0x00000002
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_SHIFT 1
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_OVERRIDE_PHY_DFI_GRANT_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_INIT_CNTRL :: PHY_DFI_GRANT_VALUE [00:00] */
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_MASK 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_INIT_CNTRL_PHY_DFI_GRANT_VALUE_DEFAULT 0x00000000
/***************************************************************************
*DRAM_INIT_STATUS - Dram initialization status
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: reserved0 [31:03] */
#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_reserved0_SHIFT 3
/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_CLIENT_BUSY [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_CLIENT_BUSY_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_CLIENT_BUSY_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_CLIENT_BUSY_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: PHY_DFI_REQUEST_VALUE [01:01] */
#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_MASK 0x00000002
#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_SHIFT 1
#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_PHY_DFI_REQUEST_VALUE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_MASK 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_INIT_STATUS_INIT_DONE_DEFAULT 0x00000000
/***************************************************************************
*DRAM_MODE_0 - Dram Mode Register 0
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_MODE_0 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_MASK 0xffff0000
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_reserved0_SHIFT 16
/* MEMC_DDR_0 :: DRAM_MODE_0 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_MASK 0x0000e000
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_SHIFT 13
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_unused_0_DEFAULT 0x00000000
/* union - case DDR3 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_MASK 0x00000e00
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_WR_DEFAULT 0x00000004
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_MASK 0x00000100
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_MASK 0x00000080
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_MASK 0x00000070
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT 0x00000004
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_MASK 0x00000008
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_RBT_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_CL_0_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_MASK 0x00000003
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR3_BL_DEFAULT 0x00000000
/* union - case DDR4 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: WR [11:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_WR_MASK 0x00000e00
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_WR_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_WR_DEFAULT 0x00000004
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: DLL_RST [08:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_DLL_RST_MASK 0x00000100
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_DLL_RST_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_DLL_RST_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: TEST_MODE [07:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_TEST_MODE_MASK 0x00000080
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_TEST_MODE_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_TEST_MODE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: CL_3_1 [06:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_3_1_MASK 0x00000070
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_3_1_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_3_1_DEFAULT 0x00000004
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: BT [03:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BT_MASK 0x00000008
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BT_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BT_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: CL_0 [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_0_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_0_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_CL_0_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: DDR4 :: BL [01:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BL_MASK 0x00000003
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BL_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_DDR4_BL_DEFAULT 0x00000000
/* union - case GDDR5M [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: WR [11:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WR_MASK 0x00000f00
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WR_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WR_DEFAULT 0x00000008
/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: TEST_MODE [07:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_TEST_MODE_MASK 0x00000080
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_TEST_MODE_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_TEST_MODE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: CL [06:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_CL_MASK 0x00000078
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_CL_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_CL_DEFAULT 0x00000009
/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5M :: WL [02:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WL_MASK 0x00000007
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WL_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5M_WL_DEFAULT 0x00000004
/* union - case GDDR5 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: WR [11:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WR_MASK 0x00000f00
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WR_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WR_DEFAULT 0x00000008
/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: TEST_MODE [07:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_TEST_MODE_MASK 0x00000080
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_TEST_MODE_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_TEST_MODE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: CL [06:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_CL_MASK 0x00000078
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_CL_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_CL_DEFAULT 0x00000009
/* MEMC_DDR_0 :: DRAM_MODE_0 :: GDDR5 :: WL [02:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WL_MASK 0x00000007
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WL_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_0_GDDR5_WL_DEFAULT 0x00000004
/***************************************************************************
*DRAM_MODE_1 - Dram Mode Register 1
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_MODE_1 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_MASK 0xffff0000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_reserved0_SHIFT 16
/* MEMC_DDR_0 :: DRAM_MODE_1 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_MASK 0x0000e000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_SHIFT 13
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_unused_0_DEFAULT 0x00000000
/* union - case DDR3 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_Q_OFF_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_MASK 0x00000800
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_SHIFT 11
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_TDQS_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_MASK 0x00000400
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK 0x00000200
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_MASK 0x00000100
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_unused_2_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_MASK 0x00000080
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK 0x00000040
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK 0x00000020
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT 5
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_MASK 0x00000018
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_AL_DEFAULT 0x00000001
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT 0x00000001
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK 0x00000002
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_MASK 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR3_DLL_EN_DISABLE 1
/* union - case DDR4 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: Q_OFF [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_Q_OFF_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: TDQS [11:11] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_MASK 0x00000800
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_SHIFT 11
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_TDQS_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: RTT_NOM [10:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_RTT_NOM_MASK 0x00000700
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_RTT_NOM_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_RTT_NOM_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: WR_LEVEL [07:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_MASK 0x00000080
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_WR_LEVEL_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: unused [06:05] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_MASK 0x00000060
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_SHIFT 5
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_unused_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: AL [04:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_AL_MASK 0x00000018
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_AL_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_AL_DEFAULT 0x00000001
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: DRIVER_IMP_CNTRL [02:01] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_MASK 0x00000006
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_SHIFT 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DRIVER_IMP_CNTRL_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: DDR4 :: DLL_EN [00:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_MASK 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_DDR4_DLL_EN_DISABLE 1
/* union - case GDDR5M [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: unused_1 [12:11] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_1_MASK 0x00001800
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_1_SHIFT 11
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: ABI [10:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_MASK 0x00000400
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ABI_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: WDBI [09:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_MASK 0x00000200
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_WDBI_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: RDBI [08:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_MASK 0x00000100
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_RDBI_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: unused_2 [07:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_2_MASK 0x00000080
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_2_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_unused_2_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: CAL_UPD [06:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_MASK 0x00000040
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_CAL_UPD_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: ADDR_CMD_TERM [05:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_MASK 0x00000030
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_ADDR_CMD_TERM_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: DATA_TERM [03:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DATA_TERM_MASK 0x0000000c
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DATA_TERM_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DATA_TERM_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5M :: DRIVER_STRENGTH [01:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_MASK 0x00000003
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5M_DRIVER_STRENGTH_DEFAULT 0x00000000
/* union - case GDDR5 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: PLL_DLL_RST [11:11] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_RST_MASK 0x00000800
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_RST_SHIFT 11
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_RST_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: ABI [10:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_MASK 0x00000400
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ABI_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: WDBI [09:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_MASK 0x00000200
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_WDBI_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: RDBI [08:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_MASK 0x00000100
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_RDBI_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: PLL_DLL [07:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_MASK 0x00000080
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_PLL_DLL_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: CAL_UPD [06:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_MASK 0x00000040
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_CAL_UPD_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: ADDR_CMD_TERM [05:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_MASK 0x00000030
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_ADDR_CMD_TERM_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: DATA_TERM [03:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DATA_TERM_MASK 0x0000000c
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DATA_TERM_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DATA_TERM_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_1 :: GDDR5 :: DRIVER_STRENGTH [01:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_MASK 0x00000003
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_1_GDDR5_DRIVER_STRENGTH_DEFAULT 0x00000000
/***************************************************************************
*DRAM_MODE_2 - Dram Mode Register 2
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_MODE_2 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_MASK 0xffff0000
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_reserved0_SHIFT 16
/* MEMC_DDR_0 :: DRAM_MODE_2 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_MASK 0x0000e000
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_SHIFT 13
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_unused_0_DEFAULT 0x00000000
/* union - case DDR3 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_MASK 0x00001800
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_SHIFT 11
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_MASK 0x00000600
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT 0x00000001
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_MASK 0x00000100
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_unused_2_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_MASK 0x00000080
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_MASK 0x00000040
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT 0x00000001
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_MASK 0x00000038
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_WCL_DEFAULT 0x00000001
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_MASK 0x00000007
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR3_PASR_DEFAULT 0x00000000
/* union - case DDR4 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: WR_DATA_CRC [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_WR_DATA_CRC_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: unused_2 [11:11] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_2_MASK 0x00000800
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_2_SHIFT 11
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_2_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: RTT_WR [10:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RTT_WR_MASK 0x00000600
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RTT_WR_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_RTT_WR_DEFAULT 0x00000001
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: unused_1 [08:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_1_MASK 0x00000100
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_1_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: LPASR [07:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_LPASR_MASK 0x000000c0
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_LPASR_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_LPASR_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: CWL [05:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_CWL_MASK 0x00000038
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_CWL_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_CWL_DEFAULT 0x00000001
/* MEMC_DDR_0 :: DRAM_MODE_2 :: DDR4 :: unused_0 [02:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_0_MASK 0x00000007
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_0_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_DDR4_unused_0_DEFAULT 0x00000000
/* union - case GDDR5M [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: ADDR_CMD_TERM_OFFSET [11:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_MASK 0x00000e00
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_ADDR_CMD_TERM_OFFSET_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: DATA_WCK_TERM_OFFSET [08:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_MASK 0x000001c0
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_DATA_WCK_TERM_OFFSET_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: OCD_PUP_DRIVER_OFFSET [05:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_MASK 0x00000038
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PUP_DRIVER_OFFSET_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5M :: OCD_PDN_DRIVER_OFFSET [02:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_MASK 0x00000007
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5M_OCD_PDN_DRIVER_OFFSET_DEFAULT 0x00000000
/* union - case GDDR5 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: ADDR_CMD_TERM_OFFSET [11:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_MASK 0x00000e00
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_ADDR_CMD_TERM_OFFSET_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: DATA_WCK_TERM_OFFSET [08:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_MASK 0x000001c0
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_DATA_WCK_TERM_OFFSET_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: OCD_PUP_DRIVER_OFFSET [05:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_MASK 0x00000038
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PUP_DRIVER_OFFSET_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_2 :: GDDR5 :: OCD_PDN_DRIVER_OFFSET [02:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_MASK 0x00000007
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_2_GDDR5_OCD_PDN_DRIVER_OFFSET_DEFAULT 0x00000000
/***************************************************************************
*DRAM_MODE_3 - Dram Mode Register 3
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_MODE_3 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_MASK 0xffff0000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_reserved0_SHIFT 16
/* MEMC_DDR_0 :: DRAM_MODE_3 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_MASK 0x0000e000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_SHIFT 13
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_unused_0_DEFAULT 0x00000000
/* union - case DDR3 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: unused_1 [12:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_unused_1_MASK 0x00001ff8
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_unused_1_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_MASK 0x00000003
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT 0x00000000
/* union - case DDR4 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MPR_READ_FORMAT [12:11] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_MASK 0x00001800
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_SHIFT 11
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_READ_FORMAT_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: WL_CRC_DM [10:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_WL_CRC_DM_MASK 0x00000600
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_WL_CRC_DM_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_WL_CRC_DM_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: FGR [08:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_FGR_MASK 0x000001c0
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_FGR_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_FGR_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: TEMP_READOUT [05:05] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_TEMP_READOUT_MASK 0x00000020
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_TEMP_READOUT_SHIFT 5
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_TEMP_READOUT_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_TEMP_READOUT_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_TEMP_READOUT_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: PER_DRAM_ADDR [04:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_MASK 0x00000010
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_PER_DRAM_ADDR_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: GEARDOWN [03:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_GEARDOWN_MASK 0x00000008
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_GEARDOWN_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_GEARDOWN_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MPR [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: DDR4 :: MPR_PAGE [01:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_PAGE_MASK 0x00000003
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_PAGE_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_DDR4_MPR_PAGE_DEFAULT 0x00000000
/* union - case GDDR5M [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: BANK_GROUPS [11:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_BANK_GROUPS_MASK 0x00000c00
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_BANK_GROUPS_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_BANK_GROUPS_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK_TERM [09:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK_TERM_MASK 0x00000300
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK_TERM_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK_TERM_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: DRAM_INFO [07:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_DRAM_INFO_MASK 0x000000c0
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_DRAM_INFO_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_DRAM_INFO_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: RDQS_MODE [05:05] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_MASK 0x00000020
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_SHIFT 5
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_RDQS_MODE_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK2CK_TRAIN [04:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_MASK 0x00000010
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK2CK_TRAIN_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK23_INVERT [03:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_MASK 0x00000008
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK23_INVERT_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: WCK01_INVERT [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_WCK01_INVERT_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5M :: SELF_REFRESH [01:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_SELF_REFRESH_MASK 0x00000003
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_SELF_REFRESH_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5M_SELF_REFRESH_DEFAULT 0x00000000
/* union - case GDDR5 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: BANK_GROUPS [11:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_BANK_GROUPS_MASK 0x00000c00
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_BANK_GROUPS_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_BANK_GROUPS_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK_TERM [09:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK_TERM_MASK 0x00000300
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK_TERM_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK_TERM_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: DRAM_INFO [07:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_DRAM_INFO_MASK 0x000000c0
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_DRAM_INFO_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_DRAM_INFO_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: RDQS_MODE [05:05] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_MASK 0x00000020
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_SHIFT 5
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_RDQS_MODE_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK2CK_TRAIN [04:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_MASK 0x00000010
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK2CK_TRAIN_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK23_INVERT [03:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_MASK 0x00000008
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK23_INVERT_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: WCK01_INVERT [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_WCK01_INVERT_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_3 :: GDDR5 :: SELF_REFRESH [01:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_SELF_REFRESH_MASK 0x00000003
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_SELF_REFRESH_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_GDDR5_SELF_REFRESH_DEFAULT 0x00000000
/* union - case Others [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_3 :: Others :: unused_1 [12:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_Others_unused_1_MASK 0x00001fff
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_Others_unused_1_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_3_Others_unused_1_DEFAULT 0x00000000
/***************************************************************************
*DRAM_MODE_4 - Dram Mode Register 4
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_MODE_4 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_reserved0_MASK 0xffff0000
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_reserved0_SHIFT 16
/* MEMC_DDR_0 :: DRAM_MODE_4 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_unused_0_MASK 0x0000e000
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_unused_0_SHIFT 13
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_unused_0_DEFAULT 0x00000000
/* union - case DDR4 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: WR_PREAMBLE [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_WR_PREAMBLE_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_WR_PREAMBLE_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_WR_PREAMBLE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: RD_PREAMBLE [11:11] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_MASK 0x00000800
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_SHIFT 11
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: RD_PREAMBLE_TRAINING [10:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_MASK 0x00000400
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_RD_PREAMBLE_TRAINING_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: SELF_REFRESH_ABORT [09:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_MASK 0x00000200
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_SELF_REFRESH_ABORT_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: CMD_ADDR_LATENCY [08:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_MASK 0x000001c0
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_CMD_ADDR_LATENCY_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: unused_2 [05:05] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_2_MASK 0x00000020
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_2_SHIFT 5
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_2_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: VREF_MONITOR [04:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_MASK 0x00000010
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_VREF_MONITOR_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: TEMP_CONTROLLED_REFRESH [03:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_MASK 0x00000008
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: TEMP_CONTROLLED_REFRESH_RANGE [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_TEMP_CONTROLLED_REFRESH_RANGE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: MAXIMUM_POWER_SAVINGS [01:01] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_MASK 0x00000002
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_SHIFT 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_MAXIMUM_POWER_SAVINGS_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_4 :: DDR4 :: unused_1 [00:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_1_MASK 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_1_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_DDR4_unused_1_DEFAULT 0x00000000
/* union - case GDDR5M [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: EDC_HOLD_INVERT [11:11] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_MASK 0x00000800
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_SHIFT 11
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_INVERT_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: WR_CRC [10:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_MASK 0x00000400
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_DEFAULT 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_WR_CRC_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: RD_CRC [09:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_MASK 0x00000200
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_DEFAULT 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_RD_CRC_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: CRC_RD_LATENCY [08:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_MASK 0x00000180
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_RD_LATENCY_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: CRC_WR_LATENCY [06:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_MASK 0x00000070
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_CRC_WR_LATENCY_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5M :: EDC_HOLD_PATTERN [03:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_MASK 0x0000000f
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5M_EDC_HOLD_PATTERN_DEFAULT 0x00000000
/* union - case GDDR5 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: EDC_HOLD_INVERT [11:11] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_MASK 0x00000800
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_SHIFT 11
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_INVERT_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: WR_CRC [10:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_MASK 0x00000400
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_DEFAULT 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_WR_CRC_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: RD_CRC [09:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_MASK 0x00000200
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_DEFAULT 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_RD_CRC_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: CRC_RD_LATENCY [08:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_MASK 0x00000180
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_RD_LATENCY_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: CRC_WR_LATENCY [06:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_MASK 0x00000070
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_CRC_WR_LATENCY_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_4 :: GDDR5 :: EDC_HOLD_PATTERN [03:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_MASK 0x0000000f
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_GDDR5_EDC_HOLD_PATTERN_DEFAULT 0x00000000
/* union - case Others [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_4 :: Others :: unused_1 [12:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_Others_unused_1_MASK 0x00001fff
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_Others_unused_1_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_4_Others_unused_1_DEFAULT 0x00000000
/***************************************************************************
*DRAM_MODE_5 - Dram Mode Register 5
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_MODE_5 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_reserved0_MASK 0xffff0000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_reserved0_SHIFT 16
/* MEMC_DDR_0 :: DRAM_MODE_5 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_unused_0_MASK 0x0000e000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_unused_0_SHIFT 13
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_unused_0_DEFAULT 0x00000000
/* union - case DDR4 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: RD_DBI [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RD_DBI_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: WR_DBI [11:11] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_MASK 0x00000800
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_SHIFT 11
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_WR_DBI_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: DM [10:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_MASK 0x00000400
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_DM_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CA_PARITY_PERSIST [09:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CA_PARITY_PERSIST_MASK 0x00000200
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CA_PARITY_PERSIST_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CA_PARITY_PERSIST_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CA_PARITY_PERSIST_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CA_PARITY_PERSIST_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: RTT_PARK [08:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RTT_PARK_MASK 0x000001c0
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RTT_PARK_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_RTT_PARK_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: ODT_INPUT_BUFFER [05:05] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_ODT_INPUT_BUFFER_MASK 0x00000020
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_ODT_INPUT_BUFFER_SHIFT 5
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_ODT_INPUT_BUFFER_DEFAULT 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_ODT_INPUT_BUFFER_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_ODT_INPUT_BUFFER_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CMD_ADDR_PARITY_ERROR [04:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_MASK 0x00000010
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_ERROR_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CRC_ERROR [03:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CRC_ERROR_MASK 0x00000008
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CRC_ERROR_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CRC_ERROR_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_5 :: DDR4 :: CMD_ADDR_PARITY_LATENCY [02:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_MASK 0x00000007
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_DDR4_CMD_ADDR_PARITY_LATENCY_DEFAULT 0x00000000
/* union - case GDDR5M [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: RAS [11:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_RAS_MASK 0x00000fc0
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_RAS_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_RAS_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: unused_2 [05:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_2_MASK 0x00000038
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_2_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_unused_2_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: LP3 [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP3_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: LP2 [01:01] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_MASK 0x00000002
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_SHIFT 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP2_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5M :: LP1 [00:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_MASK 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5M_LP1_DISABLE 0
/* union - case GDDR5 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: RAS [11:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_RAS_MASK 0x00000fc0
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_RAS_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_RAS_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: PLL_DLL_BANDWIDTH [05:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_MASK 0x00000038
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_PLL_DLL_BANDWIDTH_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: LP3 [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP3_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: LP2 [01:01] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_MASK 0x00000002
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_SHIFT 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP2_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_5 :: GDDR5 :: LP1 [00:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_MASK 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_GDDR5_LP1_DISABLE 0
/* union - case Others [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_5 :: Others :: unused_1 [12:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_Others_unused_1_MASK 0x00001fff
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_Others_unused_1_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_5_Others_unused_1_DEFAULT 0x00000000
/***************************************************************************
*DRAM_MODE_6 - Dram Mode Register 6
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_MODE_6 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_reserved0_MASK 0xffff0000
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_reserved0_SHIFT 16
/* MEMC_DDR_0 :: DRAM_MODE_6 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_unused_0_MASK 0x0000e000
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_unused_0_SHIFT 13
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_unused_0_DEFAULT 0x00000000
/* union - case DDR4 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: CCD_L [12:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_CCD_L_MASK 0x00001c00
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_CCD_L_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_CCD_L_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: unused_1 [09:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_unused_1_MASK 0x00000300
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_unused_1_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: VREF_TRAINING_ENABLE [07:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_ENABLE_MASK 0x00000080
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_ENABLE_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_ENABLE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: VREF_TRAINING_RANGE [06:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_MASK 0x00000040
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_RANGE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: DDR4 :: VREF_TRAINING [05:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_MASK 0x0000003f
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_DDR4_VREF_TRAINING_DEFAULT 0x00000000
/* union - case GDDR5M [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: VREFD_OFFSET_01 [11:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_MASK 0x00000f00
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_01_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: VREFD_OFFSET_23 [07:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_MASK 0x000000f0
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_VREFD_OFFSET_23_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: unused_2 [03:01] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_2_MASK 0x0000000e
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_2_SHIFT 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_unused_2_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5M :: WCK2CK_ALIGN [00:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_MASK 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5M_WCK2CK_ALIGN_DEFAULT 0x00000000
/* union - case GDDR5 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD_OFFSET_01 [11:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_MASK 0x00000f00
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_01_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD_OFFSET_23 [07:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_MASK 0x000000f0
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_OFFSET_23_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD [03:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MASK 0x00000008
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: AUTO_VREFD [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_AUTO_VREFD_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_AUTO_VREFD_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_AUTO_VREFD_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: VREFD_MERGE [01:01] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MERGE_MASK 0x00000002
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MERGE_SHIFT 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_VREFD_MERGE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_6 :: GDDR5 :: WCK2CK_ALIGN [00:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_MASK 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_GDDR5_WCK2CK_ALIGN_DEFAULT 0x00000000
/* union - case Others [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_6 :: Others :: unused_1 [12:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_Others_unused_1_MASK 0x00001fff
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_Others_unused_1_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_6_Others_unused_1_DEFAULT 0x00000000
/***************************************************************************
*DRAM_MODE_7 - Dram Mode Register 7
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_MODE_7 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_reserved0_MASK 0xffff0000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_reserved0_SHIFT 16
/* MEMC_DDR_0 :: DRAM_MODE_7 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_unused_0_MASK 0x0000e000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_unused_0_SHIFT 13
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_unused_0_DEFAULT 0x00000000
/* union - case GDDR5M [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: DDC [11:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DDC_MASK 0x00000c00
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DDC_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DDC_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: VDD_RANGE [09:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_VDD_RANGE_MASK 0x00000300
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_VDD_RANGE_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_VDD_RANGE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: HALF_VREFD [07:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_HALF_VREFD_MASK 0x00000080
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_HALF_VREFD_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_HALF_VREFD_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: TEMP_SENSE [06:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_MASK 0x00000040
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_TEMP_SENSE_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: DQ_PREAMBLE [05:05] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_MASK 0x00000020
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_SHIFT 5
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_DQ_PREAMBLE_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: WCK2CK_AUTO_SYNC [04:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_MASK 0x00000010
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_WCK2CK_AUTO_SYNC_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: LOW_FREQ [03:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_MASK 0x00000008
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_LOW_FREQ_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5M :: unused_2 [02:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_2_MASK 0x00000007
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_2_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5M_unused_2_DEFAULT 0x00000000
/* union - case GDDR5 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: DDC [11:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DDC_MASK 0x00000c00
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DDC_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DDC_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: VDD_RANGE [09:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_VDD_RANGE_MASK 0x00000300
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_VDD_RANGE_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_VDD_RANGE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: HALF_VREFD [07:07] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_HALF_VREFD_MASK 0x00000080
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_HALF_VREFD_SHIFT 7
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_HALF_VREFD_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: TEMP_SENSE [06:06] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_MASK 0x00000040
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_SHIFT 6
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_TEMP_SENSE_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: DQ_PREAMBLE [05:05] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_MASK 0x00000020
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_SHIFT 5
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_DQ_PREAMBLE_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: WCK2CK_AUTO_SYNC [04:04] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_MASK 0x00000010
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_SHIFT 4
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_WCK2CK_AUTO_SYNC_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: LOW_FREQ [03:03] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_MASK 0x00000008
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_SHIFT 3
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_LOW_FREQ_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: PLL_DELAY_COMP [02:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_MASK 0x00000004
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_DELAY_COMP_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: PLL_FAST_LOCK [01:01] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_MASK 0x00000002
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_SHIFT 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_FAST_LOCK_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_7 :: GDDR5 :: PLL_STANDBY [00:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_MASK 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_GDDR5_PLL_STANDBY_DISABLE 0
/* union - case Others [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_7 :: Others :: unused_1 [12:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_Others_unused_1_MASK 0x00001fff
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_Others_unused_1_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_7_Others_unused_1_DEFAULT 0x00000000
/***************************************************************************
*DRAM_MODE_8 - Dram Mode Register 8
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_MODE_8 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_reserved0_MASK 0xffff0000
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_reserved0_SHIFT 16
/* MEMC_DDR_0 :: DRAM_MODE_8 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_unused_0_MASK 0x0000e000
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_unused_0_SHIFT 13
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_unused_0_DEFAULT 0x00000000
/* union - case GDDR5 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_8 :: GDDR5 :: unused_1 [12:02] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_unused_1_MASK 0x00001ffc
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_unused_1_SHIFT 2
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_8 :: GDDR5 :: WR_EHF [01:01] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_WR_EHF_MASK 0x00000002
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_WR_EHF_SHIFT 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_WR_EHF_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_8 :: GDDR5 :: CL_EHF [00:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_CL_EHF_MASK 0x00000001
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_CL_EHF_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_GDDR5_CL_EHF_DEFAULT 0x00000000
/* union - case Others [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_8 :: Others :: unused_1 [12:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_Others_unused_1_MASK 0x00001fff
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_Others_unused_1_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_8_Others_unused_1_DEFAULT 0x00000000
/***************************************************************************
*DRAM_MODE_15 - Dram Mode Register 15
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_MODE_15 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_reserved0_MASK 0xffff0000
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_reserved0_SHIFT 16
/* MEMC_DDR_0 :: DRAM_MODE_15 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_unused_0_MASK 0x0000e000
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_unused_0_SHIFT 13
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_unused_0_DEFAULT 0x00000000
/* union - case GDDR5M [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: unused_1 [12:12] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_1_MASK 0x00001000
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_1_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: ADDR_TRAINING [11:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_MASK 0x00000c00
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_ADDR_TRAINING_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: MRE_MF1 [09:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_MASK 0x00000200
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF1_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: MRE_MF2 [08:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_MASK 0x00000100
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_MRE_MF2_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5M :: unused_2 [07:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_2_MASK 0x000000ff
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_2_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5M_unused_2_DEFAULT 0x00000000
/* union - case GDDR5 [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: unused_1 [12:11] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_1_MASK 0x00001800
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_1_SHIFT 11
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_1_DEFAULT 0x00000000
/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: ADDR_TRAINING [10:10] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_MASK 0x00000400
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_SHIFT 10
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_ENABLE 1
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_ADDR_TRAINING_DISABLE 0
/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: MRE_MF1 [09:09] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_MASK 0x00000200
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_SHIFT 9
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF1_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: MRE_MF2 [08:08] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_MASK 0x00000100
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_ENABLE 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_MRE_MF2_DISABLE 1
/* MEMC_DDR_0 :: DRAM_MODE_15 :: GDDR5 :: unused_2 [07:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_2_MASK 0x000000ff
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_2_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_GDDR5_unused_2_DEFAULT 0x00000000
/* union - case Others [12:00] */
/* MEMC_DDR_0 :: DRAM_MODE_15 :: Others :: unused_1 [12:00] */
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_Others_unused_1_MASK 0x00001fff
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_Others_unused_1_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_MODE_15_Others_unused_1_DEFAULT 0x00000000
/***************************************************************************
*PPD_CONFIG - Precharge power down mode configuration register
***************************************************************************/
/* MEMC_DDR_0 :: PPD_CONFIG :: reserved0 [31:15] */
#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_MASK 0xffff8000
#define BCHP_MEMC_DDR_0_PPD_CONFIG_reserved0_SHIFT 15
/* MEMC_DDR_0 :: PPD_CONFIG :: FORCE_PPD_EXIT [14:14] */
#define BCHP_MEMC_DDR_0_PPD_CONFIG_FORCE_PPD_EXIT_MASK 0x00004000
#define BCHP_MEMC_DDR_0_PPD_CONFIG_FORCE_PPD_EXIT_SHIFT 14
#define BCHP_MEMC_DDR_0_PPD_CONFIG_FORCE_PPD_EXIT_DEFAULT 0x00000000
/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_FORCE [13:13] */
#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_FORCE_MASK 0x00002000
#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_FORCE_SHIFT 13
#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_FORCE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: PPD_CONFIG :: PPD_EN [12:12] */
#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_MASK 0x00001000
#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_SHIFT 12
#define BCHP_MEMC_DDR_0_PPD_CONFIG_PPD_EN_DEFAULT 0x00000000
/* MEMC_DDR_0 :: PPD_CONFIG :: INACT_COUNT [11:00] */
#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_MASK 0x00000fff
#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_PPD_CONFIG_INACT_COUNT_DEFAULT 0x00000000
/***************************************************************************
*SRPD_CONFIG - Self-refresh power down mode configuration register
***************************************************************************/
/* MEMC_DDR_0 :: SRPD_CONFIG :: reserved0 [31:18] */
#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_MASK 0xfffc0000
#define BCHP_MEMC_DDR_0_SRPD_CONFIG_reserved0_SHIFT 18
/* MEMC_DDR_0 :: SRPD_CONFIG :: FORCE_SRPD_EXIT [17:17] */
#define BCHP_MEMC_DDR_0_SRPD_CONFIG_FORCE_SRPD_EXIT_MASK 0x00020000
#define BCHP_MEMC_DDR_0_SRPD_CONFIG_FORCE_SRPD_EXIT_SHIFT 17
#define BCHP_MEMC_DDR_0_SRPD_CONFIG_FORCE_SRPD_EXIT_DEFAULT 0x00000000
/* MEMC_DDR_0 :: SRPD_CONFIG :: SRPD_EN [16:16] */
#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_MASK 0x00010000
#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_SHIFT 16
#define BCHP_MEMC_DDR_0_SRPD_CONFIG_SRPD_EN_DEFAULT 0x00000000
/* MEMC_DDR_0 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_MASK 0x0000ffff
#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_SRPD_CONFIG_INACT_COUNT_DEFAULT 0x00000000
/***************************************************************************
*SSPD_CMD - Software standby power down mode
***************************************************************************/
/* MEMC_DDR_0 :: SSPD_CMD :: reserved0 [31:01] */
#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_DDR_0_SSPD_CMD_reserved0_SHIFT 1
/* MEMC_DDR_0 :: SSPD_CMD :: SSPD [00:00] */
#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK 0x00000001
#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_SHIFT 0
#define BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_DEFAULT 0x00000000
/***************************************************************************
*POWER_DOWN_STATUS - Power down status
***************************************************************************/
/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_reserved0_SHIFT 3
/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SSPD [02:02] */
#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK 0x00000004
#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_SHIFT 2
#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_DEFAULT 0x00000000
/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: SRPD [01:01] */
#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_MASK 0x00000002
#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_SHIFT 1
#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SRPD_DEFAULT 0x00000000
/* MEMC_DDR_0 :: POWER_DOWN_STATUS :: PPD [00:00] */
#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_MASK 0x00000001
#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_SHIFT 0
#define BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_PPD_DEFAULT 0x00000000
/***************************************************************************
*WARM_BOOT - Warm boot control registers
***************************************************************************/
/* MEMC_DDR_0 :: WARM_BOOT :: reserved0 [31:01] */
#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_DDR_0_WARM_BOOT_reserved0_SHIFT 1
/* MEMC_DDR_0 :: WARM_BOOT :: WARM_BOOT [00:00] */
#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_MASK 0x00000001
#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_SHIFT 0
#define BCHP_MEMC_DDR_0_WARM_BOOT_WARM_BOOT_DEFAULT 0x00000000
/***************************************************************************
*DRAM_TIMING_0 - DDR-SDRAM Timing Register 0
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_MASK 0xff000000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_SHIFT 24
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRRD_NOP_DEFAULT 0x00000006
/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_MASK 0x00ff0000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_SHIFT 16
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRCD_NOP_DEFAULT 0x00000008
/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_MASK 0x0000ff00
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRP_NOP_DEFAULT 0x00000008
/* MEMC_DDR_0 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_MASK 0x000000ff
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_TIMING_0_TRAS_NOP_DEFAULT 0x00000014
/***************************************************************************
*DRAM_TIMING_1 - DDR-SDRAM Timing Register 1
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_TIMING_1 :: reserved0 [31:28] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_MASK 0xf0000000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_reserved0_SHIFT 28
/* MEMC_DDR_0 :: DRAM_TIMING_1 :: T32AW_NOP [27:16] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_T32AW_NOP_MASK 0x0fff0000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_T32AW_NOP_SHIFT 16
#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_T32AW_NOP_DEFAULT 0x00000020
/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_MASK 0x0000ff00
#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TFAW_NOP_DEFAULT 0x0000001b
/* MEMC_DDR_0 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_MASK 0x000000ff
#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_TIMING_1_TRTP_NOP_DEFAULT 0x00000004
/***************************************************************************
*DRAM_TIMING_2 - Read to Write & write to read timing register
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_TIMING_2 :: TRRDL_NOP [31:24] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_TRRDL_NOP_MASK 0xff000000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_TRRDL_NOP_SHIFT 24
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_TRRDL_NOP_DEFAULT 0x00000006
/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RDL_NOP [23:16] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RDL_NOP_MASK 0x00ff0000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RDL_NOP_SHIFT 16
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RDL_NOP_DEFAULT 0x0000000e
/* MEMC_DDR_0 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_MASK 0x0000ff00
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_WR2RD_NOP_DEFAULT 0x0000000e
/* MEMC_DDR_0 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_MASK 0x000000ff
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_TIMING_2_RD2WR_NOP_DEFAULT 0x00000009
/***************************************************************************
*DRAM_TIMING_3 - DDR-SDRAM Timing Register 3
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_TIMING_3 :: TRCDWR_NOP [31:24] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_TRCDWR_NOP_MASK 0xff000000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_TRCDWR_NOP_SHIFT 24
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_TRCDWR_NOP_DEFAULT 0x00000008
/* MEMC_DDR_0 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:16] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK 0x00ff0000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT 16
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT 0x0000000c
/* MEMC_DDR_0 :: DRAM_TIMING_3 :: PRECHARGE_ALL_DELAY [15:08] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_PRECHARGE_ALL_DELAY_MASK 0x0000ff00
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_PRECHARGE_ALL_DELAY_SHIFT 8
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_PRECHARGE_ALL_DELAY_DEFAULT 0x00000008
/* MEMC_DDR_0 :: DRAM_TIMING_3 :: LOAD_MODE_DELAY [07:00] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_LOAD_MODE_DELAY_MASK 0x000000ff
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_LOAD_MODE_DELAY_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_TIMING_3_LOAD_MODE_DELAY_DEFAULT 0x0000000c
/***************************************************************************
*DRAM_TIMING_4 - DDR-SDRAM Timing Register 4
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_TIMING_4 :: reserved0 [31:24] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_MASK 0xff000000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_reserved0_SHIFT 24
/* MEMC_DDR_0 :: DRAM_TIMING_4 :: REFRESH_DELAY [23:12] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_MASK 0x00fff000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT 0x00000058
/* MEMC_DDR_0 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [11:00] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_MASK 0x00000fff
#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT 0x00000200
/***************************************************************************
*DRAM_TIMING_5 - DDR-SDRAM Timing Register 5
***************************************************************************/
/* MEMC_DDR_0 :: DRAM_TIMING_5 :: reserved0 [31:30] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_MASK 0xc0000000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_reserved0_SHIFT 30
/* MEMC_DDR_0 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [29:22] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK 0x3fc00000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT 22
#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT 0x00000003
/* MEMC_DDR_0 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [21:12] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK 0x003ff000
#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT 12
#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT 0x0000000d
/* MEMC_DDR_0 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [11:00] */
#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK 0x00000fff
#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT 0
#define BCHP_MEMC_DDR_0_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT 0x00000200
/***************************************************************************
*MIN_DQ_IDLE_CONTROL - Minimum DQ Idle Time Control
***************************************************************************/
/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved0 [31:23] */
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved0_MASK 0xff800000
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved0_SHIFT 23
/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: WriteDelay [22:20] */
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteDelay_MASK 0x00700000
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteDelay_SHIFT 20
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteDelay_DEFAULT 0x00000000
/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved1 [19:18] */
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved1_MASK 0x000c0000
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved1_SHIFT 18
/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: WriteForceIdle [17:17] */
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteForceIdle_MASK 0x00020000
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteForceIdle_SHIFT 17
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteForceIdle_DEFAULT 0x00000000
/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: WriteEnable [16:16] */
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteEnable_MASK 0x00010000
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteEnable_SHIFT 16
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_WriteEnable_DEFAULT 0x00000000
/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved2 [15:07] */
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved2_MASK 0x0000ff80
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved2_SHIFT 7
/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: ReadDelay [06:04] */
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadDelay_MASK 0x00000070
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadDelay_SHIFT 4
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadDelay_DEFAULT 0x00000000
/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: reserved3 [03:02] */
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved3_MASK 0x0000000c
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_reserved3_SHIFT 2
/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: ReadForceIdle [01:01] */
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadForceIdle_MASK 0x00000002
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadForceIdle_SHIFT 1
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadForceIdle_DEFAULT 0x00000000
/* MEMC_DDR_0 :: MIN_DQ_IDLE_CONTROL :: ReadEnable [00:00] */
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadEnable_MASK 0x00000001
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadEnable_SHIFT 0
#define BCHP_MEMC_DDR_0_MIN_DQ_IDLE_CONTROL_ReadEnable_DEFAULT 0x00000000
/***************************************************************************
*PHY_OP_ACCESS_PENALTY - PHY Operational Access Penalty Count.
***************************************************************************/
/* MEMC_DDR_0 :: PHY_OP_ACCESS_PENALTY :: PHY_OP_ACCESS_WAIT_PENALTY [31:00] */
#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_SHIFT 0
#define BCHP_MEMC_DDR_0_PHY_OP_ACCESS_PENALTY_PHY_OP_ACCESS_WAIT_PENALTY_DEFAULT 0x00000004
/***************************************************************************
*CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
***************************************************************************/
/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_MASK 0xfffe0000
#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_reserved0_SHIFT 17
/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_MASK 0x00010000
#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT 16
#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_MASK 0x0000ffff
#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT 0x0000ffff
/***************************************************************************
*BANK_STATUS - Memory Controller, Bank Status Register
***************************************************************************/
/* MEMC_DDR_0 :: BANK_STATUS :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_MASK 0xffff0000
#define BCHP_MEMC_DDR_0_BANK_STATUS_reserved0_SHIFT 16
/* MEMC_DDR_0 :: BANK_STATUS :: BANK_STATUS [15:00] */
#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK_STATUS_MASK 0x0000ffff
#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK_STATUS_SHIFT 0
#define BCHP_MEMC_DDR_0_BANK_STATUS_BANK_STATUS_DEFAULT 0x0000ffff
/***************************************************************************
*TESTER_LATENCY - Memory Controller, Tester Latency Register.
***************************************************************************/
/* MEMC_DDR_0 :: TESTER_LATENCY :: reserved0 [31:08] */
#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_MASK 0xffffff00
#define BCHP_MEMC_DDR_0_TESTER_LATENCY_reserved0_SHIFT 8
/* MEMC_DDR_0 :: TESTER_LATENCY :: TLATENCY_SEL [07:00] */
#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_MASK 0x000000ff
#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_SHIFT 0
#define BCHP_MEMC_DDR_0_TESTER_LATENCY_TLATENCY_SEL_DEFAULT 0x00000000
/***************************************************************************
*SEQ_RING_BUF_DEPTH - Sequencer Ring Buffer programmable depth.
***************************************************************************/
/* MEMC_DDR_0 :: SEQ_RING_BUF_DEPTH :: reserved0 [31:05] */
#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_reserved0_MASK 0xffffffe0
#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_reserved0_SHIFT 5
/* MEMC_DDR_0 :: SEQ_RING_BUF_DEPTH :: RING_BUF_DEPTH [04:00] */
#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_MASK 0x0000001f
#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_SHIFT 0
#define BCHP_MEMC_DDR_0_SEQ_RING_BUF_DEPTH_RING_BUF_DEPTH_DEFAULT 0x00000010
/***************************************************************************
*SEQ_WRDATA_ERR_INFO - Sequencer write data error info
***************************************************************************/
/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: reserved0 [31:21] */
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved0_MASK 0xffe00000
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved0_SHIFT 21
/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: INTF_ID [20:16] */
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_ID_MASK 0x001f0000
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_ID_SHIFT 16
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_ID_DEFAULT 0x00000000
/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: reserved1 [15:08] */
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved1_MASK 0x0000ff00
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_reserved1_SHIFT 8
/* MEMC_DDR_0 :: SEQ_WRDATA_ERR_INFO :: INTF_TRANSACTION_ID [07:00] */
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_MASK 0x000000ff
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_SHIFT 0
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_ERR_INFO_INTF_TRANSACTION_ID_DEFAULT 0x00000000
/***************************************************************************
*SEQ_WRDATA_TRANSID_MISMATCH_INFO - Sequencer transaction ID mismatch error info
***************************************************************************/
/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: reserved0 [31:28] */
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved0_MASK 0xf0000000
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved0_SHIFT 28
/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: INTF_TYPE [27:24] */
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_MASK 0x0f000000
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_SHIFT 24
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_TYPE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: reserved1 [23:21] */
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved1_MASK 0x00e00000
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_reserved1_SHIFT 21
/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: INTF_ID [20:16] */
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_MASK 0x001f0000
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_SHIFT 16
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_INTF_ID_DEFAULT 0x00000000
/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: CMD_TRANS_ID [15:08] */
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_MASK 0x0000ff00
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_SHIFT 8
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_CMD_TRANS_ID_DEFAULT 0x00000000
/* MEMC_DDR_0 :: SEQ_WRDATA_TRANSID_MISMATCH_INFO :: WRDATA_TRANS_ID [07:00] */
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_MASK 0x000000ff
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_SHIFT 0
#define BCHP_MEMC_DDR_0_SEQ_WRDATA_TRANSID_MISMATCH_INFO_WRDATA_TRANS_ID_DEFAULT 0x00000000
/***************************************************************************
*SEQ_CLEAR_VIOLATIONS - Sequencer Violation Info register clear.
***************************************************************************/
/* MEMC_DDR_0 :: SEQ_CLEAR_VIOLATIONS :: reserved0 [31:01] */
#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_reserved0_MASK 0xfffffffe
#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_reserved0_SHIFT 1
/* MEMC_DDR_0 :: SEQ_CLEAR_VIOLATIONS :: SEQ_CLEAR_VIOL [00:00] */
#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_MASK 0x00000001
#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_SHIFT 0
#define BCHP_MEMC_DDR_0_SEQ_CLEAR_VIOLATIONS_SEQ_CLEAR_VIOL_DEFAULT 0x00000000
/***************************************************************************
*CMD_LOOKAHEAD - Command Lookahead
***************************************************************************/
/* MEMC_DDR_0 :: CMD_LOOKAHEAD :: KEEP_OPEN_DISABLE [31:31] */
#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_KEEP_OPEN_DISABLE_MASK 0x80000000
#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_KEEP_OPEN_DISABLE_SHIFT 31
#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_KEEP_OPEN_DISABLE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: CMD_LOOKAHEAD :: KEEP_OPEN_RW_DISABLE [30:30] */
#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_KEEP_OPEN_RW_DISABLE_MASK 0x40000000
#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_KEEP_OPEN_RW_DISABLE_SHIFT 30
#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_KEEP_OPEN_RW_DISABLE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: CMD_LOOKAHEAD :: reserved_for_padding0 [29:08] */
#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_reserved_for_padding0_MASK 0x3fffff00
#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_reserved_for_padding0_SHIFT 8
/* MEMC_DDR_0 :: CMD_LOOKAHEAD :: CAS_LOOKAHEAD [07:00] */
#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_CAS_LOOKAHEAD_MASK 0x000000ff
#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_CAS_LOOKAHEAD_SHIFT 0
#define BCHP_MEMC_DDR_0_CMD_LOOKAHEAD_CAS_LOOKAHEAD_DEFAULT 0x00000002
/***************************************************************************
*DFI_PHASE_ENABLE - Sequencer DFI Phase Enable
***************************************************************************/
/* MEMC_DDR_0 :: DFI_PHASE_ENABLE :: reserved0 [31:04] */
#define BCHP_MEMC_DDR_0_DFI_PHASE_ENABLE_reserved0_MASK 0xfffffff0
#define BCHP_MEMC_DDR_0_DFI_PHASE_ENABLE_reserved0_SHIFT 4
/* MEMC_DDR_0 :: DFI_PHASE_ENABLE :: DFI_PHASE_ENABLE [03:00] */
#define BCHP_MEMC_DDR_0_DFI_PHASE_ENABLE_DFI_PHASE_ENABLE_MASK 0x0000000f
#define BCHP_MEMC_DDR_0_DFI_PHASE_ENABLE_DFI_PHASE_ENABLE_SHIFT 0
#define BCHP_MEMC_DDR_0_DFI_PHASE_ENABLE_DFI_PHASE_ENABLE_DEFAULT 0x0000000f
/***************************************************************************
*STAT_CONTROL - Statistics Control register
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CONTROL :: reserved0 [31:11] */
#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_MASK 0xfffff800
#define BCHP_MEMC_DDR_0_STAT_CONTROL_reserved0_SHIFT 11
/* MEMC_DDR_0 :: STAT_CONTROL :: PER_CLIENT_MODE [10:10] */
#define BCHP_MEMC_DDR_0_STAT_CONTROL_PER_CLIENT_MODE_MASK 0x00000400
#define BCHP_MEMC_DDR_0_STAT_CONTROL_PER_CLIENT_MODE_SHIFT 10
#define BCHP_MEMC_DDR_0_STAT_CONTROL_PER_CLIENT_MODE_DEFAULT 0x00000000
/* MEMC_DDR_0 :: STAT_CONTROL :: COUNTER_MODE [09:09] */
#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MASK 0x00000200
#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_SHIFT 9
#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT 1
#define BCHP_MEMC_DDR_0_STAT_CONTROL_COUNTER_MODE_NORMAL 0
/* MEMC_DDR_0 :: STAT_CONTROL :: STAT_ENABLE [08:08] */
#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_MASK 0x00000100
#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_SHIFT 8
#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DEFAULT 0x00000000
#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_ENABLE 1
#define BCHP_MEMC_DDR_0_STAT_CONTROL_STAT_ENABLE_DISABLE 0
/* MEMC_DDR_0 :: STAT_CONTROL :: CLIENT_ID [07:00] */
#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_MASK 0x000000ff
#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CONTROL_CLIENT_ID_DEFAULT 0x00000000
/***************************************************************************
*STAT_TIMER - Statistics Timer
***************************************************************************/
/* MEMC_DDR_0 :: STAT_TIMER :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_TIMER_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_IDLE_NOP :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_IDLE_NOP_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MAX_IDLE_NOP_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MIN_IDLE_NOP - Minimum DRAM idle_NOP cycle count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MIN_IDLE_NOP :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MIN_IDLE_NOP_COUNT_DEFAULT 0xffffffff
/***************************************************************************
*STAT_CAS_ALL - CAS Count Register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_ALL_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MAX_CAS_ALL_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MIN_CAS_ALL_COUNT_DEFAULT 0xffffffff
/***************************************************************************
*STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_PENALTY_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_PENALTY_ALL_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_PENALTY_GDDRWM - GDDR Write Mask Penalty Cycle Count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_PENALTY_GDDRWM :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_PENALTY_GDDRWM_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_PAGE_MERGE_ALL - Page Merge Event Count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_PAGE_MERGE_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_PAGE_MERGE_ALL_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_PAGE_MERGE_ALL_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_PAGE_MERGE_ALL_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT 0xffffffff
/***************************************************************************
*STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_TRANS_READ_ALL_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MAX_TRANS_ALL_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MIN_TRANS_ALL_COUNT_DEFAULT 0xffffffff
/***************************************************************************
*STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT 0xffffffff
/***************************************************************************
*STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CLIENT_SERVICE_GDDRWM_PENALTY - Service GDDR Write Mask Penalty Cycle Count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_GDDRWM_PENALTY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_GDDRWM_PENALTY_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CLIENT_SERVICE_PAGE_MERGES - Service Page Merge Event Count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_PAGE_MERGES :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_PAGE_MERGES_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_PAGE_MERGES_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_PAGE_MERGES_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0xffffffff
/***************************************************************************
*STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0xffffffff
/***************************************************************************
*STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
/***************************************************************************
*STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 0xffffffff
/***************************************************************************
*STAT_REFRESH - Total number of refreshes issued.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_REFRESH :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_REFRESH_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MIN_DQ_IDLE_WRITE - Min DQ Idle Write event counter
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MIN_DQ_IDLE_WRITE :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_WRITE_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_MIN_DQ_IDLE_READ - Min DQ Idle Read event counter
***************************************************************************/
/* MEMC_DDR_0 :: STAT_MIN_DQ_IDLE_READ :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_MIN_DQ_IDLE_READ_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_0 - CAS or consumption cycle count register for client 0.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_0_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_1 - CAS or consumption cycle count register for client 1.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_1_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_2 - CAS or consumption cycle count register for client 2.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_2_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_3 - CAS or consumption cycle count register for client 3.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_3_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_4 - CAS or consumption cycle count register for client 4.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_4_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_5 - CAS or consumption cycle count register for client 5.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_5_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_6 - CAS or consumption cycle count register for client 6.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_6_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_7 - CAS or consumption cycle count register for client 7.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_7_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_8 - CAS or consumption cycle count register for client 8.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_8_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_9 - CAS or consumption cycle count register for client 9.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_9_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_10 - CAS or consumption cycle count register for client 10.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_10_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_11 - CAS or consumption cycle count register for client 11.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_11_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_12 - CAS or consumption cycle count register for client 12.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_12_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_13 - CAS or consumption cycle count register for client 13.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_13_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_14 - CAS or consumption cycle count register for client 14.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_14_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_15 - CAS or consumption cycle count register for client 15.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_15_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_16 - CAS or consumption cycle count register for client 16.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_16_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_17 - CAS or consumption cycle count register for client 17.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_17_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_18 - CAS or consumption cycle count register for client 18.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_18_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_19 - CAS or consumption cycle count register for client 19.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_19_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_20 - CAS or consumption cycle count register for client 20.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_20_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_21 - CAS or consumption cycle count register for client 21.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_21_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_22 - CAS or consumption cycle count register for client 22.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_22_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_23 - CAS or consumption cycle count register for client 23.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_23_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_24 - CAS or consumption cycle count register for client 24.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_24_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_25 - CAS or consumption cycle count register for client 25.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_25_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_26 - CAS or consumption cycle count register for client 26.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_26_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_27 - CAS or consumption cycle count register for client 27.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_27_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_28 - CAS or consumption cycle count register for client 28.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_28_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_29 - CAS or consumption cycle count register for client 29.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_29_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_30 - CAS or consumption cycle count register for client 30.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_30_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_31 - CAS or consumption cycle count register for client 31.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_31_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_32 - CAS or consumption cycle count register for client 32.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_32_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_33 - CAS or consumption cycle count register for client 33.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_33_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_34 - CAS or consumption cycle count register for client 34.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_34_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_35 - CAS or consumption cycle count register for client 35.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_35_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_36 - CAS or consumption cycle count register for client 36.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_36_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_37 - CAS or consumption cycle count register for client 37.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_37_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_38 - CAS or consumption cycle count register for client 38.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_38_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_39 - CAS or consumption cycle count register for client 39.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_39_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_40 - CAS or consumption cycle count register for client 40.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_40_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_41 - CAS or consumption cycle count register for client 41.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_41_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_42 - CAS or consumption cycle count register for client 42.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_42_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_43 - CAS or consumption cycle count register for client 43.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_43_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_44 - CAS or consumption cycle count register for client 44.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_44_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_45 - CAS or consumption cycle count register for client 45.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_45_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_46 - CAS or consumption cycle count register for client 46.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_46_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_47 - CAS or consumption cycle count register for client 47.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_47_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_48 - CAS or consumption cycle count register for client 48.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_48_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_49 - CAS or consumption cycle count register for client 49.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_49_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_50 - CAS or consumption cycle count register for client 50.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_50_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_51 - CAS or consumption cycle count register for client 51.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_51_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_52 - CAS or consumption cycle count register for client 52.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_52_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_53 - CAS or consumption cycle count register for client 53.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_53_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_54 - CAS or consumption cycle count register for client 54.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_54_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_55 - CAS or consumption cycle count register for client 55.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_55_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_56 - CAS or consumption cycle count register for client 56.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_56_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_57 - CAS or consumption cycle count register for client 57.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_57_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_58 - CAS or consumption cycle count register for client 58.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_58_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_59 - CAS or consumption cycle count register for client 59.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_59_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_60 - CAS or consumption cycle count register for client 60.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_60_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_61 - CAS or consumption cycle count register for client 61.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_61_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_62 - CAS or consumption cycle count register for client 62.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_62_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_63 - CAS or consumption cycle count register for client 63.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_63_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_64 - CAS or consumption cycle count register for client 64.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_64_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_65 - CAS or consumption cycle count register for client 65.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_65_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_66 - CAS or consumption cycle count register for client 66.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_66_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_67 - CAS or consumption cycle count register for client 67.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_67_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_68 - CAS or consumption cycle count register for client 68.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_68_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_69 - CAS or consumption cycle count register for client 69.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_69_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_70 - CAS or consumption cycle count register for client 70.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_70_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_71 - CAS or consumption cycle count register for client 71.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_71_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_72 - CAS or consumption cycle count register for client 72.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_72_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_73 - CAS or consumption cycle count register for client 73.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_73_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_74 - CAS or consumption cycle count register for client 74.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_74_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_75 - CAS or consumption cycle count register for client 75.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_75_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_76 - CAS or consumption cycle count register for client 76.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_76_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_77 - CAS or consumption cycle count register for client 77.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_77_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_78 - CAS or consumption cycle count register for client 78.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_78_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_79 - CAS or consumption cycle count register for client 79.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_79_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_80 - CAS or consumption cycle count register for client 80.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_80_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_81 - CAS or consumption cycle count register for client 81.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_81_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_82 - CAS or consumption cycle count register for client 82.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_82_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_83 - CAS or consumption cycle count register for client 83.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_83_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_84 - CAS or consumption cycle count register for client 84.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_84_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_85 - CAS or consumption cycle count register for client 85.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_85_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_86 - CAS or consumption cycle count register for client 86.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_86_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_87 - CAS or consumption cycle count register for client 87.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_87_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_88 - CAS or consumption cycle count register for client 88.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_88_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_89 - CAS or consumption cycle count register for client 89.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_89_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_90 - CAS or consumption cycle count register for client 90.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_90_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_91 - CAS or consumption cycle count register for client 91.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_91_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_92 - CAS or consumption cycle count register for client 92.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_92_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_93 - CAS or consumption cycle count register for client 93.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_93_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_94 - CAS or consumption cycle count register for client 94.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_94_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_95 - CAS or consumption cycle count register for client 95.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_95_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_96 - CAS or consumption cycle count register for client 96.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_96_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_97 - CAS or consumption cycle count register for client 97.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_97_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_98 - CAS or consumption cycle count register for client 98.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_98_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_99 - CAS or consumption cycle count register for client 99.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_99_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_100 - CAS or consumption cycle count register for client 100.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_100_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_101 - CAS or consumption cycle count register for client 101.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_101_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_102 - CAS or consumption cycle count register for client 102.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_102_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_103 - CAS or consumption cycle count register for client 103.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_103_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_104 - CAS or consumption cycle count register for client 104.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_104_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_105 - CAS or consumption cycle count register for client 105.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_105_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_106 - CAS or consumption cycle count register for client 106.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_106_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_107 - CAS or consumption cycle count register for client 107.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_107_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_108 - CAS or consumption cycle count register for client 108.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_108_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_109 - CAS or consumption cycle count register for client 109.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_109_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_110 - CAS or consumption cycle count register for client 110.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_110_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_111 - CAS or consumption cycle count register for client 111.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_111_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_112 - CAS or consumption cycle count register for client 112.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_112_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_113 - CAS or consumption cycle count register for client 113.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_113_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_114 - CAS or consumption cycle count register for client 114.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_114_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_115 - CAS or consumption cycle count register for client 115.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_115_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_116 - CAS or consumption cycle count register for client 116.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_116_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_117 - CAS or consumption cycle count register for client 117.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_117_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_118 - CAS or consumption cycle count register for client 118.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_118_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_119 - CAS or consumption cycle count register for client 119.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_119_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_120 - CAS or consumption cycle count register for client 120.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_120_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_121 - CAS or consumption cycle count register for client 121.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_121_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_122 - CAS or consumption cycle count register for client 122.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_122_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_123 - CAS or consumption cycle count register for client 123.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_123_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_124 - CAS or consumption cycle count register for client 124.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_124_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_125 - CAS or consumption cycle count register for client 125.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_125_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_126 - CAS or consumption cycle count register for client 126.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_126_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_127 - CAS or consumption cycle count register for client 127.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_127_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_128 - CAS or consumption cycle count register for client 128.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_128 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_128_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_129 - CAS or consumption cycle count register for client 129.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_129 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_129_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_130 - CAS or consumption cycle count register for client 130.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_130 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_130_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_131 - CAS or consumption cycle count register for client 131.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_131 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_131_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_132 - CAS or consumption cycle count register for client 132.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_132 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_132_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_133 - CAS or consumption cycle count register for client 133.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_133 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_133_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_134 - CAS or consumption cycle count register for client 134.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_134 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_134_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_135 - CAS or consumption cycle count register for client 135.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_135 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_135_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_136 - CAS or consumption cycle count register for client 136.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_136 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_136_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_137 - CAS or consumption cycle count register for client 137.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_137 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_137_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_138 - CAS or consumption cycle count register for client 138.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_138 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_138_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_139 - CAS or consumption cycle count register for client 139.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_139 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_139_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_140 - CAS or consumption cycle count register for client 140.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_140 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_140_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_141 - CAS or consumption cycle count register for client 141.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_141 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_141_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_142 - CAS or consumption cycle count register for client 142.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_142 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_142_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_143 - CAS or consumption cycle count register for client 143.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_143 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_143_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_144 - CAS or consumption cycle count register for client 144.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_144 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_144_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_145 - CAS or consumption cycle count register for client 145.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_145 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_145_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_146 - CAS or consumption cycle count register for client 146.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_146 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_146_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_147 - CAS or consumption cycle count register for client 147.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_147 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_147_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_148 - CAS or consumption cycle count register for client 148.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_148 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_148_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_149 - CAS or consumption cycle count register for client 149.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_149 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_149_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_150 - CAS or consumption cycle count register for client 150.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_150 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_150_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_151 - CAS or consumption cycle count register for client 151.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_151 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_151_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_152 - CAS or consumption cycle count register for client 152.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_152 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_152_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_153 - CAS or consumption cycle count register for client 153.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_153 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_153_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_154 - CAS or consumption cycle count register for client 154.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_154 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_154_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_155 - CAS or consumption cycle count register for client 155.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_155 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_155_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_156 - CAS or consumption cycle count register for client 156.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_156 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_156_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_157 - CAS or consumption cycle count register for client 157.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_157 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_157_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_158 - CAS or consumption cycle count register for client 158.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_158 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_158_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_159 - CAS or consumption cycle count register for client 159.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_159 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_159_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_160 - CAS or consumption cycle count register for client 160.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_160 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_160_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_161 - CAS or consumption cycle count register for client 161.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_161 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_161_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_162 - CAS or consumption cycle count register for client 162.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_162 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_162_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_163 - CAS or consumption cycle count register for client 163.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_163 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_163_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_164 - CAS or consumption cycle count register for client 164.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_164 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_164_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_165 - CAS or consumption cycle count register for client 165.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_165 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_165_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_166 - CAS or consumption cycle count register for client 166.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_166 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_166_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_167 - CAS or consumption cycle count register for client 167.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_167 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_167_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_168 - CAS or consumption cycle count register for client 168.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_168 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_168_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_169 - CAS or consumption cycle count register for client 169.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_169 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_169_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_170 - CAS or consumption cycle count register for client 170.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_170 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_170_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_171 - CAS or consumption cycle count register for client 171.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_171 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_171_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_172 - CAS or consumption cycle count register for client 172.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_172 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_172_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_173 - CAS or consumption cycle count register for client 173.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_173 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_173_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_174 - CAS or consumption cycle count register for client 174.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_174 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_174_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_175 - CAS or consumption cycle count register for client 175.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_175 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_175_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_176 - CAS or consumption cycle count register for client 176.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_176 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_176_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_177 - CAS or consumption cycle count register for client 177.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_177 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_177_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_178 - CAS or consumption cycle count register for client 178.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_178 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_178_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_179 - CAS or consumption cycle count register for client 179.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_179 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_179_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_180 - CAS or consumption cycle count register for client 180.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_180 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_180_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_181 - CAS or consumption cycle count register for client 181.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_181 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_181_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_182 - CAS or consumption cycle count register for client 182.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_182 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_182_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_183 - CAS or consumption cycle count register for client 183.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_183 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_183_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_184 - CAS or consumption cycle count register for client 184.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_184 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_184_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_185 - CAS or consumption cycle count register for client 185.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_185 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_185_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_186 - CAS or consumption cycle count register for client 186.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_186 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_186_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_187 - CAS or consumption cycle count register for client 187.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_187 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_187_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_188 - CAS or consumption cycle count register for client 188.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_188 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_188_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_189 - CAS or consumption cycle count register for client 189.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_189 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_189_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_190 - CAS or consumption cycle count register for client 190.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_190 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_190_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_191 - CAS or consumption cycle count register for client 191.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_191 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_191_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_192 - CAS or consumption cycle count register for client 192.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_192 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_192_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_193 - CAS or consumption cycle count register for client 193.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_193 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_193_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_194 - CAS or consumption cycle count register for client 194.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_194 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_194_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_195 - CAS or consumption cycle count register for client 195.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_195 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_195_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_196 - CAS or consumption cycle count register for client 196.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_196 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_196_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_197 - CAS or consumption cycle count register for client 197.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_197 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_197_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_198 - CAS or consumption cycle count register for client 198.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_198 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_198_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_199 - CAS or consumption cycle count register for client 199.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_199 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_199_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_200 - CAS or consumption cycle count register for client 200.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_200 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_200_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_201 - CAS or consumption cycle count register for client 201.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_201 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_201_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_202 - CAS or consumption cycle count register for client 202.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_202 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_202_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_203 - CAS or consumption cycle count register for client 203.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_203 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_203_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_204 - CAS or consumption cycle count register for client 204.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_204 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_204_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_205 - CAS or consumption cycle count register for client 205.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_205 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_205_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_206 - CAS or consumption cycle count register for client 206.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_206 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_206_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_207 - CAS or consumption cycle count register for client 207.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_207 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_207_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_208 - CAS or consumption cycle count register for client 208.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_208 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_208_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_209 - CAS or consumption cycle count register for client 209.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_209 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_209_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_210 - CAS or consumption cycle count register for client 210.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_210 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_210_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_211 - CAS or consumption cycle count register for client 211.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_211 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_211_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_212 - CAS or consumption cycle count register for client 212.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_212 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_212_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_213 - CAS or consumption cycle count register for client 213.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_213 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_213_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_214 - CAS or consumption cycle count register for client 214.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_214 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_214_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_215 - CAS or consumption cycle count register for client 215.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_215 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_215_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_216 - CAS or consumption cycle count register for client 216.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_216 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_216_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_217 - CAS or consumption cycle count register for client 217.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_217 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_217_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_218 - CAS or consumption cycle count register for client 218.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_218 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_218_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_219 - CAS or consumption cycle count register for client 219.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_219 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_219_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_220 - CAS or consumption cycle count register for client 220.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_220 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_220_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_221 - CAS or consumption cycle count register for client 221.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_221 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_221_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_222 - CAS or consumption cycle count register for client 222.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_222 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_222_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_223 - CAS or consumption cycle count register for client 223.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_223 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_223_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_224 - CAS or consumption cycle count register for client 224.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_224 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_224_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_225 - CAS or consumption cycle count register for client 225.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_225 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_225_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_226 - CAS or consumption cycle count register for client 226.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_226 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_226_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_227 - CAS or consumption cycle count register for client 227.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_227 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_227_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_228 - CAS or consumption cycle count register for client 228.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_228 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_228_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_229 - CAS or consumption cycle count register for client 229.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_229 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_229_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_230 - CAS or consumption cycle count register for client 230.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_230 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_230_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_231 - CAS or consumption cycle count register for client 231.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_231 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_231_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_232 - CAS or consumption cycle count register for client 232.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_232 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_232_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_233 - CAS or consumption cycle count register for client 233.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_233 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_233_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_234 - CAS or consumption cycle count register for client 234.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_234 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_234_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_235 - CAS or consumption cycle count register for client 235.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_235 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_235_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_236 - CAS or consumption cycle count register for client 236.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_236 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_236_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_237 - CAS or consumption cycle count register for client 237.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_237 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_237_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_238 - CAS or consumption cycle count register for client 238.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_238 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_238_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_239 - CAS or consumption cycle count register for client 239.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_239 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_239_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_240 - CAS or consumption cycle count register for client 240.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_240 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_240_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_241 - CAS or consumption cycle count register for client 241.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_241 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_241_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_242 - CAS or consumption cycle count register for client 242.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_242 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_242_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_243 - CAS or consumption cycle count register for client 243.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_243 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_243_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_244 - CAS or consumption cycle count register for client 244.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_244 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_244_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_245 - CAS or consumption cycle count register for client 245.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_245 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_245_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_246 - CAS or consumption cycle count register for client 246.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_246 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_246_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_247 - CAS or consumption cycle count register for client 247.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_247 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_247_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_248 - CAS or consumption cycle count register for client 248.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_248 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_248_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_249 - CAS or consumption cycle count register for client 249.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_249 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_249_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_250 - CAS or consumption cycle count register for client 250.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_250 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_250_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_251 - CAS or consumption cycle count register for client 251.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_251 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_251_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_252 - CAS or consumption cycle count register for client 252.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_252 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_252_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_253 - CAS or consumption cycle count register for client 253.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_253 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_253_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_254 - CAS or consumption cycle count register for client 254.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_254 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_254_COUNT_DEFAULT 0x00000000
/***************************************************************************
*STAT_CAS_CLIENT_255 - CAS or consumption cycle count register for client 255.
***************************************************************************/
/* MEMC_DDR_0 :: STAT_CAS_CLIENT_255 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_0_STAT_CAS_CLIENT_255_COUNT_DEFAULT 0x00000000
#endif /* #ifndef BCHP_MEMC_DDR_0_H__ */
/* End of File */