/***************************************************************************
 *     Copyright (c) 1999-2013, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Wed May  8 03:09:25 2013
 *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_SWITCH_INTRL2_1_H__
#define BCHP_SWITCH_INTRL2_1_H__

/***************************************************************************
 *SWITCH_INTRL2_1
 ***************************************************************************/
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS          0x04e40380 /* CPU interrupt Status Register */
#define BCHP_SWITCH_INTRL2_1_CPU_SET             0x04e40384 /* CPU interrupt Set Register */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR           0x04e40388 /* CPU interrupt Clear Register */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS     0x04e4038c /* CPU interrupt Mask Status Register */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET        0x04e40390 /* CPU interrupt Mask Set Register */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR      0x04e40394 /* CPU interrupt Mask Clear Register */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS          0x04e40398 /* PCI interrupt Status Register */
#define BCHP_SWITCH_INTRL2_1_PCI_SET             0x04e4039c /* PCI interrupt Set Register */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR           0x04e403a0 /* PCI interrupt Clear Register */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS     0x04e403a4 /* PCI interrupt Mask Status Register */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET        0x04e403a8 /* PCI interrupt Mask Set Register */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR      0x04e403ac /* PCI interrupt Mask Clear Register */

/***************************************************************************
 *CPU_STATUS - CPU interrupt Status Register
 ***************************************************************************/
/* SWITCH_INTRL2_1 :: CPU_STATUS :: reserved0 [31:30] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_reserved0_MASK             0xc0000000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_reserved0_SHIFT            30

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_gphy_intr [29:29] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_gphy_intr_MASK          0x20000000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_gphy_intr_SHIFT         29
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_energy_off_intr [28:28] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_off_intr_MASK    0x10000000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_off_intr_SHIFT   28
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_energy_on_intr [27:27] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_on_intr_MASK     0x08000000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_on_intr_SHIFT    27
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_link_down_intr [26:26] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_down_intr_MASK     0x04000000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_down_intr_SHIFT    26
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p1_link_up_intr [25:25] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_up_intr_MASK       0x02000000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_up_intr_SHIFT      25
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p1_link_up_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_gphy_intr [24:24] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_gphy_intr_MASK          0x01000000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_gphy_intr_SHIFT         24
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_energy_off_intr [23:23] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_off_intr_MASK    0x00800000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_off_intr_SHIFT   23
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_energy_on_intr [22:22] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_on_intr_MASK     0x00400000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_on_intr_SHIFT    22
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_link_down_intr [21:21] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_down_intr_MASK     0x00200000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_down_intr_SHIFT    21
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p2_link_up_intr [20:20] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_up_intr_MASK       0x00100000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_up_intr_SHIFT      20
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p2_link_up_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_gphy_intr [19:19] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_gphy_intr_MASK          0x00080000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_gphy_intr_SHIFT         19
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_energy_off_intr [18:18] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_off_intr_MASK    0x00040000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_off_intr_SHIFT   18
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_energy_on_intr [17:17] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_on_intr_MASK     0x00020000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_on_intr_SHIFT    17
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_link_down_intr [16:16] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_down_intr_MASK     0x00010000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_down_intr_SHIFT    16
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p3_link_up_intr [15:15] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_up_intr_MASK       0x00008000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_up_intr_SHIFT      15
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p3_link_up_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_gphy_intr [14:14] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_gphy_intr_MASK          0x00004000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_gphy_intr_SHIFT         14
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_energy_off_intr [13:13] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_off_intr_MASK    0x00002000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_off_intr_SHIFT   13
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_energy_on_intr [12:12] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_on_intr_MASK     0x00001000
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_on_intr_SHIFT    12
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_link_down_intr [11:11] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_down_intr_MASK     0x00000800
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_down_intr_SHIFT    11
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p4_link_up_intr [10:10] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_up_intr_MASK       0x00000400
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_up_intr_SHIFT      10
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p4_link_up_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_gphy_intr [09:09] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_gphy_intr_MASK          0x00000200
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_gphy_intr_SHIFT         9
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_energy_off_intr [08:08] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_off_intr_MASK    0x00000100
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_off_intr_SHIFT   8
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_energy_on_intr [07:07] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_on_intr_MASK     0x00000080
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_on_intr_SHIFT    7
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_link_down_intr [06:06] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_down_intr_MASK     0x00000040
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_down_intr_SHIFT    6
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p5_link_up_intr [05:05] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_up_intr_MASK       0x00000020
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_up_intr_SHIFT      5
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p5_link_up_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_gphy_intr [04:04] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_gphy_intr_MASK          0x00000010
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_gphy_intr_SHIFT         4
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_energy_off_intr [03:03] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_off_intr_MASK    0x00000008
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_off_intr_SHIFT   3
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_energy_on_intr [02:02] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_on_intr_MASK     0x00000004
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_on_intr_SHIFT    2
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_link_down_intr [01:01] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_down_intr_MASK     0x00000002
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_down_intr_SHIFT    1
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_STATUS :: p7_link_up_intr [00:00] */
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_up_intr_MASK       0x00000001
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_up_intr_SHIFT      0
#define BCHP_SWITCH_INTRL2_1_CPU_STATUS_p7_link_up_intr_DEFAULT    0x00000000

/***************************************************************************
 *CPU_SET - CPU interrupt Set Register
 ***************************************************************************/
/* SWITCH_INTRL2_1 :: CPU_SET :: reserved0 [31:30] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_reserved0_MASK                0xc0000000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_reserved0_SHIFT               30

/* SWITCH_INTRL2_1 :: CPU_SET :: p1_gphy_intr [29:29] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_gphy_intr_MASK             0x20000000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_gphy_intr_SHIFT            29
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p1_energy_off_intr [28:28] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_off_intr_MASK       0x10000000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_off_intr_SHIFT      28
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p1_energy_on_intr [27:27] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_on_intr_MASK        0x08000000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_on_intr_SHIFT       27
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p1_link_down_intr [26:26] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_down_intr_MASK        0x04000000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_down_intr_SHIFT       26
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p1_link_up_intr [25:25] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_up_intr_MASK          0x02000000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_up_intr_SHIFT         25
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p1_link_up_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p2_gphy_intr [24:24] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_gphy_intr_MASK             0x01000000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_gphy_intr_SHIFT            24
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p2_energy_off_intr [23:23] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_off_intr_MASK       0x00800000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_off_intr_SHIFT      23
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p2_energy_on_intr [22:22] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_on_intr_MASK        0x00400000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_on_intr_SHIFT       22
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p2_link_down_intr [21:21] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_down_intr_MASK        0x00200000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_down_intr_SHIFT       21
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p2_link_up_intr [20:20] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_up_intr_MASK          0x00100000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_up_intr_SHIFT         20
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p2_link_up_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p3_gphy_intr [19:19] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_gphy_intr_MASK             0x00080000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_gphy_intr_SHIFT            19
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p3_energy_off_intr [18:18] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_off_intr_MASK       0x00040000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_off_intr_SHIFT      18
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p3_energy_on_intr [17:17] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_on_intr_MASK        0x00020000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_on_intr_SHIFT       17
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p3_link_down_intr [16:16] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_down_intr_MASK        0x00010000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_down_intr_SHIFT       16
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p3_link_up_intr [15:15] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_up_intr_MASK          0x00008000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_up_intr_SHIFT         15
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p3_link_up_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p4_gphy_intr [14:14] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_gphy_intr_MASK             0x00004000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_gphy_intr_SHIFT            14
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p4_energy_off_intr [13:13] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_off_intr_MASK       0x00002000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_off_intr_SHIFT      13
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p4_energy_on_intr [12:12] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_on_intr_MASK        0x00001000
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_on_intr_SHIFT       12
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p4_link_down_intr [11:11] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_down_intr_MASK        0x00000800
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_down_intr_SHIFT       11
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p4_link_up_intr [10:10] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_up_intr_MASK          0x00000400
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_up_intr_SHIFT         10
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p4_link_up_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p5_gphy_intr [09:09] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_gphy_intr_MASK             0x00000200
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_gphy_intr_SHIFT            9
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p5_energy_off_intr [08:08] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_off_intr_MASK       0x00000100
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_off_intr_SHIFT      8
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p5_energy_on_intr [07:07] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_on_intr_MASK        0x00000080
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_on_intr_SHIFT       7
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p5_link_down_intr [06:06] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_down_intr_MASK        0x00000040
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_down_intr_SHIFT       6
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p5_link_up_intr [05:05] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_up_intr_MASK          0x00000020
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_up_intr_SHIFT         5
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p5_link_up_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p7_gphy_intr [04:04] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_gphy_intr_MASK             0x00000010
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_gphy_intr_SHIFT            4
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p7_energy_off_intr [03:03] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_off_intr_MASK       0x00000008
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_off_intr_SHIFT      3
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p7_energy_on_intr [02:02] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_on_intr_MASK        0x00000004
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_on_intr_SHIFT       2
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p7_link_down_intr [01:01] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_down_intr_MASK        0x00000002
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_down_intr_SHIFT       1
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_SET :: p7_link_up_intr [00:00] */
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_up_intr_MASK          0x00000001
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_up_intr_SHIFT         0
#define BCHP_SWITCH_INTRL2_1_CPU_SET_p7_link_up_intr_DEFAULT       0x00000000

/***************************************************************************
 *CPU_CLEAR - CPU interrupt Clear Register
 ***************************************************************************/
/* SWITCH_INTRL2_1 :: CPU_CLEAR :: reserved0 [31:30] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_reserved0_MASK              0xc0000000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_reserved0_SHIFT             30

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_gphy_intr [29:29] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_gphy_intr_MASK           0x20000000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_gphy_intr_SHIFT          29
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_energy_off_intr [28:28] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_off_intr_MASK     0x10000000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_off_intr_SHIFT    28
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_energy_on_intr [27:27] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_on_intr_MASK      0x08000000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_on_intr_SHIFT     27
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_link_down_intr [26:26] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_down_intr_MASK      0x04000000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_down_intr_SHIFT     26
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p1_link_up_intr [25:25] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_up_intr_MASK        0x02000000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_up_intr_SHIFT       25
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p1_link_up_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_gphy_intr [24:24] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_gphy_intr_MASK           0x01000000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_gphy_intr_SHIFT          24
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_energy_off_intr [23:23] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_off_intr_MASK     0x00800000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_off_intr_SHIFT    23
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_energy_on_intr [22:22] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_on_intr_MASK      0x00400000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_on_intr_SHIFT     22
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_link_down_intr [21:21] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_down_intr_MASK      0x00200000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_down_intr_SHIFT     21
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p2_link_up_intr [20:20] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_up_intr_MASK        0x00100000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_up_intr_SHIFT       20
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p2_link_up_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_gphy_intr [19:19] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_gphy_intr_MASK           0x00080000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_gphy_intr_SHIFT          19
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_energy_off_intr [18:18] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_off_intr_MASK     0x00040000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_off_intr_SHIFT    18
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_energy_on_intr [17:17] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_on_intr_MASK      0x00020000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_on_intr_SHIFT     17
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_link_down_intr [16:16] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_down_intr_MASK      0x00010000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_down_intr_SHIFT     16
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p3_link_up_intr [15:15] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_up_intr_MASK        0x00008000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_up_intr_SHIFT       15
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p3_link_up_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_gphy_intr [14:14] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_gphy_intr_MASK           0x00004000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_gphy_intr_SHIFT          14
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_energy_off_intr [13:13] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_off_intr_MASK     0x00002000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_off_intr_SHIFT    13
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_energy_on_intr [12:12] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_on_intr_MASK      0x00001000
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_on_intr_SHIFT     12
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_link_down_intr [11:11] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_down_intr_MASK      0x00000800
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_down_intr_SHIFT     11
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p4_link_up_intr [10:10] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_up_intr_MASK        0x00000400
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_up_intr_SHIFT       10
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p4_link_up_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_gphy_intr [09:09] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_gphy_intr_MASK           0x00000200
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_gphy_intr_SHIFT          9
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_energy_off_intr [08:08] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_off_intr_MASK     0x00000100
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_off_intr_SHIFT    8
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_energy_on_intr [07:07] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_on_intr_MASK      0x00000080
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_on_intr_SHIFT     7
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_link_down_intr [06:06] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_down_intr_MASK      0x00000040
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_down_intr_SHIFT     6
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p5_link_up_intr [05:05] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_up_intr_MASK        0x00000020
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_up_intr_SHIFT       5
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p5_link_up_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_gphy_intr [04:04] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_gphy_intr_MASK           0x00000010
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_gphy_intr_SHIFT          4
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_energy_off_intr [03:03] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_off_intr_MASK     0x00000008
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_off_intr_SHIFT    3
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_energy_on_intr [02:02] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_on_intr_MASK      0x00000004
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_on_intr_SHIFT     2
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_link_down_intr [01:01] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_down_intr_MASK      0x00000002
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_down_intr_SHIFT     1
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: CPU_CLEAR :: p7_link_up_intr [00:00] */
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_up_intr_MASK        0x00000001
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_up_intr_SHIFT       0
#define BCHP_SWITCH_INTRL2_1_CPU_CLEAR_p7_link_up_intr_DEFAULT     0x00000000

/***************************************************************************
 *CPU_MASK_STATUS - CPU interrupt Mask Status Register
 ***************************************************************************/
/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: reserved0 [31:30] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_reserved0_MASK        0xc0000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_reserved0_SHIFT       30

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_gphy_intr_mask [29:29] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_gphy_intr_mask_MASK 0x20000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_gphy_intr_mask_SHIFT 29
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_energy_off_intr_mask [28:28] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_off_intr_mask_MASK 0x10000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_off_intr_mask_SHIFT 28
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_energy_on_intr_mask [27:27] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_on_intr_mask_MASK 0x08000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_on_intr_mask_SHIFT 27
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_link_down_intr_mask [26:26] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_down_intr_mask_MASK 0x04000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_down_intr_mask_SHIFT 26
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p1_link_up_intr_mask [25:25] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_up_intr_mask_MASK 0x02000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_up_intr_mask_SHIFT 25
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p1_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_gphy_intr_mask [24:24] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_gphy_intr_mask_MASK 0x01000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_gphy_intr_mask_SHIFT 24
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_energy_off_intr_mask [23:23] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_off_intr_mask_MASK 0x00800000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_off_intr_mask_SHIFT 23
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_energy_on_intr_mask [22:22] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_on_intr_mask_MASK 0x00400000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_on_intr_mask_SHIFT 22
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_link_down_intr_mask [21:21] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_down_intr_mask_MASK 0x00200000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_down_intr_mask_SHIFT 21
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p2_link_up_intr_mask [20:20] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_up_intr_mask_MASK 0x00100000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_up_intr_mask_SHIFT 20
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p2_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_gphy_intr_mask [19:19] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_gphy_intr_mask_MASK 0x00080000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_gphy_intr_mask_SHIFT 19
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_energy_off_intr_mask [18:18] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_off_intr_mask_MASK 0x00040000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_off_intr_mask_SHIFT 18
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_energy_on_intr_mask [17:17] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_on_intr_mask_MASK 0x00020000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_on_intr_mask_SHIFT 17
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_link_down_intr_mask [16:16] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_down_intr_mask_MASK 0x00010000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_down_intr_mask_SHIFT 16
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p3_link_up_intr_mask [15:15] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_up_intr_mask_MASK 0x00008000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_up_intr_mask_SHIFT 15
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p3_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_gphy_intr_mask [14:14] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_gphy_intr_mask_MASK 0x00004000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_gphy_intr_mask_SHIFT 14
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_energy_off_intr_mask [13:13] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_off_intr_mask_MASK 0x00002000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_off_intr_mask_SHIFT 13
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_energy_on_intr_mask [12:12] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_on_intr_mask_MASK 0x00001000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_on_intr_mask_SHIFT 12
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_link_down_intr_mask [11:11] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_down_intr_mask_MASK 0x00000800
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_down_intr_mask_SHIFT 11
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p4_link_up_intr_mask [10:10] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_up_intr_mask_MASK 0x00000400
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_up_intr_mask_SHIFT 10
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p4_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_gphy_intr_mask [09:09] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_gphy_intr_mask_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_gphy_intr_mask_SHIFT 9
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_energy_off_intr_mask [08:08] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_off_intr_mask_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_off_intr_mask_SHIFT 8
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_energy_on_intr_mask [07:07] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_on_intr_mask_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_on_intr_mask_SHIFT 7
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_link_down_intr_mask [06:06] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_down_intr_mask_MASK 0x00000040
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_down_intr_mask_SHIFT 6
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p5_link_up_intr_mask [05:05] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_up_intr_mask_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_up_intr_mask_SHIFT 5
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p5_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_gphy_intr_mask [04:04] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_gphy_intr_mask_MASK 0x00000010
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_gphy_intr_mask_SHIFT 4
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_energy_off_intr_mask [03:03] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_off_intr_mask_MASK 0x00000008
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_off_intr_mask_SHIFT 3
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_energy_on_intr_mask [02:02] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_on_intr_mask_MASK 0x00000004
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_on_intr_mask_SHIFT 2
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_link_down_intr_mask [01:01] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_down_intr_mask_MASK 0x00000002
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_down_intr_mask_SHIFT 1
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_STATUS :: p7_link_up_intr_mask [00:00] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_up_intr_mask_MASK 0x00000001
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_up_intr_mask_SHIFT 0
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_STATUS_p7_link_up_intr_mask_DEFAULT 0x00000001

/***************************************************************************
 *CPU_MASK_SET - CPU interrupt Mask Set Register
 ***************************************************************************/
/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: reserved0 [31:30] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_reserved0_MASK           0xc0000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_reserved0_SHIFT          30

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_gphy_intr_mask [29:29] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_gphy_intr_mask_MASK   0x20000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_gphy_intr_mask_SHIFT  29
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_energy_off_intr_mask [28:28] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_off_intr_mask_MASK 0x10000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_off_intr_mask_SHIFT 28
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_energy_on_intr_mask [27:27] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_on_intr_mask_MASK 0x08000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_on_intr_mask_SHIFT 27
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_link_down_intr_mask [26:26] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_down_intr_mask_MASK 0x04000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_down_intr_mask_SHIFT 26
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p1_link_up_intr_mask [25:25] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_up_intr_mask_MASK 0x02000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_up_intr_mask_SHIFT 25
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p1_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_gphy_intr_mask [24:24] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_gphy_intr_mask_MASK   0x01000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_gphy_intr_mask_SHIFT  24
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_energy_off_intr_mask [23:23] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_off_intr_mask_MASK 0x00800000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_off_intr_mask_SHIFT 23
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_energy_on_intr_mask [22:22] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_on_intr_mask_MASK 0x00400000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_on_intr_mask_SHIFT 22
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_link_down_intr_mask [21:21] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_down_intr_mask_MASK 0x00200000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_down_intr_mask_SHIFT 21
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p2_link_up_intr_mask [20:20] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_up_intr_mask_MASK 0x00100000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_up_intr_mask_SHIFT 20
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p2_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_gphy_intr_mask [19:19] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_gphy_intr_mask_MASK   0x00080000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_gphy_intr_mask_SHIFT  19
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_energy_off_intr_mask [18:18] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_off_intr_mask_MASK 0x00040000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_off_intr_mask_SHIFT 18
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_energy_on_intr_mask [17:17] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_on_intr_mask_MASK 0x00020000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_on_intr_mask_SHIFT 17
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_link_down_intr_mask [16:16] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_down_intr_mask_MASK 0x00010000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_down_intr_mask_SHIFT 16
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p3_link_up_intr_mask [15:15] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_up_intr_mask_MASK 0x00008000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_up_intr_mask_SHIFT 15
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p3_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_gphy_intr_mask [14:14] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_gphy_intr_mask_MASK   0x00004000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_gphy_intr_mask_SHIFT  14
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_energy_off_intr_mask [13:13] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_off_intr_mask_MASK 0x00002000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_off_intr_mask_SHIFT 13
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_energy_on_intr_mask [12:12] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_on_intr_mask_MASK 0x00001000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_on_intr_mask_SHIFT 12
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_link_down_intr_mask [11:11] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_down_intr_mask_MASK 0x00000800
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_down_intr_mask_SHIFT 11
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p4_link_up_intr_mask [10:10] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_up_intr_mask_MASK 0x00000400
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_up_intr_mask_SHIFT 10
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p4_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_gphy_intr_mask [09:09] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_gphy_intr_mask_MASK   0x00000200
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_gphy_intr_mask_SHIFT  9
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_energy_off_intr_mask [08:08] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_off_intr_mask_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_off_intr_mask_SHIFT 8
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_energy_on_intr_mask [07:07] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_on_intr_mask_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_on_intr_mask_SHIFT 7
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_link_down_intr_mask [06:06] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_down_intr_mask_MASK 0x00000040
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_down_intr_mask_SHIFT 6
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p5_link_up_intr_mask [05:05] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_up_intr_mask_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_up_intr_mask_SHIFT 5
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p5_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_gphy_intr_mask [04:04] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_gphy_intr_mask_MASK   0x00000010
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_gphy_intr_mask_SHIFT  4
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_energy_off_intr_mask [03:03] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_off_intr_mask_MASK 0x00000008
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_off_intr_mask_SHIFT 3
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_energy_on_intr_mask [02:02] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_on_intr_mask_MASK 0x00000004
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_on_intr_mask_SHIFT 2
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_link_down_intr_mask [01:01] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_down_intr_mask_MASK 0x00000002
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_down_intr_mask_SHIFT 1
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_SET :: p7_link_up_intr_mask [00:00] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_up_intr_mask_MASK 0x00000001
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_up_intr_mask_SHIFT 0
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_SET_p7_link_up_intr_mask_DEFAULT 0x00000001

/***************************************************************************
 *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
 ***************************************************************************/
/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: reserved0 [31:30] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_reserved0_MASK         0xc0000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_reserved0_SHIFT        30

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_gphy_intr_mask [29:29] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_gphy_intr_mask_MASK 0x20000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_gphy_intr_mask_SHIFT 29
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_energy_off_intr_mask [28:28] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_off_intr_mask_MASK 0x10000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_off_intr_mask_SHIFT 28
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_energy_on_intr_mask [27:27] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_on_intr_mask_MASK 0x08000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_on_intr_mask_SHIFT 27
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_link_down_intr_mask [26:26] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_down_intr_mask_MASK 0x04000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_down_intr_mask_SHIFT 26
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p1_link_up_intr_mask [25:25] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_up_intr_mask_MASK 0x02000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_up_intr_mask_SHIFT 25
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p1_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_gphy_intr_mask [24:24] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_gphy_intr_mask_MASK 0x01000000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_gphy_intr_mask_SHIFT 24
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_energy_off_intr_mask [23:23] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_off_intr_mask_MASK 0x00800000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_off_intr_mask_SHIFT 23
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_energy_on_intr_mask [22:22] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_on_intr_mask_MASK 0x00400000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_on_intr_mask_SHIFT 22
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_link_down_intr_mask [21:21] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_down_intr_mask_MASK 0x00200000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_down_intr_mask_SHIFT 21
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p2_link_up_intr_mask [20:20] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_up_intr_mask_MASK 0x00100000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_up_intr_mask_SHIFT 20
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p2_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_gphy_intr_mask [19:19] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_gphy_intr_mask_MASK 0x00080000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_gphy_intr_mask_SHIFT 19
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_energy_off_intr_mask [18:18] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_off_intr_mask_MASK 0x00040000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_off_intr_mask_SHIFT 18
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_energy_on_intr_mask [17:17] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_on_intr_mask_MASK 0x00020000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_on_intr_mask_SHIFT 17
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_link_down_intr_mask [16:16] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_down_intr_mask_MASK 0x00010000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_down_intr_mask_SHIFT 16
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p3_link_up_intr_mask [15:15] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_up_intr_mask_MASK 0x00008000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_up_intr_mask_SHIFT 15
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p3_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_gphy_intr_mask [14:14] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_gphy_intr_mask_MASK 0x00004000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_gphy_intr_mask_SHIFT 14
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_energy_off_intr_mask [13:13] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_off_intr_mask_MASK 0x00002000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_off_intr_mask_SHIFT 13
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_energy_on_intr_mask [12:12] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_on_intr_mask_MASK 0x00001000
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_on_intr_mask_SHIFT 12
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_link_down_intr_mask [11:11] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_down_intr_mask_MASK 0x00000800
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_down_intr_mask_SHIFT 11
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p4_link_up_intr_mask [10:10] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_up_intr_mask_MASK 0x00000400
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_up_intr_mask_SHIFT 10
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p4_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_gphy_intr_mask [09:09] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_gphy_intr_mask_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_gphy_intr_mask_SHIFT 9
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_energy_off_intr_mask [08:08] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_off_intr_mask_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_off_intr_mask_SHIFT 8
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_energy_on_intr_mask [07:07] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_on_intr_mask_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_on_intr_mask_SHIFT 7
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_link_down_intr_mask [06:06] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_down_intr_mask_MASK 0x00000040
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_down_intr_mask_SHIFT 6
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p5_link_up_intr_mask [05:05] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_up_intr_mask_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_up_intr_mask_SHIFT 5
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p5_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_gphy_intr_mask [04:04] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_gphy_intr_mask_MASK 0x00000010
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_gphy_intr_mask_SHIFT 4
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_energy_off_intr_mask [03:03] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_off_intr_mask_MASK 0x00000008
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_off_intr_mask_SHIFT 3
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_energy_on_intr_mask [02:02] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_on_intr_mask_MASK 0x00000004
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_on_intr_mask_SHIFT 2
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_link_down_intr_mask [01:01] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_down_intr_mask_MASK 0x00000002
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_down_intr_mask_SHIFT 1
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: CPU_MASK_CLEAR :: p7_link_up_intr_mask [00:00] */
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_up_intr_mask_MASK 0x00000001
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_up_intr_mask_SHIFT 0
#define BCHP_SWITCH_INTRL2_1_CPU_MASK_CLEAR_p7_link_up_intr_mask_DEFAULT 0x00000001

/***************************************************************************
 *PCI_STATUS - PCI interrupt Status Register
 ***************************************************************************/
/* SWITCH_INTRL2_1 :: PCI_STATUS :: reserved0 [31:30] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_reserved0_MASK             0xc0000000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_reserved0_SHIFT            30

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_gphy_intr [29:29] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_gphy_intr_MASK          0x20000000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_gphy_intr_SHIFT         29
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_energy_off_intr [28:28] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_off_intr_MASK    0x10000000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_off_intr_SHIFT   28
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_energy_on_intr [27:27] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_on_intr_MASK     0x08000000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_on_intr_SHIFT    27
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_link_down_intr [26:26] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_down_intr_MASK     0x04000000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_down_intr_SHIFT    26
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p1_link_up_intr [25:25] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_up_intr_MASK       0x02000000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_up_intr_SHIFT      25
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p1_link_up_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_gphy_intr [24:24] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_gphy_intr_MASK          0x01000000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_gphy_intr_SHIFT         24
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_energy_off_intr [23:23] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_off_intr_MASK    0x00800000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_off_intr_SHIFT   23
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_energy_on_intr [22:22] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_on_intr_MASK     0x00400000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_on_intr_SHIFT    22
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_link_down_intr [21:21] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_down_intr_MASK     0x00200000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_down_intr_SHIFT    21
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p2_link_up_intr [20:20] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_up_intr_MASK       0x00100000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_up_intr_SHIFT      20
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p2_link_up_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_gphy_intr [19:19] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_gphy_intr_MASK          0x00080000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_gphy_intr_SHIFT         19
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_energy_off_intr [18:18] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_off_intr_MASK    0x00040000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_off_intr_SHIFT   18
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_energy_on_intr [17:17] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_on_intr_MASK     0x00020000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_on_intr_SHIFT    17
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_link_down_intr [16:16] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_down_intr_MASK     0x00010000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_down_intr_SHIFT    16
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p3_link_up_intr [15:15] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_up_intr_MASK       0x00008000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_up_intr_SHIFT      15
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p3_link_up_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_gphy_intr [14:14] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_gphy_intr_MASK          0x00004000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_gphy_intr_SHIFT         14
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_energy_off_intr [13:13] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_off_intr_MASK    0x00002000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_off_intr_SHIFT   13
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_energy_on_intr [12:12] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_on_intr_MASK     0x00001000
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_on_intr_SHIFT    12
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_link_down_intr [11:11] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_down_intr_MASK     0x00000800
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_down_intr_SHIFT    11
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p4_link_up_intr [10:10] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_up_intr_MASK       0x00000400
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_up_intr_SHIFT      10
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p4_link_up_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_gphy_intr [09:09] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_gphy_intr_MASK          0x00000200
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_gphy_intr_SHIFT         9
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_energy_off_intr [08:08] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_off_intr_MASK    0x00000100
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_off_intr_SHIFT   8
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_energy_on_intr [07:07] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_on_intr_MASK     0x00000080
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_on_intr_SHIFT    7
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_link_down_intr [06:06] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_down_intr_MASK     0x00000040
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_down_intr_SHIFT    6
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p5_link_up_intr [05:05] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_up_intr_MASK       0x00000020
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_up_intr_SHIFT      5
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p5_link_up_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_gphy_intr [04:04] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_gphy_intr_MASK          0x00000010
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_gphy_intr_SHIFT         4
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_gphy_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_energy_off_intr [03:03] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_off_intr_MASK    0x00000008
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_off_intr_SHIFT   3
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_off_intr_DEFAULT 0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_energy_on_intr [02:02] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_on_intr_MASK     0x00000004
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_on_intr_SHIFT    2
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_energy_on_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_link_down_intr [01:01] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_down_intr_MASK     0x00000002
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_down_intr_SHIFT    1
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_down_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_STATUS :: p7_link_up_intr [00:00] */
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_up_intr_MASK       0x00000001
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_up_intr_SHIFT      0
#define BCHP_SWITCH_INTRL2_1_PCI_STATUS_p7_link_up_intr_DEFAULT    0x00000000

/***************************************************************************
 *PCI_SET - PCI interrupt Set Register
 ***************************************************************************/
/* SWITCH_INTRL2_1 :: PCI_SET :: reserved0 [31:30] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_reserved0_MASK                0xc0000000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_reserved0_SHIFT               30

/* SWITCH_INTRL2_1 :: PCI_SET :: p1_gphy_intr [29:29] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_gphy_intr_MASK             0x20000000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_gphy_intr_SHIFT            29
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p1_energy_off_intr [28:28] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_off_intr_MASK       0x10000000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_off_intr_SHIFT      28
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p1_energy_on_intr [27:27] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_on_intr_MASK        0x08000000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_on_intr_SHIFT       27
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p1_link_down_intr [26:26] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_down_intr_MASK        0x04000000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_down_intr_SHIFT       26
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p1_link_up_intr [25:25] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_up_intr_MASK          0x02000000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_up_intr_SHIFT         25
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p1_link_up_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p2_gphy_intr [24:24] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_gphy_intr_MASK             0x01000000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_gphy_intr_SHIFT            24
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p2_energy_off_intr [23:23] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_off_intr_MASK       0x00800000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_off_intr_SHIFT      23
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p2_energy_on_intr [22:22] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_on_intr_MASK        0x00400000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_on_intr_SHIFT       22
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p2_link_down_intr [21:21] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_down_intr_MASK        0x00200000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_down_intr_SHIFT       21
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p2_link_up_intr [20:20] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_up_intr_MASK          0x00100000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_up_intr_SHIFT         20
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p2_link_up_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p3_gphy_intr [19:19] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_gphy_intr_MASK             0x00080000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_gphy_intr_SHIFT            19
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p3_energy_off_intr [18:18] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_off_intr_MASK       0x00040000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_off_intr_SHIFT      18
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p3_energy_on_intr [17:17] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_on_intr_MASK        0x00020000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_on_intr_SHIFT       17
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p3_link_down_intr [16:16] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_down_intr_MASK        0x00010000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_down_intr_SHIFT       16
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p3_link_up_intr [15:15] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_up_intr_MASK          0x00008000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_up_intr_SHIFT         15
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p3_link_up_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p4_gphy_intr [14:14] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_gphy_intr_MASK             0x00004000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_gphy_intr_SHIFT            14
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p4_energy_off_intr [13:13] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_off_intr_MASK       0x00002000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_off_intr_SHIFT      13
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p4_energy_on_intr [12:12] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_on_intr_MASK        0x00001000
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_on_intr_SHIFT       12
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p4_link_down_intr [11:11] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_down_intr_MASK        0x00000800
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_down_intr_SHIFT       11
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p4_link_up_intr [10:10] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_up_intr_MASK          0x00000400
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_up_intr_SHIFT         10
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p4_link_up_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p5_gphy_intr [09:09] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_gphy_intr_MASK             0x00000200
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_gphy_intr_SHIFT            9
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p5_energy_off_intr [08:08] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_off_intr_MASK       0x00000100
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_off_intr_SHIFT      8
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p5_energy_on_intr [07:07] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_on_intr_MASK        0x00000080
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_on_intr_SHIFT       7
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p5_link_down_intr [06:06] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_down_intr_MASK        0x00000040
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_down_intr_SHIFT       6
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p5_link_up_intr [05:05] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_up_intr_MASK          0x00000020
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_up_intr_SHIFT         5
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p5_link_up_intr_DEFAULT       0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p7_gphy_intr [04:04] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_gphy_intr_MASK             0x00000010
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_gphy_intr_SHIFT            4
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_gphy_intr_DEFAULT          0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p7_energy_off_intr [03:03] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_off_intr_MASK       0x00000008
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_off_intr_SHIFT      3
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_off_intr_DEFAULT    0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p7_energy_on_intr [02:02] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_on_intr_MASK        0x00000004
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_on_intr_SHIFT       2
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_energy_on_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p7_link_down_intr [01:01] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_down_intr_MASK        0x00000002
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_down_intr_SHIFT       1
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_down_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_SET :: p7_link_up_intr [00:00] */
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_up_intr_MASK          0x00000001
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_up_intr_SHIFT         0
#define BCHP_SWITCH_INTRL2_1_PCI_SET_p7_link_up_intr_DEFAULT       0x00000000

/***************************************************************************
 *PCI_CLEAR - PCI interrupt Clear Register
 ***************************************************************************/
/* SWITCH_INTRL2_1 :: PCI_CLEAR :: reserved0 [31:30] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_reserved0_MASK              0xc0000000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_reserved0_SHIFT             30

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_gphy_intr [29:29] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_gphy_intr_MASK           0x20000000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_gphy_intr_SHIFT          29
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_energy_off_intr [28:28] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_off_intr_MASK     0x10000000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_off_intr_SHIFT    28
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_energy_on_intr [27:27] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_on_intr_MASK      0x08000000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_on_intr_SHIFT     27
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_link_down_intr [26:26] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_down_intr_MASK      0x04000000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_down_intr_SHIFT     26
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p1_link_up_intr [25:25] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_up_intr_MASK        0x02000000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_up_intr_SHIFT       25
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p1_link_up_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_gphy_intr [24:24] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_gphy_intr_MASK           0x01000000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_gphy_intr_SHIFT          24
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_energy_off_intr [23:23] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_off_intr_MASK     0x00800000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_off_intr_SHIFT    23
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_energy_on_intr [22:22] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_on_intr_MASK      0x00400000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_on_intr_SHIFT     22
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_link_down_intr [21:21] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_down_intr_MASK      0x00200000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_down_intr_SHIFT     21
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p2_link_up_intr [20:20] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_up_intr_MASK        0x00100000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_up_intr_SHIFT       20
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p2_link_up_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_gphy_intr [19:19] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_gphy_intr_MASK           0x00080000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_gphy_intr_SHIFT          19
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_energy_off_intr [18:18] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_off_intr_MASK     0x00040000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_off_intr_SHIFT    18
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_energy_on_intr [17:17] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_on_intr_MASK      0x00020000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_on_intr_SHIFT     17
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_link_down_intr [16:16] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_down_intr_MASK      0x00010000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_down_intr_SHIFT     16
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p3_link_up_intr [15:15] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_up_intr_MASK        0x00008000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_up_intr_SHIFT       15
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p3_link_up_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_gphy_intr [14:14] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_gphy_intr_MASK           0x00004000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_gphy_intr_SHIFT          14
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_energy_off_intr [13:13] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_off_intr_MASK     0x00002000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_off_intr_SHIFT    13
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_energy_on_intr [12:12] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_on_intr_MASK      0x00001000
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_on_intr_SHIFT     12
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_link_down_intr [11:11] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_down_intr_MASK      0x00000800
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_down_intr_SHIFT     11
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p4_link_up_intr [10:10] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_up_intr_MASK        0x00000400
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_up_intr_SHIFT       10
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p4_link_up_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_gphy_intr [09:09] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_gphy_intr_MASK           0x00000200
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_gphy_intr_SHIFT          9
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_energy_off_intr [08:08] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_off_intr_MASK     0x00000100
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_off_intr_SHIFT    8
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_energy_on_intr [07:07] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_on_intr_MASK      0x00000080
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_on_intr_SHIFT     7
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_link_down_intr [06:06] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_down_intr_MASK      0x00000040
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_down_intr_SHIFT     6
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p5_link_up_intr [05:05] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_up_intr_MASK        0x00000020
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_up_intr_SHIFT       5
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p5_link_up_intr_DEFAULT     0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_gphy_intr [04:04] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_gphy_intr_MASK           0x00000010
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_gphy_intr_SHIFT          4
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_gphy_intr_DEFAULT        0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_energy_off_intr [03:03] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_off_intr_MASK     0x00000008
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_off_intr_SHIFT    3
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_off_intr_DEFAULT  0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_energy_on_intr [02:02] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_on_intr_MASK      0x00000004
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_on_intr_SHIFT     2
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_energy_on_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_link_down_intr [01:01] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_down_intr_MASK      0x00000002
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_down_intr_SHIFT     1
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_down_intr_DEFAULT   0x00000000

/* SWITCH_INTRL2_1 :: PCI_CLEAR :: p7_link_up_intr [00:00] */
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_up_intr_MASK        0x00000001
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_up_intr_SHIFT       0
#define BCHP_SWITCH_INTRL2_1_PCI_CLEAR_p7_link_up_intr_DEFAULT     0x00000000

/***************************************************************************
 *PCI_MASK_STATUS - PCI interrupt Mask Status Register
 ***************************************************************************/
/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: reserved0 [31:30] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_reserved0_MASK        0xc0000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_reserved0_SHIFT       30

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_gphy_intr_mask [29:29] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_gphy_intr_mask_MASK 0x20000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_gphy_intr_mask_SHIFT 29
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_energy_off_intr_mask [28:28] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_off_intr_mask_MASK 0x10000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_off_intr_mask_SHIFT 28
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_energy_on_intr_mask [27:27] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_on_intr_mask_MASK 0x08000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_on_intr_mask_SHIFT 27
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_link_down_intr_mask [26:26] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_down_intr_mask_MASK 0x04000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_down_intr_mask_SHIFT 26
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p1_link_up_intr_mask [25:25] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_up_intr_mask_MASK 0x02000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_up_intr_mask_SHIFT 25
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p1_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_gphy_intr_mask [24:24] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_gphy_intr_mask_MASK 0x01000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_gphy_intr_mask_SHIFT 24
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_energy_off_intr_mask [23:23] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_off_intr_mask_MASK 0x00800000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_off_intr_mask_SHIFT 23
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_energy_on_intr_mask [22:22] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_on_intr_mask_MASK 0x00400000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_on_intr_mask_SHIFT 22
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_link_down_intr_mask [21:21] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_down_intr_mask_MASK 0x00200000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_down_intr_mask_SHIFT 21
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p2_link_up_intr_mask [20:20] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_up_intr_mask_MASK 0x00100000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_up_intr_mask_SHIFT 20
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p2_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_gphy_intr_mask [19:19] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_gphy_intr_mask_MASK 0x00080000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_gphy_intr_mask_SHIFT 19
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_energy_off_intr_mask [18:18] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_off_intr_mask_MASK 0x00040000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_off_intr_mask_SHIFT 18
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_energy_on_intr_mask [17:17] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_on_intr_mask_MASK 0x00020000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_on_intr_mask_SHIFT 17
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_link_down_intr_mask [16:16] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_down_intr_mask_MASK 0x00010000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_down_intr_mask_SHIFT 16
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p3_link_up_intr_mask [15:15] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_up_intr_mask_MASK 0x00008000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_up_intr_mask_SHIFT 15
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p3_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_gphy_intr_mask [14:14] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_gphy_intr_mask_MASK 0x00004000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_gphy_intr_mask_SHIFT 14
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_energy_off_intr_mask [13:13] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_off_intr_mask_MASK 0x00002000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_off_intr_mask_SHIFT 13
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_energy_on_intr_mask [12:12] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_on_intr_mask_MASK 0x00001000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_on_intr_mask_SHIFT 12
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_link_down_intr_mask [11:11] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_down_intr_mask_MASK 0x00000800
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_down_intr_mask_SHIFT 11
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p4_link_up_intr_mask [10:10] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_up_intr_mask_MASK 0x00000400
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_up_intr_mask_SHIFT 10
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p4_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_gphy_intr_mask [09:09] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_gphy_intr_mask_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_gphy_intr_mask_SHIFT 9
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_energy_off_intr_mask [08:08] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_off_intr_mask_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_off_intr_mask_SHIFT 8
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_energy_on_intr_mask [07:07] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_on_intr_mask_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_on_intr_mask_SHIFT 7
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_link_down_intr_mask [06:06] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_down_intr_mask_MASK 0x00000040
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_down_intr_mask_SHIFT 6
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p5_link_up_intr_mask [05:05] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_up_intr_mask_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_up_intr_mask_SHIFT 5
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p5_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_gphy_intr_mask [04:04] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_gphy_intr_mask_MASK 0x00000010
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_gphy_intr_mask_SHIFT 4
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_energy_off_intr_mask [03:03] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_off_intr_mask_MASK 0x00000008
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_off_intr_mask_SHIFT 3
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_energy_on_intr_mask [02:02] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_on_intr_mask_MASK 0x00000004
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_on_intr_mask_SHIFT 2
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_link_down_intr_mask [01:01] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_down_intr_mask_MASK 0x00000002
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_down_intr_mask_SHIFT 1
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_STATUS :: p7_link_up_intr_mask [00:00] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_up_intr_mask_MASK 0x00000001
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_up_intr_mask_SHIFT 0
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_STATUS_p7_link_up_intr_mask_DEFAULT 0x00000001

/***************************************************************************
 *PCI_MASK_SET - PCI interrupt Mask Set Register
 ***************************************************************************/
/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: reserved0 [31:30] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_reserved0_MASK           0xc0000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_reserved0_SHIFT          30

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_gphy_intr_mask [29:29] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_gphy_intr_mask_MASK   0x20000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_gphy_intr_mask_SHIFT  29
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_energy_off_intr_mask [28:28] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_off_intr_mask_MASK 0x10000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_off_intr_mask_SHIFT 28
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_energy_on_intr_mask [27:27] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_on_intr_mask_MASK 0x08000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_on_intr_mask_SHIFT 27
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_link_down_intr_mask [26:26] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_down_intr_mask_MASK 0x04000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_down_intr_mask_SHIFT 26
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p1_link_up_intr_mask [25:25] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_up_intr_mask_MASK 0x02000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_up_intr_mask_SHIFT 25
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p1_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_gphy_intr_mask [24:24] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_gphy_intr_mask_MASK   0x01000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_gphy_intr_mask_SHIFT  24
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_energy_off_intr_mask [23:23] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_off_intr_mask_MASK 0x00800000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_off_intr_mask_SHIFT 23
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_energy_on_intr_mask [22:22] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_on_intr_mask_MASK 0x00400000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_on_intr_mask_SHIFT 22
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_link_down_intr_mask [21:21] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_down_intr_mask_MASK 0x00200000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_down_intr_mask_SHIFT 21
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p2_link_up_intr_mask [20:20] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_up_intr_mask_MASK 0x00100000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_up_intr_mask_SHIFT 20
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p2_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_gphy_intr_mask [19:19] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_gphy_intr_mask_MASK   0x00080000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_gphy_intr_mask_SHIFT  19
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_energy_off_intr_mask [18:18] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_off_intr_mask_MASK 0x00040000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_off_intr_mask_SHIFT 18
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_energy_on_intr_mask [17:17] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_on_intr_mask_MASK 0x00020000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_on_intr_mask_SHIFT 17
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_link_down_intr_mask [16:16] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_down_intr_mask_MASK 0x00010000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_down_intr_mask_SHIFT 16
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p3_link_up_intr_mask [15:15] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_up_intr_mask_MASK 0x00008000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_up_intr_mask_SHIFT 15
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p3_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_gphy_intr_mask [14:14] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_gphy_intr_mask_MASK   0x00004000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_gphy_intr_mask_SHIFT  14
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_energy_off_intr_mask [13:13] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_off_intr_mask_MASK 0x00002000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_off_intr_mask_SHIFT 13
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_energy_on_intr_mask [12:12] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_on_intr_mask_MASK 0x00001000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_on_intr_mask_SHIFT 12
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_link_down_intr_mask [11:11] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_down_intr_mask_MASK 0x00000800
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_down_intr_mask_SHIFT 11
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p4_link_up_intr_mask [10:10] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_up_intr_mask_MASK 0x00000400
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_up_intr_mask_SHIFT 10
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p4_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_gphy_intr_mask [09:09] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_gphy_intr_mask_MASK   0x00000200
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_gphy_intr_mask_SHIFT  9
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_energy_off_intr_mask [08:08] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_off_intr_mask_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_off_intr_mask_SHIFT 8
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_energy_on_intr_mask [07:07] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_on_intr_mask_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_on_intr_mask_SHIFT 7
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_link_down_intr_mask [06:06] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_down_intr_mask_MASK 0x00000040
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_down_intr_mask_SHIFT 6
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p5_link_up_intr_mask [05:05] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_up_intr_mask_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_up_intr_mask_SHIFT 5
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p5_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_gphy_intr_mask [04:04] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_gphy_intr_mask_MASK   0x00000010
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_gphy_intr_mask_SHIFT  4
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_energy_off_intr_mask [03:03] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_off_intr_mask_MASK 0x00000008
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_off_intr_mask_SHIFT 3
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_energy_on_intr_mask [02:02] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_on_intr_mask_MASK 0x00000004
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_on_intr_mask_SHIFT 2
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_link_down_intr_mask [01:01] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_down_intr_mask_MASK 0x00000002
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_down_intr_mask_SHIFT 1
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_SET :: p7_link_up_intr_mask [00:00] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_up_intr_mask_MASK 0x00000001
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_up_intr_mask_SHIFT 0
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_SET_p7_link_up_intr_mask_DEFAULT 0x00000001

/***************************************************************************
 *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
 ***************************************************************************/
/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: reserved0 [31:30] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_reserved0_MASK         0xc0000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_reserved0_SHIFT        30

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_gphy_intr_mask [29:29] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_gphy_intr_mask_MASK 0x20000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_gphy_intr_mask_SHIFT 29
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_energy_off_intr_mask [28:28] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_off_intr_mask_MASK 0x10000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_off_intr_mask_SHIFT 28
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_energy_on_intr_mask [27:27] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_on_intr_mask_MASK 0x08000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_on_intr_mask_SHIFT 27
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_link_down_intr_mask [26:26] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_down_intr_mask_MASK 0x04000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_down_intr_mask_SHIFT 26
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p1_link_up_intr_mask [25:25] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_up_intr_mask_MASK 0x02000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_up_intr_mask_SHIFT 25
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p1_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_gphy_intr_mask [24:24] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_gphy_intr_mask_MASK 0x01000000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_gphy_intr_mask_SHIFT 24
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_energy_off_intr_mask [23:23] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_off_intr_mask_MASK 0x00800000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_off_intr_mask_SHIFT 23
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_energy_on_intr_mask [22:22] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_on_intr_mask_MASK 0x00400000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_on_intr_mask_SHIFT 22
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_link_down_intr_mask [21:21] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_down_intr_mask_MASK 0x00200000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_down_intr_mask_SHIFT 21
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p2_link_up_intr_mask [20:20] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_up_intr_mask_MASK 0x00100000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_up_intr_mask_SHIFT 20
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p2_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_gphy_intr_mask [19:19] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_gphy_intr_mask_MASK 0x00080000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_gphy_intr_mask_SHIFT 19
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_energy_off_intr_mask [18:18] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_off_intr_mask_MASK 0x00040000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_off_intr_mask_SHIFT 18
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_energy_on_intr_mask [17:17] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_on_intr_mask_MASK 0x00020000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_on_intr_mask_SHIFT 17
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_link_down_intr_mask [16:16] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_down_intr_mask_MASK 0x00010000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_down_intr_mask_SHIFT 16
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p3_link_up_intr_mask [15:15] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_up_intr_mask_MASK 0x00008000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_up_intr_mask_SHIFT 15
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p3_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_gphy_intr_mask [14:14] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_gphy_intr_mask_MASK 0x00004000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_gphy_intr_mask_SHIFT 14
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_energy_off_intr_mask [13:13] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_off_intr_mask_MASK 0x00002000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_off_intr_mask_SHIFT 13
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_energy_on_intr_mask [12:12] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_on_intr_mask_MASK 0x00001000
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_on_intr_mask_SHIFT 12
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_link_down_intr_mask [11:11] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_down_intr_mask_MASK 0x00000800
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_down_intr_mask_SHIFT 11
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p4_link_up_intr_mask [10:10] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_up_intr_mask_MASK 0x00000400
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_up_intr_mask_SHIFT 10
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p4_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_gphy_intr_mask [09:09] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_gphy_intr_mask_MASK 0x00000200
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_gphy_intr_mask_SHIFT 9
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_energy_off_intr_mask [08:08] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_off_intr_mask_MASK 0x00000100
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_off_intr_mask_SHIFT 8
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_energy_on_intr_mask [07:07] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_on_intr_mask_MASK 0x00000080
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_on_intr_mask_SHIFT 7
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_link_down_intr_mask [06:06] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_down_intr_mask_MASK 0x00000040
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_down_intr_mask_SHIFT 6
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p5_link_up_intr_mask [05:05] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_up_intr_mask_MASK 0x00000020
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_up_intr_mask_SHIFT 5
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p5_link_up_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_gphy_intr_mask [04:04] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_gphy_intr_mask_MASK 0x00000010
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_gphy_intr_mask_SHIFT 4
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_gphy_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_energy_off_intr_mask [03:03] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_off_intr_mask_MASK 0x00000008
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_off_intr_mask_SHIFT 3
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_off_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_energy_on_intr_mask [02:02] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_on_intr_mask_MASK 0x00000004
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_on_intr_mask_SHIFT 2
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_energy_on_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_link_down_intr_mask [01:01] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_down_intr_mask_MASK 0x00000002
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_down_intr_mask_SHIFT 1
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_down_intr_mask_DEFAULT 0x00000001

/* SWITCH_INTRL2_1 :: PCI_MASK_CLEAR :: p7_link_up_intr_mask [00:00] */
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_up_intr_mask_MASK 0x00000001
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_up_intr_mask_SHIFT 0
#define BCHP_SWITCH_INTRL2_1_PCI_MASK_CLEAR_p7_link_up_intr_mask_DEFAULT 0x00000001

#endif /* #ifndef BCHP_SWITCH_INTRL2_1_H__ */

/* End of File */