/***************************************************************************
 *     Copyright (c) 1999-2013, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Sat Apr  6 03:07:49 2013
 *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_NAND_H__
#define BCHP_NAND_H__

/***************************************************************************
 *NAND - Nand Flash Control Registers
 ***************************************************************************/
#define BCHP_NAND_REVISION                       0x203d2800 /* NAND Revision */
#define BCHP_NAND_CMD_START                      0x203d2804 /* Nand Flash Command Start */
#define BCHP_NAND_CMD_EXT_ADDRESS                0x203d2808 /* Nand Flash Command Extended Address */
#define BCHP_NAND_CMD_ADDRESS                    0x203d280c /* Nand Flash Command Address */
#define BCHP_NAND_CMD_END_ADDRESS                0x203d2810 /* Nand Flash Command End Address */
#define BCHP_NAND_INTFC_STATUS                   0x203d2814 /* Nand Flash Interface Status */
#define BCHP_NAND_CS_NAND_SELECT                 0x203d2818 /* Nand Flash EBI CS Select */
#define BCHP_NAND_CS_NAND_XOR                    0x203d281c /* Nand Flash EBI CS XOR masking on CPU address Control */
#define BCHP_NAND_LL_OP                          0x203d2820 /* Nand Flash Low Level Operation */
#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS        0x203d2824 /* Nand Flash Multiplane base address */
#define BCHP_NAND_MPLANE_BASE_ADDRESS            0x203d2828 /* Nand Flash Multiplane base address */
#define BCHP_NAND_ACC_CONTROL_CS0                0x203d2850 /* Nand Flash Access Control */
#define BCHP_NAND_CONFIG_CS0                     0x203d2854 /* Nand Flash Config */
#define BCHP_NAND_TIMING_1_CS0                   0x203d2858 /* Nand Flash Timing Parameters 1 */
#define BCHP_NAND_TIMING_2_CS0                   0x203d285c /* Nand Flash Timing Parameters 2 */
#define BCHP_NAND_ACC_CONTROL_CS1                0x203d2860 /* Nand Flash Access Control */
#define BCHP_NAND_CONFIG_CS1                     0x203d2864 /* Nand Flash Config */
#define BCHP_NAND_TIMING_1_CS1                   0x203d2868 /* Nand Flash Timing Parameters 1 */
#define BCHP_NAND_TIMING_2_CS1                   0x203d286c /* Nand Flash Timing Parameters 2 */
#define BCHP_NAND_ACC_CONTROL_CS2                0x203d2870 /* Nand Flash Access Control */
#define BCHP_NAND_CONFIG_CS2                     0x203d2874 /* Nand Flash Config */
#define BCHP_NAND_TIMING_1_CS2                   0x203d2878 /* Nand Flash Timing Parameters 1 */
#define BCHP_NAND_TIMING_2_CS2                   0x203d287c /* Nand Flash Timing Parameters 2 */
#define BCHP_NAND_ACC_CONTROL_CS3                0x203d2880 /* Nand Flash Access Control */
#define BCHP_NAND_CONFIG_CS3                     0x203d2884 /* Nand Flash Config */
#define BCHP_NAND_TIMING_1_CS3                   0x203d2888 /* Nand Flash Timing Parameters 1 */
#define BCHP_NAND_TIMING_2_CS3                   0x203d288c /* Nand Flash Timing Parameters 2 */
#define BCHP_NAND_ACC_CONTROL_CS4                0x203d2890 /* Nand Flash Access Control */
#define BCHP_NAND_CONFIG_CS4                     0x203d2894 /* Nand Flash Config */
#define BCHP_NAND_TIMING_1_CS4                   0x203d2898 /* Nand Flash Timing Parameters 1 */
#define BCHP_NAND_TIMING_2_CS4                   0x203d289c /* Nand Flash Timing Parameters 2 */
#define BCHP_NAND_ACC_CONTROL_CS5                0x203d28a0 /* Nand Flash Access Control */
#define BCHP_NAND_CONFIG_CS5                     0x203d28a4 /* Nand Flash Config */
#define BCHP_NAND_TIMING_1_CS5                   0x203d28a8 /* Nand Flash Timing Parameters 1 */
#define BCHP_NAND_TIMING_2_CS5                   0x203d28ac /* Nand Flash Timing Parameters 2 */
#define BCHP_NAND_ACC_CONTROL_CS6                0x203d28b0 /* Nand Flash Access Control */
#define BCHP_NAND_CONFIG_CS6                     0x203d28b4 /* Nand Flash Config */
#define BCHP_NAND_TIMING_1_CS6                   0x203d28b8 /* Nand Flash Timing Parameters 1 */
#define BCHP_NAND_TIMING_2_CS6                   0x203d28bc /* Nand Flash Timing Parameters 2 */
#define BCHP_NAND_CORR_STAT_THRESHOLD            0x203d28c0 /* Correctable Error Reporting Threshold */
#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT        0x203d28c4 /* Correctable Error Reporting Threshold */
#define BCHP_NAND_BLK_WR_PROTECT                 0x203d28c8 /* Block Write Protect Enable and Size for EBI_CS0b */
#define BCHP_NAND_MULTIPLANE_OPCODES_1           0x203d28cc /* Nand Flash Multiplane Customerized Opcodes */
#define BCHP_NAND_MULTIPLANE_OPCODES_2           0x203d28d0 /* Nand Flash Multiplane Customerized Opcodes */
#define BCHP_NAND_MULTIPLANE_CTRL                0x203d28d4 /* Nand Flash Multiplane Control */
#define BCHP_NAND_UNCORR_ERROR_COUNT             0x203d28fc /* Read Uncorrectable Event Count */
#define BCHP_NAND_CORR_ERROR_COUNT               0x203d2900 /* Read Error Count */
#define BCHP_NAND_READ_ERROR_COUNT               0x203d2904 /* Read Error Count */
#define BCHP_NAND_BLOCK_LOCK_STATUS              0x203d2908 /* Nand Flash Block Lock Status */
#define BCHP_NAND_ECC_CORR_EXT_ADDR              0x203d290c /* ECC Correctable Error Extended Address */
#define BCHP_NAND_ECC_CORR_ADDR                  0x203d2910 /* ECC Correctable Error Address */
#define BCHP_NAND_ECC_UNC_EXT_ADDR               0x203d2914 /* ECC Uncorrectable Error Extended Address */
#define BCHP_NAND_ECC_UNC_ADDR                   0x203d2918 /* ECC Uncorrectable Error Address */
#define BCHP_NAND_FLASH_READ_EXT_ADDR            0x203d291c /* Flash Read Data Extended Address */
#define BCHP_NAND_FLASH_READ_ADDR                0x203d2920 /* Flash Read Data Address */
#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR          0x203d2924 /* Page Program Extended Address */
#define BCHP_NAND_PROGRAM_PAGE_ADDR              0x203d2928 /* Page Program Address */
#define BCHP_NAND_COPY_BACK_EXT_ADDR             0x203d292c /* Copy Back Extended Address */
#define BCHP_NAND_COPY_BACK_ADDR                 0x203d2930 /* Copy Back Address */
#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR           0x203d2934 /* Block Erase Extended Address */
#define BCHP_NAND_BLOCK_ERASE_ADDR               0x203d2938 /* Block Erase Address */
#define BCHP_NAND_INV_READ_EXT_ADDR              0x203d293c /* Flash Invalid Data Extended Address */
#define BCHP_NAND_INV_READ_ADDR                  0x203d2940 /* Flash Invalid Data Address */
#define BCHP_NAND_INIT_STATUS                    0x203d2944 /* Initialization status */
#define BCHP_NAND_ONFI_STATUS                    0x203d2948 /* ONFI Status */
#define BCHP_NAND_ONFI_DEBUG_DATA                0x203d294c /* ONFI Debug Data */
#define BCHP_NAND_SEMAPHORE                      0x203d2950 /* Semaphore */
#define BCHP_NAND_FLASH_DEVICE_ID                0x203d2994 /* Nand Flash Device ID */
#define BCHP_NAND_FLASH_DEVICE_ID_EXT            0x203d2998 /* Nand Flash Extended Device ID */
#define BCHP_NAND_LL_RDDATA                      0x203d299c /* Nand Flash Low Level Read Data */
#define BCHP_NAND_SPARE_AREA_READ_OFS_0          0x203d2a00 /* Nand Flash Spare Area Read Bytes 0-3 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_4          0x203d2a04 /* Nand Flash Spare Area Read Bytes 4-7 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_8          0x203d2a08 /* Nand Flash Spare Area Read Bytes 8-11 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_C          0x203d2a0c /* Nand Flash Spare Area Read Bytes 12-15 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_10         0x203d2a10 /* Nand Flash Spare Area Read Bytes 16-19 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_14         0x203d2a14 /* Nand Flash Spare Area Read Bytes 20-23 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_18         0x203d2a18 /* Nand Flash Spare Area Read Bytes 24-27 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C         0x203d2a1c /* Nand Flash Spare Area Read Bytes 28-31 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_20         0x203d2a20 /* Nand Flash Spare Area Read Bytes 32-35 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_24         0x203d2a24 /* Nand Flash Spare Area Read Bytes 36-39 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_28         0x203d2a28 /* Nand Flash Spare Area Read Bytes 40-43 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C         0x203d2a2c /* Nand Flash Spare Area Read Bytes 44-47 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_30         0x203d2a30 /* Nand Flash Spare Area Read Bytes 48-51 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_34         0x203d2a34 /* Nand Flash Spare Area Read Bytes 52-55 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_38         0x203d2a38 /* Nand Flash Spare Area Read Bytes 56-59 */
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C         0x203d2a3c /* Nand Flash Spare Area Read Bytes 60-63 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0         0x203d2a80 /* Nand Flash Spare Area Write Bytes 0-3 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4         0x203d2a84 /* Nand Flash Spare Area Write Bytes 4-7 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8         0x203d2a88 /* Nand Flash Spare Area Write Bytes 8-11 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C         0x203d2a8c /* Nand Flash Spare Area Write Bytes 12-15 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10        0x203d2a90 /* Nand Flash Spare Area Write Bytes 16-19 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14        0x203d2a94 /* Nand Flash Spare Area Write Bytes 20-23 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18        0x203d2a98 /* Nand Flash Spare Area Write Bytes 24-27 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C        0x203d2a9c /* Nand Flash Spare Area Write Bytes 28-31 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20        0x203d2aa0 /* Nand Flash Spare Area Write Bytes 32-35 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24        0x203d2aa4 /* Nand Flash Spare Area Write Bytes 36-39 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28        0x203d2aa8 /* Nand Flash Spare Area Write Bytes 40-43 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C        0x203d2aac /* Nand Flash Spare Area Write Bytes 44-47 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30        0x203d2ab0 /* Nand Flash Spare Area Write Bytes 48-51 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34        0x203d2ab4 /* Nand Flash Spare Area Write Bytes 52-55 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38        0x203d2ab8 /* Nand Flash Spare Area Write Bytes 56-59 */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C        0x203d2abc /* Nand Flash Spare Area Write Bytes 60-63 */
#define BCHP_NAND_DDR_TIMING                     0x203d2ac0 /* Nand Flash DDR TIMING */
#define BCHP_NAND_DDR_NCDL_CALIB_CTL             0x203d2ac4 /* Nand Flash Calibration Control for Master DLL */
#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD          0x203d2ac8 /* Nand Flash Calibration Period */
#define BCHP_NAND_DDR_NCDL_CALIB_STAT            0x203d2acc /* Nand Flash Calibration Status for Master DLL */
#define BCHP_NAND_DDR_NCDL_MODE                  0x203d2ad0 /* Nand Flash NCDL mode for Slave DLLs */
#define BCHP_NAND_DDR_NCDL_OFFSET                0x203d2ad4 /* Nand Flash NCDL offset for Slave DLLs */
#define BCHP_NAND_DDR_PHY_CTL                    0x203d2ad8 /* Nand Flash DDR PHY CONTROL */
#define BCHP_NAND_DDR_PHY_BIST_CTL               0x203d2adc /* Nand Flash DDR PHY BIST CONTROL */
#define BCHP_NAND_DDR_PHY_BIST_STAT              0x203d2ae0 /* Nand Flash DDR PHY BIST STATUS */
#define BCHP_NAND_DDR_DIAG_STAT0                 0x203d2ae4 /* Nand Flash DDR DIAG STATUS0 */
#define BCHP_NAND_DDR_DIAG_STAT1                 0x203d2ae8 /* Nand Flash DDR DIAG STATUS1 */

/***************************************************************************
 *REVISION - NAND Revision
 ***************************************************************************/
/* NAND :: REVISION :: 8KB_PAGE_SUPPORT [31:31] */
#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_MASK                   0x80000000
#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_SHIFT                  31
#define BCHP_NAND_REVISION_8KB_PAGE_SUPPORT_DEFAULT                0x00000001

/* NAND :: REVISION :: reserved0 [30:16] */
#define BCHP_NAND_REVISION_reserved0_MASK                          0x7fff0000
#define BCHP_NAND_REVISION_reserved0_SHIFT                         16

/* NAND :: REVISION :: MAJOR [15:08] */
#define BCHP_NAND_REVISION_MAJOR_MASK                              0x0000ff00
#define BCHP_NAND_REVISION_MAJOR_SHIFT                             8
#define BCHP_NAND_REVISION_MAJOR_DEFAULT                           0x00000007

/* NAND :: REVISION :: MINOR [07:00] */
#define BCHP_NAND_REVISION_MINOR_MASK                              0x000000ff
#define BCHP_NAND_REVISION_MINOR_SHIFT                             0
#define BCHP_NAND_REVISION_MINOR_DEFAULT                           0x00000000

/***************************************************************************
 *CMD_START - Nand Flash Command Start
 ***************************************************************************/
/* NAND :: CMD_START :: reserved0 [31:05] */
#define BCHP_NAND_CMD_START_reserved0_MASK                         0xffffffe0
#define BCHP_NAND_CMD_START_reserved0_SHIFT                        5

/* NAND :: CMD_START :: OPCODE [04:00] */
#define BCHP_NAND_CMD_START_OPCODE_MASK                            0x0000001f
#define BCHP_NAND_CMD_START_OPCODE_SHIFT                           0
#define BCHP_NAND_CMD_START_OPCODE_DEFAULT                         0x00000000
#define BCHP_NAND_CMD_START_OPCODE_NULL                            0
#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ                       1
#define BCHP_NAND_CMD_START_OPCODE_SPARE_AREA_READ                 2
#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ                     3
#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE                    4
#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_SPARE_AREA              5
#define BCHP_NAND_CMD_START_OPCODE_COPY_BACK                       6
#define BCHP_NAND_CMD_START_OPCODE_DEVICE_ID_READ                  7
#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE                     8
#define BCHP_NAND_CMD_START_OPCODE_FLASH_RESET                     9
#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK                     10
#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_LOCK_DOWN                11
#define BCHP_NAND_CMD_START_OPCODE_BLOCKS_UNLOCK                   12
#define BCHP_NAND_CMD_START_OPCODE_READ_BLOCKS_LOCK_STATUS         13
#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_READ                  14
#define BCHP_NAND_CMD_START_OPCODE_PARAMETER_CHANGE_COL            15
#define BCHP_NAND_CMD_START_OPCODE_LOW_LEVEL_OP                    16
#define BCHP_NAND_CMD_START_OPCODE_PAGE_READ_MULTI                 17
#define BCHP_NAND_CMD_START_OPCODE_STATUS_READ_MULTI               18
#define BCHP_NAND_CMD_START_OPCODE_PROGRAM_PAGE_MULTI              19
#define BCHP_NAND_CMD_START_OPCODE_BLOCK_ERASE_MULTI               21

/***************************************************************************
 *CMD_EXT_ADDRESS - Nand Flash Command Extended Address
 ***************************************************************************/
/* NAND :: CMD_EXT_ADDRESS :: reserved0 [31:19] */
#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_MASK                   0xfff80000
#define BCHP_NAND_CMD_EXT_ADDRESS_reserved0_SHIFT                  19

/* NAND :: CMD_EXT_ADDRESS :: CS_SEL [18:16] */
#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_MASK                      0x00070000
#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_SHIFT                     16
#define BCHP_NAND_CMD_EXT_ADDRESS_CS_SEL_DEFAULT                   0x00000000

/* NAND :: CMD_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_MASK                 0x0000ffff
#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_SHIFT                0
#define BCHP_NAND_CMD_EXT_ADDRESS_EXT_ADDRESS_DEFAULT              0x00000000

/***************************************************************************
 *CMD_ADDRESS - Nand Flash Command Address
 ***************************************************************************/
/* NAND :: CMD_ADDRESS :: ADDRESS [31:00] */
#define BCHP_NAND_CMD_ADDRESS_ADDRESS_MASK                         0xffffffff
#define BCHP_NAND_CMD_ADDRESS_ADDRESS_SHIFT                        0
#define BCHP_NAND_CMD_ADDRESS_ADDRESS_DEFAULT                      0x00000000

/***************************************************************************
 *CMD_END_ADDRESS - Nand Flash Command End Address
 ***************************************************************************/
/* NAND :: CMD_END_ADDRESS :: ADDRESS [31:00] */
#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_MASK                     0xffffffff
#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_SHIFT                    0
#define BCHP_NAND_CMD_END_ADDRESS_ADDRESS_DEFAULT                  0x00000000

/***************************************************************************
 *INTFC_STATUS - Nand Flash Interface Status
 ***************************************************************************/
/* NAND :: INTFC_STATUS :: CTLR_READY [31:31] */
#define BCHP_NAND_INTFC_STATUS_CTLR_READY_MASK                     0x80000000
#define BCHP_NAND_INTFC_STATUS_CTLR_READY_SHIFT                    31

/* NAND :: INTFC_STATUS :: FLASH_READY [30:30] */
#define BCHP_NAND_INTFC_STATUS_FLASH_READY_MASK                    0x40000000
#define BCHP_NAND_INTFC_STATUS_FLASH_READY_SHIFT                   30

/* NAND :: INTFC_STATUS :: CACHE_VALID [29:29] */
#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_MASK                    0x20000000
#define BCHP_NAND_INTFC_STATUS_CACHE_VALID_SHIFT                   29

/* NAND :: INTFC_STATUS :: SPARE_AREA_VALID [28:28] */
#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_MASK               0x10000000
#define BCHP_NAND_INTFC_STATUS_SPARE_AREA_VALID_SHIFT              28

/* NAND :: INTFC_STATUS :: ERASED [27:27] */
#define BCHP_NAND_INTFC_STATUS_ERASED_MASK                         0x08000000
#define BCHP_NAND_INTFC_STATUS_ERASED_SHIFT                        27

/* NAND :: INTFC_STATUS :: PLANE_READY [26:26] */
#define BCHP_NAND_INTFC_STATUS_PLANE_READY_MASK                    0x04000000
#define BCHP_NAND_INTFC_STATUS_PLANE_READY_SHIFT                   26

/* NAND :: INTFC_STATUS :: reserved0 [25:08] */
#define BCHP_NAND_INTFC_STATUS_reserved0_MASK                      0x03ffff00
#define BCHP_NAND_INTFC_STATUS_reserved0_SHIFT                     8

/* NAND :: INTFC_STATUS :: FLASH_STATUS [07:00] */
#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_MASK                   0x000000ff
#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_SHIFT                  0
#define BCHP_NAND_INTFC_STATUS_FLASH_STATUS_DEFAULT                0x00000000

/***************************************************************************
 *CS_NAND_SELECT - Nand Flash EBI CS Select
 ***************************************************************************/
/* NAND :: CS_NAND_SELECT :: CS_LOCK [31:31] */
#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_MASK                      0x80000000
#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_SHIFT                     31
#define BCHP_NAND_CS_NAND_SELECT_CS_LOCK_DEFAULT                   0x00000000

/* NAND :: CS_NAND_SELECT :: AUTO_DEVICE_ID_CONFIG [30:30] */
#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_MASK        0x40000000
#define BCHP_NAND_CS_NAND_SELECT_AUTO_DEVICE_ID_CONFIG_SHIFT       30

/* NAND :: CS_NAND_SELECT :: NAND_WP [29:29] */
#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_MASK                      0x20000000
#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_SHIFT                     29
#define BCHP_NAND_CS_NAND_SELECT_NAND_WP_DEFAULT                   0x00000001

/* NAND :: CS_NAND_SELECT :: WR_PROTECT_BLK0 [28:28] */
#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_MASK              0x10000000
#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_SHIFT             28
#define BCHP_NAND_CS_NAND_SELECT_WR_PROTECT_BLK0_DEFAULT           0x00000000

/* NAND :: CS_NAND_SELECT :: reserved0 [27:16] */
#define BCHP_NAND_CS_NAND_SELECT_reserved0_MASK                    0x0fff0000
#define BCHP_NAND_CS_NAND_SELECT_reserved0_SHIFT                   16

/* NAND :: CS_NAND_SELECT :: EBI_CS_7_USES_NAND [15:15] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_MASK           0x00008000
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_SHIFT          15
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_USES_NAND_DEFAULT        0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_6_USES_NAND [14:14] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_MASK           0x00004000
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_SHIFT          14
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_USES_NAND_DEFAULT        0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_5_USES_NAND [13:13] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_MASK           0x00002000
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_SHIFT          13
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_USES_NAND_DEFAULT        0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_4_USES_NAND [12:12] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_MASK           0x00001000
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_SHIFT          12
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_USES_NAND_DEFAULT        0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_3_USES_NAND [11:11] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_MASK           0x00000800
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_SHIFT          11
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_USES_NAND_DEFAULT        0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_2_USES_NAND [10:10] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_MASK           0x00000400
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_SHIFT          10
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_USES_NAND_DEFAULT        0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_1_USES_NAND [09:09] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_MASK           0x00000200
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_SHIFT          9
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_USES_NAND_DEFAULT        0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_0_USES_NAND [08:08] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_MASK           0x00000100
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_USES_NAND_SHIFT          8

/* NAND :: CS_NAND_SELECT :: EBI_CS_7_SEL [07:07] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_MASK                 0x00000080
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_SHIFT                7
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_7_SEL_DEFAULT              0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_6_SEL [06:06] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_MASK                 0x00000040
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_SHIFT                6
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_6_SEL_DEFAULT              0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_5_SEL [05:05] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_MASK                 0x00000020
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_SHIFT                5
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_5_SEL_DEFAULT              0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_4_SEL [04:04] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_MASK                 0x00000010
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_SHIFT                4
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_4_SEL_DEFAULT              0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_3_SEL [03:03] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_MASK                 0x00000008
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_SHIFT                3
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_3_SEL_DEFAULT              0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_2_SEL [02:02] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_MASK                 0x00000004
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_SHIFT                2
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_2_SEL_DEFAULT              0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_1_SEL [01:01] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_MASK                 0x00000002
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_SHIFT                1
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_1_SEL_DEFAULT              0x00000000

/* NAND :: CS_NAND_SELECT :: EBI_CS_0_SEL [00:00] */
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_MASK                 0x00000001
#define BCHP_NAND_CS_NAND_SELECT_EBI_CS_0_SEL_SHIFT                0

/***************************************************************************
 *CS_NAND_XOR - Nand Flash EBI CS XOR masking on CPU address Control
 ***************************************************************************/
/* NAND :: CS_NAND_XOR :: ONLY_BLOCK_0_XOR [31:31] */
#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_MASK                0x80000000
#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_SHIFT               31
#define BCHP_NAND_CS_NAND_XOR_ONLY_BLOCK_0_XOR_DEFAULT             0x00000000

/* NAND :: CS_NAND_XOR :: reserved0 [30:08] */
#define BCHP_NAND_CS_NAND_XOR_reserved0_MASK                       0x7fffff00
#define BCHP_NAND_CS_NAND_XOR_reserved0_SHIFT                      8

/* NAND :: CS_NAND_XOR :: EBI_CS_7_ADDR_XOR [07:07] */
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_MASK               0x00000080
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_SHIFT              7
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_7_ADDR_XOR_DEFAULT            0x00000000

/* NAND :: CS_NAND_XOR :: EBI_CS_6_ADDR_XOR [06:06] */
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_MASK               0x00000040
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_SHIFT              6
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_6_ADDR_XOR_DEFAULT            0x00000000

/* NAND :: CS_NAND_XOR :: EBI_CS_5_ADDR_XOR [05:05] */
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_MASK               0x00000020
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_SHIFT              5
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_5_ADDR_XOR_DEFAULT            0x00000000

/* NAND :: CS_NAND_XOR :: EBI_CS_4_ADDR_XOR [04:04] */
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_MASK               0x00000010
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_SHIFT              4
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_4_ADDR_XOR_DEFAULT            0x00000000

/* NAND :: CS_NAND_XOR :: EBI_CS_3_ADDR_XOR [03:03] */
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_MASK               0x00000008
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_SHIFT              3
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_3_ADDR_XOR_DEFAULT            0x00000000

/* NAND :: CS_NAND_XOR :: EBI_CS_2_ADDR_XOR [02:02] */
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_MASK               0x00000004
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_SHIFT              2
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_2_ADDR_XOR_DEFAULT            0x00000000

/* NAND :: CS_NAND_XOR :: EBI_CS_1_ADDR_XOR [01:01] */
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_MASK               0x00000002
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_SHIFT              1
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_1_ADDR_XOR_DEFAULT            0x00000000

/* NAND :: CS_NAND_XOR :: EBI_CS_0_ADDR_XOR [00:00] */
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_MASK               0x00000001
#define BCHP_NAND_CS_NAND_XOR_EBI_CS_0_ADDR_XOR_SHIFT              0

/***************************************************************************
 *LL_OP - Nand Flash Low Level Operation
 ***************************************************************************/
/* NAND :: LL_OP :: RETURN_IDLE [31:31] */
#define BCHP_NAND_LL_OP_RETURN_IDLE_MASK                           0x80000000
#define BCHP_NAND_LL_OP_RETURN_IDLE_SHIFT                          31
#define BCHP_NAND_LL_OP_RETURN_IDLE_DEFAULT                        0x00000000

/* NAND :: LL_OP :: reserved0 [30:20] */
#define BCHP_NAND_LL_OP_reserved0_MASK                             0x7ff00000
#define BCHP_NAND_LL_OP_reserved0_SHIFT                            20

/* NAND :: LL_OP :: CLE [19:19] */
#define BCHP_NAND_LL_OP_CLE_MASK                                   0x00080000
#define BCHP_NAND_LL_OP_CLE_SHIFT                                  19
#define BCHP_NAND_LL_OP_CLE_DEFAULT                                0x00000000

/* NAND :: LL_OP :: ALE [18:18] */
#define BCHP_NAND_LL_OP_ALE_MASK                                   0x00040000
#define BCHP_NAND_LL_OP_ALE_SHIFT                                  18
#define BCHP_NAND_LL_OP_ALE_DEFAULT                                0x00000000

/* NAND :: LL_OP :: WE [17:17] */
#define BCHP_NAND_LL_OP_WE_MASK                                    0x00020000
#define BCHP_NAND_LL_OP_WE_SHIFT                                   17
#define BCHP_NAND_LL_OP_WE_DEFAULT                                 0x00000000

/* NAND :: LL_OP :: RE [16:16] */
#define BCHP_NAND_LL_OP_RE_MASK                                    0x00010000
#define BCHP_NAND_LL_OP_RE_SHIFT                                   16
#define BCHP_NAND_LL_OP_RE_DEFAULT                                 0x00000000

/* NAND :: LL_OP :: DATA [15:00] */
#define BCHP_NAND_LL_OP_DATA_MASK                                  0x0000ffff
#define BCHP_NAND_LL_OP_DATA_SHIFT                                 0
#define BCHP_NAND_LL_OP_DATA_DEFAULT                               0x00000000

/***************************************************************************
 *MPLANE_BASE_EXT_ADDRESS - Nand Flash Multiplane base address
 ***************************************************************************/
/* NAND :: MPLANE_BASE_EXT_ADDRESS :: reserved0 [31:16] */
#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_MASK           0xffff0000
#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_reserved0_SHIFT          16

/* NAND :: MPLANE_BASE_EXT_ADDRESS :: EXT_ADDRESS [15:00] */
#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_MASK         0x0000ffff
#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_SHIFT        0
#define BCHP_NAND_MPLANE_BASE_EXT_ADDRESS_EXT_ADDRESS_DEFAULT      0x00000000

/***************************************************************************
 *MPLANE_BASE_ADDRESS - Nand Flash Multiplane base address
 ***************************************************************************/
/* NAND :: MPLANE_BASE_ADDRESS :: ADDRESS [31:00] */
#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_MASK                 0xffffffff
#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_SHIFT                0
#define BCHP_NAND_MPLANE_BASE_ADDRESS_ADDRESS_DEFAULT              0x00000000

/***************************************************************************
 *ACC_CONTROL_CS0 - Nand Flash Access Control
 ***************************************************************************/
/* NAND :: ACC_CONTROL_CS0 :: RD_ECC_EN [31:31] */
#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_MASK                   0x80000000
#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_SHIFT                  31
#define BCHP_NAND_ACC_CONTROL_CS0_RD_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS0 :: WR_ECC_EN [30:30] */
#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_MASK                   0x40000000
#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_SHIFT                  30
#define BCHP_NAND_ACC_CONTROL_CS0_WR_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS0 :: CE_CARE [29:29] */
#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_MASK                     0x20000000
#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_SHIFT                    29
#define BCHP_NAND_ACC_CONTROL_CS0_CE_CARE_DEFAULT                  0x00000000

/* NAND :: ACC_CONTROL_CS0 :: reserved0 [28:28] */
#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_MASK                   0x10000000
#define BCHP_NAND_ACC_CONTROL_CS0_reserved0_SHIFT                  28

/* NAND :: ACC_CONTROL_CS0 :: RD_ERASED_ECC_EN [27:27] */
#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_MASK            0x08000000
#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_SHIFT           27
#define BCHP_NAND_ACC_CONTROL_CS0_RD_ERASED_ECC_EN_DEFAULT         0x00000000

/* NAND :: ACC_CONTROL_CS0 :: PARTIAL_PAGE_EN [26:26] */
#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_MASK             0x04000000
#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_SHIFT            26
#define BCHP_NAND_ACC_CONTROL_CS0_PARTIAL_PAGE_EN_DEFAULT          0x00000000

/* NAND :: ACC_CONTROL_CS0 :: WR_PREEMPT_EN [25:25] */
#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_MASK               0x02000000
#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_SHIFT              25
#define BCHP_NAND_ACC_CONTROL_CS0_WR_PREEMPT_EN_DEFAULT            0x00000001

/* NAND :: ACC_CONTROL_CS0 :: PAGE_HIT_EN [24:24] */
#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_MASK                 0x01000000
#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_SHIFT                24
#define BCHP_NAND_ACC_CONTROL_CS0_PAGE_HIT_EN_DEFAULT              0x00000001

/* NAND :: ACC_CONTROL_CS0 :: PREFETCH_EN [23:23] */
#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_MASK                 0x00800000
#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_SHIFT                23
#define BCHP_NAND_ACC_CONTROL_CS0_PREFETCH_EN_DEFAULT              0x00000000

/* NAND :: ACC_CONTROL_CS0 :: CACHE_MODE_EN [22:22] */
#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_MASK               0x00400000
#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_SHIFT              22
#define BCHP_NAND_ACC_CONTROL_CS0_CACHE_MODE_EN_DEFAULT            0x00000000

/* NAND :: ACC_CONTROL_CS0 :: reserved1 [21:21] */
#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_MASK                   0x00200000
#define BCHP_NAND_ACC_CONTROL_CS0_reserved1_SHIFT                  21

/* NAND :: ACC_CONTROL_CS0 :: ECC_LEVEL [20:16] */
#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_MASK                   0x001f0000
#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_SHIFT                  16
#define BCHP_NAND_ACC_CONTROL_CS0_ECC_LEVEL_DEFAULT                0x0000000f

/* NAND :: ACC_CONTROL_CS0 :: reserved2 [15:08] */
#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_MASK                   0x0000ff00
#define BCHP_NAND_ACC_CONTROL_CS0_reserved2_SHIFT                  8

/* NAND :: ACC_CONTROL_CS0 :: SECTOR_SIZE_1K [07:07] */
#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_MASK              0x00000080
#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_SHIFT             7
#define BCHP_NAND_ACC_CONTROL_CS0_SECTOR_SIZE_1K_DEFAULT           0x00000000

/* NAND :: ACC_CONTROL_CS0 :: SPARE_AREA_SIZE [06:00] */
#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_MASK             0x0000007f
#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_SHIFT            0
#define BCHP_NAND_ACC_CONTROL_CS0_SPARE_AREA_SIZE_DEFAULT          0x00000010

/***************************************************************************
 *CONFIG_CS0 - Nand Flash Config
 ***************************************************************************/
/* NAND :: CONFIG_CS0 :: CONFIG_LOCK [31:31] */
#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_MASK                      0x80000000
#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_SHIFT                     31
#define BCHP_NAND_CONFIG_CS0_CONFIG_LOCK_DEFAULT                   0x00000000

/* NAND :: CONFIG_CS0 :: BLOCK_SIZE [30:28] */
#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_MASK                       0x70000000
#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_SHIFT                      28
#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_2048KB             6
#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_1024KB             5
#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_512KB              4
#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_256KB              3
#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_128KB              2
#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_16KB               1
#define BCHP_NAND_CONFIG_CS0_BLOCK_SIZE_BK_SIZE_8KB                0

/* NAND :: CONFIG_CS0 :: DEVICE_SIZE [27:24] */
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_MASK                      0x0f000000
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_SHIFT                     24
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4MB              0
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8MB              1
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16MB             2
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32MB             3
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64MB             4
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128MB            5
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_256MB            6
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_512MB            7
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_1GB              8
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_2GB              9
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_4GB              10
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_8GB              11
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_16GB             12
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_32GB             13
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_64GB             14
#define BCHP_NAND_CONFIG_CS0_DEVICE_SIZE_DVC_SIZE_128GB            15

/* NAND :: CONFIG_CS0 :: DEVICE_WIDTH [23:23] */
#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_MASK                     0x00800000
#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_SHIFT                    23
#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_8              0
#define BCHP_NAND_CONFIG_CS0_DEVICE_WIDTH_DVC_WIDTH_16             1

/* NAND :: CONFIG_CS0 :: reserved0 [22:22] */
#define BCHP_NAND_CONFIG_CS0_reserved0_MASK                        0x00400000
#define BCHP_NAND_CONFIG_CS0_reserved0_SHIFT                       22

/* NAND :: CONFIG_CS0 :: PAGE_SIZE [21:20] */
#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_MASK                        0x00300000
#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_SHIFT                       20
#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_512                 0
#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_2KB                 1
#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_4KB                 2
#define BCHP_NAND_CONFIG_CS0_PAGE_SIZE_PG_SIZE_8KB                 3

/* NAND :: CONFIG_CS0 :: reserved1 [19:19] */
#define BCHP_NAND_CONFIG_CS0_reserved1_MASK                        0x00080000
#define BCHP_NAND_CONFIG_CS0_reserved1_SHIFT                       19

/* NAND :: CONFIG_CS0 :: FUL_ADR_BYTES [18:16] */
#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_MASK                    0x00070000
#define BCHP_NAND_CONFIG_CS0_FUL_ADR_BYTES_SHIFT                   16

/* NAND :: CONFIG_CS0 :: reserved2 [15:15] */
#define BCHP_NAND_CONFIG_CS0_reserved2_MASK                        0x00008000
#define BCHP_NAND_CONFIG_CS0_reserved2_SHIFT                       15

/* NAND :: CONFIG_CS0 :: COL_ADR_BYTES [14:12] */
#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_MASK                    0x00007000
#define BCHP_NAND_CONFIG_CS0_COL_ADR_BYTES_SHIFT                   12

/* NAND :: CONFIG_CS0 :: reserved3 [11:11] */
#define BCHP_NAND_CONFIG_CS0_reserved3_MASK                        0x00000800
#define BCHP_NAND_CONFIG_CS0_reserved3_SHIFT                       11

/* NAND :: CONFIG_CS0 :: BLK_ADR_BYTES [10:08] */
#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_MASK                    0x00000700
#define BCHP_NAND_CONFIG_CS0_BLK_ADR_BYTES_SHIFT                   8

/* NAND :: CONFIG_CS0 :: reserved4 [07:00] */
#define BCHP_NAND_CONFIG_CS0_reserved4_MASK                        0x000000ff
#define BCHP_NAND_CONFIG_CS0_reserved4_SHIFT                       0

/***************************************************************************
 *TIMING_1_CS0 - Nand Flash Timing Parameters 1
 ***************************************************************************/
/* NAND :: TIMING_1_CS0 :: tWP [31:28] */
#define BCHP_NAND_TIMING_1_CS0_tWP_MASK                            0xf0000000
#define BCHP_NAND_TIMING_1_CS0_tWP_SHIFT                           28
#define BCHP_NAND_TIMING_1_CS0_tWP_DEFAULT                         0x00000006

/* NAND :: TIMING_1_CS0 :: tWH [27:24] */
#define BCHP_NAND_TIMING_1_CS0_tWH_MASK                            0x0f000000
#define BCHP_NAND_TIMING_1_CS0_tWH_SHIFT                           24
#define BCHP_NAND_TIMING_1_CS0_tWH_DEFAULT                         0x00000005

/* NAND :: TIMING_1_CS0 :: tRP [23:20] */
#define BCHP_NAND_TIMING_1_CS0_tRP_MASK                            0x00f00000
#define BCHP_NAND_TIMING_1_CS0_tRP_SHIFT                           20
#define BCHP_NAND_TIMING_1_CS0_tRP_DEFAULT                         0x00000007

/* NAND :: TIMING_1_CS0 :: tREH [19:16] */
#define BCHP_NAND_TIMING_1_CS0_tREH_MASK                           0x000f0000
#define BCHP_NAND_TIMING_1_CS0_tREH_SHIFT                          16
#define BCHP_NAND_TIMING_1_CS0_tREH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS0 :: tCS [15:12] */
#define BCHP_NAND_TIMING_1_CS0_tCS_MASK                            0x0000f000
#define BCHP_NAND_TIMING_1_CS0_tCS_SHIFT                           12
#define BCHP_NAND_TIMING_1_CS0_tCS_DEFAULT                         0x00000008

/* NAND :: TIMING_1_CS0 :: tCLH [11:08] */
#define BCHP_NAND_TIMING_1_CS0_tCLH_MASK                           0x00000f00
#define BCHP_NAND_TIMING_1_CS0_tCLH_SHIFT                          8
#define BCHP_NAND_TIMING_1_CS0_tCLH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS0 :: tALH [07:04] */
#define BCHP_NAND_TIMING_1_CS0_tALH_MASK                           0x000000f0
#define BCHP_NAND_TIMING_1_CS0_tALH_SHIFT                          4
#define BCHP_NAND_TIMING_1_CS0_tALH_DEFAULT                        0x00000005

/* NAND :: TIMING_1_CS0 :: tADL [03:00] */
#define BCHP_NAND_TIMING_1_CS0_tADL_MASK                           0x0000000f
#define BCHP_NAND_TIMING_1_CS0_tADL_SHIFT                          0
#define BCHP_NAND_TIMING_1_CS0_tADL_DEFAULT                        0x0000000b

/***************************************************************************
 *TIMING_2_CS0 - Nand Flash Timing Parameters 2
 ***************************************************************************/
/* NAND :: TIMING_2_CS0 :: CLK_SELECT [31:31] */
#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_MASK                     0x80000000
#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_SHIFT                    31
#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_DEFAULT                  0x00000000
#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_108                  0
#define BCHP_NAND_TIMING_2_CS0_CLK_SELECT_CLK_216                  1

/* NAND :: TIMING_2_CS0 :: reserved0 [30:13] */
#define BCHP_NAND_TIMING_2_CS0_reserved0_MASK                      0x7fffe000
#define BCHP_NAND_TIMING_2_CS0_reserved0_SHIFT                     13

/* NAND :: TIMING_2_CS0 :: tWB [12:09] */
#define BCHP_NAND_TIMING_2_CS0_tWB_MASK                            0x00001e00
#define BCHP_NAND_TIMING_2_CS0_tWB_SHIFT                           9
#define BCHP_NAND_TIMING_2_CS0_tWB_DEFAULT                         0x0000000f

/* NAND :: TIMING_2_CS0 :: tWHR [08:04] */
#define BCHP_NAND_TIMING_2_CS0_tWHR_MASK                           0x000001f0
#define BCHP_NAND_TIMING_2_CS0_tWHR_SHIFT                          4
#define BCHP_NAND_TIMING_2_CS0_tWHR_DEFAULT                        0x00000009

/* NAND :: TIMING_2_CS0 :: tREAD [03:00] */
#define BCHP_NAND_TIMING_2_CS0_tREAD_MASK                          0x0000000f
#define BCHP_NAND_TIMING_2_CS0_tREAD_SHIFT                         0
#define BCHP_NAND_TIMING_2_CS0_tREAD_DEFAULT                       0x00000006

/***************************************************************************
 *ACC_CONTROL_CS1 - Nand Flash Access Control
 ***************************************************************************/
/* NAND :: ACC_CONTROL_CS1 :: RD_ECC_EN [31:31] */
#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_MASK                   0x80000000
#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_SHIFT                  31
#define BCHP_NAND_ACC_CONTROL_CS1_RD_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS1 :: WR_ECC_EN [30:30] */
#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_MASK                   0x40000000
#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_SHIFT                  30
#define BCHP_NAND_ACC_CONTROL_CS1_WR_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS1 :: CE_CARE [29:29] */
#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_MASK                     0x20000000
#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_SHIFT                    29
#define BCHP_NAND_ACC_CONTROL_CS1_CE_CARE_DEFAULT                  0x00000000

/* NAND :: ACC_CONTROL_CS1 :: reserved0 [28:28] */
#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_MASK                   0x10000000
#define BCHP_NAND_ACC_CONTROL_CS1_reserved0_SHIFT                  28

/* NAND :: ACC_CONTROL_CS1 :: RD_ERASED_ECC_EN [27:27] */
#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_MASK            0x08000000
#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_SHIFT           27
#define BCHP_NAND_ACC_CONTROL_CS1_RD_ERASED_ECC_EN_DEFAULT         0x00000000

/* NAND :: ACC_CONTROL_CS1 :: PARTIAL_PAGE_EN [26:26] */
#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_MASK             0x04000000
#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_SHIFT            26
#define BCHP_NAND_ACC_CONTROL_CS1_PARTIAL_PAGE_EN_DEFAULT          0x00000000

/* NAND :: ACC_CONTROL_CS1 :: WR_PREEMPT_EN [25:25] */
#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_MASK               0x02000000
#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_SHIFT              25
#define BCHP_NAND_ACC_CONTROL_CS1_WR_PREEMPT_EN_DEFAULT            0x00000001

/* NAND :: ACC_CONTROL_CS1 :: PAGE_HIT_EN [24:24] */
#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_MASK                 0x01000000
#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_SHIFT                24
#define BCHP_NAND_ACC_CONTROL_CS1_PAGE_HIT_EN_DEFAULT              0x00000001

/* NAND :: ACC_CONTROL_CS1 :: PREFETCH_EN [23:23] */
#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_MASK                 0x00800000
#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_SHIFT                23
#define BCHP_NAND_ACC_CONTROL_CS1_PREFETCH_EN_DEFAULT              0x00000000

/* NAND :: ACC_CONTROL_CS1 :: CACHE_MODE_EN [22:22] */
#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_MASK               0x00400000
#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_SHIFT              22
#define BCHP_NAND_ACC_CONTROL_CS1_CACHE_MODE_EN_DEFAULT            0x00000000

/* NAND :: ACC_CONTROL_CS1 :: reserved1 [21:21] */
#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_MASK                   0x00200000
#define BCHP_NAND_ACC_CONTROL_CS1_reserved1_SHIFT                  21

/* NAND :: ACC_CONTROL_CS1 :: ECC_LEVEL [20:16] */
#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_MASK                   0x001f0000
#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_SHIFT                  16
#define BCHP_NAND_ACC_CONTROL_CS1_ECC_LEVEL_DEFAULT                0x0000000f

/* NAND :: ACC_CONTROL_CS1 :: reserved2 [15:08] */
#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_MASK                   0x0000ff00
#define BCHP_NAND_ACC_CONTROL_CS1_reserved2_SHIFT                  8

/* NAND :: ACC_CONTROL_CS1 :: SECTOR_SIZE_1K [07:07] */
#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_MASK              0x00000080
#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_SHIFT             7
#define BCHP_NAND_ACC_CONTROL_CS1_SECTOR_SIZE_1K_DEFAULT           0x00000000

/* NAND :: ACC_CONTROL_CS1 :: SPARE_AREA_SIZE [06:00] */
#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_MASK             0x0000007f
#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_SHIFT            0
#define BCHP_NAND_ACC_CONTROL_CS1_SPARE_AREA_SIZE_DEFAULT          0x00000010

/***************************************************************************
 *CONFIG_CS1 - Nand Flash Config
 ***************************************************************************/
/* NAND :: CONFIG_CS1 :: CONFIG_LOCK [31:31] */
#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_MASK                      0x80000000
#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_SHIFT                     31
#define BCHP_NAND_CONFIG_CS1_CONFIG_LOCK_DEFAULT                   0x00000000

/* NAND :: CONFIG_CS1 :: BLOCK_SIZE [30:28] */
#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_MASK                       0x70000000
#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_SHIFT                      28
#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_2048KB             6
#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_1024KB             5
#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_512KB              4
#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_256KB              3
#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_128KB              2
#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_16KB               1
#define BCHP_NAND_CONFIG_CS1_BLOCK_SIZE_BK_SIZE_8KB                0

/* NAND :: CONFIG_CS1 :: DEVICE_SIZE [27:24] */
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_MASK                      0x0f000000
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_SHIFT                     24
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4MB              0
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8MB              1
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16MB             2
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32MB             3
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64MB             4
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128MB            5
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_256MB            6
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_512MB            7
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_1GB              8
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_2GB              9
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_4GB              10
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_8GB              11
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_16GB             12
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_32GB             13
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_64GB             14
#define BCHP_NAND_CONFIG_CS1_DEVICE_SIZE_DVC_SIZE_128GB            15

/* NAND :: CONFIG_CS1 :: DEVICE_WIDTH [23:23] */
#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_MASK                     0x00800000
#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_SHIFT                    23
#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_8              0
#define BCHP_NAND_CONFIG_CS1_DEVICE_WIDTH_DVC_WIDTH_16             1

/* NAND :: CONFIG_CS1 :: reserved0 [22:22] */
#define BCHP_NAND_CONFIG_CS1_reserved0_MASK                        0x00400000
#define BCHP_NAND_CONFIG_CS1_reserved0_SHIFT                       22

/* NAND :: CONFIG_CS1 :: PAGE_SIZE [21:20] */
#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_MASK                        0x00300000
#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_SHIFT                       20
#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_512                 0
#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_2KB                 1
#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_4KB                 2
#define BCHP_NAND_CONFIG_CS1_PAGE_SIZE_PG_SIZE_8KB                 3

/* NAND :: CONFIG_CS1 :: reserved1 [19:19] */
#define BCHP_NAND_CONFIG_CS1_reserved1_MASK                        0x00080000
#define BCHP_NAND_CONFIG_CS1_reserved1_SHIFT                       19

/* NAND :: CONFIG_CS1 :: FUL_ADR_BYTES [18:16] */
#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_MASK                    0x00070000
#define BCHP_NAND_CONFIG_CS1_FUL_ADR_BYTES_SHIFT                   16

/* NAND :: CONFIG_CS1 :: reserved2 [15:15] */
#define BCHP_NAND_CONFIG_CS1_reserved2_MASK                        0x00008000
#define BCHP_NAND_CONFIG_CS1_reserved2_SHIFT                       15

/* NAND :: CONFIG_CS1 :: COL_ADR_BYTES [14:12] */
#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_MASK                    0x00007000
#define BCHP_NAND_CONFIG_CS1_COL_ADR_BYTES_SHIFT                   12

/* NAND :: CONFIG_CS1 :: reserved3 [11:11] */
#define BCHP_NAND_CONFIG_CS1_reserved3_MASK                        0x00000800
#define BCHP_NAND_CONFIG_CS1_reserved3_SHIFT                       11

/* NAND :: CONFIG_CS1 :: BLK_ADR_BYTES [10:08] */
#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_MASK                    0x00000700
#define BCHP_NAND_CONFIG_CS1_BLK_ADR_BYTES_SHIFT                   8

/* NAND :: CONFIG_CS1 :: reserved4 [07:00] */
#define BCHP_NAND_CONFIG_CS1_reserved4_MASK                        0x000000ff
#define BCHP_NAND_CONFIG_CS1_reserved4_SHIFT                       0

/***************************************************************************
 *TIMING_1_CS1 - Nand Flash Timing Parameters 1
 ***************************************************************************/
/* NAND :: TIMING_1_CS1 :: tWP [31:28] */
#define BCHP_NAND_TIMING_1_CS1_tWP_MASK                            0xf0000000
#define BCHP_NAND_TIMING_1_CS1_tWP_SHIFT                           28
#define BCHP_NAND_TIMING_1_CS1_tWP_DEFAULT                         0x00000006

/* NAND :: TIMING_1_CS1 :: tWH [27:24] */
#define BCHP_NAND_TIMING_1_CS1_tWH_MASK                            0x0f000000
#define BCHP_NAND_TIMING_1_CS1_tWH_SHIFT                           24
#define BCHP_NAND_TIMING_1_CS1_tWH_DEFAULT                         0x00000005

/* NAND :: TIMING_1_CS1 :: tRP [23:20] */
#define BCHP_NAND_TIMING_1_CS1_tRP_MASK                            0x00f00000
#define BCHP_NAND_TIMING_1_CS1_tRP_SHIFT                           20
#define BCHP_NAND_TIMING_1_CS1_tRP_DEFAULT                         0x00000007

/* NAND :: TIMING_1_CS1 :: tREH [19:16] */
#define BCHP_NAND_TIMING_1_CS1_tREH_MASK                           0x000f0000
#define BCHP_NAND_TIMING_1_CS1_tREH_SHIFT                          16
#define BCHP_NAND_TIMING_1_CS1_tREH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS1 :: tCS [15:12] */
#define BCHP_NAND_TIMING_1_CS1_tCS_MASK                            0x0000f000
#define BCHP_NAND_TIMING_1_CS1_tCS_SHIFT                           12
#define BCHP_NAND_TIMING_1_CS1_tCS_DEFAULT                         0x00000008

/* NAND :: TIMING_1_CS1 :: tCLH [11:08] */
#define BCHP_NAND_TIMING_1_CS1_tCLH_MASK                           0x00000f00
#define BCHP_NAND_TIMING_1_CS1_tCLH_SHIFT                          8
#define BCHP_NAND_TIMING_1_CS1_tCLH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS1 :: tALH [07:04] */
#define BCHP_NAND_TIMING_1_CS1_tALH_MASK                           0x000000f0
#define BCHP_NAND_TIMING_1_CS1_tALH_SHIFT                          4
#define BCHP_NAND_TIMING_1_CS1_tALH_DEFAULT                        0x00000005

/* NAND :: TIMING_1_CS1 :: tADL [03:00] */
#define BCHP_NAND_TIMING_1_CS1_tADL_MASK                           0x0000000f
#define BCHP_NAND_TIMING_1_CS1_tADL_SHIFT                          0
#define BCHP_NAND_TIMING_1_CS1_tADL_DEFAULT                        0x0000000b

/***************************************************************************
 *TIMING_2_CS1 - Nand Flash Timing Parameters 2
 ***************************************************************************/
/* NAND :: TIMING_2_CS1 :: CLK_SELECT [31:31] */
#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_MASK                     0x80000000
#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_SHIFT                    31
#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_DEFAULT                  0x00000000
#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_108                  0
#define BCHP_NAND_TIMING_2_CS1_CLK_SELECT_CLK_216                  1

/* NAND :: TIMING_2_CS1 :: reserved0 [30:13] */
#define BCHP_NAND_TIMING_2_CS1_reserved0_MASK                      0x7fffe000
#define BCHP_NAND_TIMING_2_CS1_reserved0_SHIFT                     13

/* NAND :: TIMING_2_CS1 :: tWB [12:09] */
#define BCHP_NAND_TIMING_2_CS1_tWB_MASK                            0x00001e00
#define BCHP_NAND_TIMING_2_CS1_tWB_SHIFT                           9
#define BCHP_NAND_TIMING_2_CS1_tWB_DEFAULT                         0x0000000f

/* NAND :: TIMING_2_CS1 :: tWHR [08:04] */
#define BCHP_NAND_TIMING_2_CS1_tWHR_MASK                           0x000001f0
#define BCHP_NAND_TIMING_2_CS1_tWHR_SHIFT                          4
#define BCHP_NAND_TIMING_2_CS1_tWHR_DEFAULT                        0x00000009

/* NAND :: TIMING_2_CS1 :: tREAD [03:00] */
#define BCHP_NAND_TIMING_2_CS1_tREAD_MASK                          0x0000000f
#define BCHP_NAND_TIMING_2_CS1_tREAD_SHIFT                         0
#define BCHP_NAND_TIMING_2_CS1_tREAD_DEFAULT                       0x00000006

/***************************************************************************
 *ACC_CONTROL_CS2 - Nand Flash Access Control
 ***************************************************************************/
/* NAND :: ACC_CONTROL_CS2 :: RD_ECC_EN [31:31] */
#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_MASK                   0x80000000
#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_SHIFT                  31
#define BCHP_NAND_ACC_CONTROL_CS2_RD_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS2 :: WR_ECC_EN [30:30] */
#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_MASK                   0x40000000
#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_SHIFT                  30
#define BCHP_NAND_ACC_CONTROL_CS2_WR_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS2 :: CE_CARE [29:29] */
#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_MASK                     0x20000000
#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_SHIFT                    29
#define BCHP_NAND_ACC_CONTROL_CS2_CE_CARE_DEFAULT                  0x00000000

/* NAND :: ACC_CONTROL_CS2 :: reserved0 [28:28] */
#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_MASK                   0x10000000
#define BCHP_NAND_ACC_CONTROL_CS2_reserved0_SHIFT                  28

/* NAND :: ACC_CONTROL_CS2 :: RD_ERASED_ECC_EN [27:27] */
#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_MASK            0x08000000
#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_SHIFT           27
#define BCHP_NAND_ACC_CONTROL_CS2_RD_ERASED_ECC_EN_DEFAULT         0x00000000

/* NAND :: ACC_CONTROL_CS2 :: PARTIAL_PAGE_EN [26:26] */
#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_MASK             0x04000000
#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_SHIFT            26
#define BCHP_NAND_ACC_CONTROL_CS2_PARTIAL_PAGE_EN_DEFAULT          0x00000000

/* NAND :: ACC_CONTROL_CS2 :: WR_PREEMPT_EN [25:25] */
#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_MASK               0x02000000
#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_SHIFT              25
#define BCHP_NAND_ACC_CONTROL_CS2_WR_PREEMPT_EN_DEFAULT            0x00000001

/* NAND :: ACC_CONTROL_CS2 :: PAGE_HIT_EN [24:24] */
#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_MASK                 0x01000000
#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_SHIFT                24
#define BCHP_NAND_ACC_CONTROL_CS2_PAGE_HIT_EN_DEFAULT              0x00000001

/* NAND :: ACC_CONTROL_CS2 :: PREFETCH_EN [23:23] */
#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_MASK                 0x00800000
#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_SHIFT                23
#define BCHP_NAND_ACC_CONTROL_CS2_PREFETCH_EN_DEFAULT              0x00000000

/* NAND :: ACC_CONTROL_CS2 :: CACHE_MODE_EN [22:22] */
#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_MASK               0x00400000
#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_SHIFT              22
#define BCHP_NAND_ACC_CONTROL_CS2_CACHE_MODE_EN_DEFAULT            0x00000000

/* NAND :: ACC_CONTROL_CS2 :: reserved1 [21:21] */
#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_MASK                   0x00200000
#define BCHP_NAND_ACC_CONTROL_CS2_reserved1_SHIFT                  21

/* NAND :: ACC_CONTROL_CS2 :: ECC_LEVEL [20:16] */
#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_MASK                   0x001f0000
#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_SHIFT                  16
#define BCHP_NAND_ACC_CONTROL_CS2_ECC_LEVEL_DEFAULT                0x0000000f

/* NAND :: ACC_CONTROL_CS2 :: reserved2 [15:08] */
#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_MASK                   0x0000ff00
#define BCHP_NAND_ACC_CONTROL_CS2_reserved2_SHIFT                  8

/* NAND :: ACC_CONTROL_CS2 :: SECTOR_SIZE_1K [07:07] */
#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_MASK              0x00000080
#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_SHIFT             7
#define BCHP_NAND_ACC_CONTROL_CS2_SECTOR_SIZE_1K_DEFAULT           0x00000000

/* NAND :: ACC_CONTROL_CS2 :: SPARE_AREA_SIZE [06:00] */
#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_MASK             0x0000007f
#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_SHIFT            0
#define BCHP_NAND_ACC_CONTROL_CS2_SPARE_AREA_SIZE_DEFAULT          0x00000010

/***************************************************************************
 *CONFIG_CS2 - Nand Flash Config
 ***************************************************************************/
/* NAND :: CONFIG_CS2 :: CONFIG_LOCK [31:31] */
#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_MASK                      0x80000000
#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_SHIFT                     31
#define BCHP_NAND_CONFIG_CS2_CONFIG_LOCK_DEFAULT                   0x00000000

/* NAND :: CONFIG_CS2 :: BLOCK_SIZE [30:28] */
#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_MASK                       0x70000000
#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_SHIFT                      28
#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_2048KB             6
#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_1024KB             5
#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_512KB              4
#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_256KB              3
#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_128KB              2
#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_16KB               1
#define BCHP_NAND_CONFIG_CS2_BLOCK_SIZE_BK_SIZE_8KB                0

/* NAND :: CONFIG_CS2 :: DEVICE_SIZE [27:24] */
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_MASK                      0x0f000000
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_SHIFT                     24
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4MB              0
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8MB              1
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16MB             2
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32MB             3
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64MB             4
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128MB            5
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_256MB            6
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_512MB            7
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_1GB              8
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_2GB              9
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_4GB              10
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_8GB              11
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_16GB             12
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_32GB             13
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_64GB             14
#define BCHP_NAND_CONFIG_CS2_DEVICE_SIZE_DVC_SIZE_128GB            15

/* NAND :: CONFIG_CS2 :: DEVICE_WIDTH [23:23] */
#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_MASK                     0x00800000
#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_SHIFT                    23
#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_8              0
#define BCHP_NAND_CONFIG_CS2_DEVICE_WIDTH_DVC_WIDTH_16             1

/* NAND :: CONFIG_CS2 :: reserved0 [22:22] */
#define BCHP_NAND_CONFIG_CS2_reserved0_MASK                        0x00400000
#define BCHP_NAND_CONFIG_CS2_reserved0_SHIFT                       22

/* NAND :: CONFIG_CS2 :: PAGE_SIZE [21:20] */
#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_MASK                        0x00300000
#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_SHIFT                       20
#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_512                 0
#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_2KB                 1
#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_4KB                 2
#define BCHP_NAND_CONFIG_CS2_PAGE_SIZE_PG_SIZE_8KB                 3

/* NAND :: CONFIG_CS2 :: reserved1 [19:19] */
#define BCHP_NAND_CONFIG_CS2_reserved1_MASK                        0x00080000
#define BCHP_NAND_CONFIG_CS2_reserved1_SHIFT                       19

/* NAND :: CONFIG_CS2 :: FUL_ADR_BYTES [18:16] */
#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_MASK                    0x00070000
#define BCHP_NAND_CONFIG_CS2_FUL_ADR_BYTES_SHIFT                   16

/* NAND :: CONFIG_CS2 :: reserved2 [15:15] */
#define BCHP_NAND_CONFIG_CS2_reserved2_MASK                        0x00008000
#define BCHP_NAND_CONFIG_CS2_reserved2_SHIFT                       15

/* NAND :: CONFIG_CS2 :: COL_ADR_BYTES [14:12] */
#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_MASK                    0x00007000
#define BCHP_NAND_CONFIG_CS2_COL_ADR_BYTES_SHIFT                   12

/* NAND :: CONFIG_CS2 :: reserved3 [11:11] */
#define BCHP_NAND_CONFIG_CS2_reserved3_MASK                        0x00000800
#define BCHP_NAND_CONFIG_CS2_reserved3_SHIFT                       11

/* NAND :: CONFIG_CS2 :: BLK_ADR_BYTES [10:08] */
#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_MASK                    0x00000700
#define BCHP_NAND_CONFIG_CS2_BLK_ADR_BYTES_SHIFT                   8

/* NAND :: CONFIG_CS2 :: reserved4 [07:00] */
#define BCHP_NAND_CONFIG_CS2_reserved4_MASK                        0x000000ff
#define BCHP_NAND_CONFIG_CS2_reserved4_SHIFT                       0

/***************************************************************************
 *TIMING_1_CS2 - Nand Flash Timing Parameters 1
 ***************************************************************************/
/* NAND :: TIMING_1_CS2 :: tWP [31:28] */
#define BCHP_NAND_TIMING_1_CS2_tWP_MASK                            0xf0000000
#define BCHP_NAND_TIMING_1_CS2_tWP_SHIFT                           28
#define BCHP_NAND_TIMING_1_CS2_tWP_DEFAULT                         0x00000006

/* NAND :: TIMING_1_CS2 :: tWH [27:24] */
#define BCHP_NAND_TIMING_1_CS2_tWH_MASK                            0x0f000000
#define BCHP_NAND_TIMING_1_CS2_tWH_SHIFT                           24
#define BCHP_NAND_TIMING_1_CS2_tWH_DEFAULT                         0x00000005

/* NAND :: TIMING_1_CS2 :: tRP [23:20] */
#define BCHP_NAND_TIMING_1_CS2_tRP_MASK                            0x00f00000
#define BCHP_NAND_TIMING_1_CS2_tRP_SHIFT                           20
#define BCHP_NAND_TIMING_1_CS2_tRP_DEFAULT                         0x00000007

/* NAND :: TIMING_1_CS2 :: tREH [19:16] */
#define BCHP_NAND_TIMING_1_CS2_tREH_MASK                           0x000f0000
#define BCHP_NAND_TIMING_1_CS2_tREH_SHIFT                          16
#define BCHP_NAND_TIMING_1_CS2_tREH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS2 :: tCS [15:12] */
#define BCHP_NAND_TIMING_1_CS2_tCS_MASK                            0x0000f000
#define BCHP_NAND_TIMING_1_CS2_tCS_SHIFT                           12
#define BCHP_NAND_TIMING_1_CS2_tCS_DEFAULT                         0x00000008

/* NAND :: TIMING_1_CS2 :: tCLH [11:08] */
#define BCHP_NAND_TIMING_1_CS2_tCLH_MASK                           0x00000f00
#define BCHP_NAND_TIMING_1_CS2_tCLH_SHIFT                          8
#define BCHP_NAND_TIMING_1_CS2_tCLH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS2 :: tALH [07:04] */
#define BCHP_NAND_TIMING_1_CS2_tALH_MASK                           0x000000f0
#define BCHP_NAND_TIMING_1_CS2_tALH_SHIFT                          4
#define BCHP_NAND_TIMING_1_CS2_tALH_DEFAULT                        0x00000005

/* NAND :: TIMING_1_CS2 :: tADL [03:00] */
#define BCHP_NAND_TIMING_1_CS2_tADL_MASK                           0x0000000f
#define BCHP_NAND_TIMING_1_CS2_tADL_SHIFT                          0
#define BCHP_NAND_TIMING_1_CS2_tADL_DEFAULT                        0x0000000b

/***************************************************************************
 *TIMING_2_CS2 - Nand Flash Timing Parameters 2
 ***************************************************************************/
/* NAND :: TIMING_2_CS2 :: CLK_SELECT [31:31] */
#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_MASK                     0x80000000
#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_SHIFT                    31
#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_DEFAULT                  0x00000000
#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_108                  0
#define BCHP_NAND_TIMING_2_CS2_CLK_SELECT_CLK_216                  1

/* NAND :: TIMING_2_CS2 :: reserved0 [30:13] */
#define BCHP_NAND_TIMING_2_CS2_reserved0_MASK                      0x7fffe000
#define BCHP_NAND_TIMING_2_CS2_reserved0_SHIFT                     13

/* NAND :: TIMING_2_CS2 :: tWB [12:09] */
#define BCHP_NAND_TIMING_2_CS2_tWB_MASK                            0x00001e00
#define BCHP_NAND_TIMING_2_CS2_tWB_SHIFT                           9
#define BCHP_NAND_TIMING_2_CS2_tWB_DEFAULT                         0x0000000f

/* NAND :: TIMING_2_CS2 :: tWHR [08:04] */
#define BCHP_NAND_TIMING_2_CS2_tWHR_MASK                           0x000001f0
#define BCHP_NAND_TIMING_2_CS2_tWHR_SHIFT                          4
#define BCHP_NAND_TIMING_2_CS2_tWHR_DEFAULT                        0x00000009

/* NAND :: TIMING_2_CS2 :: tREAD [03:00] */
#define BCHP_NAND_TIMING_2_CS2_tREAD_MASK                          0x0000000f
#define BCHP_NAND_TIMING_2_CS2_tREAD_SHIFT                         0
#define BCHP_NAND_TIMING_2_CS2_tREAD_DEFAULT                       0x00000006

/***************************************************************************
 *ACC_CONTROL_CS3 - Nand Flash Access Control
 ***************************************************************************/
/* NAND :: ACC_CONTROL_CS3 :: RD_ECC_EN [31:31] */
#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_MASK                   0x80000000
#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_SHIFT                  31
#define BCHP_NAND_ACC_CONTROL_CS3_RD_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS3 :: WR_ECC_EN [30:30] */
#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_MASK                   0x40000000
#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_SHIFT                  30
#define BCHP_NAND_ACC_CONTROL_CS3_WR_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS3 :: CE_CARE [29:29] */
#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_MASK                     0x20000000
#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_SHIFT                    29
#define BCHP_NAND_ACC_CONTROL_CS3_CE_CARE_DEFAULT                  0x00000000

/* NAND :: ACC_CONTROL_CS3 :: reserved0 [28:28] */
#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_MASK                   0x10000000
#define BCHP_NAND_ACC_CONTROL_CS3_reserved0_SHIFT                  28

/* NAND :: ACC_CONTROL_CS3 :: RD_ERASED_ECC_EN [27:27] */
#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_MASK            0x08000000
#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_SHIFT           27
#define BCHP_NAND_ACC_CONTROL_CS3_RD_ERASED_ECC_EN_DEFAULT         0x00000000

/* NAND :: ACC_CONTROL_CS3 :: PARTIAL_PAGE_EN [26:26] */
#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_MASK             0x04000000
#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_SHIFT            26
#define BCHP_NAND_ACC_CONTROL_CS3_PARTIAL_PAGE_EN_DEFAULT          0x00000000

/* NAND :: ACC_CONTROL_CS3 :: WR_PREEMPT_EN [25:25] */
#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_MASK               0x02000000
#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_SHIFT              25
#define BCHP_NAND_ACC_CONTROL_CS3_WR_PREEMPT_EN_DEFAULT            0x00000001

/* NAND :: ACC_CONTROL_CS3 :: PAGE_HIT_EN [24:24] */
#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_MASK                 0x01000000
#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_SHIFT                24
#define BCHP_NAND_ACC_CONTROL_CS3_PAGE_HIT_EN_DEFAULT              0x00000001

/* NAND :: ACC_CONTROL_CS3 :: PREFETCH_EN [23:23] */
#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_MASK                 0x00800000
#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_SHIFT                23
#define BCHP_NAND_ACC_CONTROL_CS3_PREFETCH_EN_DEFAULT              0x00000000

/* NAND :: ACC_CONTROL_CS3 :: CACHE_MODE_EN [22:22] */
#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_MASK               0x00400000
#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_SHIFT              22
#define BCHP_NAND_ACC_CONTROL_CS3_CACHE_MODE_EN_DEFAULT            0x00000000

/* NAND :: ACC_CONTROL_CS3 :: reserved1 [21:21] */
#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_MASK                   0x00200000
#define BCHP_NAND_ACC_CONTROL_CS3_reserved1_SHIFT                  21

/* NAND :: ACC_CONTROL_CS3 :: ECC_LEVEL [20:16] */
#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_MASK                   0x001f0000
#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_SHIFT                  16
#define BCHP_NAND_ACC_CONTROL_CS3_ECC_LEVEL_DEFAULT                0x0000000f

/* NAND :: ACC_CONTROL_CS3 :: reserved2 [15:08] */
#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_MASK                   0x0000ff00
#define BCHP_NAND_ACC_CONTROL_CS3_reserved2_SHIFT                  8

/* NAND :: ACC_CONTROL_CS3 :: SECTOR_SIZE_1K [07:07] */
#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_MASK              0x00000080
#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_SHIFT             7
#define BCHP_NAND_ACC_CONTROL_CS3_SECTOR_SIZE_1K_DEFAULT           0x00000000

/* NAND :: ACC_CONTROL_CS3 :: SPARE_AREA_SIZE [06:00] */
#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_MASK             0x0000007f
#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_SHIFT            0
#define BCHP_NAND_ACC_CONTROL_CS3_SPARE_AREA_SIZE_DEFAULT          0x00000010

/***************************************************************************
 *CONFIG_CS3 - Nand Flash Config
 ***************************************************************************/
/* NAND :: CONFIG_CS3 :: CONFIG_LOCK [31:31] */
#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_MASK                      0x80000000
#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_SHIFT                     31
#define BCHP_NAND_CONFIG_CS3_CONFIG_LOCK_DEFAULT                   0x00000000

/* NAND :: CONFIG_CS3 :: BLOCK_SIZE [30:28] */
#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_MASK                       0x70000000
#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_SHIFT                      28
#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_2048KB             6
#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_1024KB             5
#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_512KB              4
#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_256KB              3
#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_128KB              2
#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_16KB               1
#define BCHP_NAND_CONFIG_CS3_BLOCK_SIZE_BK_SIZE_8KB                0

/* NAND :: CONFIG_CS3 :: DEVICE_SIZE [27:24] */
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_MASK                      0x0f000000
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_SHIFT                     24
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4MB              0
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8MB              1
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16MB             2
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32MB             3
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64MB             4
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128MB            5
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_256MB            6
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_512MB            7
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_1GB              8
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_2GB              9
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_4GB              10
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_8GB              11
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_16GB             12
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_32GB             13
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_64GB             14
#define BCHP_NAND_CONFIG_CS3_DEVICE_SIZE_DVC_SIZE_128GB            15

/* NAND :: CONFIG_CS3 :: DEVICE_WIDTH [23:23] */
#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_MASK                     0x00800000
#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_SHIFT                    23
#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_8              0
#define BCHP_NAND_CONFIG_CS3_DEVICE_WIDTH_DVC_WIDTH_16             1

/* NAND :: CONFIG_CS3 :: reserved0 [22:22] */
#define BCHP_NAND_CONFIG_CS3_reserved0_MASK                        0x00400000
#define BCHP_NAND_CONFIG_CS3_reserved0_SHIFT                       22

/* NAND :: CONFIG_CS3 :: PAGE_SIZE [21:20] */
#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_MASK                        0x00300000
#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_SHIFT                       20
#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_512                 0
#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_2KB                 1
#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_4KB                 2
#define BCHP_NAND_CONFIG_CS3_PAGE_SIZE_PG_SIZE_8KB                 3

/* NAND :: CONFIG_CS3 :: reserved1 [19:19] */
#define BCHP_NAND_CONFIG_CS3_reserved1_MASK                        0x00080000
#define BCHP_NAND_CONFIG_CS3_reserved1_SHIFT                       19

/* NAND :: CONFIG_CS3 :: FUL_ADR_BYTES [18:16] */
#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_MASK                    0x00070000
#define BCHP_NAND_CONFIG_CS3_FUL_ADR_BYTES_SHIFT                   16

/* NAND :: CONFIG_CS3 :: reserved2 [15:15] */
#define BCHP_NAND_CONFIG_CS3_reserved2_MASK                        0x00008000
#define BCHP_NAND_CONFIG_CS3_reserved2_SHIFT                       15

/* NAND :: CONFIG_CS3 :: COL_ADR_BYTES [14:12] */
#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_MASK                    0x00007000
#define BCHP_NAND_CONFIG_CS3_COL_ADR_BYTES_SHIFT                   12

/* NAND :: CONFIG_CS3 :: reserved3 [11:11] */
#define BCHP_NAND_CONFIG_CS3_reserved3_MASK                        0x00000800
#define BCHP_NAND_CONFIG_CS3_reserved3_SHIFT                       11

/* NAND :: CONFIG_CS3 :: BLK_ADR_BYTES [10:08] */
#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_MASK                    0x00000700
#define BCHP_NAND_CONFIG_CS3_BLK_ADR_BYTES_SHIFT                   8

/* NAND :: CONFIG_CS3 :: reserved4 [07:00] */
#define BCHP_NAND_CONFIG_CS3_reserved4_MASK                        0x000000ff
#define BCHP_NAND_CONFIG_CS3_reserved4_SHIFT                       0

/***************************************************************************
 *TIMING_1_CS3 - Nand Flash Timing Parameters 1
 ***************************************************************************/
/* NAND :: TIMING_1_CS3 :: tWP [31:28] */
#define BCHP_NAND_TIMING_1_CS3_tWP_MASK                            0xf0000000
#define BCHP_NAND_TIMING_1_CS3_tWP_SHIFT                           28
#define BCHP_NAND_TIMING_1_CS3_tWP_DEFAULT                         0x00000006

/* NAND :: TIMING_1_CS3 :: tWH [27:24] */
#define BCHP_NAND_TIMING_1_CS3_tWH_MASK                            0x0f000000
#define BCHP_NAND_TIMING_1_CS3_tWH_SHIFT                           24
#define BCHP_NAND_TIMING_1_CS3_tWH_DEFAULT                         0x00000005

/* NAND :: TIMING_1_CS3 :: tRP [23:20] */
#define BCHP_NAND_TIMING_1_CS3_tRP_MASK                            0x00f00000
#define BCHP_NAND_TIMING_1_CS3_tRP_SHIFT                           20
#define BCHP_NAND_TIMING_1_CS3_tRP_DEFAULT                         0x00000007

/* NAND :: TIMING_1_CS3 :: tREH [19:16] */
#define BCHP_NAND_TIMING_1_CS3_tREH_MASK                           0x000f0000
#define BCHP_NAND_TIMING_1_CS3_tREH_SHIFT                          16
#define BCHP_NAND_TIMING_1_CS3_tREH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS3 :: tCS [15:12] */
#define BCHP_NAND_TIMING_1_CS3_tCS_MASK                            0x0000f000
#define BCHP_NAND_TIMING_1_CS3_tCS_SHIFT                           12
#define BCHP_NAND_TIMING_1_CS3_tCS_DEFAULT                         0x00000008

/* NAND :: TIMING_1_CS3 :: tCLH [11:08] */
#define BCHP_NAND_TIMING_1_CS3_tCLH_MASK                           0x00000f00
#define BCHP_NAND_TIMING_1_CS3_tCLH_SHIFT                          8
#define BCHP_NAND_TIMING_1_CS3_tCLH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS3 :: tALH [07:04] */
#define BCHP_NAND_TIMING_1_CS3_tALH_MASK                           0x000000f0
#define BCHP_NAND_TIMING_1_CS3_tALH_SHIFT                          4
#define BCHP_NAND_TIMING_1_CS3_tALH_DEFAULT                        0x00000005

/* NAND :: TIMING_1_CS3 :: tADL [03:00] */
#define BCHP_NAND_TIMING_1_CS3_tADL_MASK                           0x0000000f
#define BCHP_NAND_TIMING_1_CS3_tADL_SHIFT                          0
#define BCHP_NAND_TIMING_1_CS3_tADL_DEFAULT                        0x0000000b

/***************************************************************************
 *TIMING_2_CS3 - Nand Flash Timing Parameters 2
 ***************************************************************************/
/* NAND :: TIMING_2_CS3 :: CLK_SELECT [31:31] */
#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_MASK                     0x80000000
#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_SHIFT                    31
#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_DEFAULT                  0x00000000
#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_108                  0
#define BCHP_NAND_TIMING_2_CS3_CLK_SELECT_CLK_216                  1

/* NAND :: TIMING_2_CS3 :: reserved0 [30:13] */
#define BCHP_NAND_TIMING_2_CS3_reserved0_MASK                      0x7fffe000
#define BCHP_NAND_TIMING_2_CS3_reserved0_SHIFT                     13

/* NAND :: TIMING_2_CS3 :: tWB [12:09] */
#define BCHP_NAND_TIMING_2_CS3_tWB_MASK                            0x00001e00
#define BCHP_NAND_TIMING_2_CS3_tWB_SHIFT                           9
#define BCHP_NAND_TIMING_2_CS3_tWB_DEFAULT                         0x0000000f

/* NAND :: TIMING_2_CS3 :: tWHR [08:04] */
#define BCHP_NAND_TIMING_2_CS3_tWHR_MASK                           0x000001f0
#define BCHP_NAND_TIMING_2_CS3_tWHR_SHIFT                          4
#define BCHP_NAND_TIMING_2_CS3_tWHR_DEFAULT                        0x00000009

/* NAND :: TIMING_2_CS3 :: tREAD [03:00] */
#define BCHP_NAND_TIMING_2_CS3_tREAD_MASK                          0x0000000f
#define BCHP_NAND_TIMING_2_CS3_tREAD_SHIFT                         0
#define BCHP_NAND_TIMING_2_CS3_tREAD_DEFAULT                       0x00000006

/***************************************************************************
 *ACC_CONTROL_CS4 - Nand Flash Access Control
 ***************************************************************************/
/* NAND :: ACC_CONTROL_CS4 :: RD_ECC_EN [31:31] */
#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_MASK                   0x80000000
#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_SHIFT                  31
#define BCHP_NAND_ACC_CONTROL_CS4_RD_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS4 :: WR_ECC_EN [30:30] */
#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_MASK                   0x40000000
#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_SHIFT                  30
#define BCHP_NAND_ACC_CONTROL_CS4_WR_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS4 :: CE_CARE [29:29] */
#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_MASK                     0x20000000
#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_SHIFT                    29
#define BCHP_NAND_ACC_CONTROL_CS4_CE_CARE_DEFAULT                  0x00000000

/* NAND :: ACC_CONTROL_CS4 :: reserved0 [28:28] */
#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_MASK                   0x10000000
#define BCHP_NAND_ACC_CONTROL_CS4_reserved0_SHIFT                  28

/* NAND :: ACC_CONTROL_CS4 :: RD_ERASED_ECC_EN [27:27] */
#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_MASK            0x08000000
#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_SHIFT           27
#define BCHP_NAND_ACC_CONTROL_CS4_RD_ERASED_ECC_EN_DEFAULT         0x00000000

/* NAND :: ACC_CONTROL_CS4 :: PARTIAL_PAGE_EN [26:26] */
#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_MASK             0x04000000
#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_SHIFT            26
#define BCHP_NAND_ACC_CONTROL_CS4_PARTIAL_PAGE_EN_DEFAULT          0x00000000

/* NAND :: ACC_CONTROL_CS4 :: WR_PREEMPT_EN [25:25] */
#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_MASK               0x02000000
#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_SHIFT              25
#define BCHP_NAND_ACC_CONTROL_CS4_WR_PREEMPT_EN_DEFAULT            0x00000001

/* NAND :: ACC_CONTROL_CS4 :: PAGE_HIT_EN [24:24] */
#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_MASK                 0x01000000
#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_SHIFT                24
#define BCHP_NAND_ACC_CONTROL_CS4_PAGE_HIT_EN_DEFAULT              0x00000001

/* NAND :: ACC_CONTROL_CS4 :: PREFETCH_EN [23:23] */
#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_MASK                 0x00800000
#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_SHIFT                23
#define BCHP_NAND_ACC_CONTROL_CS4_PREFETCH_EN_DEFAULT              0x00000000

/* NAND :: ACC_CONTROL_CS4 :: CACHE_MODE_EN [22:22] */
#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_MASK               0x00400000
#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_SHIFT              22
#define BCHP_NAND_ACC_CONTROL_CS4_CACHE_MODE_EN_DEFAULT            0x00000000

/* NAND :: ACC_CONTROL_CS4 :: reserved1 [21:21] */
#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_MASK                   0x00200000
#define BCHP_NAND_ACC_CONTROL_CS4_reserved1_SHIFT                  21

/* NAND :: ACC_CONTROL_CS4 :: ECC_LEVEL [20:16] */
#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_MASK                   0x001f0000
#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_SHIFT                  16
#define BCHP_NAND_ACC_CONTROL_CS4_ECC_LEVEL_DEFAULT                0x0000000f

/* NAND :: ACC_CONTROL_CS4 :: reserved2 [15:08] */
#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_MASK                   0x0000ff00
#define BCHP_NAND_ACC_CONTROL_CS4_reserved2_SHIFT                  8

/* NAND :: ACC_CONTROL_CS4 :: SECTOR_SIZE_1K [07:07] */
#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_MASK              0x00000080
#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_SHIFT             7
#define BCHP_NAND_ACC_CONTROL_CS4_SECTOR_SIZE_1K_DEFAULT           0x00000000

/* NAND :: ACC_CONTROL_CS4 :: SPARE_AREA_SIZE [06:00] */
#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_MASK             0x0000007f
#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_SHIFT            0
#define BCHP_NAND_ACC_CONTROL_CS4_SPARE_AREA_SIZE_DEFAULT          0x00000010

/***************************************************************************
 *CONFIG_CS4 - Nand Flash Config
 ***************************************************************************/
/* NAND :: CONFIG_CS4 :: CONFIG_LOCK [31:31] */
#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_MASK                      0x80000000
#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_SHIFT                     31
#define BCHP_NAND_CONFIG_CS4_CONFIG_LOCK_DEFAULT                   0x00000000

/* NAND :: CONFIG_CS4 :: BLOCK_SIZE [30:28] */
#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_MASK                       0x70000000
#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_SHIFT                      28
#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_2048KB             6
#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_1024KB             5
#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_512KB              4
#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_256KB              3
#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_128KB              2
#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_16KB               1
#define BCHP_NAND_CONFIG_CS4_BLOCK_SIZE_BK_SIZE_8KB                0

/* NAND :: CONFIG_CS4 :: DEVICE_SIZE [27:24] */
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_MASK                      0x0f000000
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_SHIFT                     24
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4MB              0
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8MB              1
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16MB             2
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32MB             3
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64MB             4
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128MB            5
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_256MB            6
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_512MB            7
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_1GB              8
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_2GB              9
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_4GB              10
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_8GB              11
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_16GB             12
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_32GB             13
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_64GB             14
#define BCHP_NAND_CONFIG_CS4_DEVICE_SIZE_DVC_SIZE_128GB            15

/* NAND :: CONFIG_CS4 :: DEVICE_WIDTH [23:23] */
#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_MASK                     0x00800000
#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_SHIFT                    23
#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_8              0
#define BCHP_NAND_CONFIG_CS4_DEVICE_WIDTH_DVC_WIDTH_16             1

/* NAND :: CONFIG_CS4 :: reserved0 [22:22] */
#define BCHP_NAND_CONFIG_CS4_reserved0_MASK                        0x00400000
#define BCHP_NAND_CONFIG_CS4_reserved0_SHIFT                       22

/* NAND :: CONFIG_CS4 :: PAGE_SIZE [21:20] */
#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_MASK                        0x00300000
#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_SHIFT                       20
#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_512                 0
#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_2KB                 1
#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_4KB                 2
#define BCHP_NAND_CONFIG_CS4_PAGE_SIZE_PG_SIZE_8KB                 3

/* NAND :: CONFIG_CS4 :: reserved1 [19:19] */
#define BCHP_NAND_CONFIG_CS4_reserved1_MASK                        0x00080000
#define BCHP_NAND_CONFIG_CS4_reserved1_SHIFT                       19

/* NAND :: CONFIG_CS4 :: FUL_ADR_BYTES [18:16] */
#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_MASK                    0x00070000
#define BCHP_NAND_CONFIG_CS4_FUL_ADR_BYTES_SHIFT                   16

/* NAND :: CONFIG_CS4 :: reserved2 [15:15] */
#define BCHP_NAND_CONFIG_CS4_reserved2_MASK                        0x00008000
#define BCHP_NAND_CONFIG_CS4_reserved2_SHIFT                       15

/* NAND :: CONFIG_CS4 :: COL_ADR_BYTES [14:12] */
#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_MASK                    0x00007000
#define BCHP_NAND_CONFIG_CS4_COL_ADR_BYTES_SHIFT                   12

/* NAND :: CONFIG_CS4 :: reserved3 [11:11] */
#define BCHP_NAND_CONFIG_CS4_reserved3_MASK                        0x00000800
#define BCHP_NAND_CONFIG_CS4_reserved3_SHIFT                       11

/* NAND :: CONFIG_CS4 :: BLK_ADR_BYTES [10:08] */
#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_MASK                    0x00000700
#define BCHP_NAND_CONFIG_CS4_BLK_ADR_BYTES_SHIFT                   8

/* NAND :: CONFIG_CS4 :: reserved4 [07:00] */
#define BCHP_NAND_CONFIG_CS4_reserved4_MASK                        0x000000ff
#define BCHP_NAND_CONFIG_CS4_reserved4_SHIFT                       0

/***************************************************************************
 *TIMING_1_CS4 - Nand Flash Timing Parameters 1
 ***************************************************************************/
/* NAND :: TIMING_1_CS4 :: tWP [31:28] */
#define BCHP_NAND_TIMING_1_CS4_tWP_MASK                            0xf0000000
#define BCHP_NAND_TIMING_1_CS4_tWP_SHIFT                           28
#define BCHP_NAND_TIMING_1_CS4_tWP_DEFAULT                         0x00000006

/* NAND :: TIMING_1_CS4 :: tWH [27:24] */
#define BCHP_NAND_TIMING_1_CS4_tWH_MASK                            0x0f000000
#define BCHP_NAND_TIMING_1_CS4_tWH_SHIFT                           24
#define BCHP_NAND_TIMING_1_CS4_tWH_DEFAULT                         0x00000005

/* NAND :: TIMING_1_CS4 :: tRP [23:20] */
#define BCHP_NAND_TIMING_1_CS4_tRP_MASK                            0x00f00000
#define BCHP_NAND_TIMING_1_CS4_tRP_SHIFT                           20
#define BCHP_NAND_TIMING_1_CS4_tRP_DEFAULT                         0x00000007

/* NAND :: TIMING_1_CS4 :: tREH [19:16] */
#define BCHP_NAND_TIMING_1_CS4_tREH_MASK                           0x000f0000
#define BCHP_NAND_TIMING_1_CS4_tREH_SHIFT                          16
#define BCHP_NAND_TIMING_1_CS4_tREH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS4 :: tCS [15:12] */
#define BCHP_NAND_TIMING_1_CS4_tCS_MASK                            0x0000f000
#define BCHP_NAND_TIMING_1_CS4_tCS_SHIFT                           12
#define BCHP_NAND_TIMING_1_CS4_tCS_DEFAULT                         0x00000008

/* NAND :: TIMING_1_CS4 :: tCLH [11:08] */
#define BCHP_NAND_TIMING_1_CS4_tCLH_MASK                           0x00000f00
#define BCHP_NAND_TIMING_1_CS4_tCLH_SHIFT                          8
#define BCHP_NAND_TIMING_1_CS4_tCLH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS4 :: tALH [07:04] */
#define BCHP_NAND_TIMING_1_CS4_tALH_MASK                           0x000000f0
#define BCHP_NAND_TIMING_1_CS4_tALH_SHIFT                          4
#define BCHP_NAND_TIMING_1_CS4_tALH_DEFAULT                        0x00000005

/* NAND :: TIMING_1_CS4 :: tADL [03:00] */
#define BCHP_NAND_TIMING_1_CS4_tADL_MASK                           0x0000000f
#define BCHP_NAND_TIMING_1_CS4_tADL_SHIFT                          0
#define BCHP_NAND_TIMING_1_CS4_tADL_DEFAULT                        0x0000000b

/***************************************************************************
 *TIMING_2_CS4 - Nand Flash Timing Parameters 2
 ***************************************************************************/
/* NAND :: TIMING_2_CS4 :: CLK_SELECT [31:31] */
#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_MASK                     0x80000000
#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_SHIFT                    31
#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_DEFAULT                  0x00000000
#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_108                  0
#define BCHP_NAND_TIMING_2_CS4_CLK_SELECT_CLK_216                  1

/* NAND :: TIMING_2_CS4 :: reserved0 [30:13] */
#define BCHP_NAND_TIMING_2_CS4_reserved0_MASK                      0x7fffe000
#define BCHP_NAND_TIMING_2_CS4_reserved0_SHIFT                     13

/* NAND :: TIMING_2_CS4 :: tWB [12:09] */
#define BCHP_NAND_TIMING_2_CS4_tWB_MASK                            0x00001e00
#define BCHP_NAND_TIMING_2_CS4_tWB_SHIFT                           9
#define BCHP_NAND_TIMING_2_CS4_tWB_DEFAULT                         0x0000000f

/* NAND :: TIMING_2_CS4 :: tWHR [08:04] */
#define BCHP_NAND_TIMING_2_CS4_tWHR_MASK                           0x000001f0
#define BCHP_NAND_TIMING_2_CS4_tWHR_SHIFT                          4
#define BCHP_NAND_TIMING_2_CS4_tWHR_DEFAULT                        0x00000009

/* NAND :: TIMING_2_CS4 :: tREAD [03:00] */
#define BCHP_NAND_TIMING_2_CS4_tREAD_MASK                          0x0000000f
#define BCHP_NAND_TIMING_2_CS4_tREAD_SHIFT                         0
#define BCHP_NAND_TIMING_2_CS4_tREAD_DEFAULT                       0x00000006

/***************************************************************************
 *ACC_CONTROL_CS5 - Nand Flash Access Control
 ***************************************************************************/
/* NAND :: ACC_CONTROL_CS5 :: RD_ECC_EN [31:31] */
#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_MASK                   0x80000000
#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_SHIFT                  31
#define BCHP_NAND_ACC_CONTROL_CS5_RD_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS5 :: WR_ECC_EN [30:30] */
#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_MASK                   0x40000000
#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_SHIFT                  30
#define BCHP_NAND_ACC_CONTROL_CS5_WR_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS5 :: CE_CARE [29:29] */
#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_MASK                     0x20000000
#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_SHIFT                    29
#define BCHP_NAND_ACC_CONTROL_CS5_CE_CARE_DEFAULT                  0x00000000

/* NAND :: ACC_CONTROL_CS5 :: reserved0 [28:28] */
#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_MASK                   0x10000000
#define BCHP_NAND_ACC_CONTROL_CS5_reserved0_SHIFT                  28

/* NAND :: ACC_CONTROL_CS5 :: RD_ERASED_ECC_EN [27:27] */
#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_MASK            0x08000000
#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_SHIFT           27
#define BCHP_NAND_ACC_CONTROL_CS5_RD_ERASED_ECC_EN_DEFAULT         0x00000000

/* NAND :: ACC_CONTROL_CS5 :: PARTIAL_PAGE_EN [26:26] */
#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_MASK             0x04000000
#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_SHIFT            26
#define BCHP_NAND_ACC_CONTROL_CS5_PARTIAL_PAGE_EN_DEFAULT          0x00000000

/* NAND :: ACC_CONTROL_CS5 :: WR_PREEMPT_EN [25:25] */
#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_MASK               0x02000000
#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_SHIFT              25
#define BCHP_NAND_ACC_CONTROL_CS5_WR_PREEMPT_EN_DEFAULT            0x00000001

/* NAND :: ACC_CONTROL_CS5 :: PAGE_HIT_EN [24:24] */
#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_MASK                 0x01000000
#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_SHIFT                24
#define BCHP_NAND_ACC_CONTROL_CS5_PAGE_HIT_EN_DEFAULT              0x00000001

/* NAND :: ACC_CONTROL_CS5 :: PREFETCH_EN [23:23] */
#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_MASK                 0x00800000
#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_SHIFT                23
#define BCHP_NAND_ACC_CONTROL_CS5_PREFETCH_EN_DEFAULT              0x00000000

/* NAND :: ACC_CONTROL_CS5 :: CACHE_MODE_EN [22:22] */
#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_MASK               0x00400000
#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_SHIFT              22
#define BCHP_NAND_ACC_CONTROL_CS5_CACHE_MODE_EN_DEFAULT            0x00000000

/* NAND :: ACC_CONTROL_CS5 :: reserved1 [21:21] */
#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_MASK                   0x00200000
#define BCHP_NAND_ACC_CONTROL_CS5_reserved1_SHIFT                  21

/* NAND :: ACC_CONTROL_CS5 :: ECC_LEVEL [20:16] */
#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_MASK                   0x001f0000
#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_SHIFT                  16
#define BCHP_NAND_ACC_CONTROL_CS5_ECC_LEVEL_DEFAULT                0x0000000f

/* NAND :: ACC_CONTROL_CS5 :: reserved2 [15:08] */
#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_MASK                   0x0000ff00
#define BCHP_NAND_ACC_CONTROL_CS5_reserved2_SHIFT                  8

/* NAND :: ACC_CONTROL_CS5 :: SECTOR_SIZE_1K [07:07] */
#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_MASK              0x00000080
#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_SHIFT             7
#define BCHP_NAND_ACC_CONTROL_CS5_SECTOR_SIZE_1K_DEFAULT           0x00000000

/* NAND :: ACC_CONTROL_CS5 :: SPARE_AREA_SIZE [06:00] */
#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_MASK             0x0000007f
#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_SHIFT            0
#define BCHP_NAND_ACC_CONTROL_CS5_SPARE_AREA_SIZE_DEFAULT          0x00000010

/***************************************************************************
 *CONFIG_CS5 - Nand Flash Config
 ***************************************************************************/
/* NAND :: CONFIG_CS5 :: CONFIG_LOCK [31:31] */
#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_MASK                      0x80000000
#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_SHIFT                     31
#define BCHP_NAND_CONFIG_CS5_CONFIG_LOCK_DEFAULT                   0x00000000

/* NAND :: CONFIG_CS5 :: BLOCK_SIZE [30:28] */
#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_MASK                       0x70000000
#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_SHIFT                      28
#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_2048KB             6
#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_1024KB             5
#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_512KB              4
#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_256KB              3
#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_128KB              2
#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_16KB               1
#define BCHP_NAND_CONFIG_CS5_BLOCK_SIZE_BK_SIZE_8KB                0

/* NAND :: CONFIG_CS5 :: DEVICE_SIZE [27:24] */
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_MASK                      0x0f000000
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_SHIFT                     24
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4MB              0
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8MB              1
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16MB             2
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32MB             3
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64MB             4
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128MB            5
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_256MB            6
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_512MB            7
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_1GB              8
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_2GB              9
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_4GB              10
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_8GB              11
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_16GB             12
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_32GB             13
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_64GB             14
#define BCHP_NAND_CONFIG_CS5_DEVICE_SIZE_DVC_SIZE_128GB            15

/* NAND :: CONFIG_CS5 :: DEVICE_WIDTH [23:23] */
#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_MASK                     0x00800000
#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_SHIFT                    23
#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_8              0
#define BCHP_NAND_CONFIG_CS5_DEVICE_WIDTH_DVC_WIDTH_16             1

/* NAND :: CONFIG_CS5 :: reserved0 [22:22] */
#define BCHP_NAND_CONFIG_CS5_reserved0_MASK                        0x00400000
#define BCHP_NAND_CONFIG_CS5_reserved0_SHIFT                       22

/* NAND :: CONFIG_CS5 :: PAGE_SIZE [21:20] */
#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_MASK                        0x00300000
#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_SHIFT                       20
#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_512                 0
#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_2KB                 1
#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_4KB                 2
#define BCHP_NAND_CONFIG_CS5_PAGE_SIZE_PG_SIZE_8KB                 3

/* NAND :: CONFIG_CS5 :: reserved1 [19:19] */
#define BCHP_NAND_CONFIG_CS5_reserved1_MASK                        0x00080000
#define BCHP_NAND_CONFIG_CS5_reserved1_SHIFT                       19

/* NAND :: CONFIG_CS5 :: FUL_ADR_BYTES [18:16] */
#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_MASK                    0x00070000
#define BCHP_NAND_CONFIG_CS5_FUL_ADR_BYTES_SHIFT                   16

/* NAND :: CONFIG_CS5 :: reserved2 [15:15] */
#define BCHP_NAND_CONFIG_CS5_reserved2_MASK                        0x00008000
#define BCHP_NAND_CONFIG_CS5_reserved2_SHIFT                       15

/* NAND :: CONFIG_CS5 :: COL_ADR_BYTES [14:12] */
#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_MASK                    0x00007000
#define BCHP_NAND_CONFIG_CS5_COL_ADR_BYTES_SHIFT                   12

/* NAND :: CONFIG_CS5 :: reserved3 [11:11] */
#define BCHP_NAND_CONFIG_CS5_reserved3_MASK                        0x00000800
#define BCHP_NAND_CONFIG_CS5_reserved3_SHIFT                       11

/* NAND :: CONFIG_CS5 :: BLK_ADR_BYTES [10:08] */
#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_MASK                    0x00000700
#define BCHP_NAND_CONFIG_CS5_BLK_ADR_BYTES_SHIFT                   8

/* NAND :: CONFIG_CS5 :: reserved4 [07:00] */
#define BCHP_NAND_CONFIG_CS5_reserved4_MASK                        0x000000ff
#define BCHP_NAND_CONFIG_CS5_reserved4_SHIFT                       0

/***************************************************************************
 *TIMING_1_CS5 - Nand Flash Timing Parameters 1
 ***************************************************************************/
/* NAND :: TIMING_1_CS5 :: tWP [31:28] */
#define BCHP_NAND_TIMING_1_CS5_tWP_MASK                            0xf0000000
#define BCHP_NAND_TIMING_1_CS5_tWP_SHIFT                           28
#define BCHP_NAND_TIMING_1_CS5_tWP_DEFAULT                         0x00000006

/* NAND :: TIMING_1_CS5 :: tWH [27:24] */
#define BCHP_NAND_TIMING_1_CS5_tWH_MASK                            0x0f000000
#define BCHP_NAND_TIMING_1_CS5_tWH_SHIFT                           24
#define BCHP_NAND_TIMING_1_CS5_tWH_DEFAULT                         0x00000005

/* NAND :: TIMING_1_CS5 :: tRP [23:20] */
#define BCHP_NAND_TIMING_1_CS5_tRP_MASK                            0x00f00000
#define BCHP_NAND_TIMING_1_CS5_tRP_SHIFT                           20
#define BCHP_NAND_TIMING_1_CS5_tRP_DEFAULT                         0x00000007

/* NAND :: TIMING_1_CS5 :: tREH [19:16] */
#define BCHP_NAND_TIMING_1_CS5_tREH_MASK                           0x000f0000
#define BCHP_NAND_TIMING_1_CS5_tREH_SHIFT                          16
#define BCHP_NAND_TIMING_1_CS5_tREH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS5 :: tCS [15:12] */
#define BCHP_NAND_TIMING_1_CS5_tCS_MASK                            0x0000f000
#define BCHP_NAND_TIMING_1_CS5_tCS_SHIFT                           12
#define BCHP_NAND_TIMING_1_CS5_tCS_DEFAULT                         0x00000008

/* NAND :: TIMING_1_CS5 :: tCLH [11:08] */
#define BCHP_NAND_TIMING_1_CS5_tCLH_MASK                           0x00000f00
#define BCHP_NAND_TIMING_1_CS5_tCLH_SHIFT                          8
#define BCHP_NAND_TIMING_1_CS5_tCLH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS5 :: tALH [07:04] */
#define BCHP_NAND_TIMING_1_CS5_tALH_MASK                           0x000000f0
#define BCHP_NAND_TIMING_1_CS5_tALH_SHIFT                          4
#define BCHP_NAND_TIMING_1_CS5_tALH_DEFAULT                        0x00000005

/* NAND :: TIMING_1_CS5 :: tADL [03:00] */
#define BCHP_NAND_TIMING_1_CS5_tADL_MASK                           0x0000000f
#define BCHP_NAND_TIMING_1_CS5_tADL_SHIFT                          0
#define BCHP_NAND_TIMING_1_CS5_tADL_DEFAULT                        0x0000000b

/***************************************************************************
 *TIMING_2_CS5 - Nand Flash Timing Parameters 2
 ***************************************************************************/
/* NAND :: TIMING_2_CS5 :: CLK_SELECT [31:31] */
#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_MASK                     0x80000000
#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_SHIFT                    31
#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_DEFAULT                  0x00000000
#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_108                  0
#define BCHP_NAND_TIMING_2_CS5_CLK_SELECT_CLK_216                  1

/* NAND :: TIMING_2_CS5 :: reserved0 [30:13] */
#define BCHP_NAND_TIMING_2_CS5_reserved0_MASK                      0x7fffe000
#define BCHP_NAND_TIMING_2_CS5_reserved0_SHIFT                     13

/* NAND :: TIMING_2_CS5 :: tWB [12:09] */
#define BCHP_NAND_TIMING_2_CS5_tWB_MASK                            0x00001e00
#define BCHP_NAND_TIMING_2_CS5_tWB_SHIFT                           9
#define BCHP_NAND_TIMING_2_CS5_tWB_DEFAULT                         0x0000000f

/* NAND :: TIMING_2_CS5 :: tWHR [08:04] */
#define BCHP_NAND_TIMING_2_CS5_tWHR_MASK                           0x000001f0
#define BCHP_NAND_TIMING_2_CS5_tWHR_SHIFT                          4
#define BCHP_NAND_TIMING_2_CS5_tWHR_DEFAULT                        0x00000009

/* NAND :: TIMING_2_CS5 :: tREAD [03:00] */
#define BCHP_NAND_TIMING_2_CS5_tREAD_MASK                          0x0000000f
#define BCHP_NAND_TIMING_2_CS5_tREAD_SHIFT                         0
#define BCHP_NAND_TIMING_2_CS5_tREAD_DEFAULT                       0x00000006

/***************************************************************************
 *ACC_CONTROL_CS6 - Nand Flash Access Control
 ***************************************************************************/
/* NAND :: ACC_CONTROL_CS6 :: RD_ECC_EN [31:31] */
#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_MASK                   0x80000000
#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_SHIFT                  31
#define BCHP_NAND_ACC_CONTROL_CS6_RD_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS6 :: WR_ECC_EN [30:30] */
#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_MASK                   0x40000000
#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_SHIFT                  30
#define BCHP_NAND_ACC_CONTROL_CS6_WR_ECC_EN_DEFAULT                0x00000001

/* NAND :: ACC_CONTROL_CS6 :: CE_CARE [29:29] */
#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_MASK                     0x20000000
#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_SHIFT                    29
#define BCHP_NAND_ACC_CONTROL_CS6_CE_CARE_DEFAULT                  0x00000000

/* NAND :: ACC_CONTROL_CS6 :: reserved0 [28:28] */
#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_MASK                   0x10000000
#define BCHP_NAND_ACC_CONTROL_CS6_reserved0_SHIFT                  28

/* NAND :: ACC_CONTROL_CS6 :: RD_ERASED_ECC_EN [27:27] */
#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_MASK            0x08000000
#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_SHIFT           27
#define BCHP_NAND_ACC_CONTROL_CS6_RD_ERASED_ECC_EN_DEFAULT         0x00000000

/* NAND :: ACC_CONTROL_CS6 :: PARTIAL_PAGE_EN [26:26] */
#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_MASK             0x04000000
#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_SHIFT            26
#define BCHP_NAND_ACC_CONTROL_CS6_PARTIAL_PAGE_EN_DEFAULT          0x00000000

/* NAND :: ACC_CONTROL_CS6 :: WR_PREEMPT_EN [25:25] */
#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_MASK               0x02000000
#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_SHIFT              25
#define BCHP_NAND_ACC_CONTROL_CS6_WR_PREEMPT_EN_DEFAULT            0x00000001

/* NAND :: ACC_CONTROL_CS6 :: PAGE_HIT_EN [24:24] */
#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_MASK                 0x01000000
#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_SHIFT                24
#define BCHP_NAND_ACC_CONTROL_CS6_PAGE_HIT_EN_DEFAULT              0x00000001

/* NAND :: ACC_CONTROL_CS6 :: PREFETCH_EN [23:23] */
#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_MASK                 0x00800000
#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_SHIFT                23
#define BCHP_NAND_ACC_CONTROL_CS6_PREFETCH_EN_DEFAULT              0x00000000

/* NAND :: ACC_CONTROL_CS6 :: CACHE_MODE_EN [22:22] */
#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_MASK               0x00400000
#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_SHIFT              22
#define BCHP_NAND_ACC_CONTROL_CS6_CACHE_MODE_EN_DEFAULT            0x00000000

/* NAND :: ACC_CONTROL_CS6 :: reserved1 [21:21] */
#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_MASK                   0x00200000
#define BCHP_NAND_ACC_CONTROL_CS6_reserved1_SHIFT                  21

/* NAND :: ACC_CONTROL_CS6 :: ECC_LEVEL [20:16] */
#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_MASK                   0x001f0000
#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_SHIFT                  16
#define BCHP_NAND_ACC_CONTROL_CS6_ECC_LEVEL_DEFAULT                0x0000000f

/* NAND :: ACC_CONTROL_CS6 :: reserved2 [15:08] */
#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_MASK                   0x0000ff00
#define BCHP_NAND_ACC_CONTROL_CS6_reserved2_SHIFT                  8

/* NAND :: ACC_CONTROL_CS6 :: SECTOR_SIZE_1K [07:07] */
#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_MASK              0x00000080
#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_SHIFT             7
#define BCHP_NAND_ACC_CONTROL_CS6_SECTOR_SIZE_1K_DEFAULT           0x00000000

/* NAND :: ACC_CONTROL_CS6 :: SPARE_AREA_SIZE [06:00] */
#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_MASK             0x0000007f
#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_SHIFT            0
#define BCHP_NAND_ACC_CONTROL_CS6_SPARE_AREA_SIZE_DEFAULT          0x00000010

/***************************************************************************
 *CONFIG_CS6 - Nand Flash Config
 ***************************************************************************/
/* NAND :: CONFIG_CS6 :: CONFIG_LOCK [31:31] */
#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_MASK                      0x80000000
#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_SHIFT                     31
#define BCHP_NAND_CONFIG_CS6_CONFIG_LOCK_DEFAULT                   0x00000000

/* NAND :: CONFIG_CS6 :: BLOCK_SIZE [30:28] */
#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_MASK                       0x70000000
#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_SHIFT                      28
#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_2048KB             6
#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_1024KB             5
#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_512KB              4
#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_256KB              3
#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_128KB              2
#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_16KB               1
#define BCHP_NAND_CONFIG_CS6_BLOCK_SIZE_BK_SIZE_8KB                0

/* NAND :: CONFIG_CS6 :: DEVICE_SIZE [27:24] */
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_MASK                      0x0f000000
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_SHIFT                     24
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4MB              0
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8MB              1
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16MB             2
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32MB             3
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64MB             4
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128MB            5
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_256MB            6
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_512MB            7
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_1GB              8
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_2GB              9
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_4GB              10
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_8GB              11
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_16GB             12
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_32GB             13
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_64GB             14
#define BCHP_NAND_CONFIG_CS6_DEVICE_SIZE_DVC_SIZE_128GB            15

/* NAND :: CONFIG_CS6 :: DEVICE_WIDTH [23:23] */
#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_MASK                     0x00800000
#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_SHIFT                    23
#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_8              0
#define BCHP_NAND_CONFIG_CS6_DEVICE_WIDTH_DVC_WIDTH_16             1

/* NAND :: CONFIG_CS6 :: reserved0 [22:22] */
#define BCHP_NAND_CONFIG_CS6_reserved0_MASK                        0x00400000
#define BCHP_NAND_CONFIG_CS6_reserved0_SHIFT                       22

/* NAND :: CONFIG_CS6 :: PAGE_SIZE [21:20] */
#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_MASK                        0x00300000
#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_SHIFT                       20
#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_PG_SIZE_512                 0
#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_PG_SIZE_2KB                 1
#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_PG_SIZE_4KB                 2
#define BCHP_NAND_CONFIG_CS6_PAGE_SIZE_PG_SIZE_8KB                 3

/* NAND :: CONFIG_CS6 :: reserved1 [19:19] */
#define BCHP_NAND_CONFIG_CS6_reserved1_MASK                        0x00080000
#define BCHP_NAND_CONFIG_CS6_reserved1_SHIFT                       19

/* NAND :: CONFIG_CS6 :: FUL_ADR_BYTES [18:16] */
#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_MASK                    0x00070000
#define BCHP_NAND_CONFIG_CS6_FUL_ADR_BYTES_SHIFT                   16

/* NAND :: CONFIG_CS6 :: reserved2 [15:15] */
#define BCHP_NAND_CONFIG_CS6_reserved2_MASK                        0x00008000
#define BCHP_NAND_CONFIG_CS6_reserved2_SHIFT                       15

/* NAND :: CONFIG_CS6 :: COL_ADR_BYTES [14:12] */
#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_MASK                    0x00007000
#define BCHP_NAND_CONFIG_CS6_COL_ADR_BYTES_SHIFT                   12

/* NAND :: CONFIG_CS6 :: reserved3 [11:11] */
#define BCHP_NAND_CONFIG_CS6_reserved3_MASK                        0x00000800
#define BCHP_NAND_CONFIG_CS6_reserved3_SHIFT                       11

/* NAND :: CONFIG_CS6 :: BLK_ADR_BYTES [10:08] */
#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_MASK                    0x00000700
#define BCHP_NAND_CONFIG_CS6_BLK_ADR_BYTES_SHIFT                   8

/* NAND :: CONFIG_CS6 :: reserved4 [07:00] */
#define BCHP_NAND_CONFIG_CS6_reserved4_MASK                        0x000000ff
#define BCHP_NAND_CONFIG_CS6_reserved4_SHIFT                       0

/***************************************************************************
 *TIMING_1_CS6 - Nand Flash Timing Parameters 1
 ***************************************************************************/
/* NAND :: TIMING_1_CS6 :: tWP [31:28] */
#define BCHP_NAND_TIMING_1_CS6_tWP_MASK                            0xf0000000
#define BCHP_NAND_TIMING_1_CS6_tWP_SHIFT                           28
#define BCHP_NAND_TIMING_1_CS6_tWP_DEFAULT                         0x00000006

/* NAND :: TIMING_1_CS6 :: tWH [27:24] */
#define BCHP_NAND_TIMING_1_CS6_tWH_MASK                            0x0f000000
#define BCHP_NAND_TIMING_1_CS6_tWH_SHIFT                           24
#define BCHP_NAND_TIMING_1_CS6_tWH_DEFAULT                         0x00000005

/* NAND :: TIMING_1_CS6 :: tRP [23:20] */
#define BCHP_NAND_TIMING_1_CS6_tRP_MASK                            0x00f00000
#define BCHP_NAND_TIMING_1_CS6_tRP_SHIFT                           20
#define BCHP_NAND_TIMING_1_CS6_tRP_DEFAULT                         0x00000007

/* NAND :: TIMING_1_CS6 :: tREH [19:16] */
#define BCHP_NAND_TIMING_1_CS6_tREH_MASK                           0x000f0000
#define BCHP_NAND_TIMING_1_CS6_tREH_SHIFT                          16
#define BCHP_NAND_TIMING_1_CS6_tREH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS6 :: tCS [15:12] */
#define BCHP_NAND_TIMING_1_CS6_tCS_MASK                            0x0000f000
#define BCHP_NAND_TIMING_1_CS6_tCS_SHIFT                           12
#define BCHP_NAND_TIMING_1_CS6_tCS_DEFAULT                         0x00000008

/* NAND :: TIMING_1_CS6 :: tCLH [11:08] */
#define BCHP_NAND_TIMING_1_CS6_tCLH_MASK                           0x00000f00
#define BCHP_NAND_TIMING_1_CS6_tCLH_SHIFT                          8
#define BCHP_NAND_TIMING_1_CS6_tCLH_DEFAULT                        0x00000004

/* NAND :: TIMING_1_CS6 :: tALH [07:04] */
#define BCHP_NAND_TIMING_1_CS6_tALH_MASK                           0x000000f0
#define BCHP_NAND_TIMING_1_CS6_tALH_SHIFT                          4
#define BCHP_NAND_TIMING_1_CS6_tALH_DEFAULT                        0x00000005

/* NAND :: TIMING_1_CS6 :: tADL [03:00] */
#define BCHP_NAND_TIMING_1_CS6_tADL_MASK                           0x0000000f
#define BCHP_NAND_TIMING_1_CS6_tADL_SHIFT                          0
#define BCHP_NAND_TIMING_1_CS6_tADL_DEFAULT                        0x0000000b

/***************************************************************************
 *TIMING_2_CS6 - Nand Flash Timing Parameters 2
 ***************************************************************************/
/* NAND :: TIMING_2_CS6 :: CLK_SELECT [31:31] */
#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_MASK                     0x80000000
#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_SHIFT                    31
#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_DEFAULT                  0x00000000
#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_108                  0
#define BCHP_NAND_TIMING_2_CS6_CLK_SELECT_CLK_216                  1

/* NAND :: TIMING_2_CS6 :: reserved0 [30:13] */
#define BCHP_NAND_TIMING_2_CS6_reserved0_MASK                      0x7fffe000
#define BCHP_NAND_TIMING_2_CS6_reserved0_SHIFT                     13

/* NAND :: TIMING_2_CS6 :: tWB [12:09] */
#define BCHP_NAND_TIMING_2_CS6_tWB_MASK                            0x00001e00
#define BCHP_NAND_TIMING_2_CS6_tWB_SHIFT                           9
#define BCHP_NAND_TIMING_2_CS6_tWB_DEFAULT                         0x0000000f

/* NAND :: TIMING_2_CS6 :: tWHR [08:04] */
#define BCHP_NAND_TIMING_2_CS6_tWHR_MASK                           0x000001f0
#define BCHP_NAND_TIMING_2_CS6_tWHR_SHIFT                          4
#define BCHP_NAND_TIMING_2_CS6_tWHR_DEFAULT                        0x00000009

/* NAND :: TIMING_2_CS6 :: tREAD [03:00] */
#define BCHP_NAND_TIMING_2_CS6_tREAD_MASK                          0x0000000f
#define BCHP_NAND_TIMING_2_CS6_tREAD_SHIFT                         0
#define BCHP_NAND_TIMING_2_CS6_tREAD_DEFAULT                       0x00000006

/***************************************************************************
 *CORR_STAT_THRESHOLD - Correctable Error Reporting Threshold
 ***************************************************************************/
/* NAND :: CORR_STAT_THRESHOLD :: reserved0 [31:30] */
#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_MASK               0xc0000000
#define BCHP_NAND_CORR_STAT_THRESHOLD_reserved0_SHIFT              30

/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS4 [29:24] */
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_MASK 0x3f000000
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_SHIFT 24
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS4_DEFAULT 0x00000001

/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS3 [23:18] */
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_MASK 0x00fc0000
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_SHIFT 18
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS3_DEFAULT 0x00000001

/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS2 [17:12] */
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_MASK 0x0003f000
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_SHIFT 12
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS2_DEFAULT 0x00000001

/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS1 [11:06] */
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_MASK 0x00000fc0
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_SHIFT 6
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS1_DEFAULT 0x00000001

/* NAND :: CORR_STAT_THRESHOLD :: CORR_STAT_THRESHOLD_CS0 [05:00] */
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_MASK 0x0000003f
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_SHIFT 0
#define BCHP_NAND_CORR_STAT_THRESHOLD_CORR_STAT_THRESHOLD_CS0_DEFAULT 0x00000001

/***************************************************************************
 *CORR_STAT_THRESHOLD_EXT - Correctable Error Reporting Threshold
 ***************************************************************************/
/* NAND :: CORR_STAT_THRESHOLD_EXT :: reserved0 [31:12] */
#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_MASK           0xfffff000
#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_reserved0_SHIFT          12

/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS6 [11:06] */
#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_MASK 0x00000fc0
#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_SHIFT 6
#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS6_DEFAULT 0x00000001

/* NAND :: CORR_STAT_THRESHOLD_EXT :: CORR_STAT_THRESHOLD_CS5 [05:00] */
#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_MASK 0x0000003f
#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_SHIFT 0
#define BCHP_NAND_CORR_STAT_THRESHOLD_EXT_CORR_STAT_THRESHOLD_CS5_DEFAULT 0x00000001

/***************************************************************************
 *BLK_WR_PROTECT - Block Write Protect Enable and Size for EBI_CS0b
 ***************************************************************************/
/* NAND :: BLK_WR_PROTECT :: BLK_END_ADDR [31:00] */
#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_MASK                 0xffffffff
#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_SHIFT                0
#define BCHP_NAND_BLK_WR_PROTECT_BLK_END_ADDR_DEFAULT              0x00000000

/***************************************************************************
 *MULTIPLANE_OPCODES_1 - Nand Flash Multiplane Customerized Opcodes
 ***************************************************************************/
/* NAND :: MULTIPLANE_OPCODES_1 :: ERASE_CYC2_OPCODE [31:24] */
#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_MASK      0xff000000
#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_SHIFT     24
#define BCHP_NAND_MULTIPLANE_OPCODES_1_ERASE_CYC2_OPCODE_DEFAULT   0x000000d1

/* NAND :: MULTIPLANE_OPCODES_1 :: READ_STATUS_OPCODE [23:16] */
#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_MASK     0x00ff0000
#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_SHIFT    16
#define BCHP_NAND_MULTIPLANE_OPCODES_1_READ_STATUS_OPCODE_DEFAULT  0x00000070

/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_ODD_PLANE_OPCODE [15:08] */
#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_MASK  0x0000ff00
#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_SHIFT 8
#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_ODD_PLANE_OPCODE_DEFAULT 0x00000080

/* NAND :: MULTIPLANE_OPCODES_1 :: PROG_TR_OPCODE [07:00] */
#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_MASK         0x000000ff
#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_SHIFT        0
#define BCHP_NAND_MULTIPLANE_OPCODES_1_PROG_TR_OPCODE_DEFAULT      0x00000010

/***************************************************************************
 *MULTIPLANE_OPCODES_2 - Nand Flash Multiplane Customerized Opcodes
 ***************************************************************************/
/* NAND :: MULTIPLANE_OPCODES_2 :: PROG_CACHE_TR_OPCODE [31:24] */
#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_MASK   0xff000000
#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_SHIFT  24
#define BCHP_NAND_MULTIPLANE_OPCODES_2_PROG_CACHE_TR_OPCODE_DEFAULT 0x00000015

/* NAND :: MULTIPLANE_OPCODES_2 :: TWO_PLANE_READ_STATUS_OPCODE [23:16] */
#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_MASK 0x00ff0000
#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_SHIFT 16
#define BCHP_NAND_MULTIPLANE_OPCODES_2_TWO_PLANE_READ_STATUS_OPCODE_DEFAULT 0x00000078

/* NAND :: MULTIPLANE_OPCODES_2 :: READ_OPCODE [15:08] */
#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_MASK            0x0000ff00
#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_SHIFT           8
#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_OPCODE_DEFAULT         0x00000000

/* NAND :: MULTIPLANE_OPCODES_2 :: READ_RAND_OPCODE [07:00] */
#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_MASK       0x000000ff
#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_SHIFT      0
#define BCHP_NAND_MULTIPLANE_OPCODES_2_READ_RAND_OPCODE_DEFAULT    0x00000000

/***************************************************************************
 *MULTIPLANE_CTRL - Nand Flash Multiplane Control
 ***************************************************************************/
/* NAND :: MULTIPLANE_CTRL :: ERASE_CYC2_OP_ENABLE [31:31] */
#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_MASK        0x80000000
#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_SHIFT       31
#define BCHP_NAND_MULTIPLANE_CTRL_ERASE_CYC2_OP_ENABLE_DEFAULT     0x00000000

/* NAND :: MULTIPLANE_CTRL :: READ_ADR_SIZE [30:30] */
#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_MASK               0x40000000
#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_SHIFT              30
#define BCHP_NAND_MULTIPLANE_CTRL_READ_ADR_SIZE_DEFAULT            0x00000000

/* NAND :: MULTIPLANE_CTRL :: READ_CYC_ADR_FLAG [29:29] */
#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_MASK           0x20000000
#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_SHIFT          29
#define BCHP_NAND_MULTIPLANE_CTRL_READ_CYC_ADR_FLAG_DEFAULT        0x00000000

/* NAND :: MULTIPLANE_CTRL :: READ_NEXT_PAGE_FLAG [28:28] */
#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_MASK         0x10000000
#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_SHIFT        28
#define BCHP_NAND_MULTIPLANE_CTRL_READ_NEXT_PAGE_FLAG_DEFAULT      0x00000000

/* NAND :: MULTIPLANE_CTRL :: reserved0 [27:00] */
#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_MASK                   0x0fffffff
#define BCHP_NAND_MULTIPLANE_CTRL_reserved0_SHIFT                  0

/***************************************************************************
 *UNCORR_ERROR_COUNT - Read Uncorrectable Event Count
 ***************************************************************************/
/* NAND :: UNCORR_ERROR_COUNT :: UNCORR_ERROR_COUNT [31:00] */
#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_MASK       0xffffffff
#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_SHIFT      0
#define BCHP_NAND_UNCORR_ERROR_COUNT_UNCORR_ERROR_COUNT_DEFAULT    0x00000000

/***************************************************************************
 *CORR_ERROR_COUNT - Read Error Count
 ***************************************************************************/
/* NAND :: CORR_ERROR_COUNT :: CORR_ERROR_COUNT [31:00] */
#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_MASK           0xffffffff
#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_SHIFT          0
#define BCHP_NAND_CORR_ERROR_COUNT_CORR_ERROR_COUNT_DEFAULT        0x00000000

/***************************************************************************
 *READ_ERROR_COUNT - Read Error Count
 ***************************************************************************/
/* NAND :: READ_ERROR_COUNT :: READ_ERROR_COUNT [31:00] */
#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_MASK           0xffffffff
#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_SHIFT          0
#define BCHP_NAND_READ_ERROR_COUNT_READ_ERROR_COUNT_DEFAULT        0x00000000

/***************************************************************************
 *BLOCK_LOCK_STATUS - Nand Flash Block Lock Status
 ***************************************************************************/
/* NAND :: BLOCK_LOCK_STATUS :: reserved0 [31:08] */
#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_MASK                 0xffffff00
#define BCHP_NAND_BLOCK_LOCK_STATUS_reserved0_SHIFT                8

/* NAND :: BLOCK_LOCK_STATUS :: STATUS [07:00] */
#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_MASK                    0x000000ff
#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_SHIFT                   0
#define BCHP_NAND_BLOCK_LOCK_STATUS_STATUS_DEFAULT                 0x00000000

/***************************************************************************
 *ECC_CORR_EXT_ADDR - ECC Correctable Error Extended Address
 ***************************************************************************/
/* NAND :: ECC_CORR_EXT_ADDR :: reserved0 [31:19] */
#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_MASK                 0xfff80000
#define BCHP_NAND_ECC_CORR_EXT_ADDR_reserved0_SHIFT                19

/* NAND :: ECC_CORR_EXT_ADDR :: CS_SEL [18:16] */
#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_MASK                    0x00070000
#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_SHIFT                   16
#define BCHP_NAND_ECC_CORR_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000

/* NAND :: ECC_CORR_EXT_ADDR :: EXT_ADDRESS [15:00] */
#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_SHIFT              0
#define BCHP_NAND_ECC_CORR_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000

/***************************************************************************
 *ECC_CORR_ADDR - ECC Correctable Error Address
 ***************************************************************************/
/* NAND :: ECC_CORR_ADDR :: ADDRESS [31:00] */
#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_MASK                       0xffffffff
#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_SHIFT                      0
#define BCHP_NAND_ECC_CORR_ADDR_ADDRESS_DEFAULT                    0x00000000

/***************************************************************************
 *ECC_UNC_EXT_ADDR - ECC Uncorrectable Error Extended Address
 ***************************************************************************/
/* NAND :: ECC_UNC_EXT_ADDR :: reserved0 [31:19] */
#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_MASK                  0xfff80000
#define BCHP_NAND_ECC_UNC_EXT_ADDR_reserved0_SHIFT                 19

/* NAND :: ECC_UNC_EXT_ADDR :: CS_SEL [18:16] */
#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_MASK                     0x00070000
#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_SHIFT                    16
#define BCHP_NAND_ECC_UNC_EXT_ADDR_CS_SEL_DEFAULT                  0x00000000

/* NAND :: ECC_UNC_EXT_ADDR :: EXT_ADDRESS [15:00] */
#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_MASK                0x0000ffff
#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_SHIFT               0
#define BCHP_NAND_ECC_UNC_EXT_ADDR_EXT_ADDRESS_DEFAULT             0x00000000

/***************************************************************************
 *ECC_UNC_ADDR - ECC Uncorrectable Error Address
 ***************************************************************************/
/* NAND :: ECC_UNC_ADDR :: ADDRESS [31:00] */
#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_MASK                        0xffffffff
#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_SHIFT                       0
#define BCHP_NAND_ECC_UNC_ADDR_ADDRESS_DEFAULT                     0x00000000

/***************************************************************************
 *FLASH_READ_EXT_ADDR - Flash Read Data Extended Address
 ***************************************************************************/
/* NAND :: FLASH_READ_EXT_ADDR :: reserved0 [31:19] */
#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_MASK               0xfff80000
#define BCHP_NAND_FLASH_READ_EXT_ADDR_reserved0_SHIFT              19

/* NAND :: FLASH_READ_EXT_ADDR :: CS_SEL [18:16] */
#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_MASK                  0x00070000
#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_SHIFT                 16
#define BCHP_NAND_FLASH_READ_EXT_ADDR_CS_SEL_DEFAULT               0x00000000

/* NAND :: FLASH_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_MASK             0x0000ffff
#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_SHIFT            0
#define BCHP_NAND_FLASH_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT          0x00000000

/***************************************************************************
 *FLASH_READ_ADDR - Flash Read Data Address
 ***************************************************************************/
/* NAND :: FLASH_READ_ADDR :: ADDRESS [31:00] */
#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_MASK                     0xffffffff
#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_SHIFT                    0
#define BCHP_NAND_FLASH_READ_ADDR_ADDRESS_DEFAULT                  0x00000000

/***************************************************************************
 *PROGRAM_PAGE_EXT_ADDR - Page Program Extended Address
 ***************************************************************************/
/* NAND :: PROGRAM_PAGE_EXT_ADDR :: reserved0 [31:19] */
#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_MASK             0xfff80000
#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_reserved0_SHIFT            19

/* NAND :: PROGRAM_PAGE_EXT_ADDR :: CS_SEL [18:16] */
#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_MASK                0x00070000
#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_SHIFT               16
#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_CS_SEL_DEFAULT             0x00000000

/* NAND :: PROGRAM_PAGE_EXT_ADDR :: EXT_ADDRESS [15:00] */
#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_MASK           0x0000ffff
#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_SHIFT          0
#define BCHP_NAND_PROGRAM_PAGE_EXT_ADDR_EXT_ADDRESS_DEFAULT        0x00000000

/***************************************************************************
 *PROGRAM_PAGE_ADDR - Page Program Address
 ***************************************************************************/
/* NAND :: PROGRAM_PAGE_ADDR :: ADDRESS [31:00] */
#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_MASK                   0xffffffff
#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_SHIFT                  0
#define BCHP_NAND_PROGRAM_PAGE_ADDR_ADDRESS_DEFAULT                0x00000000

/***************************************************************************
 *COPY_BACK_EXT_ADDR - Copy Back Extended Address
 ***************************************************************************/
/* NAND :: COPY_BACK_EXT_ADDR :: reserved0 [31:19] */
#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_MASK                0xfff80000
#define BCHP_NAND_COPY_BACK_EXT_ADDR_reserved0_SHIFT               19

/* NAND :: COPY_BACK_EXT_ADDR :: CS_SEL [18:16] */
#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_MASK                   0x00070000
#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_SHIFT                  16
#define BCHP_NAND_COPY_BACK_EXT_ADDR_CS_SEL_DEFAULT                0x00000000

/* NAND :: COPY_BACK_EXT_ADDR :: EXT_ADDRESS [15:00] */
#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_MASK              0x0000ffff
#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_SHIFT             0
#define BCHP_NAND_COPY_BACK_EXT_ADDR_EXT_ADDRESS_DEFAULT           0x00000000

/***************************************************************************
 *COPY_BACK_ADDR - Copy Back Address
 ***************************************************************************/
/* NAND :: COPY_BACK_ADDR :: ADDRESS [31:00] */
#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_MASK                      0xffffffff
#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_SHIFT                     0
#define BCHP_NAND_COPY_BACK_ADDR_ADDRESS_DEFAULT                   0x00000000

/***************************************************************************
 *BLOCK_ERASE_EXT_ADDR - Block Erase Extended Address
 ***************************************************************************/
/* NAND :: BLOCK_ERASE_EXT_ADDR :: reserved0 [31:19] */
#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_MASK              0xfff80000
#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_reserved0_SHIFT             19

/* NAND :: BLOCK_ERASE_EXT_ADDR :: CS_SEL [18:16] */
#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_MASK                 0x00070000
#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_SHIFT                16
#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_CS_SEL_DEFAULT              0x00000000

/* NAND :: BLOCK_ERASE_EXT_ADDR :: EXT_ADDRESS [15:00] */
#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_MASK            0x0000ffff
#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_SHIFT           0
#define BCHP_NAND_BLOCK_ERASE_EXT_ADDR_EXT_ADDRESS_DEFAULT         0x00000000

/***************************************************************************
 *BLOCK_ERASE_ADDR - Block Erase Address
 ***************************************************************************/
/* NAND :: BLOCK_ERASE_ADDR :: ADDRESS [31:00] */
#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_MASK                    0xffffffff
#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_SHIFT                   0
#define BCHP_NAND_BLOCK_ERASE_ADDR_ADDRESS_DEFAULT                 0x00000000

/***************************************************************************
 *INV_READ_EXT_ADDR - Flash Invalid Data Extended Address
 ***************************************************************************/
/* NAND :: INV_READ_EXT_ADDR :: reserved0 [31:19] */
#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_MASK                 0xfff80000
#define BCHP_NAND_INV_READ_EXT_ADDR_reserved0_SHIFT                19

/* NAND :: INV_READ_EXT_ADDR :: CS_SEL [18:16] */
#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_MASK                    0x00070000
#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_SHIFT                   16
#define BCHP_NAND_INV_READ_EXT_ADDR_CS_SEL_DEFAULT                 0x00000000

/* NAND :: INV_READ_EXT_ADDR :: EXT_ADDRESS [15:00] */
#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_MASK               0x0000ffff
#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_SHIFT              0
#define BCHP_NAND_INV_READ_EXT_ADDR_EXT_ADDRESS_DEFAULT            0x00000000

/***************************************************************************
 *INV_READ_ADDR - Flash Invalid Data Address
 ***************************************************************************/
/* NAND :: INV_READ_ADDR :: ADDRESS [31:00] */
#define BCHP_NAND_INV_READ_ADDR_ADDRESS_MASK                       0xffffffff
#define BCHP_NAND_INV_READ_ADDR_ADDRESS_SHIFT                      0
#define BCHP_NAND_INV_READ_ADDR_ADDRESS_DEFAULT                    0x00000000

/***************************************************************************
 *INIT_STATUS - Initialization status
 ***************************************************************************/
/* NAND :: INIT_STATUS :: ONFI_INIT_DONE [31:31] */
#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_MASK                  0x80000000
#define BCHP_NAND_INIT_STATUS_ONFI_INIT_DONE_SHIFT                 31

/* NAND :: INIT_STATUS :: DEVICE_ID_INIT_DONE [30:30] */
#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_MASK             0x40000000
#define BCHP_NAND_INIT_STATUS_DEVICE_ID_INIT_DONE_SHIFT            30

/* NAND :: INIT_STATUS :: INIT_SUCCESS [29:29] */
#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_MASK                    0x20000000
#define BCHP_NAND_INIT_STATUS_INIT_SUCCESS_SHIFT                   29

/* NAND :: INIT_STATUS :: INIT_FAIL [28:28] */
#define BCHP_NAND_INIT_STATUS_INIT_FAIL_MASK                       0x10000000
#define BCHP_NAND_INIT_STATUS_INIT_FAIL_SHIFT                      28

/* NAND :: INIT_STATUS :: INIT_BLANK [27:27] */
#define BCHP_NAND_INIT_STATUS_INIT_BLANK_MASK                      0x08000000
#define BCHP_NAND_INIT_STATUS_INIT_BLANK_SHIFT                     27

/* NAND :: INIT_STATUS :: INIT_TIMEOUT [26:26] */
#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_MASK                    0x04000000
#define BCHP_NAND_INIT_STATUS_INIT_TIMEOUT_SHIFT                   26

/* NAND :: INIT_STATUS :: INIT_UNC_ERROR [25:25] */
#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_MASK                  0x02000000
#define BCHP_NAND_INIT_STATUS_INIT_UNC_ERROR_SHIFT                 25

/* NAND :: INIT_STATUS :: INIT_CORR_ERROR [24:24] */
#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_MASK                 0x01000000
#define BCHP_NAND_INIT_STATUS_INIT_CORR_ERROR_SHIFT                24

/* NAND :: INIT_STATUS :: PARAMETER_READY [23:23] */
#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_MASK                 0x00800000
#define BCHP_NAND_INIT_STATUS_PARAMETER_READY_SHIFT                23

/* NAND :: INIT_STATUS :: AUTHENTICATION_FAIL [22:22] */
#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_MASK             0x00400000
#define BCHP_NAND_INIT_STATUS_AUTHENTICATION_FAIL_SHIFT            22

/* NAND :: INIT_STATUS :: reserved0 [21:00] */
#define BCHP_NAND_INIT_STATUS_reserved0_MASK                       0x003fffff
#define BCHP_NAND_INIT_STATUS_reserved0_SHIFT                      0

/***************************************************************************
 *ONFI_STATUS - ONFI Status
 ***************************************************************************/
/* NAND :: ONFI_STATUS :: ONFI_DEBUG_SEL [31:28] */
#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_MASK                  0xf0000000
#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_SHIFT                 28
#define BCHP_NAND_ONFI_STATUS_ONFI_DEBUG_SEL_DEFAULT               0x00000000

/* NAND :: ONFI_STATUS :: ONFI_detected [27:27] */
#define BCHP_NAND_ONFI_STATUS_ONFI_detected_MASK                   0x08000000
#define BCHP_NAND_ONFI_STATUS_ONFI_detected_SHIFT                  27

/* NAND :: ONFI_STATUS :: reserved0 [26:06] */
#define BCHP_NAND_ONFI_STATUS_reserved0_MASK                       0x07ffffc0
#define BCHP_NAND_ONFI_STATUS_reserved0_SHIFT                      6

/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG2 [05:05] */
#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_MASK              0x00000020
#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG2_SHIFT             5

/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG1 [04:04] */
#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_MASK              0x00000010
#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG1_SHIFT             4

/* NAND :: ONFI_STATUS :: ONFI_BAD_IDENT_PG0 [03:03] */
#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_MASK              0x00000008
#define BCHP_NAND_ONFI_STATUS_ONFI_BAD_IDENT_PG0_SHIFT             3

/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG2 [02:02] */
#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_MASK              0x00000004
#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG2_SHIFT             2

/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG1 [01:01] */
#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_MASK              0x00000002
#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG1_SHIFT             1

/* NAND :: ONFI_STATUS :: ONFI_CRC_ERROR_PG0 [00:00] */
#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_MASK              0x00000001
#define BCHP_NAND_ONFI_STATUS_ONFI_CRC_ERROR_PG0_SHIFT             0

/***************************************************************************
 *ONFI_DEBUG_DATA - ONFI Debug Data
 ***************************************************************************/
/* NAND :: ONFI_DEBUG_DATA :: ONFI_DEBUG_DATA [31:00] */
#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_MASK             0xffffffff
#define BCHP_NAND_ONFI_DEBUG_DATA_ONFI_DEBUG_DATA_SHIFT            0

/***************************************************************************
 *SEMAPHORE - Semaphore
 ***************************************************************************/
/* NAND :: SEMAPHORE :: reserved0 [31:08] */
#define BCHP_NAND_SEMAPHORE_reserved0_MASK                         0xffffff00
#define BCHP_NAND_SEMAPHORE_reserved0_SHIFT                        8

/* NAND :: SEMAPHORE :: semaphore_ctrl [07:00] */
#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_MASK                    0x000000ff
#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_SHIFT                   0
#define BCHP_NAND_SEMAPHORE_semaphore_ctrl_DEFAULT                 0x00000000

/***************************************************************************
 *FLASH_DEVICE_ID - Nand Flash Device ID
 ***************************************************************************/
/* NAND :: FLASH_DEVICE_ID :: BYTE_0 [31:24] */
#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_MASK                      0xff000000
#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_0_SHIFT                     24

/* NAND :: FLASH_DEVICE_ID :: BYTE_1 [23:16] */
#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_MASK                      0x00ff0000
#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_1_SHIFT                     16

/* NAND :: FLASH_DEVICE_ID :: BYTE_2 [15:08] */
#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_MASK                      0x0000ff00
#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_2_SHIFT                     8

/* NAND :: FLASH_DEVICE_ID :: BYTE_3 [07:00] */
#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_MASK                      0x000000ff
#define BCHP_NAND_FLASH_DEVICE_ID_BYTE_3_SHIFT                     0

/***************************************************************************
 *FLASH_DEVICE_ID_EXT - Nand Flash Extended Device ID
 ***************************************************************************/
/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_4 [31:24] */
#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_MASK                  0xff000000
#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_4_SHIFT                 24

/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_5 [23:16] */
#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_MASK                  0x00ff0000
#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_5_SHIFT                 16

/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_6 [15:08] */
#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_MASK                  0x0000ff00
#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_6_SHIFT                 8

/* NAND :: FLASH_DEVICE_ID_EXT :: BYTE_7 [07:00] */
#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_MASK                  0x000000ff
#define BCHP_NAND_FLASH_DEVICE_ID_EXT_BYTE_7_SHIFT                 0

/***************************************************************************
 *LL_RDDATA - Nand Flash Low Level Read Data
 ***************************************************************************/
/* NAND :: LL_RDDATA :: reserved0 [31:16] */
#define BCHP_NAND_LL_RDDATA_reserved0_MASK                         0xffff0000
#define BCHP_NAND_LL_RDDATA_reserved0_SHIFT                        16

/* NAND :: LL_RDDATA :: DATA [15:00] */
#define BCHP_NAND_LL_RDDATA_DATA_MASK                              0x0000ffff
#define BCHP_NAND_LL_RDDATA_DATA_SHIFT                             0
#define BCHP_NAND_LL_RDDATA_DATA_DEFAULT                           0x00000000

/***************************************************************************
 *SPARE_AREA_READ_OFS_0 - Nand Flash Spare Area Read Bytes 0-3
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_0 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_MASK            0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_SHIFT           24
#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_0_DEFAULT         0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_1 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_MASK            0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_SHIFT           16
#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_1_DEFAULT         0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_2 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_MASK            0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_SHIFT           8
#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_2_DEFAULT         0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_0 :: BYTE_OFS_3 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_MASK            0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_SHIFT           0
#define BCHP_NAND_SPARE_AREA_READ_OFS_0_BYTE_OFS_3_DEFAULT         0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_4 - Nand Flash Spare Area Read Bytes 4-7
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_4 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_MASK            0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_SHIFT           24
#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_4_DEFAULT         0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_5 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_MASK            0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_SHIFT           16
#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_5_DEFAULT         0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_6 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_MASK            0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_SHIFT           8
#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_6_DEFAULT         0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_4 :: BYTE_OFS_7 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_MASK            0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_SHIFT           0
#define BCHP_NAND_SPARE_AREA_READ_OFS_4_BYTE_OFS_7_DEFAULT         0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_8 - Nand Flash Spare Area Read Bytes 8-11
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_8 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_MASK            0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_SHIFT           24
#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_8_DEFAULT         0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_9 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_MASK            0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_SHIFT           16
#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_9_DEFAULT         0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_10 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_MASK           0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_SHIFT          8
#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_10_DEFAULT        0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_8 :: BYTE_OFS_11 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_MASK           0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_SHIFT          0
#define BCHP_NAND_SPARE_AREA_READ_OFS_8_BYTE_OFS_11_DEFAULT        0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_C - Nand Flash Spare Area Read Bytes 12-15
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_12 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_MASK           0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_SHIFT          24
#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_12_DEFAULT        0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_13 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_MASK           0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_SHIFT          16
#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_13_DEFAULT        0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_14 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_MASK           0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_SHIFT          8
#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_14_DEFAULT        0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_C :: BYTE_OFS_15 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_MASK           0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_SHIFT          0
#define BCHP_NAND_SPARE_AREA_READ_OFS_C_BYTE_OFS_15_DEFAULT        0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_10 - Nand Flash Spare Area Read Bytes 16-19
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_16 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_SHIFT         24
#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_16_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_17 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_SHIFT         16
#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_17_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_18 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_SHIFT         8
#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_18_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_10 :: BYTE_OFS_19 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_SHIFT         0
#define BCHP_NAND_SPARE_AREA_READ_OFS_10_BYTE_OFS_19_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_14 - Nand Flash Spare Area Read Bytes 20-23
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_20 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_SHIFT         24
#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_20_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_21 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_SHIFT         16
#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_21_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_22 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_SHIFT         8
#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_22_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_14 :: BYTE_OFS_23 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_SHIFT         0
#define BCHP_NAND_SPARE_AREA_READ_OFS_14_BYTE_OFS_23_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_18 - Nand Flash Spare Area Read Bytes 24-27
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_24 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_SHIFT         24
#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_24_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_25 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_SHIFT         16
#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_25_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_26 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_SHIFT         8
#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_26_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_18 :: BYTE_OFS_27 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_SHIFT         0
#define BCHP_NAND_SPARE_AREA_READ_OFS_18_BYTE_OFS_27_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_1C - Nand Flash Spare Area Read Bytes 28-31
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_28 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_SHIFT         24
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_28_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_29 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_SHIFT         16
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_29_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_30 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_SHIFT         8
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_30_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_1C :: BYTE_OFS_31 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_SHIFT         0
#define BCHP_NAND_SPARE_AREA_READ_OFS_1C_BYTE_OFS_31_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_20 - Nand Flash Spare Area Read Bytes 32-35
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_32 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_SHIFT         24
#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_32_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_33 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_SHIFT         16
#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_33_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_34 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_SHIFT         8
#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_34_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_20 :: BYTE_OFS_35 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_SHIFT         0
#define BCHP_NAND_SPARE_AREA_READ_OFS_20_BYTE_OFS_35_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_24 - Nand Flash Spare Area Read Bytes 36-39
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_36 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_SHIFT         24
#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_36_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_37 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_SHIFT         16
#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_37_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_38 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_SHIFT         8
#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_38_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_24 :: BYTE_OFS_39 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_SHIFT         0
#define BCHP_NAND_SPARE_AREA_READ_OFS_24_BYTE_OFS_39_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_28 - Nand Flash Spare Area Read Bytes 40-43
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_40 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_SHIFT         24
#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_40_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_41 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_SHIFT         16
#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_41_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_42 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_SHIFT         8
#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_42_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_28 :: BYTE_OFS_43 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_SHIFT         0
#define BCHP_NAND_SPARE_AREA_READ_OFS_28_BYTE_OFS_43_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_2C - Nand Flash Spare Area Read Bytes 44-47
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_44 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_SHIFT         24
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_44_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_45 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_SHIFT         16
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_45_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_46 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_SHIFT         8
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_46_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_2C :: BYTE_OFS_47 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_SHIFT         0
#define BCHP_NAND_SPARE_AREA_READ_OFS_2C_BYTE_OFS_47_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_30 - Nand Flash Spare Area Read Bytes 48-51
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_48 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_SHIFT         24
#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_48_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_49 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_SHIFT         16
#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_49_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_50 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_SHIFT         8
#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_50_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_30 :: BYTE_OFS_51 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_SHIFT         0
#define BCHP_NAND_SPARE_AREA_READ_OFS_30_BYTE_OFS_51_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_34 - Nand Flash Spare Area Read Bytes 52-55
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_52 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_SHIFT         24
#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_52_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_53 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_SHIFT         16
#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_53_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_54 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_SHIFT         8
#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_54_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_34 :: BYTE_OFS_55 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_SHIFT         0
#define BCHP_NAND_SPARE_AREA_READ_OFS_34_BYTE_OFS_55_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_38 - Nand Flash Spare Area Read Bytes 56-59
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_56 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_SHIFT         24
#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_56_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_57 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_SHIFT         16
#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_57_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_58 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_SHIFT         8
#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_58_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_38 :: BYTE_OFS_59 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_SHIFT         0
#define BCHP_NAND_SPARE_AREA_READ_OFS_38_BYTE_OFS_59_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_READ_OFS_3C - Nand Flash Spare Area Read Bytes 60-63
 ***************************************************************************/
/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_60 [31:24] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_SHIFT         24
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_60_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_61 [23:16] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_SHIFT         16
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_61_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_62 [15:08] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_SHIFT         8
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_62_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_READ_OFS_3C :: BYTE_OFS_63 [07:00] */
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_SHIFT         0
#define BCHP_NAND_SPARE_AREA_READ_OFS_3C_BYTE_OFS_63_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_0 - Nand Flash Spare Area Write Bytes 0-3
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_0 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_MASK           0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_SHIFT          24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_0_DEFAULT        0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_1 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_MASK           0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_SHIFT          16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_1_DEFAULT        0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_2 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_MASK           0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_SHIFT          8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_2_DEFAULT        0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_0 :: BYTE_OFS_3 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_MASK           0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_SHIFT          0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_0_BYTE_OFS_3_DEFAULT        0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_4 - Nand Flash Spare Area Write Bytes 4-7
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_4 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_MASK           0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_SHIFT          24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_4_DEFAULT        0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_5 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_MASK           0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_SHIFT          16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_5_DEFAULT        0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_6 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_MASK           0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_SHIFT          8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_6_DEFAULT        0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_4 :: BYTE_OFS_7 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_MASK           0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_SHIFT          0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_4_BYTE_OFS_7_DEFAULT        0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_8 - Nand Flash Spare Area Write Bytes 8-11
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_8 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_MASK           0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_SHIFT          24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_8_DEFAULT        0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_9 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_MASK           0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_SHIFT          16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_9_DEFAULT        0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_10 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_SHIFT         8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_10_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_8 :: BYTE_OFS_11 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_SHIFT         0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_8_BYTE_OFS_11_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_C - Nand Flash Spare Area Write Bytes 12-15
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_12 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_MASK          0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_SHIFT         24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_12_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_13 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_MASK          0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_SHIFT         16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_13_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_14 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_MASK          0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_SHIFT         8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_14_DEFAULT       0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_C :: BYTE_OFS_15 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_MASK          0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_SHIFT         0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_C_BYTE_OFS_15_DEFAULT       0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_10 - Nand Flash Spare Area Write Bytes 16-19
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_16 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_MASK         0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_SHIFT        24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_16_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_17 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_MASK         0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_SHIFT        16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_17_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_18 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_MASK         0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_SHIFT        8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_18_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_10 :: BYTE_OFS_19 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_MASK         0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_SHIFT        0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_10_BYTE_OFS_19_DEFAULT      0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_14 - Nand Flash Spare Area Write Bytes 20-23
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_20 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_MASK         0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_SHIFT        24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_20_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_21 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_MASK         0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_SHIFT        16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_21_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_22 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_MASK         0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_SHIFT        8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_22_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_14 :: BYTE_OFS_23 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_MASK         0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_SHIFT        0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_14_BYTE_OFS_23_DEFAULT      0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_18 - Nand Flash Spare Area Write Bytes 24-27
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_24 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_MASK         0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_SHIFT        24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_24_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_25 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_MASK         0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_SHIFT        16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_25_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_26 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_MASK         0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_SHIFT        8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_26_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_18 :: BYTE_OFS_27 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_MASK         0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_SHIFT        0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_18_BYTE_OFS_27_DEFAULT      0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_1C - Nand Flash Spare Area Write Bytes 28-31
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_28 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_MASK         0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_SHIFT        24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_28_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_29 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_MASK         0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_SHIFT        16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_29_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_30 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_MASK         0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_SHIFT        8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_30_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_1C :: BYTE_OFS_31 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_MASK         0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_SHIFT        0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_1C_BYTE_OFS_31_DEFAULT      0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_20 - Nand Flash Spare Area Write Bytes 32-35
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_32 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_MASK         0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_SHIFT        24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_32_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_33 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_MASK         0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_SHIFT        16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_33_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_34 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_MASK         0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_SHIFT        8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_34_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_20 :: BYTE_OFS_35 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_MASK         0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_SHIFT        0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_20_BYTE_OFS_35_DEFAULT      0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_24 - Nand Flash Spare Area Write Bytes 36-39
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_36 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_MASK         0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_SHIFT        24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_36_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_37 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_MASK         0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_SHIFT        16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_37_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_38 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_MASK         0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_SHIFT        8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_38_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_24 :: BYTE_OFS_39 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_MASK         0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_SHIFT        0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_24_BYTE_OFS_39_DEFAULT      0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_28 - Nand Flash Spare Area Write Bytes 40-43
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_40 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_MASK         0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_SHIFT        24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_40_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_41 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_MASK         0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_SHIFT        16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_41_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_42 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_MASK         0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_SHIFT        8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_42_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_28 :: BYTE_OFS_43 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_MASK         0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_SHIFT        0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_28_BYTE_OFS_43_DEFAULT      0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_2C - Nand Flash Spare Area Write Bytes 44-47
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_44 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_MASK         0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_SHIFT        24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_44_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_45 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_MASK         0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_SHIFT        16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_45_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_46 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_MASK         0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_SHIFT        8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_46_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_2C :: BYTE_OFS_47 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_MASK         0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_SHIFT        0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_2C_BYTE_OFS_47_DEFAULT      0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_30 - Nand Flash Spare Area Write Bytes 48-51
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_48 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_MASK         0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_SHIFT        24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_48_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_49 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_MASK         0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_SHIFT        16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_49_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_50 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_MASK         0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_SHIFT        8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_50_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_30 :: BYTE_OFS_51 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_MASK         0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_SHIFT        0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_30_BYTE_OFS_51_DEFAULT      0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_34 - Nand Flash Spare Area Write Bytes 52-55
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_52 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_MASK         0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_SHIFT        24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_52_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_53 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_MASK         0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_SHIFT        16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_53_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_54 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_MASK         0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_SHIFT        8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_54_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_34 :: BYTE_OFS_55 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_MASK         0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_SHIFT        0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_34_BYTE_OFS_55_DEFAULT      0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_38 - Nand Flash Spare Area Write Bytes 56-59
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_56 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_MASK         0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_SHIFT        24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_56_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_57 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_MASK         0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_SHIFT        16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_57_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_58 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_MASK         0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_SHIFT        8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_58_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_38 :: BYTE_OFS_59 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_MASK         0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_SHIFT        0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_38_BYTE_OFS_59_DEFAULT      0x000000ff

/***************************************************************************
 *SPARE_AREA_WRITE_OFS_3C - Nand Flash Spare Area Write Bytes 60-63
 ***************************************************************************/
/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_60 [31:24] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_MASK         0xff000000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_SHIFT        24
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_60_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_61 [23:16] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_MASK         0x00ff0000
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_SHIFT        16
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_61_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_62 [15:08] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_MASK         0x0000ff00
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_SHIFT        8
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_62_DEFAULT      0x000000ff

/* NAND :: SPARE_AREA_WRITE_OFS_3C :: BYTE_OFS_63 [07:00] */
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_MASK         0x000000ff
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_SHIFT        0
#define BCHP_NAND_SPARE_AREA_WRITE_OFS_3C_BYTE_OFS_63_DEFAULT      0x000000ff

/***************************************************************************
 *DDR_TIMING - Nand Flash DDR TIMING
 ***************************************************************************/
/* NAND :: DDR_TIMING :: reserved0 [31:24] */
#define BCHP_NAND_DDR_TIMING_reserved0_MASK                        0xff000000
#define BCHP_NAND_DDR_TIMING_reserved0_SHIFT                       24

/* NAND :: DDR_TIMING :: tCAD [23:20] */
#define BCHP_NAND_DDR_TIMING_tCAD_MASK                             0x00f00000
#define BCHP_NAND_DDR_TIMING_tCAD_SHIFT                            20
#define BCHP_NAND_DDR_TIMING_tCAD_DEFAULT                          0x00000004

/* NAND :: DDR_TIMING :: reserved1 [19:17] */
#define BCHP_NAND_DDR_TIMING_reserved1_MASK                        0x000e0000
#define BCHP_NAND_DDR_TIMING_reserved1_SHIFT                       17

/* NAND :: DDR_TIMING :: tWHR [16:12] */
#define BCHP_NAND_DDR_TIMING_tWHR_MASK                             0x0001f000
#define BCHP_NAND_DDR_TIMING_tWHR_SHIFT                            12
#define BCHP_NAND_DDR_TIMING_tWHR_DEFAULT                          0x00000014

/* NAND :: DDR_TIMING :: tCS [11:08] */
#define BCHP_NAND_DDR_TIMING_tCS_MASK                              0x00000f00
#define BCHP_NAND_DDR_TIMING_tCS_SHIFT                             8
#define BCHP_NAND_DDR_TIMING_tCS_DEFAULT                           0x00000002

/* NAND :: DDR_TIMING :: tWB [07:04] */
#define BCHP_NAND_DDR_TIMING_tWB_MASK                              0x000000f0
#define BCHP_NAND_DDR_TIMING_tWB_SHIFT                             4
#define BCHP_NAND_DDR_TIMING_tWB_DEFAULT                           0x0000000f

/* NAND :: DDR_TIMING :: tADL [03:00] */
#define BCHP_NAND_DDR_TIMING_tADL_MASK                             0x0000000f
#define BCHP_NAND_DDR_TIMING_tADL_SHIFT                            0
#define BCHP_NAND_DDR_TIMING_tADL_DEFAULT                          0x00000007

/***************************************************************************
 *DDR_NCDL_CALIB_CTL - Nand Flash Calibration Control for Master DLL
 ***************************************************************************/
/* NAND :: DDR_NCDL_CALIB_CTL :: reserved0 [31:04] */
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_MASK                0xfffffff0
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_reserved0_SHIFT               4

/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_PERIODIC [03:03] */
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_MASK           0x00000008
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_SHIFT          3
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_PERIODIC_DEFAULT        0x00000000

/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ALWAYS [02:02] */
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_MASK             0x00000004
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_SHIFT            2
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ALWAYS_DEFAULT          0x00000000

/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_ONCE [01:01] */
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_MASK               0x00000002
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_SHIFT              1
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_ONCE_DEFAULT            0x00000000

/* NAND :: DDR_NCDL_CALIB_CTL :: CALIB_EN [00:00] */
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_MASK                 0x00000001
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_SHIFT                0
#define BCHP_NAND_DDR_NCDL_CALIB_CTL_CALIB_EN_DEFAULT              0x00000000

/***************************************************************************
 *DDR_NCDL_CALIB_PERIOD - Nand Flash Calibration Period
 ***************************************************************************/
/* NAND :: DDR_NCDL_CALIB_PERIOD :: reserved0 [31:20] */
#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_MASK             0xfff00000
#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_reserved0_SHIFT            20

/* NAND :: DDR_NCDL_CALIB_PERIOD :: CALIB_PERIOD [19:00] */
#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_MASK          0x000fffff
#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_SHIFT         0
#define BCHP_NAND_DDR_NCDL_CALIB_PERIOD_CALIB_PERIOD_DEFAULT       0x00000000

/***************************************************************************
 *DDR_NCDL_CALIB_STAT - Nand Flash Calibration Status for Master DLL
 ***************************************************************************/
/* NAND :: DDR_NCDL_CALIB_STAT :: reserved0 [31:16] */
#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_MASK               0xffff0000
#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved0_SHIFT              16

/* NAND :: DDR_NCDL_CALIB_STAT :: NCDL_PHASE [15:08] */
#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_MASK              0x0000ff00
#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_SHIFT             8
#define BCHP_NAND_DDR_NCDL_CALIB_STAT_NCDL_PHASE_DEFAULT           0x00000000

/* NAND :: DDR_NCDL_CALIB_STAT :: reserved1 [07:01] */
#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_MASK               0x000000fe
#define BCHP_NAND_DDR_NCDL_CALIB_STAT_reserved1_SHIFT              1

/* NAND :: DDR_NCDL_CALIB_STAT :: CALIB_LOCK [00:00] */
#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_MASK              0x00000001
#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_SHIFT             0
#define BCHP_NAND_DDR_NCDL_CALIB_STAT_CALIB_LOCK_DEFAULT           0x00000000

/***************************************************************************
 *DDR_NCDL_MODE - Nand Flash NCDL mode for Slave DLLs
 ***************************************************************************/
/* NAND :: DDR_NCDL_MODE :: reserved0 [31:05] */
#define BCHP_NAND_DDR_NCDL_MODE_reserved0_MASK                     0xffffffe0
#define BCHP_NAND_DDR_NCDL_MODE_reserved0_SHIFT                    5

/* NAND :: DDR_NCDL_MODE :: RDNCDL [04:04] */
#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_MASK                        0x00000010
#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_SHIFT                       4
#define BCHP_NAND_DDR_NCDL_MODE_RDNCDL_DEFAULT                     0x00000000

/* NAND :: DDR_NCDL_MODE :: reserved1 [03:01] */
#define BCHP_NAND_DDR_NCDL_MODE_reserved1_MASK                     0x0000000e
#define BCHP_NAND_DDR_NCDL_MODE_reserved1_SHIFT                    1

/* NAND :: DDR_NCDL_MODE :: WRNCDL [00:00] */
#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_MASK                        0x00000001
#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_SHIFT                       0
#define BCHP_NAND_DDR_NCDL_MODE_WRNCDL_DEFAULT                     0x00000000

/***************************************************************************
 *DDR_NCDL_OFFSET - Nand Flash NCDL offset for Slave DLLs
 ***************************************************************************/
/* NAND :: DDR_NCDL_OFFSET :: reserved0 [31:25] */
#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_MASK                   0xfe000000
#define BCHP_NAND_DDR_NCDL_OFFSET_reserved0_SHIFT                  25

/* NAND :: DDR_NCDL_OFFSET :: RDNCDL_OFF [24:16] */
#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_MASK                  0x01ff0000
#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_SHIFT                 16
#define BCHP_NAND_DDR_NCDL_OFFSET_RDNCDL_OFF_DEFAULT               0x00000000

/* NAND :: DDR_NCDL_OFFSET :: reserved1 [15:09] */
#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_MASK                   0x0000fe00
#define BCHP_NAND_DDR_NCDL_OFFSET_reserved1_SHIFT                  9

/* NAND :: DDR_NCDL_OFFSET :: WRNCDL_OFF [08:00] */
#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_MASK                  0x000001ff
#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_SHIFT                 0
#define BCHP_NAND_DDR_NCDL_OFFSET_WRNCDL_OFF_DEFAULT               0x00000000

/***************************************************************************
 *DDR_PHY_CTL - Nand Flash DDR PHY CONTROL
 ***************************************************************************/
/* NAND :: DDR_PHY_CTL :: reserved0 [31:02] */
#define BCHP_NAND_DDR_PHY_CTL_reserved0_MASK                       0xfffffffc
#define BCHP_NAND_DDR_PHY_CTL_reserved0_SHIFT                      2

/* NAND :: DDR_PHY_CTL :: DDR_MODE [01:01] */
#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_MASK                        0x00000002
#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_SHIFT                       1
#define BCHP_NAND_DDR_PHY_CTL_DDR_MODE_DEFAULT                     0x00000000

/* NAND :: DDR_PHY_CTL :: reserved1 [00:00] */
#define BCHP_NAND_DDR_PHY_CTL_reserved1_MASK                       0x00000001
#define BCHP_NAND_DDR_PHY_CTL_reserved1_SHIFT                      0

/***************************************************************************
 *DDR_PHY_BIST_CTL - Nand Flash DDR PHY BIST CONTROL
 ***************************************************************************/
/* NAND :: DDR_PHY_BIST_CTL :: reserved0 [31:05] */
#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_MASK                  0xffffffe0
#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved0_SHIFT                 5

/* NAND :: DDR_PHY_BIST_CTL :: BIST_CLR [04:04] */
#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_MASK                   0x00000010
#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_SHIFT                  4
#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_CLR_DEFAULT                0x00000000

/* NAND :: DDR_PHY_BIST_CTL :: reserved1 [03:01] */
#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_MASK                  0x0000000e
#define BCHP_NAND_DDR_PHY_BIST_CTL_reserved1_SHIFT                 1

/* NAND :: DDR_PHY_BIST_CTL :: BIST_START [00:00] */
#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_MASK                 0x00000001
#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_SHIFT                0
#define BCHP_NAND_DDR_PHY_BIST_CTL_BIST_START_DEFAULT              0x00000000

/***************************************************************************
 *DDR_PHY_BIST_STAT - Nand Flash DDR PHY BIST STATUS
 ***************************************************************************/
/* NAND :: DDR_PHY_BIST_STAT :: reserved0 [31:07] */
#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_MASK                 0xffffff80
#define BCHP_NAND_DDR_PHY_BIST_STAT_reserved0_SHIFT                7

/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_RDPH_ERR [06:06] */
#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_MASK          0x00000040
#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_RDPH_ERR_SHIFT         6

/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_RDPH_ERR [05:05] */
#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_MASK          0x00000020
#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_RDPH_ERR_SHIFT         5

/* NAND :: DDR_PHY_BIST_STAT :: W1_DATA_WRPH_ERR [04:04] */
#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_MASK          0x00000010
#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_DATA_WRPH_ERR_SHIFT         4

/* NAND :: DDR_PHY_BIST_STAT :: W0_DATA_WRPH_ERR [03:03] */
#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_MASK          0x00000008
#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_DATA_WRPH_ERR_SHIFT         3

/* NAND :: DDR_PHY_BIST_STAT :: W1_ADDR_ERR [02:02] */
#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_MASK               0x00000004
#define BCHP_NAND_DDR_PHY_BIST_STAT_W1_ADDR_ERR_SHIFT              2

/* NAND :: DDR_PHY_BIST_STAT :: W0_ADDR_ERR [01:01] */
#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_MASK               0x00000002
#define BCHP_NAND_DDR_PHY_BIST_STAT_W0_ADDR_ERR_SHIFT              1

/* NAND :: DDR_PHY_BIST_STAT :: BIST_DONE [00:00] */
#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_MASK                 0x00000001
#define BCHP_NAND_DDR_PHY_BIST_STAT_BIST_DONE_SHIFT                0

/***************************************************************************
 *DDR_DIAG_STAT0 - Nand Flash DDR DIAG STATUS0
 ***************************************************************************/
/* NAND :: DDR_DIAG_STAT0 :: DIAG_STATUS [31:00] */
#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_MASK                  0xffffffff
#define BCHP_NAND_DDR_DIAG_STAT0_DIAG_STATUS_SHIFT                 0

/***************************************************************************
 *DDR_DIAG_STAT1 - Nand Flash DDR DIAG STATUS1
 ***************************************************************************/
/* NAND :: DDR_DIAG_STAT1 :: DIAG_STATUS [31:00] */
#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_MASK                  0xffffffff
#define BCHP_NAND_DDR_DIAG_STAT1_DIAG_STATUS_SHIFT                 0

/***************************************************************************
 *FLASH_CACHE%i - Flash Cache Buffer Read Access
 ***************************************************************************/
#define BCHP_NAND_FLASH_CACHEi_ARRAY_BASE                          0x203d2c00
#define BCHP_NAND_FLASH_CACHEi_ARRAY_START                         0
#define BCHP_NAND_FLASH_CACHEi_ARRAY_END                           127
#define BCHP_NAND_FLASH_CACHEi_ARRAY_ELEMENT_SIZE                  32

/***************************************************************************
 *FLASH_CACHE%i - Flash Cache Buffer Read Access
 ***************************************************************************/
/* NAND :: FLASH_CACHEi :: WORD [31:00] */
#define BCHP_NAND_FLASH_CACHEi_WORD_MASK                           0xffffffff
#define BCHP_NAND_FLASH_CACHEi_WORD_SHIFT                          0


#endif /* #ifndef BCHP_NAND_H__ */

/* End of File */