/***************************************************************************
 *     Copyright (c) 1999-2013, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Sat Apr  6 03:07:45 2013
 *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_CLKGEN_H__
#define BCHP_CLKGEN_H__

/***************************************************************************
 *CLKGEN - clkgen registers
 ***************************************************************************/
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON 0x20480000 /* Bandgap Power on */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x20480004 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x20480008 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x2048000c /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x20480010 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x20480014 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV      0x20480018 /* Pre multiplier */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN     0x2048001c /* PLL GAIN */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL 0x20480020 /* Hold PLL all channels */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL 0x20480024 /* Ldo voltage control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON 0x20480028 /* LDO Power on */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS 0x2048002c /* Lock Status */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC     0x20480030 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2    0x20480034 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON    0x20480038 /* Poweron */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET    0x2048003c /* Resets */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x20480040 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x20480044 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS   0x20480048 /* Status */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON 0x2048004c /* Bandgap Power on */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x20480050 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x20480054 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x20480058 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x2048005c /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x20480060 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV      0x20480064 /* Pre multiplier */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN     0x20480068 /* PLL GAIN */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL 0x2048006c /* Hold PLL all channels */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL 0x20480070 /* Ldo voltage control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON 0x20480074 /* LDO Power on */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS 0x20480078 /* Lock Status */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC     0x2048007c /* Mscellaneous control bus. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2    0x20480080 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON    0x20480084 /* Poweron */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET    0x20480088 /* Resets */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x2048008c /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x20480090 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS   0x20480094 /* Status */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON 0x20480098 /* Bandgap Power on */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 0x2048009c /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV      0x204800a0 /* Pre multiplier */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN     0x204800a4 /* PLL GAIN */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL 0x204800a8 /* Hold PLL all channels */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL 0x204800ac /* Ldo voltage control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON 0x204800b0 /* LDO Power on */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS 0x204800b4 /* Lock Status */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC     0x204800b8 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2    0x204800bc /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON    0x204800c0 /* Poweron */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET    0x204800c4 /* Resets */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH 0x204800c8 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW 0x204800cc /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS   0x204800d0 /* Status */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON      0x204800d4 /* Bandgap Power on */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x204800d8 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x204800dc /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL      0x204800e0 /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON     0x204800e4 /* LDO Power on */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x204800e8 /* Lock Status */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON         0x204800ec /* Poweron */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x204800f0 /* Resets */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x204800f4 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x204800f8 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x204800fc /* Status */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON      0x20480100 /* Bandgap Power on */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x20480104 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x20480108 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL      0x2048010c /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON     0x20480110 /* LDO Power on */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x20480114 /* Lock Status */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON         0x20480118 /* Poweron */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x2048011c /* Resets */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x20480120 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x20480124 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x20480128 /* Status */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON      0x2048012c /* Bandgap Power on */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV           0x20480130 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN          0x20480134 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL      0x20480138 /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON     0x2048013c /* LDO Power on */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS   0x20480140 /* Lock Status */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON         0x20480144 /* Poweron */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET         0x20480148 /* Resets */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH 0x2048014c /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW 0x20480150 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS        0x20480154 /* Status */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x20480158 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x2048015c /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x20480160 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3 0x20480164 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4 0x20480168 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV              0x2048016c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN             0x20480170 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON        0x20480174 /* LDO Power on */
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS      0x20480178 /* Lock Status */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC             0x2048017c /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2            0x20480180 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON            0x20480184 /* Poweron */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET            0x20480188 /* Resets */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x2048018c /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x20480190 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS           0x20480194 /* Status */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 0x20480198 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 0x2048019c /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV         0x204801a0 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC        0x204801a4 /* Fractional */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN        0x204801a8 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON   0x204801ac /* LDO Power on */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS 0x204801b0 /* Lock Status */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC        0x204801b4 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2       0x204801b8 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON       0x204801bc /* Poweron */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET       0x204801c0 /* Resets */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH 0x204801c4 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW 0x204801c8 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS      0x204801cc /* Status */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 0x204801d0 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 0x204801d4 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV       0x204801d8 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_FRAC      0x204801dc /* Fractional */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN      0x204801e0 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LDO_PWRON 0x204801e4 /* LDO Power on */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS 0x204801e8 /* Lock Status */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC      0x204801ec /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2     0x204801f0 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_PWRON     0x204801f4 /* Poweron */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET     0x204801f8 /* Resets */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH 0x204801fc /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW 0x20480200 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_STATUS    0x20480204 /* Status */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0 0x20480208 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1 0x2048020c /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2 0x20480210 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3 0x20480214 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL           0x20480218 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_LC_PLL_DIV               0x2048021c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN              0x20480220 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL       0x20480224 /* Hold PLL all channels */
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL          0x20480228 /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON         0x2048022c /* LDO Power on */
#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS       0x20480230 /* Lock Status */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC              0x20480234 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2             0x20480238 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL        0x2048023c /* selection of the output clock from the PLL core */
#define BCHP_CLKGEN_PLL_LC_PLL_PWRON             0x20480240 /* Poweron */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET             0x20480244 /* Resets */
#define BCHP_CLKGEN_PLL_LC_PLL_STATUS            0x20480248 /* Status */
#define BCHP_CLKGEN_PLL_LC_PLL_TEST              0x2048024c /* enable and selection pf PLL test */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x20480250 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x20480254 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x20480258 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x2048025c /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV             0x20480260 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN            0x20480264 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON       0x20480268 /* LDO Power on */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS     0x2048026c /* Lock Status */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC            0x20480270 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2           0x20480274 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON           0x20480278 /* Poweron */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET           0x2048027c /* Resets */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x20480280 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x20480284 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS          0x20480288 /* Status */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x2048028c /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 0x20480290 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 0x20480294 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 0x20480298 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 0x2048029c /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV            0x204802a0 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN           0x204802a4 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON      0x204802a8 /* LDO Power on */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS    0x204802ac /* Lock Status */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC           0x204802b0 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2          0x204802b4 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON          0x204802b8 /* Poweron */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET          0x204802bc /* Resets */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x204802c0 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x204802c4 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS         0x204802c8 /* Status */
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0 0x204802cc /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV              0x204802d0 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC             0x204802d4 /* Fractional */
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN             0x204802d8 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON        0x204802dc /* LDO Power on */
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS      0x204802e0 /* Lock Status */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC             0x204802e4 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2            0x204802e8 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON            0x204802ec /* Poweron */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET            0x204802f0 /* Resets */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH 0x204802f4 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW 0x204802f8 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS           0x204802fc /* Status */
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0 0x20480300 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV              0x20480304 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC             0x20480308 /* Fractional */
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN             0x2048030c /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON        0x20480310 /* LDO Power on */
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS      0x20480314 /* Lock Status */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC             0x20480318 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2            0x2048031c /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON            0x20480320 /* Poweron */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET            0x20480324 /* Resets */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH 0x20480328 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW 0x2048032c /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS           0x20480330 /* Status */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 0x20480334 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 0x20480338 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 0x2048033c /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV           0x20480340 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN          0x20480344 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON     0x20480348 /* LDO Power on */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS   0x2048034c /* Lock Status */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC          0x20480350 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2         0x20480354 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON         0x20480358 /* Poweron */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET         0x2048035c /* Resets */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH 0x20480360 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW 0x20480364 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS        0x20480368 /* Status */
#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON        0x2048036c /* Bandgap Power on */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x20480370 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x20480374 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x20480378 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x2048037c /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x20480380 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x20480384 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x20480388 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x2048038c /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL     0x20480390 /* Hold PLL all channels */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL        0x20480394 /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON       0x20480398 /* LDO Power on */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x2048039c /* Lock Status */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x204803a0 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x204803a4 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON           0x204803a8 /* Poweron */
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET           0x204803ac /* Resets */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x204803b0 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x204803b4 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x204803b8 /* Status */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON       0x204803bc /* Bandgap Power on */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 0x204803c0 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 0x204803c4 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 0x204803c8 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV            0x204803cc /* Pre multiplier */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC           0x204803d0 /* Fractional */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN           0x204803d4 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL    0x204803d8 /* Hold PLL all channels */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL       0x204803dc /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON      0x204803e0 /* LDO Power on */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS    0x204803e4 /* Lock Status */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC           0x204803e8 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2          0x204803ec /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON          0x204803f0 /* Poweron */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET          0x204803f4 /* Resets */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH 0x204803f8 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW 0x204803fc /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS         0x20480400 /* Status */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON       0x20480404 /* Bandgap Power on */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 0x20480408 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 0x2048040c /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 0x20480410 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV            0x20480414 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC           0x20480418 /* Fractional */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN           0x2048041c /* PLL GAIN */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL    0x20480420 /* Hold PLL all channels */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL       0x20480424 /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON      0x20480428 /* LDO Power on */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS    0x2048042c /* Lock Status */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC           0x20480430 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2          0x20480434 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON          0x20480438 /* Poweron */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET          0x2048043c /* Resets */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH 0x20480440 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW 0x20480444 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS         0x20480448 /* Status */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON       0x2048044c /* Bandgap Power on */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 0x20480450 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 0x20480454 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 0x20480458 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV            0x2048045c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC           0x20480460 /* Fractional */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN           0x20480464 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL    0x20480468 /* Hold PLL all channels */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL       0x2048046c /* Ldo voltage control */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON      0x20480470 /* LDO Power on */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS    0x20480474 /* Lock Status */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC           0x20480478 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2          0x2048047c /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON          0x20480480 /* Poweron */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET          0x20480484 /* Resets */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH 0x20480488 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW 0x2048048c /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS         0x20480490 /* Status */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0 0x20480494 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1 0x20480498 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2 0x2048049c /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3 0x204804a0 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4 0x204804a4 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5 0x204804a8 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV              0x204804ac /* Pre multiplier */
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN             0x204804b0 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON        0x204804b4 /* LDO Power on */
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS      0x204804b8 /* Lock Status */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC             0x204804bc /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2            0x204804c0 /* Mscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON            0x204804c4 /* Poweron */
#define BCHP_CLKGEN_PLL_XPT_PLL_RESET            0x204804c8 /* Resets */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH 0x204804cc /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW 0x204804d0 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS           0x204804d4 /* Status */
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x204804d8 /* Disable ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x204804dc /* Clock Disable Status */
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE 0x204804e0 /* Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks */
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS 0x204804e4 /* Clock Disable Status */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE 0x204804e8 /* Apm chip top inst clock enable */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS 0x204804ec /* Clock Enable Status */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE 0x204804f0 /* Avd sid1 top inst clock enable */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID 0x204804f4 /* Avd sid1 top inst clock enable sid */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS 0x204804f8 /* Clock Enable Status */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS 0x204804fc /* Clock Enable Status */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK 0x20480500 /* Avd sid1 top inst observe clock */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE 0x20480504 /* Bvn mvp top inst clock enable */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS 0x20480508 /* Clock Enable Status */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE    0x2048050c /* Bvn top inst clock enable */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS 0x20480510 /* Clock Enable Status */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x20480514 /* Disable CLKGEN's clocks */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS  0x20480518 /* Clock Disable Status */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE     0x2048051c /* Clkgen inst clock enable */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS 0x20480520 /* Clock Enable Status */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x20480524 /* Clock Monitor Control */
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x20480528 /* Clock Monitor Max Reference Count */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x2048052c /* Clock Monitor Reference Counter */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x20480530 /* Clock Monitor Reference Counter */
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x20480534 /* Clock Monitor View Counter */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE   0x20480538 /* Core xpt inst clock enable */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS 0x2048053c /* Clock Enable Status */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK  0x20480540 /* Core xpt inst observe clock */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE 0x20480544 /* Disable CPU4355_BCM_MIPS_TOP_INST's clocks */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS 0x20480548 /* Clock Disable Status */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE 0x2048054c /* Cpu4355 bcm mips top inst clock enable */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS 0x20480550 /* Clock Enable Status */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE 0x20480554 /* Disable D3DSMAC_X4_TOP_INST's clocks */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS 0x20480558 /* Clock Disable Status */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE 0x2048055c /* D3dsmac x4 top inst clock enable */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS 0x20480560 /* Clock Enable Status */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE 0x20480564 /* Disable DECT_UBUS_TOP_INST's clocks */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS 0x20480568 /* Clock Disable Status */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE 0x2048056c /* Dect ubus top inst clock enable */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS 0x20480570 /* Clock Enable Status */
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2    0x20480574 /* Disable AVS_TOP 54MHz clocks during S2 standby. */
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE 0x20480578 /* Secure AVS_TOP clock disable. Set at start-up to guarantee AVS_TOP is clock gated in S2 standby. */
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT            0x2048057c /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL 0x20480580 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS 0x20480584 /* DOCSIS_PLL_SYS2 Reset Status */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE    0x20480588 /* Ds topa inst clock enable */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS 0x2048058c /* Clock Enable Status */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE    0x20480590 /* Ds topb inst clock enable */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS 0x20480594 /* Clock Enable Status */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE    0x20480598 /* Ds topc inst clock enable */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS 0x2048059c /* Clock Enable Status */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE    0x204805a0 /* Ds topd inst clock enable */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS 0x204805a4 /* Clock Enable Status */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE 0x204805a8 /* Ds wfe top inst clock enable */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS 0x204805ac /* Clock Enable Status */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE 0x204805b0 /* Disable DTP_DFAP_TOP_INST's clocks */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS 0x204805b4 /* Clock Disable Status */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE 0x204805b8 /* Dtp dfap top inst clock enable */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS 0x204805bc /* Clock Enable Status */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE    0x204805c0 /* Disable DVP_HR_INST's clocks */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS 0x204805c4 /* Clock Disable Status */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE     0x204805c8 /* Dvp hr inst clock enable */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS 0x204805cc /* Clock Enable Status */
#define BCHP_CLKGEN_DVP_HR_INST_ENABLE           0x204805d0 /* Dvp hr inst enable */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK    0x204805d4 /* Dvp hr inst observe clock */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE    0x204805d8 /* Disable DVP_HT_INST's clocks */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS 0x204805dc /* Clock Disable Status */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE     0x204805e0 /* Dvp ht inst clock enable */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS 0x204805e4 /* Clock Enable Status */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK    0x204805e8 /* Dvp ht inst observe clock */
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE 0x204805ec /* Eaglet top core inst clock enable */
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS 0x204805f0 /* Clock Enable Status */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE 0x204805f4 /* Eaglet top router inst clock enable */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS 0x204805f8 /* Clock Enable Status */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_SELECT 0x204805fc /* Eaglet top router inst select */
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT 0x20480600 /* Egphy28 4port 33v 90o fc inst clock select */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE 0x20480604 /* G2u u2u ubus mod ss inst clock enable */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS 0x20480608 /* Clock Enable Status */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE  0x2048060c /* Disable GFAP_TOP_INST's clocks */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS 0x20480610 /* Clock Disable Status */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE   0x20480614 /* Gfap top inst clock enable */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0  0x20480618 /* Gfap top inst clock enable0 */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS 0x2048061c /* Clock Enable Status */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS 0x20480620 /* Clock Enable Status */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE   0x20480624 /* Graphics inst clock enable */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0  0x20480628 /* Graphics inst clock enable0 */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS 0x2048062c /* Clock Enable Status */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1  0x20480630 /* Graphics inst clock enable1 */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS 0x20480634 /* Clock Enable Status */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0 0x20480638 /* Graphics inst clock enable m2mc0 */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS 0x2048063c /* Clock Enable Status */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1 0x20480640 /* Graphics inst clock enable m2mc1 */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS 0x20480644 /* Clock Enable Status */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS 0x20480648 /* Clock Enable Status */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK  0x2048064c /* Graphics inst observe clock */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE       0x20480650 /* Disable HIF_INST's clocks */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS 0x20480654 /* Clock Disable Status */
#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE        0x20480658 /* Hif inst clock enable */
#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS 0x2048065c /* Clock Enable Status */
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK       0x20480660 /* Hif inst observe clock */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE   0x20480664 /* Hvd0 top inst clock enable */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS 0x20480668 /* Clock Enable Status */
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK  0x2048066c /* Hvd0 top inst observe clock */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x20480670 /* Mux selects for Internal clocks */
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT          0x20480674 /* Mux selects for itu656_0 clocks */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE  0x20480678 /* Disable LEAP_TOP_INST's clocks */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS 0x2048067c /* Clock Disable Status */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE   0x20480680 /* Leap top inst clock enable */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS 0x20480684 /* Clock Enable Status */
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK  0x20480688 /* Leap top inst observe clock */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE 0x2048068c /* Memsys 32 wrapper 0 inst clock enable */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS 0x20480690 /* Clock Enable Status */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK 0x20480694 /* Memsys 32 wrapper 0 inst observe clock */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS 0x20480698 /* Memsys 32 wrapper 0 inst status */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE 0x2048069c /* Memsys 32 wrapper 1 inst clock enable */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS 0x204806a0 /* Clock Enable Status */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK 0x204806a4 /* Memsys 32 wrapper 1 inst observe clock */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS 0x204806a8 /* Memsys 32 wrapper 1 inst status */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE 0x204806ac /* Mocamac top inst clock enable */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS 0x204806b0 /* Clock Enable Status */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK 0x204806b4 /* Mocamac top inst observe clock */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE 0x204806b8 /* Mocaphy top inst clock enable */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS 0x204806bc /* Clock Enable Status */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK 0x204806c0 /* Mocaphy top inst observe clock */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE          0x204806c4 /* Disable MULTI's clocks */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS   0x204806c8 /* Clock Disable Status */
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION     0x204806cc /* Select observation clk */
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION     0x204806d0 /* Select observation clk */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x204806d4 /* Disable PAD's clocks */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS     0x204806d8 /* Clock Disable Status */
#define BCHP_CLKGEN_PAD_MUX_SELECT               0x204806dc /* Mux selects for Pad clocks */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE 0x204806e0 /* Disable PCIE_X2_TOP_INST's clocks */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS 0x204806e4 /* Clock Disable Status */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE 0x204806e8 /* Pcie x2 top inst clock enable */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS 0x204806ec /* Clock Enable Status */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK 0x204806f0 /* Pcie x2 top inst observe clock */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x204806f4 /* PLL_AUDIO0 Reset Status */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x204806f8 /* PLL_AUDIO1 Reset Status */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS  0x204806fc /* PLL_AUDIO2 Reset Status */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS     0x20480700 /* PLL_AVD Reset Status */
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL       0x20480704 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST 0x20480708 /* PLL_CPU_CORE Glitchless Clock Switching */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS 0x2048070c /* PLL_CPU_CORE Glitchless Switching */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS 0x20480710 /* PLL_CPU_CORE Reset Status */
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL  0x20480714 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS 0x20480718 /* PLL_CPU_ROUTER Reset Status */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL 0x2048071c /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS      0x20480720 /* PLL_LC Reset Status */
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL        0x20480724 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS    0x20480728 /* PLL_MOCA Reset Status */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL      0x2048072c /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS   0x20480730 /* PLL_RAAGA Reset Status */
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL     0x20480734 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS     0x20480738 /* PLL_SC0 Reset Status */
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL       0x2048073c /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS     0x20480740 /* PLL_SC1 Reset Status */
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL       0x20480744 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE           0x20480748 /* Disable */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS  0x2048074c /* PLL_SWITCH Reset Status */
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL      0x20480750 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS   0x20480754 /* PLL_VCXO0 Reset Status */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS   0x20480758 /* PLL_VCXO1 Reset Status */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS   0x2048075c /* PLL_VCXO2 Reset Status */
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL       0x20480760 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL     0x20480764 /* Select clocks that can stay alive during power management standby mode. */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x20480768 /* PLL Alive in Standby Mode */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x2048076c /* Power management LDO PLL */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE  0x20480770 /* Disable PROD_OTP_INST's clocks */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS 0x20480774 /* Clock Disable Status */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE   0x20480778 /* Prod otp inst clock enable */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS 0x2048077c /* Clock Enable Status */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE 0x20480780 /* Raaga dsp top 0 inst clock enable */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS 0x20480784 /* Clock Enable Status */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK 0x20480788 /* Raaga dsp top 0 inst observe clock */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE 0x2048078c /* Raaga dsp top 1 inst clock enable */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS 0x20480790 /* Clock Enable Status */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK 0x20480794 /* Raaga dsp top 1 inst observe clock */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE    0x20480798 /* Rfm top inst clock enable */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS 0x2048079c /* Clock Enable Status */
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK   0x204807a0 /* Rfm top inst observe clock */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE 0x204807a4 /* Disable SATA3_TOP_INST's clocks */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS 0x204807a8 /* Clock Disable Status */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE  0x204807ac /* Sata3 top inst clock enable */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS 0x204807b0 /* Clock Enable Status */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT  0x204807b4 /* Sata3 top inst clock select */
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK 0x204807b8 /* Sata3 top inst observe clock */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE     0x204807bc /* Sectop inst clock enable */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS 0x204807c0 /* Clock Enable Status */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x204807c4 /* Sectop inst observe clock */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x204807c8 /* Mux selects for Smartcard clocks */
#define BCHP_CLKGEN_SPARE                        0x204807cc /* Spares */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE 0x204807d0 /* Disable SWITCH_TOP_INST's clocks */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS 0x204807d4 /* Clock Disable Status */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE 0x204807d8 /* Switch top inst clock enable */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS 0x204807dc /* Clock Enable Status */
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK 0x204807e0 /* Switch top inst observe clock */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE  0x204807e4 /* Disable SYS_CTRL_INST's clocks */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS 0x204807e8 /* Clock Disable Status */
#define BCHP_CLKGEN_TESTPORT                     0x204807ec /* Special Testport Controls */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE 0x204807f0 /* Disable UBUS_MOD_PERIPH_FPM_INST's clocks */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS 0x204807f4 /* Clock Disable Status */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE 0x204807f8 /* Ubus mod periph fpm inst clock enable */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS 0x204807fc /* Clock Enable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE 0x20480800 /* Disable UNIMAC_MBDMA_TOP_ROUTER_1_INST's clocks */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS 0x20480804 /* Clock Disable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE 0x20480808 /* Unimac mbdma top router 1 inst clock enable */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS 0x2048080c /* Clock Enable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE 0x20480810 /* Disable UNIMAC_MBDMA_TOP_ROUTER_INST's clocks */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS 0x20480814 /* Clock Disable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE 0x20480818 /* Unimac mbdma top router inst clock enable */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS 0x2048081c /* Clock Enable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE 0x20480820 /* Disable UNIMAC_MBDMA_TOP_STB_INST's clocks */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS 0x20480824 /* Clock Disable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE 0x20480828 /* Unimac mbdma top stb inst clock enable */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS 0x2048082c /* Clock Enable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE 0x20480830 /* Disable UNIMAC_MBDMA_TOP_WAN_INST's clocks */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS 0x20480834 /* Clock Disable Status */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE 0x20480838 /* Unimac mbdma top wan inst clock enable */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS 0x2048083c /* Clock Enable Status */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE  0x20480840 /* Disable USB0_TOP_INST's clocks */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS 0x20480844 /* Clock Disable Status */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE   0x20480848 /* Usb0 top inst clock enable */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB 0x2048084c /* Usb0 top inst clock enable ahb */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS 0x20480850 /* Clock Enable Status */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI 0x20480854 /* Usb0 top inst clock enable axi */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS 0x20480858 /* Clock Enable Status */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS 0x2048085c /* Clock Enable Status */
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK  0x20480860 /* Usb0 top inst observe clock */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE 0x20480864 /* Disable USMAC_TC8X_DAVIC_TOP_INST's clocks */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS 0x20480868 /* Clock Disable Status */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE 0x2048086c /* Usmac tc8x davic top inst clock enable */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS 0x20480870 /* Clock Enable Status */
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE     0x20480874 /* Us top inst clock enable */
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS 0x20480878 /* Clock Enable Status */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE 0x2048087c /* Disable UTP_CRYPTO_SEGDMA_TOP_INST's clocks */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS 0x20480880 /* Clock Disable Status */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE 0x20480884 /* Utp crypto segdma top inst clock enable */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS 0x20480888 /* Clock Enable Status */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE    0x2048088c /* V3d top inst clock enable */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS 0x20480890 /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x20480894 /* Disable VEC_AIO_TOP_INST's clocks */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS 0x20480898 /* Clock Disable Status */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x2048089c /* Vec aio top inst clock enable */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS 0x204808a0 /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF 0x204808a4 /* Vec aio top inst clock enable vec qdac intf */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS 0x204808a8 /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x204808ac /* Vec aio top inst observe clock */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE    0x204808b0 /* Vice2 0 inst clock enable */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS 0x204808b4 /* Clock Enable Status */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE    0x204808b8 /* Vice2 1 inst clock enable */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS 0x204808bc /* Clock Enable Status */

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_reserved0_SHIFT   1

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000000c

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000e

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000012

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000090

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000024

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_reserved0_MASK         0xffffc000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_reserved0_SHIFT        14

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_PDIV_MASK              0x00003c00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_PDIV_SHIFT             10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_PDIV_DEFAULT           0x00000002

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_NDIV_INT_MASK          0x000003ff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT         0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT       0x00000090

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_reserved0_MASK        0xfffffc00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_reserved0_SHIFT       10

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_reserved0_MASK    0xffff0000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_reserved0_SHIFT   16

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_MASK     0x0000ffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_SHIFT    0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT  0x00000005

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_reserved0_SHIFT  1

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT 2

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK      0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT     0

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_MASK    0x80000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_SHIFT   31
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_MASK   0x40000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_SHIFT  30
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_DIV2_MASK         0x20000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_DIV2_SHIFT        29
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_VCO_DIV2_DEFAULT      0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK      0x10000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT     28
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK      0x0e000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT     25
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_RESET_MASK       0x01000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_RESET_SHIFT      24
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_RESET_DEFAULT    0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_MODE_MASK        0x00c00000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT       22
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT     0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_MASK     0x00200000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_SHIFT    21
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_DEFAULT  0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_PWM_RATE_MASK         0x00180000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT        19
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT      0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK      0x00010000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT     16
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK        0x00008000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT       15
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT     0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DITHER_DISABLE_MASK   0x00004000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DITHER_DISABLE_SHIFT  14
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK  0x00001ffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK         0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT        0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT      0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_PLLRESERVED0_MASK    0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_PLLRESERVED0_SHIFT   1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_MASK   0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_SHIFT  0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_reserved0_SHIFT      1

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_PWRON_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_reserved0_SHIFT      1

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_RESET :: RESETD [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_RESETD_MASK          0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_RESETD_SHIFT         0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_RESET_RESETD_DEFAULT       0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS0_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_reserved0_MASK      0xfffff000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_reserved0_SHIFT     12

/* CLKGEN :: DOCSIS_PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK    0x00000fff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT   0

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_reserved0_SHIFT   1

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000006

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000012

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000024

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000000c

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_reserved0_MASK         0xffffc000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_reserved0_SHIFT        14

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_PDIV_MASK              0x00003c00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_PDIV_SHIFT             10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_PDIV_DEFAULT           0x00000003

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_NDIV_INT_MASK          0x000003ff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT         0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT       0x000000c8

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_reserved0_MASK        0xfffffc00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_reserved0_SHIFT       10

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_reserved0_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_reserved0_MASK    0xffff0000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_reserved0_SHIFT   16

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_LDO_CTRL_MASK     0x0000ffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_LDO_CTRL_SHIFT    0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT  0x00000005

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_reserved0_SHIFT  1

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT 2

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK      0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT     0

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_LOW_MASK    0x80000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_LOW_SHIFT   31
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_HIGH_MASK   0x40000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_HIGH_SHIFT  30
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_DIV2_MASK         0x20000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_DIV2_SHIFT        29
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_VCO_DIV2_DEFAULT      0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK      0x10000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT     28
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK      0x0e000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT     25
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_RESET_MASK       0x01000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_RESET_SHIFT      24
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_RESET_DEFAULT    0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_MODE_MASK        0x00c00000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT       22
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT     0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_REF_ALT_OFFS_MASK     0x00200000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_REF_ALT_OFFS_SHIFT    21
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_REF_ALT_OFFS_DEFAULT  0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_PWM_RATE_MASK         0x00180000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT        19
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT      0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_NDIV_RELOCK_MASK      0x00010000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_NDIV_RELOCK_SHIFT     16
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_NDIV_RELOCK_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK        0x00008000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT       15
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT     0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DITHER_DISABLE_MASK   0x00004000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DITHER_DISABLE_SHIFT  14
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK  0x00001ffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK         0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT        0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT      0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_PLLRESERVED0_MASK    0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_PLLRESERVED0_SHIFT   1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_DIG_INPUT_SEL_MASK   0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_DIG_INPUT_SEL_SHIFT  0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_reserved0_SHIFT      1

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_PWRON_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_RESET :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_reserved0_SHIFT      1

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_RESET :: RESETD [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_RESETD_MASK          0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_RESETD_SHIFT         0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_RESET_RESETD_DEFAULT       0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_reserved0_MASK      0xfffff000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_reserved0_SHIFT     12

/* CLKGEN :: DOCSIS_PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK    0x00000fff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT   0

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_reserved0_SHIFT   1

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_BG_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000009

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_reserved0_MASK         0xffffc000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_reserved0_SHIFT        14

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_PDIV_MASK              0x00003c00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_PDIV_SHIFT             10
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_PDIV_DEFAULT           0x00000003

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_NDIV_INT_MASK          0x000003ff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_NDIV_INT_SHIFT         0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_DIV_NDIV_INT_DEFAULT       0x0000007d

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_reserved0_MASK        0xfffffc00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_reserved0_SHIFT       10

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_reserved0_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_reserved0_MASK    0xffff0000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_reserved0_SHIFT   16

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_LDO_CTRL_MASK     0x0000ffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_LDO_CTRL_SHIFT    0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_CTRL_LDO_CTRL_DEFAULT  0x00000005

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_reserved0_SHIFT  1

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_reserved0_SHIFT 2

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000002
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_MASK      0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_LOCK_STATUS_LOCK_SHIFT     0

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_LOW_MASK    0x80000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_LOW_SHIFT   31
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_LOW_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_HIGH_MASK   0x40000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_HIGH_SHIFT  30
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_RANGE_HIGH_DEFAULT 0x00000001

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_DIV2_MASK         0x20000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_DIV2_SHIFT        29
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_VCO_DIV2_DEFAULT      0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_UPDATE_MASK      0x10000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_UPDATE_SHIFT     28
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_UPDATE_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_SELECT_MASK      0x0e000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_SELECT_SHIFT     25
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_SELECT_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_RESET_MASK       0x01000000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_RESET_SHIFT      24
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_RESET_DEFAULT    0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_MODE_MASK        0x00c00000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_MODE_SHIFT       22
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_STAT_MODE_DEFAULT     0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_REF_ALT_OFFS_MASK     0x00200000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_REF_ALT_OFFS_SHIFT    21
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_REF_ALT_OFFS_DEFAULT  0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_PWM_RATE_MASK         0x00180000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_PWM_RATE_SHIFT        19
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_PWM_RATE_DEFAULT      0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_POST_CTRL_RESETB_MASK 0x00060000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_POST_CTRL_RESETB_SHIFT 17
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_NDIV_RELOCK_MASK      0x00010000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_NDIV_RELOCK_SHIFT     16
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_NDIV_RELOCK_DEFAULT   0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_FAST_LOCK_MASK        0x00008000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_FAST_LOCK_SHIFT       15
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_FAST_LOCK_DEFAULT     0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DITHER_DISABLE_MASK   0x00004000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DITHER_DISABLE_SHIFT  14
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DITHER_DISABLE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_MASK  0x00001ffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_AUX_CTRL_MASK         0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_AUX_CTRL_SHIFT        0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC_AUX_CTRL_DEFAULT      0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_PLLRESERVED0_MASK    0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_PLLRESERVED0_SHIFT   1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_PLLRESERVED0_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_DIG_INPUT_SEL_MASK   0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_DIG_INPUT_SEL_SHIFT  0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_MISC2_DIG_INPUT_SEL_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_reserved0_SHIFT      1

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_PWRON_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_reserved0_SHIFT      2

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETD_MASK          0x00000002
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETD_SHIFT         1
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETD_DEFAULT       0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETA_MASK          0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETA_SHIFT         0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_RESETA_DEFAULT       0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_reserved0_MASK      0xfffff000
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_reserved0_SHIFT     12

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_TEST_STATUS_MASK    0x00000fff
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_STATUS_TEST_STATUS_SHIFT   0

/***************************************************************************
 *PLL_AUDIO0_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_reserved0_SHIFT        1

/* CLKGEN :: PLL_AUDIO0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_BG_PWRON_PLL_MASK      0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT     0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT   0x00000001

/***************************************************************************
 *PLL_AUDIO0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             4

/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [03:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x0000000f
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                0x00000000

/***************************************************************************
 *PLL_AUDIO0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xfffffc00
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            10

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000038
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    3
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000000

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004

/***************************************************************************
 *PLL_AUDIO0_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_reserved0_MASK         0xffff0000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_reserved0_SHIFT        16

/* CLKGEN :: PLL_AUDIO0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_LDO_CTRL_MASK          0x0000ffff
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_LDO_CTRL_SHIFT         0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT       0x00000005

/***************************************************************************
 *PLL_AUDIO0_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_reserved0_SHIFT       1

/* CLKGEN :: PLL_AUDIO0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK    0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT   0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_LOST_MASK      0x00000002
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT     1

/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0

/***************************************************************************
 *PLL_AUDIO0_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_reserved0_SHIFT           1

/* CLKGEN :: PLL_AUDIO0_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_PWRON_PLL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_PWRON_PLL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRON_PWRON_PLL_DEFAULT         0x00000001

/***************************************************************************
 *PLL_AUDIO0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2

/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0x00000000

/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0x00000000

/***************************************************************************
 *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AUDIO0_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12

/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0

/***************************************************************************
 *PLL_AUDIO1_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_reserved0_SHIFT        1

/* CLKGEN :: PLL_AUDIO1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_BG_PWRON_PLL_MASK      0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT     0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT   0x00000001

/***************************************************************************
 *PLL_AUDIO1_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             4

/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [03:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x0000000f
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                0x00000000

/***************************************************************************
 *PLL_AUDIO1_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xfffffc00
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            10

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000038
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    3
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000000

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004

/***************************************************************************
 *PLL_AUDIO1_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_reserved0_MASK         0xffff0000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_reserved0_SHIFT        16

/* CLKGEN :: PLL_AUDIO1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_LDO_CTRL_MASK          0x0000ffff
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_LDO_CTRL_SHIFT         0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT       0x00000005

/***************************************************************************
 *PLL_AUDIO1_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_reserved0_SHIFT       1

/* CLKGEN :: PLL_AUDIO1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK    0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT   0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_LOST_MASK      0x00000002
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT     1

/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0

/***************************************************************************
 *PLL_AUDIO1_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_reserved0_SHIFT           1

/* CLKGEN :: PLL_AUDIO1_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_PWRON_PLL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_PWRON_PLL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRON_PWRON_PLL_DEFAULT         0x00000001

/***************************************************************************
 *PLL_AUDIO1_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2

/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0x00000000

/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0x00000000

/***************************************************************************
 *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AUDIO1_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12

/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0

/***************************************************************************
 *PLL_AUDIO2_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_reserved0_SHIFT        1

/* CLKGEN :: PLL_AUDIO2_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_BG_PWRON_PLL_MASK      0x00000001
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT     0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT   0x00000001

/***************************************************************************
 *PLL_AUDIO2_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_DIV :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_MASK              0xfffffff0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_SHIFT             4

/* CLKGEN :: PLL_AUDIO2_PLL_DIV :: PDIV [03:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_MASK                   0x0000000f
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_SHIFT                  0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_DEFAULT                0x00000000

/***************************************************************************
 *PLL_AUDIO2_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_MASK             0xfffffc00
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_SHIFT            10

/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008

/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000038
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    3
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000000

/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004

/***************************************************************************
 *PLL_AUDIO2_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_reserved0_MASK         0xffff0000
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_reserved0_SHIFT        16

/* CLKGEN :: PLL_AUDIO2_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_LDO_CTRL_MASK          0x0000ffff
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_LDO_CTRL_SHIFT         0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_CTRL_LDO_CTRL_DEFAULT       0x00000005

/***************************************************************************
 *PLL_AUDIO2_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_reserved0_SHIFT       1

/* CLKGEN :: PLL_AUDIO2_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK    0x00000001
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT   0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *PLL_AUDIO2_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_LOST_MASK      0x00000002
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_LOST_SHIFT     1

/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_SHIFT          0

/***************************************************************************
 *PLL_AUDIO2_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_reserved0_SHIFT           1

/* CLKGEN :: PLL_AUDIO2_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_PWRON_PLL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_PWRON_PLL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRON_PWRON_PLL_DEFAULT         0x00000001

/***************************************************************************
 *PLL_AUDIO2_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_SHIFT           2

/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_MASK               0x00000002
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_SHIFT              1
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_DEFAULT            0x00000000

/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_SHIFT              0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_DEFAULT            0x00000000

/***************************************************************************
 *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AUDIO2_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_MASK           0xfffff000
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_SHIFT          12

/* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_SHIFT        0

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  11

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000007

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  11

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT  11

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000007

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT  11

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK                 0xffffc000
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT                14

/* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK                      0x00003c00
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT                     10
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT                   0x00000003

/* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK                  0x000003ff
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT                 0
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT               0x000000c8

/***************************************************************************
 *PLL_AVD_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK                0xfffffc00
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT               10

/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000

/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_AVD_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_reserved0_SHIFT          1

/* CLKGEN :: PLL_AVD_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_AVD_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_AVD_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1

/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT             0

/***************************************************************************
 *PLL_AVD_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_RANGE_MASK                0xc0000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_RANGE_SHIFT               30
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_RANGE_DEFAULT             0x00000002

/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_FB_DIV2_SHIFT             29
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000001

/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK              0x10000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT             28
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK              0x0e000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT             25
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET_MASK               0x01000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET_SHIFT              24
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET_DEFAULT            0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK                0x00c00000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT               22
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT             0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK                 0x00300000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT                20
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT              0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED2_MASK             0x00030000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED2_SHIFT            16
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED1_MASK             0x00008000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED1_SHIFT            15
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT             14
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK                0x00002000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT               13
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000

/***************************************************************************
 *PLL_AVD_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_PLLRESERVED0_SHIFT           2
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000

/* CLKGEN :: PLL_AVD_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_LDO_MASK                     0x00000003
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_LDO_SHIFT                    0
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_LDO_DEFAULT                  0x00000001

/***************************************************************************
 *PLL_AVD_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_reserved0_SHIFT              1

/* CLKGEN :: PLL_AVD_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_PWRON_PLL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_PWRON_PLL_SHIFT              0
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001

/***************************************************************************
 *PLL_AVD_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT              2

/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK                  0x00000002
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT                 1
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT               0x00000000

/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT                 0
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT               0x00000000

/***************************************************************************
 *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK              0xfffff000
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT             12

/* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT           0

/***************************************************************************
 *PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000002

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000064

/* CLKGEN :: PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000001

/***************************************************************************
 *PLL_CPU_CORE_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_reserved0_MASK            0xffffc000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_reserved0_SHIFT           14

/* CLKGEN :: PLL_CPU_CORE_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_PDIV_MASK                 0x00003c00
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_PDIV_SHIFT                10
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_PDIV_DEFAULT              0x00000003

/* CLKGEN :: PLL_CPU_CORE_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_NDIV_INT_MASK             0x000003ff
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_NDIV_INT_SHIFT            0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_DIV_NDIV_INT_DEFAULT          0x000000a7

/***************************************************************************
 *PLL_CPU_CORE_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_reserved0_MASK           0xfff00000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_reserved0_SHIFT          20

/* CLKGEN :: PLL_CPU_CORE_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_FRAC_CONTROL_MASK        0x000fffff
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_FRAC_CONTROL_SHIFT       0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_FRAC_FRAC_CONTROL_DEFAULT     0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_reserved0_MASK           0xfffffc00
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_reserved0_SHIFT          10

/* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK   0x00000038
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT  3
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_CPU_CORE_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_reserved0_SHIFT     1

/* CLKGEN :: PLL_CPU_CORE_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK  0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *PLL_CPU_CORE_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_reserved0_SHIFT   2

/* CLKGEN :: PLL_CPU_CORE_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_LOST_MASK    0x00000002
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_LOST_SHIFT   1

/* CLKGEN :: PLL_CPU_CORE_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_MASK         0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_LOCK_STATUS_LOCK_SHIFT        0

/***************************************************************************
 *PLL_CPU_CORE_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_RANGE_MASK           0xc0000000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_RANGE_SHIFT          30
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_RANGE_DEFAULT        0x00000002

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_FB_DIV2_MASK         0x20000000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_FB_DIV2_SHIFT        29
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_VCO_FB_DIV2_DEFAULT      0x00000001

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_UPDATE_MASK         0x10000000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_UPDATE_SHIFT        28
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_UPDATE_DEFAULT      0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_SELECT_MASK         0x0e000000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_SELECT_SHIFT        25
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_SELECT_DEFAULT      0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_RESET_MASK          0x01000000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_RESET_SHIFT         24
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_RESET_DEFAULT       0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_MODE_MASK           0x00c00000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_MODE_SHIFT          22
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_STAT_MODE_DEFAULT        0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PWM_RATE_MASK            0x00300000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PWM_RATE_SHIFT           20
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PWM_RATE_DEFAULT         0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_POST_CTRL_RESETB_MASK    0x000c0000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_POST_CTRL_RESETB_SHIFT   18
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000003

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED2_MASK        0x00030000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED2_SHIFT       16
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED2_DEFAULT     0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED1_MASK        0x00008000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED1_SHIFT       15
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_PLLRESERVED1_DEFAULT     0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_NDIV_RELOCK_MASK         0x00004000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_NDIV_RELOCK_SHIFT        14
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_NDIV_RELOCK_DEFAULT      0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_FAST_LOCK_MASK           0x00002000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_FAST_LOCK_SHIFT          13
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_FAST_LOCK_DEFAULT        0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_MASK     0x00000fff
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_SHIFT    0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT  0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_PLLRESERVED0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_PLLRESERVED0_SHIFT      2
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_PLLRESERVED0_DEFAULT    0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_LDO_MASK                0x00000003
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_LDO_SHIFT               0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_MISC2_LDO_DEFAULT             0x00000001

/***************************************************************************
 *PLL_CPU_CORE_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_reserved0_SHIFT         1

/* CLKGEN :: PLL_CPU_CORE_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_PWRON_PLL_MASK          0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_PWRON_PLL_SHIFT         0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_PWRON_PWRON_PLL_DEFAULT       0x00000001

/***************************************************************************
 *PLL_CPU_CORE_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_reserved0_MASK          0xfffffffc
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_reserved0_SHIFT         2

/* CLKGEN :: PLL_CPU_CORE_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETD_MASK             0x00000002
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETD_SHIFT            1
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETD_DEFAULT          0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETA_MASK             0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETA_SHIFT            0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_RESETA_DEFAULT          0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_CORE_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_reserved0_MASK         0xfffff000
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_reserved0_SHIFT        12

/* CLKGEN :: PLL_CPU_CORE_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_TEST_STATUS_MASK       0x00000fff
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_STATUS_TEST_STATUS_SHIFT      0

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000002

/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000064

/* CLKGEN :: PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000001

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_reserved0_MASK          0xffffc000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_reserved0_SHIFT         14

/* CLKGEN :: PLL_CPU_ROUTER_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_PDIV_MASK               0x00003c00
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_PDIV_SHIFT              10
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_PDIV_DEFAULT            0x00000003

/* CLKGEN :: PLL_CPU_ROUTER_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_NDIV_INT_MASK           0x000003ff
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_NDIV_INT_SHIFT          0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_DIV_NDIV_INT_DEFAULT        0x000000a7

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_FRAC_reserved0_MASK         0xfff00000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_FRAC_reserved0_SHIFT        20

/* CLKGEN :: PLL_CPU_ROUTER_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_FRAC_FRAC_CONTROL_MASK      0x000fffff
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_FRAC_FRAC_CONTROL_SHIFT     0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_FRAC_FRAC_CONTROL_DEFAULT   0x00000000

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_reserved0_MASK         0xfffffc00
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_reserved0_SHIFT        10

/* CLKGEN :: PLL_CPU_ROUTER_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: PLL_CPU_ROUTER_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000038
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 3
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LDO_PWRON_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LDO_PWRON_reserved0_SHIFT   1

/* CLKGEN :: PLL_CPU_ROUTER_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS_reserved0_MASK  0xfffffffc
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS_reserved0_SHIFT 2

/* CLKGEN :: PLL_CPU_ROUTER_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS_LOCK_LOST_MASK  0x00000002
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 1

/* CLKGEN :: PLL_CPU_ROUTER_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS_LOCK_MASK       0x00000001
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_LOCK_STATUS_LOCK_SHIFT      0

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_VCO_RANGE_MASK         0xc0000000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_VCO_RANGE_SHIFT        30
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_VCO_RANGE_DEFAULT      0x00000002

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_VCO_FB_DIV2_MASK       0x20000000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_VCO_FB_DIV2_SHIFT      29
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_VCO_FB_DIV2_DEFAULT    0x00000001

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_UPDATE_MASK       0x10000000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_UPDATE_SHIFT      28
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_UPDATE_DEFAULT    0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_SELECT_MASK       0x0e000000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_SELECT_SHIFT      25
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_SELECT_DEFAULT    0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_RESET_MASK        0x01000000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_RESET_SHIFT       24
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_RESET_DEFAULT     0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_MODE_MASK         0x00c00000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_MODE_SHIFT        22
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_STAT_MODE_DEFAULT      0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PWM_RATE_MASK          0x00300000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PWM_RATE_SHIFT         20
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PWM_RATE_DEFAULT       0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_POST_CTRL_RESETB_MASK  0x000c0000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_POST_CTRL_RESETB_SHIFT 18
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_POST_CTRL_RESETB_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PLLRESERVED2_MASK      0x00030000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PLLRESERVED2_SHIFT     16
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PLLRESERVED2_DEFAULT   0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PLLRESERVED1_MASK      0x00008000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PLLRESERVED1_SHIFT     15
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_PLLRESERVED1_DEFAULT   0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_NDIV_RELOCK_MASK       0x00004000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_NDIV_RELOCK_SHIFT      14
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_NDIV_RELOCK_DEFAULT    0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_FAST_LOCK_MASK         0x00002000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_FAST_LOCK_SHIFT        13
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_FAST_LOCK_DEFAULT      0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_DCO_CTRL_BYPASS_MASK   0x00000fff
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_DCO_CTRL_BYPASS_SHIFT  0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2_PLLRESERVED0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2_PLLRESERVED0_SHIFT    2
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2_PLLRESERVED0_DEFAULT  0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2_LDO_MASK              0x00000003
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2_LDO_SHIFT             0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_MISC2_LDO_DEFAULT           0x00000001

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_PWRON_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_PWRON_reserved0_SHIFT       1

/* CLKGEN :: PLL_CPU_ROUTER_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_PWRON_PWRON_PLL_MASK        0x00000001
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_PWRON_PWRON_PLL_SHIFT       0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_PWRON_PWRON_PLL_DEFAULT     0x00000001

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_reserved0_SHIFT       2

/* CLKGEN :: PLL_CPU_ROUTER_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_RESETD_MASK           0x00000002
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_RESETD_SHIFT          1
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_RESETD_DEFAULT        0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_RESETA_MASK           0x00000001
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_RESETA_SHIFT          0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_RESETA_DEFAULT        0x00000000

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_STATUS_reserved0_MASK       0xfffff000
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_STATUS_reserved0_SHIFT      12

/* CLKGEN :: PLL_CPU_ROUTER_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_STATUS_TEST_STATUS_MASK     0x00000fff
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_STATUS_TEST_STATUS_SHIFT    0

/***************************************************************************
 *PLL_LC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xfffff800
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   11

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  0x0000006c

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_LC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xfffff800
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   11

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  0x0000002d

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_LC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK    0xfffff800
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT   11

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK     0x000001fe
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT    1
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT  0x00000036

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_LC_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK    0xfffff800
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT   11

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK     0x000001fe
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT    1
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT  0x00000036

/* CLKGEN :: PLL_LC_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_LC_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000001

/***************************************************************************
 *PLL_LC_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_reserved0_SHIFT             1

/* CLKGEN :: PLL_LC_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_SHIFT               0
#define BCHP_CLKGEN_PLL_LC_PLL_CONTROL_REF_SEL_DEFAULT             0x00000000

/***************************************************************************
 *PLL_LC_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_MASK                  0xffffc000
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_reserved0_SHIFT                 14

/* CLKGEN :: PLL_LC_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_MASK                       0x00003c00
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_SHIFT                      10
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_PDIV_DEFAULT                    0x00000002

/* CLKGEN :: PLL_LC_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_SHIFT                  0
#define BCHP_CLKGEN_PLL_LC_PLL_DIV_NDIV_INT_DEFAULT                0x00000064

/***************************************************************************
 *PLL_LC_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_GAIN :: reserved0 [31:07] */
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_MASK                 0xffffff80
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_reserved0_SHIFT                7

/* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [06:03] */
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000078
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006

/* CLKGEN :: PLL_LC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_LC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_LC_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_reserved0_SHIFT         1

/* CLKGEN :: PLL_LC_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK        0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT       0
#define BCHP_CLKGEN_PLL_LC_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT     0x00000000

/***************************************************************************
 *PLL_LC_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: reserved0 [31:06] */
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_MASK             0xffffffc0
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_reserved0_SHIFT            6

/* CLKGEN :: PLL_LC_PLL_LDO_CTRL :: LDO_CTRL [05:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_MASK              0x0000003f
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_SHIFT             0
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_CTRL_LDO_CTRL_DEFAULT           0x00000004

/***************************************************************************
 *PLL_LC_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_reserved0_SHIFT           1

/* CLKGEN :: PLL_LC_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK        0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT       0
#define BCHP_CLKGEN_PLL_LC_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT     0x00000001

/***************************************************************************
 *PLL_LC_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_reserved0_SHIFT         1

/* CLKGEN :: PLL_LC_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_LOCK_STATUS_LOCK_SHIFT              0

/***************************************************************************
 *PLL_LC_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_MISC :: VCO_PREDIV_RATIO [31:31] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_MASK          0x80000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_SHIFT         31
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_VCO_PREDIV_RATIO_DEFAULT       0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: T2D_DELAY_SEL_LOW [30:28] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_MASK         0x70000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_SHIFT        28
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_T2D_DELAY_SEL_LOW_DEFAULT      0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: SEL_MEASURE_UNIT [27:25] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_MASK          0x0e000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_SHIFT         25
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_SEL_MEASURE_UNIT_DEFAULT       0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: RESET_MEASURE_MODE [24:24] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_MASK        0x01000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_SHIFT       24
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_RESET_MEASURE_MODE_DEFAULT     0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: LOAD_DCO_BYP_WORD [23:23] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_MASK         0x00800000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_SHIFT        23
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_LOAD_DCO_BYP_WORD_DEFAULT      0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: FREQ_BYP_WORD [22:07] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_MASK             0x007fff80
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_SHIFT            7
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_FREQ_BYP_WORD_DEFAULT          0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: EN_VCO_OUTPUT [06:06] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_MASK             0x00000040
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_SHIFT            6
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_VCO_OUTPUT_DEFAULT          0x00000001

/* CLKGEN :: PLL_LC_PLL_MISC :: EN_DCO_BYP_WORD [05:05] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_MASK           0x00000020
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_SHIFT          5
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_DCO_BYP_WORD_DEFAULT        0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: EN_BANGBANG_MODE [04:04] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_MASK          0x00000010
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_SHIFT         4
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_EN_BANGBANG_MODE_DEFAULT       0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: CTRL_MEASURE_MODE [03:02] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_MASK         0x0000000c
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_SHIFT        2
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CTRL_MEASURE_MODE_DEFAULT      0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: CHANGE_MEASURE_UNIT [01:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_MASK       0x00000002
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_SHIFT      1
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_CHANGE_MEASURE_UNIT_DEFAULT    0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC :: BOOST_BIAS_CIRCUIT [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_MASK        0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_SHIFT       0
#define BCHP_CLKGEN_PLL_LC_PLL_MISC_BOOST_BIAS_CIRCUIT_DEFAULT     0x00000000

/***************************************************************************
 *PLL_LC_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_MISC2 :: T2D_DELAY_SEL_HIGH [31:31] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_MASK       0x80000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_SHIFT      31
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_T2D_DELAY_SEL_HIGH_DEFAULT    0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_TEST_CLK [30:30] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_MASK             0x40000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_SHIFT            30
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_TEST_CLK_DEFAULT          0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: SEL_DIFF_REFCLK_SRC [29:29] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_MASK      0x20000000
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_SHIFT     29
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_SEL_DIFF_REFCLK_SRC_DEFAULT   0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: PLLRESERVED0 [28:11] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_MASK             0x1ffff800
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_SHIFT            11
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_PLLRESERVED0_DEFAULT          0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: INTERNAL_RESET_MODE [10:09] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_MASK      0x00000600
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_SHIFT     9
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_INTERNAL_RESET_MODE_DEFAULT   0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_TEST_CLK [08:08] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_MASK              0x00000100
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_SHIFT             8
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_TEST_CLK_DEFAULT           0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_1 [07:07] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_MASK              0x00000080
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_SHIFT             7
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_1_DEFAULT           0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: EN_BYPCLK_0 [06:06] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_MASK              0x00000040
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_SHIFT             6
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_EN_BYPCLK_0_DEFAULT           0x00000000

/* CLKGEN :: PLL_LC_PLL_MISC2 :: DCO_PWM_RATE_CTRL [05:04] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_MASK        0x00000030
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_SHIFT       4
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_DCO_PWM_RATE_CTRL_DEFAULT     0x00000002

/* CLKGEN :: PLL_LC_PLL_MISC2 :: CTRL_2ND_POLE [03:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_MASK            0x0000000f
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_SHIFT           0
#define BCHP_CLKGEN_PLL_LC_PLL_MISC2_CTRL_2ND_POLE_DEFAULT         0x00000000

/***************************************************************************
 *PLL_LC_PLL_OUTSEL_SEL - selection of the output clock from the PLL core
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_MASK           0xfffffff8
#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_reserved0_SHIFT          3

/* CLKGEN :: PLL_LC_PLL_OUTSEL_SEL :: OUTPUT_SEL [02:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_MASK          0x00000007
#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_SHIFT         0
#define BCHP_CLKGEN_PLL_LC_PLL_OUTSEL_SEL_OUTPUT_SEL_DEFAULT       0x00000000

/***************************************************************************
 *PLL_LC_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_MASK                0xfffffffe
#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_reserved0_SHIFT               1

/* CLKGEN :: PLL_LC_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_SHIFT               0
#define BCHP_CLKGEN_PLL_LC_PLL_PWRON_PWRON_PLL_DEFAULT             0x00000001

/***************************************************************************
 *PLL_LC_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_MASK                0xfffffffc
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_reserved0_SHIFT               2

/* CLKGEN :: PLL_LC_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_MASK                   0x00000002
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_SHIFT                  1
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETD_DEFAULT                0x00000000

/* CLKGEN :: PLL_LC_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_MASK                   0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_SHIFT                  0
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_RESETA_DEFAULT                0x00000000

/***************************************************************************
 *PLL_LC_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_STATUS :: TEST_STATUS [31:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_MASK             0xffffffff
#define BCHP_CLKGEN_PLL_LC_PLL_STATUS_TEST_STATUS_SHIFT            0

/***************************************************************************
 *PLL_LC_PLL_TEST - enable and selection pf PLL test
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_TEST :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_MASK                 0xfffffff0
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_reserved0_SHIFT                4

/* CLKGEN :: PLL_LC_PLL_TEST :: TEST_SEL [03:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_MASK                  0x0000000e
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_SHIFT                 1
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_SEL_DEFAULT               0x00000000

/* CLKGEN :: PLL_LC_PLL_TEST :: TEST_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_MASK               0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_SHIFT              0
#define BCHP_CLKGEN_PLL_LC_PLL_TEST_TEST_ENABLE_DEFAULT            0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000009

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000009

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000024

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000012

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK                0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT               14

/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK                     0x00003c00
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT                    10
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT                  0x00000003

/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK                 0x000003ff
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT                0
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT              0x000000c8

/***************************************************************************
 *PLL_MOCA_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK               0xfffffc00
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT              10

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000038
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      3
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000000

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_MOCA_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_reserved0_SHIFT         1

/* CLKGEN :: PLL_MOCA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK      0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT     0
#define BCHP_CLKGEN_PLL_MOCA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT   0x00000001

/***************************************************************************
 *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1

/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT            0

/***************************************************************************
 *PLL_MOCA_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_MASK               0xc0000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_SHIFT              30
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_RANGE_DEFAULT            0x00000002

/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_MASK             0x20000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_SHIFT            29
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_FB_DIV2_DEFAULT          0x00000001

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK             0x10000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT            28
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK             0x0e000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT            25
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_MASK              0x01000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_SHIFT             24
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET_DEFAULT           0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK               0x00c00000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT              22
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT            0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK                0x00300000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT               20
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT             0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_MASK        0x000c0000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_SHIFT       18
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POST_CTRL_RESETB_DEFAULT     0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_MASK            0x00030000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_SHIFT           16
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED2_DEFAULT         0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_MASK            0x00008000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_SHIFT           15
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PLLRESERVED1_DEFAULT         0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK             0x00004000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT            14
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK               0x00002000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT              13
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_MASK           0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_SHIFT          2
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_PLLRESERVED0_DEFAULT        0x00000000

/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_MASK                    0x00000003
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_SHIFT                   0
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_LDO_DEFAULT                 0x00000001

/***************************************************************************
 *PLL_MOCA_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_reserved0_SHIFT             1

/* CLKGEN :: PLL_MOCA_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRON_PWRON_PLL_DEFAULT           0x00000001

/***************************************************************************
 *PLL_MOCA_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT             2

/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK                 0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT                1
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT              0x00000000

/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT                0
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT              0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000007

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000007

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000b

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000b

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000064

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000001

/***************************************************************************
 *PLL_RAAGA_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK               0xffffc000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT              14

/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK                    0x00003c00
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT                   10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT                 0x00000002

/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK                0x000003ff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT               0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT             0x0000008f

/***************************************************************************
 *PLL_RAAGA_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK              0xfffffc00
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT             10

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000038
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     3
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_RAAGA_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_reserved0_SHIFT        1

/* CLKGEN :: PLL_RAAGA_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT    0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT  0x00000001

/***************************************************************************
 *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1

/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT           0

/***************************************************************************
 *PLL_RAAGA_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_MASK              0xc0000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_SHIFT             30
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_RANGE_DEFAULT           0x00000002

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_MASK            0x20000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_SHIFT           29
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_FB_DIV2_DEFAULT         0x00000001

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK            0x10000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT           28
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK            0x0e000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT           25
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_MASK             0x01000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_SHIFT            24
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET_DEFAULT          0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK              0x00c00000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT             22
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT           0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK               0x00300000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT              20
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT            0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_MASK       0x000c0000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_SHIFT      18
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POST_CTRL_RESETB_DEFAULT    0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_MASK           0x00030000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_SHIFT          16
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED2_DEFAULT        0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_MASK           0x00008000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_SHIFT          15
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PLLRESERVED1_DEFAULT        0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK            0x00004000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT           14
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK              0x00002000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT             13
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_MASK          0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_SHIFT         2
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_PLLRESERVED0_DEFAULT       0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_MASK                   0x00000003
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_SHIFT                  0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_LDO_DEFAULT                0x00000001

/***************************************************************************
 *PLL_RAAGA_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_reserved0_SHIFT            1

/* CLKGEN :: PLL_RAAGA_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRON_PWRON_PLL_DEFAULT          0x00000001

/***************************************************************************
 *PLL_RAAGA_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT             0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT             0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_SC0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11

/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030

/* CLKGEN :: PLL_SC0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SC0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_MASK                 0xffffc000
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_reserved0_SHIFT                14

/* CLKGEN :: PLL_SC0_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_MASK                      0x00003c00
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_SHIFT                     10
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_PDIV_DEFAULT                   0x00000002

/* CLKGEN :: PLL_SC0_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_MASK                  0x000003ff
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_SHIFT                 0
#define BCHP_CLKGEN_PLL_SC0_PLL_DIV_NDIV_INT_DEFAULT               0x00000030

/***************************************************************************
 *PLL_SC0_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_MASK                0xfff00000
#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_reserved0_SHIFT               20

/* CLKGEN :: PLL_SC0_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_SHIFT            0
#define BCHP_CLKGEN_PLL_SC0_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000

/***************************************************************************
 *PLL_SC0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_MASK                0xfffffc00
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_reserved0_SHIFT               10

/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000

/* CLKGEN :: PLL_SC0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_SC0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_SC0_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_reserved0_SHIFT          1

/* CLKGEN :: PLL_SC0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_SC0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_SC0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1

/* CLKGEN :: PLL_SC0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SC0_PLL_LOCK_STATUS_LOCK_SHIFT             0

/***************************************************************************
 *PLL_SC0_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_MASK                0xc0000000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_SHIFT               30
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_RANGE_DEFAULT             0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_SHIFT             29
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_MASK              0x10000000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_SHIFT             28
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_MASK              0x0e000000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_SHIFT             25
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_MASK               0x01000000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_SHIFT              24
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_RESET_DEFAULT            0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_MASK                0x00c00000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_SHIFT               22
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_STAT_MODE_DEFAULT             0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_MASK                 0x00300000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_SHIFT                20
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PWM_RATE_DEFAULT              0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_MASK             0x00030000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_SHIFT            16
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_MASK             0x00008000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_SHIFT            15
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_SHIFT             14
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_MASK                0x00002000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_SHIFT               13
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000

/***************************************************************************
 *PLL_SC0_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_SHIFT           2
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000

/* CLKGEN :: PLL_SC0_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_MASK                     0x00000003
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_SHIFT                    0
#define BCHP_CLKGEN_PLL_SC0_PLL_MISC2_LDO_DEFAULT                  0x00000001

/***************************************************************************
 *PLL_SC0_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_reserved0_SHIFT              1

/* CLKGEN :: PLL_SC0_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_SHIFT              0
#define BCHP_CLKGEN_PLL_SC0_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001

/***************************************************************************
 *PLL_SC0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_reserved0_SHIFT              2

/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_MASK                  0x00000002
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_SHIFT                 1
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETD_DEFAULT               0x00000000

/* CLKGEN :: PLL_SC0_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_SHIFT                 0
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_RESETA_DEFAULT               0x00000000

/***************************************************************************
 *PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_SC0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC0_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_MASK              0xfffff000
#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_reserved0_SHIFT             12

/* CLKGEN :: PLL_SC0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
#define BCHP_CLKGEN_PLL_SC0_PLL_STATUS_TEST_STATUS_SHIFT           0

/***************************************************************************
 *PLL_SC1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11

/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000030

/* CLKGEN :: PLL_SC1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SC1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC1_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_MASK                 0xffffc000
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_reserved0_SHIFT                14

/* CLKGEN :: PLL_SC1_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_MASK                      0x00003c00
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_SHIFT                     10
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_PDIV_DEFAULT                   0x00000002

/* CLKGEN :: PLL_SC1_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_MASK                  0x000003ff
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_SHIFT                 0
#define BCHP_CLKGEN_PLL_SC1_PLL_DIV_NDIV_INT_DEFAULT               0x00000030

/***************************************************************************
 *PLL_SC1_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_MASK                0xfff00000
#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_reserved0_SHIFT               20

/* CLKGEN :: PLL_SC1_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_MASK             0x000fffff
#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_SHIFT            0
#define BCHP_CLKGEN_PLL_SC1_PLL_FRAC_FRAC_CONTROL_DEFAULT          0x00000000

/***************************************************************************
 *PLL_SC1_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_MASK                0xfffffc00
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_reserved0_SHIFT               10

/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000

/* CLKGEN :: PLL_SC1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_SC1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_SC1_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_reserved0_SHIFT          1

/* CLKGEN :: PLL_SC1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_SC1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_SC1_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1

/* CLKGEN :: PLL_SC1_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SC1_PLL_LOCK_STATUS_LOCK_SHIFT             0

/***************************************************************************
 *PLL_SC1_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_MASK                0xc0000000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_SHIFT               30
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_RANGE_DEFAULT             0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_SHIFT             29
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_MASK              0x10000000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_SHIFT             28
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_MASK              0x0e000000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_SHIFT             25
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_MASK               0x01000000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_SHIFT              24
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_RESET_DEFAULT            0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_MASK                0x00c00000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_SHIFT               22
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_STAT_MODE_DEFAULT             0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_MASK                 0x00300000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_SHIFT                20
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PWM_RATE_DEFAULT              0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_MASK             0x00030000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_SHIFT            16
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_MASK             0x00008000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_SHIFT            15
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_SHIFT             14
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_MASK                0x00002000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_SHIFT               13
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000

/***************************************************************************
 *PLL_SC1_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_SHIFT           2
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000

/* CLKGEN :: PLL_SC1_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_MASK                     0x00000003
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_SHIFT                    0
#define BCHP_CLKGEN_PLL_SC1_PLL_MISC2_LDO_DEFAULT                  0x00000001

/***************************************************************************
 *PLL_SC1_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_reserved0_SHIFT              1

/* CLKGEN :: PLL_SC1_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_SHIFT              0
#define BCHP_CLKGEN_PLL_SC1_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001

/***************************************************************************
 *PLL_SC1_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_reserved0_SHIFT              2

/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_MASK                  0x00000002
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_SHIFT                 1
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETD_DEFAULT               0x00000000

/* CLKGEN :: PLL_SC1_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_SHIFT                 0
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_RESETA_DEFAULT               0x00000000

/***************************************************************************
 *PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_SC1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SC1_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_MASK              0xfffff000
#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_reserved0_SHIFT             12

/* CLKGEN :: PLL_SC1_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
#define BCHP_CLKGEN_PLL_SC1_PLL_STATUS_TEST_STATUS_SHIFT           0

/***************************************************************************
 *PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000005a

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000009

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000005

/* CLKGEN :: PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_reserved0_MASK              0xffffc000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_reserved0_SHIFT             14

/* CLKGEN :: PLL_SWITCH_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_PDIV_MASK                   0x00003c00
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_PDIV_SHIFT                  10
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_PDIV_DEFAULT                0x00000003

/* CLKGEN :: PLL_SWITCH_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_NDIV_INT_MASK               0x000003ff
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_NDIV_INT_SHIFT              0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_DIV_NDIV_INT_DEFAULT            0x0000007d

/***************************************************************************
 *PLL_SWITCH_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_reserved0_MASK             0xfffffc00
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_reserved0_SHIFT            10

/* CLKGEN :: PLL_SWITCH_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: PLL_SWITCH_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000038
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    3
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_SWITCH_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_reserved0_SHIFT       1

/* CLKGEN :: PLL_SWITCH_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK    0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT   0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT 0x00000001

/***************************************************************************
 *PLL_SWITCH_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_SWITCH_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_LOCK_LOST_MASK      0x00000002
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_LOCK_LOST_SHIFT     1

/* CLKGEN :: PLL_SWITCH_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_LOCK_STATUS_LOCK_SHIFT          0

/***************************************************************************
 *PLL_SWITCH_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_RANGE_MASK             0xc0000000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_RANGE_SHIFT            30
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_RANGE_DEFAULT          0x00000002

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_FB_DIV2_MASK           0x20000000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_FB_DIV2_SHIFT          29
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_VCO_FB_DIV2_DEFAULT        0x00000001

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_UPDATE_MASK           0x10000000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_UPDATE_SHIFT          28
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_UPDATE_DEFAULT        0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_SELECT_MASK           0x0e000000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_SELECT_SHIFT          25
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_SELECT_DEFAULT        0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_RESET_MASK            0x01000000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_RESET_SHIFT           24
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_RESET_DEFAULT         0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_MODE_MASK             0x00c00000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_MODE_SHIFT            22
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_STAT_MODE_DEFAULT          0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PWM_RATE_MASK              0x00300000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PWM_RATE_SHIFT             20
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PWM_RATE_DEFAULT           0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_POST_CTRL_RESETB_MASK      0x000c0000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_POST_CTRL_RESETB_SHIFT     18
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_POST_CTRL_RESETB_DEFAULT   0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED2_MASK          0x00030000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED2_SHIFT         16
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED2_DEFAULT       0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED1_MASK          0x00008000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED1_SHIFT         15
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_PLLRESERVED1_DEFAULT       0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_NDIV_RELOCK_MASK           0x00004000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_NDIV_RELOCK_SHIFT          14
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_NDIV_RELOCK_DEFAULT        0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_FAST_LOCK_MASK             0x00002000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_FAST_LOCK_SHIFT            13
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_FAST_LOCK_DEFAULT          0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_MASK       0x00000fff
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_SHIFT      0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT    0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_PLLRESERVED0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_PLLRESERVED0_SHIFT        2
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_PLLRESERVED0_DEFAULT      0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_LDO_MASK                  0x00000003
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_LDO_SHIFT                 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_MISC2_LDO_DEFAULT               0x00000001

/***************************************************************************
 *PLL_SWITCH_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_reserved0_SHIFT           1

/* CLKGEN :: PLL_SWITCH_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_PWRON_PLL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_PWRON_PLL_SHIFT           0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_PWRON_PWRON_PLL_DEFAULT         0x00000001

/***************************************************************************
 *PLL_SWITCH_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_reserved0_SHIFT           2

/* CLKGEN :: PLL_SWITCH_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETD_MASK               0x00000002
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETD_SHIFT              1
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETD_DEFAULT            0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETA_MASK               0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETA_SHIFT              0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_RESETA_DEFAULT            0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_SWITCH_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS_reserved0_MASK           0xfffff000
#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS_reserved0_SHIFT          12

/* CLKGEN :: PLL_SWITCH_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_SWITCH_PLL_STATUS_TEST_STATUS_SHIFT        0

/***************************************************************************
 *PLL_SYS0_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_reserved0_SHIFT          1

/* CLKGEN :: PLL_SYS0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_MASK        0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT       0
#define BCHP_CLKGEN_PLL_SYS0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT     0x00000001

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000012

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000c

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 11

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x00000012

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 11

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000024

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xfffff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 11

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000012

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               14

/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00003c00
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  0x00000001

/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              0x00000048

/***************************************************************************
 *PLL_SYS0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xfffffc00
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              10

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000038
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      3
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000000

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004

/***************************************************************************
 *PLL_SYS0_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_reserved0_SHIFT       1

/* CLKGEN :: PLL_SYS0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK      0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT     0
#define BCHP_CLKGEN_PLL_SYS0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT   0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_reserved0_MASK           0xffff0000
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_reserved0_SHIFT          16

/* CLKGEN :: PLL_SYS0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_MASK            0x0000ffff
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_SHIFT           0
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT         0x00000005

/***************************************************************************
 *PLL_SYS0_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_reserved0_SHIFT         1

/* CLKGEN :: PLL_SYS0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK      0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT     0
#define BCHP_CLKGEN_PLL_SYS0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT   0x00000001

/***************************************************************************
 *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1

/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0

/***************************************************************************
 *PLL_SYS0_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_MASK           0x80000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_SHIFT          31
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_LOW_DEFAULT        0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_MASK          0x40000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_SHIFT         30
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT       0x00000001

/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_MASK                0x20000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_SHIFT               29
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DIV2_DEFAULT             0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x10000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            28
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x0e000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            25
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_MASK              0x01000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_SHIFT             24
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET_DEFAULT           0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00c00000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              22
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_MASK            0x00200000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_SHIFT           21
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REF_ALT_OFFS_DEFAULT         0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x00180000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               19
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_MASK        0x00060000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_SHIFT       17
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POST_CTRL_RESETB_DEFAULT     0x00000003

/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00008000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              15
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_MASK          0x00004000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_SHIFT         14
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DITHER_DISABLE_DEFAULT       0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_SHIFT          1
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_PLLRESERVED0_DEFAULT        0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_MASK          0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_SHIFT         0
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT       0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_reserved0_SHIFT             1

/* CLKGEN :: PLL_SYS0_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRON_PWRON_PLL_DEFAULT           0x00000001

/***************************************************************************
 *PLL_SYS0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT             1

/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT                0
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT              0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_VCXO0_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_reserved0_SHIFT         1

/* CLKGEN :: PLL_VCXO0_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_MASK               0xffffc000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_SHIFT              14

/* CLKGEN :: PLL_VCXO0_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_MASK                    0x00003c00
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_SHIFT                   10
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_DEFAULT                 0x00000002

/* CLKGEN :: PLL_VCXO0_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_MASK                0x000003ff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_DEFAULT             0x00000040

/***************************************************************************
 *PLL_VCXO0_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_MASK              0xfff00000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_SHIFT             20

/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_MASK              0xfffffc00
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_SHIFT             10

/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008

/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000038
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     3
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004

/***************************************************************************
 *PLL_VCXO0_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_reserved0_SHIFT      1

/* CLKGEN :: PLL_VCXO0_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT    0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT  0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_reserved0_MASK          0xffff0000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_reserved0_SHIFT         16

/* CLKGEN :: PLL_VCXO0_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_MASK           0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_CTRL_LDO_CTRL_DEFAULT        0x00000005

/***************************************************************************
 *PLL_VCXO0_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_reserved0_SHIFT        1

/* CLKGEN :: PLL_VCXO0_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT    0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT  0x00000001

/***************************************************************************
 *PLL_VCXO0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1

/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_SHIFT           0

/***************************************************************************
 *PLL_VCXO0_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_MASK          0x80000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_SHIFT         31
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_LOW_DEFAULT       0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_MASK         0x40000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_SHIFT        30
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_RANGE_HIGH_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_MASK               0x20000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_SHIFT              29
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DIV2_DEFAULT            0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_MASK            0x10000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_SHIFT           28
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_MASK            0x0e000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_SHIFT           25
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_MASK             0x01000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_SHIFT            24
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET_DEFAULT          0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_MASK              0x00c00000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_SHIFT             22
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_DEFAULT           0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_MASK           0x00200000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_SHIFT          21
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REF_ALT_OFFS_DEFAULT        0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_MASK               0x00180000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_SHIFT              19
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_DEFAULT            0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_MASK       0x00060000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_SHIFT      17
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_POST_CTRL_RESETB_DEFAULT    0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_SHIFT           16
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_MASK              0x00008000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_SHIFT             15
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_MASK         0x00004000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_SHIFT        14
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DITHER_DISABLE_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_SHIFT              0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_SHIFT         1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_PLLRESERVED0_DEFAULT       0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_MASK         0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_SHIFT        0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC2_DIG_INPUT_SEL_DEFAULT      0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_reserved0_SHIFT            1

/* CLKGEN :: PLL_VCXO0_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRON_PWRON_PLL_DEFAULT          0x00000001

/***************************************************************************
 *PLL_VCXO0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_DEFAULT             0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_DEFAULT             0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_VCXO1_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_reserved0_SHIFT         1

/* CLKGEN :: PLL_VCXO1_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_MASK               0xffffc000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_SHIFT              14

/* CLKGEN :: PLL_VCXO1_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_MASK                    0x00003c00
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_SHIFT                   10
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_DEFAULT                 0x00000002

/* CLKGEN :: PLL_VCXO1_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_MASK                0x000003ff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_DEFAULT             0x00000040

/***************************************************************************
 *PLL_VCXO1_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_MASK              0xfff00000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_SHIFT             20

/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_MASK              0xfffffc00
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_SHIFT             10

/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008

/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000038
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     3
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004

/***************************************************************************
 *PLL_VCXO1_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_reserved0_SHIFT      1

/* CLKGEN :: PLL_VCXO1_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT    0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT  0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_reserved0_MASK          0xffff0000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_reserved0_SHIFT         16

/* CLKGEN :: PLL_VCXO1_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_MASK           0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_CTRL_LDO_CTRL_DEFAULT        0x00000005

/***************************************************************************
 *PLL_VCXO1_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_reserved0_SHIFT        1

/* CLKGEN :: PLL_VCXO1_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT    0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT  0x00000001

/***************************************************************************
 *PLL_VCXO1_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1

/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_SHIFT           0

/***************************************************************************
 *PLL_VCXO1_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_MASK          0x80000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_SHIFT         31
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_LOW_DEFAULT       0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_MASK         0x40000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_SHIFT        30
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_RANGE_HIGH_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_MASK               0x20000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_SHIFT              29
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DIV2_DEFAULT            0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_MASK            0x10000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_SHIFT           28
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_MASK            0x0e000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_SHIFT           25
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_MASK             0x01000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_SHIFT            24
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET_DEFAULT          0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_MASK              0x00c00000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_SHIFT             22
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_DEFAULT           0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_MASK           0x00200000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_SHIFT          21
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REF_ALT_OFFS_DEFAULT        0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_MASK               0x00180000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_SHIFT              19
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_DEFAULT            0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_MASK       0x00060000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_SHIFT      17
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_POST_CTRL_RESETB_DEFAULT    0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_SHIFT           16
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_MASK              0x00008000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_SHIFT             15
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_MASK         0x00004000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_SHIFT        14
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DITHER_DISABLE_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_SHIFT              0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_SHIFT         1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_PLLRESERVED0_DEFAULT       0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_MASK         0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_SHIFT        0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC2_DIG_INPUT_SEL_DEFAULT      0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_reserved0_SHIFT            1

/* CLKGEN :: PLL_VCXO1_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRON_PWRON_PLL_DEFAULT          0x00000001

/***************************************************************************
 *PLL_VCXO1_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_DEFAULT             0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_DEFAULT             0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO1_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_VCXO2_PLL_BG_PWRON - Bandgap Power on
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_BG_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_reserved0_SHIFT         1

/* CLKGEN :: PLL_VCXO2_PLL_BG_PWRON :: BG_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_BG_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_BG_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_BG_PWRON_BG_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xfffff800
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 11

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000007d

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_MASK               0xffffc000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_SHIFT              14

/* CLKGEN :: PLL_VCXO2_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_MASK                    0x00003c00
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_SHIFT                   10
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_DEFAULT                 0x00000002

/* CLKGEN :: PLL_VCXO2_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_MASK                0x000003ff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_DEFAULT             0x00000040

/***************************************************************************
 *PLL_VCXO2_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_MASK              0xfff00000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_SHIFT             20

/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_DEFAULT        0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_MASK              0xfffffc00
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_SHIFT             10

/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008

/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000038
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     3
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000004

/***************************************************************************
 *PLL_VCXO2_PLL_HOLD_CH_ALL - Hold PLL all channels
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_HOLD_CH_ALL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_reserved0_SHIFT      1

/* CLKGEN :: PLL_VCXO2_PLL_HOLD_CH_ALL :: HOLD_CH_ALL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_SHIFT    0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_HOLD_CH_ALL_HOLD_CH_ALL_DEFAULT  0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_LDO_CTRL - Ldo voltage control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_LDO_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_reserved0_MASK          0xffff0000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_reserved0_SHIFT         16

/* CLKGEN :: PLL_VCXO2_PLL_LDO_CTRL :: LDO_CTRL [15:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_LDO_CTRL_MASK           0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_LDO_CTRL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_CTRL_LDO_CTRL_DEFAULT        0x00000005

/***************************************************************************
 *PLL_VCXO2_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_reserved0_SHIFT        1

/* CLKGEN :: PLL_VCXO2_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK     0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT    0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT  0x00000001

/***************************************************************************
 *PLL_VCXO2_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1

/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_SHIFT           0

/***************************************************************************
 *PLL_VCXO2_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_RANGE_LOW [31:31] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_LOW_MASK          0x80000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_LOW_SHIFT         31
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_LOW_DEFAULT       0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_RANGE_HIGH [30:30] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_HIGH_MASK         0x40000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_HIGH_SHIFT        30
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_RANGE_HIGH_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DIV2_MASK               0x20000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DIV2_SHIFT              29
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DIV2_DEFAULT            0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_MASK            0x10000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_SHIFT           28
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_MASK            0x0e000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_SHIFT           25
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET_MASK             0x01000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET_SHIFT            24
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET_DEFAULT          0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_MASK              0x00c00000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_SHIFT             22
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_DEFAULT           0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: REF_ALT_OFFS [21:21] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REF_ALT_OFFS_MASK           0x00200000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REF_ALT_OFFS_SHIFT          21
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REF_ALT_OFFS_DEFAULT        0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: PWM_RATE [20:19] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_MASK               0x00180000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_SHIFT              19
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_DEFAULT            0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: POST_CTRL_RESETB [18:17] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_POST_CTRL_RESETB_MASK       0x00060000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_POST_CTRL_RESETB_SHIFT      17
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_POST_CTRL_RESETB_DEFAULT    0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_NDIV_RELOCK_SHIFT           16
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_NDIV_RELOCK_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: FAST_LOCK [15:15] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_MASK              0x00008000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_SHIFT             15
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DITHER_DISABLE [14:14] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DITHER_DISABLE_MASK         0x00004000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DITHER_DISABLE_SHIFT        14
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DITHER_DISABLE_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_SHIFT              0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_DEFAULT            0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_MISC2 :: PLLRESERVED0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_PLLRESERVED0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_PLLRESERVED0_SHIFT         1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_PLLRESERVED0_DEFAULT       0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_MISC2 :: DIG_INPUT_SEL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_DIG_INPUT_SEL_MASK         0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_DIG_INPUT_SEL_SHIFT        0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC2_DIG_INPUT_SEL_DEFAULT      0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_reserved0_SHIFT            1

/* CLKGEN :: PLL_VCXO2_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_PWRON_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_PWRON_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRON_PWRON_PLL_DEFAULT          0x00000001

/***************************************************************************
 *PLL_VCXO2_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_DEFAULT             0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_DEFAULT             0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO2_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_XPT_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  11

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [10:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000400
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 10
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [09:09] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000200
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  11

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [10:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000400
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 10
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [09:09] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000200
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000c

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  11

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [10:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000400
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 10
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [09:09] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000200
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000a

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT  11

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [10:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000400
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 10
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [09:09] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000200
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT   1
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000f

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT  11

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [10:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000400
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 10
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [09:09] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000200
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT   1
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x0000000a

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK   0xfffff800
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT  11

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [10:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000400
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 10
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [09:09] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000200
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT   1
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000008

/* CLKGEN :: PLL_XPT_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_DIV :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_MASK                 0xffffc000
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_reserved0_SHIFT                14

/* CLKGEN :: PLL_XPT_PLL_DIV :: PDIV [13:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_MASK                      0x00003c00
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_SHIFT                     10
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_PDIV_DEFAULT                   0x00000002

/* CLKGEN :: PLL_XPT_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_MASK                  0x000003ff
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_SHIFT                 0
#define BCHP_CLKGEN_PLL_XPT_PLL_DIV_NDIV_INT_DEFAULT               0x00000078

/***************************************************************************
 *PLL_XPT_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_MASK                0xfffffc00
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_reserved0_SHIFT               10

/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000005

/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_IN_FREQ [05:03] */
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000038
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       3
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     0x00000000

/* CLKGEN :: PLL_XPT_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [02:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000007
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/***************************************************************************
 *PLL_XPT_PLL_LDO_PWRON - LDO Power on
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_reserved0_SHIFT          1

/* CLKGEN :: PLL_XPT_PLL_LDO_PWRON :: LDO_PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_MASK       0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_SHIFT      0
#define BCHP_CLKGEN_PLL_XPT_PLL_LDO_PWRON_LDO_PWRON_PLL_DEFAULT    0x00000001

/***************************************************************************
 *PLL_XPT_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1

/* CLKGEN :: PLL_XPT_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_LOCK_STATUS_LOCK_SHIFT             0

/***************************************************************************
 *PLL_XPT_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_RANGE [31:30] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_MASK                0xc0000000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_SHIFT               30
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_RANGE_DEFAULT             0x00000002

/* CLKGEN :: PLL_XPT_PLL_MISC :: VCO_FB_DIV2 [29:29] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_MASK              0x20000000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_SHIFT             29
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_VCO_FB_DIV2_DEFAULT           0x00000001

/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_UPDATE [28:28] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_MASK              0x10000000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_SHIFT             28
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_UPDATE_DEFAULT           0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_SELECT [27:25] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_MASK              0x0e000000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_SHIFT             25
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_SELECT_DEFAULT           0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_RESET [24:24] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_MASK               0x01000000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_SHIFT              24
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_RESET_DEFAULT            0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: STAT_MODE [23:22] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_MASK                0x00c00000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_SHIFT               22
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_STAT_MODE_DEFAULT             0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: PWM_RATE [21:20] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_MASK                 0x00300000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_SHIFT                20
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PWM_RATE_DEFAULT              0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: POST_CTRL_RESETB [19:18] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_MASK         0x000c0000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_SHIFT        18
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_POST_CTRL_RESETB_DEFAULT      0x00000003

/* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED2 [17:16] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_MASK             0x00030000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_SHIFT            16
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED2_DEFAULT          0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: PLLRESERVED1 [15:15] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_MASK             0x00008000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_SHIFT            15
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_PLLRESERVED1_DEFAULT          0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: NDIV_RELOCK [14:14] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_MASK              0x00004000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_SHIFT             14
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_NDIV_RELOCK_DEFAULT           0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: FAST_LOCK [13:13] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_MASK                0x00002000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_SHIFT               13
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_FAST_LOCK_DEFAULT             0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0x00000000

/***************************************************************************
 *PLL_XPT_PLL_MISC2 - Mscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_MISC2 :: PLLRESERVED0 [31:02] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_SHIFT           2
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_PLLRESERVED0_DEFAULT         0x00000000

/* CLKGEN :: PLL_XPT_PLL_MISC2 :: LDO [01:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_MASK                     0x00000003
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_SHIFT                    0
#define BCHP_CLKGEN_PLL_XPT_PLL_MISC2_LDO_DEFAULT                  0x00000001

/***************************************************************************
 *PLL_XPT_PLL_PWRON - Poweron
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_PWRON :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_reserved0_SHIFT              1

/* CLKGEN :: PLL_XPT_PLL_PWRON :: PWRON_PLL [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_SHIFT              0
#define BCHP_CLKGEN_PLL_XPT_PLL_PWRON_PWRON_PLL_DEFAULT            0x00000001

/***************************************************************************
 *PLL_XPT_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_RESET :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_reserved0_SHIFT              1

/* CLKGEN :: PLL_XPT_PLL_RESET :: RESETD [00:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_SHIFT                 0
#define BCHP_CLKGEN_PLL_XPT_PLL_RESET_RESETD_DEFAULT               0x00000000

/***************************************************************************
 *PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_XPT_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_XPT_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_MASK              0xfffff000
#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_reserved0_SHIFT             12

/* CLKGEN :: PLL_XPT_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
#define BCHP_CLKGEN_PLL_XPT_PLL_STATUS_TEST_STATUS_SHIFT           0

/***************************************************************************
 *ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST's clocks
 ***************************************************************************/
/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_ADC_4P5_CLOCK [00:00] */
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_ADC_4P5_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_ADC_4P5_CLOCK_SHIFT 0
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_ADC_4P5_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_ADC_4P5_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_ADC_4P5_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_ANA_QDAC_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_ADC_4P5_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE - Disable ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST's clocks
 ***************************************************************************/
/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE :: DISABLE_SYSTEM_54_VR_CLOCK [00:00] */
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_SHIFT 0
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_DISABLE_SYSTEM_54_VR_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSTEM_54_VR_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_ANA_SW_AVS_TS28HPM_6MX_2MR_FC_H_E_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_54_VR_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *APM_CHIP_TOP_INST_CLOCK_ENABLE - Apm chip top inst clock enable
 ***************************************************************************/
/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_ENABLE :: APM_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_APM_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_APM_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_APM_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS :: APM_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS_APM_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_APM_CHIP_TOP_INST_CLOCK_ENABLE_STATUS_APM_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *AVD_SID1_TOP_INST_CLOCK_ENABLE - Avd sid1 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_reserved0_MASK  0xffffffe0
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 5

/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE :: AVD_SID1_SCB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_SCB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_SCB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE :: AVD_SID1_GISB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_GISB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_GISB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE :: AVD_SID1_CPU_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_CPU_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_CPU_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_CPU_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE :: AVD_SID1_CORE_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_CORE_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_CORE_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE :: AVD_SID1_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_AVD_SID1_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *AVD_SID1_TOP_INST_CLOCK_ENABLE_SID - Avd sid1 top inst clock enable sid
 ***************************************************************************/
/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_SID :: reserved0 [31:01] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_reserved0_SHIFT 1

/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_SID :: SID_CORE_CLOCK_ENABLE_SID [00:00] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_SID_CORE_CLOCK_ENABLE_SID_MASK 0x00000001
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_SID_CORE_CLOCK_ENABLE_SID_SHIFT 0
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_SID_CORE_CLOCK_ENABLE_SID_DEFAULT 0x00000001

/***************************************************************************
 *AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_reserved0_SHIFT 1

/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS :: SID_CORE_CLOCK_ENABLE_SID_STATUS [00:00] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_SID_CORE_CLOCK_ENABLE_SID_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_SID_STATUS_SID_CORE_CLOCK_ENABLE_SID_STATUS_SHIFT 0

/***************************************************************************
 *AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5

/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: AVD_SID1_SCB_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_SCB_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: AVD_SID1_GISB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_GISB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: AVD_SID1_CPU_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_CPU_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: AVD_SID1_CORE_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_CORE_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS :: AVD_SID1_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_CLOCK_ENABLE_STATUS_AVD_SID1_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *AVD_SID1_TOP_INST_OBSERVE_CLOCK - Avd sid1 top inst observe clock
 ***************************************************************************/
/* CLKGEN :: AVD_SID1_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: AVD_SID1_TOP_INST_OBSERVE_CLOCK :: AVD_SID1_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: AVD_SID1_TOP_INST_OBSERVE_CLOCK :: AVD_SID1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: AVD_SID1_TOP_INST_OBSERVE_CLOCK :: AVD_SID1_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_AVD_SID1_TOP_INST_OBSERVE_CLOCK_AVD_SID1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *BVN_MVP_TOP_INST_CLOCK_ENABLE - Bvn mvp top inst clock enable
 ***************************************************************************/
/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff0
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  4

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_BVB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_BVB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE :: BVND_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_SCB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_SCB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_BVB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_BVB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS :: BVND_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_BVN_MVP_TOP_INST_CLOCK_ENABLE_STATUS_BVND_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
 ***************************************************************************/
/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      4

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_BVB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_BVB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *BVN_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_SCB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_SCB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_BVB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_BVB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE_STATUS :: BVN_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_STATUS_BVN_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
 ***************************************************************************/
/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           1

/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [00:00] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK     0xfffffffe
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT    1

/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_OSC_DIGITAL_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_OSC_DIGITAL_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *CLKGEN_INST_CLOCK_ENABLE - Clkgen inst clock enable
 ***************************************************************************/
/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffff8
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_SHIFT       3

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_TP_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_TP_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_TP_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_TP_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *CLKGEN_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_TP_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_TP_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_TP_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE_STATUS :: CG_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_STATUS_CG_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *CLOCK_MONITOR_CONTROL - Clock Monitor Control
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   0x00000001

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001

/***************************************************************************
 *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff

/***************************************************************************
 *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0

/***************************************************************************
 *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1

/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0

/***************************************************************************
 *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0

/***************************************************************************
 *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK      0xffffffe0
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT     5

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_GISB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_CORE_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_CORE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *CORE_XPT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_SCB_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_GISB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_GISB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_CORE_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_CORE_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE - Disable CPU4355_BCM_MIPS_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE :: DISABLE_MIPS_MCLK_CLOCK [00:00] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_DISABLE_MIPS_MCLK_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_DISABLE_MIPS_MCLK_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_DISABLE_MIPS_MCLK_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_MIPS_MCLK_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_MIPS_MCLK_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_MIPS_MCLK_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE - Cpu4355 bcm mips top inst clock enable
 ***************************************************************************/
/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE :: MIPS_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_MIPS_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS :: MIPS_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS :: MIPS_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CPU4355_BCM_MIPS_TOP_INST_CLOCK_ENABLE_STATUS_MIPS_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *D3DSMAC_X4_TOP_INST_CLOCK_DISABLE - Disable D3DSMAC_X4_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE :: DISABLE_DSMAC_MPEG_SCAN_CLOCK [01:01] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MPEG_SCAN_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MPEG_SCAN_CLOCK_SHIFT 1
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MPEG_SCAN_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE :: DISABLE_DSMAC_MAC_CLOCK [00:00] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MAC_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MAC_CLOCK_SHIFT 0
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_DISABLE_DSMAC_MAC_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DSMAC_MPEG_SCAN_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMAC_MPEG_SCAN_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMAC_MPEG_SCAN_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DSMAC_MAC_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMAC_MAC_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DSMAC_MAC_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *D3DSMAC_X4_TOP_INST_CLOCK_ENABLE - D3dsmac x4 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE :: DSMAC_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE :: DSMAC_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_DSMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS :: DSMAC_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS :: DSMAC_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_D3DSMAC_X4_TOP_INST_CLOCK_ENABLE_STATUS_DSMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DECT_UBUS_TOP_INST_CLOCK_DISABLE - Disable DECT_UBUS_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE :: DISABLE_DECT_DEV_278_CLOCK [00:00] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_DISABLE_DECT_DEV_278_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_DISABLE_DECT_DEV_278_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_DISABLE_DECT_DEV_278_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DECT_DEV_278_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DECT_DEV_278_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DECT_DEV_278_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DECT_UBUS_TOP_INST_CLOCK_ENABLE - Dect ubus top inst clock enable
 ***************************************************************************/
/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE :: DECT_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_DECT_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_DECT_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_DECT_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS :: DECT_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_DECT_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DECT_UBUS_TOP_INST_CLOCK_ENABLE_STATUS_DECT_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DISABLE_AVS_TOP_DURING_S2 - Disable AVS_TOP 54MHz clocks during S2 standby.
 ***************************************************************************/
/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_reserved0_SHIFT      1

/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2 :: DISABLE_AVS_TOP [00:00] */
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_MASK 0x00000001
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_SHIFT 0
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_DISABLE_AVS_TOP_DEFAULT 0x00000000

/***************************************************************************
 *DISABLE_AVS_TOP_DURING_S2_SECURE - Secure AVS_TOP clock disable. Set at start-up to guarantee AVS_TOP is clock gated in S2 standby.
 ***************************************************************************/
/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_reserved0_SHIFT 1

/* CLKGEN :: DISABLE_AVS_TOP_DURING_S2_SECURE :: DISABLE_AVS_TOP_SECURE [00:00] */
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_MASK 0x00000001
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_SHIFT 0
#define BCHP_CLKGEN_DISABLE_AVS_TOP_DURING_S2_SECURE_DISABLE_AVS_TOP_SECURE_DEFAULT 0x00000000

/***************************************************************************
 *BSPI_CLOCK_SELECT - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: BSPI_CLOCK_SELECT :: reserved0 [31:03] */
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_MASK               0xfffffff8
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_SHIFT              3

/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_FREQ_SEL [02:01] */
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_MASK      0x00000006
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_SHIFT     1
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_DEFAULT   0x00000000

/* CLKGEN :: BSPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS1_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: reserved0 [31:09] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_reserved0_MASK  0xfffffe00
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_reserved0_SHIFT 9

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS1_CHANNEL4_FREQ_DISABLE_RDB_MACRO [08:08] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL4_FREQ_DISABLE_RDB_MACRO_MASK 0x00000100
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL4_FREQ_DISABLE_RDB_MACRO_SHIFT 8
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL4_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS1_CHANNEL3_FREQ_DISABLE_RDB_MACRO [07:07] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL3_FREQ_DISABLE_RDB_MACRO_MASK 0x00000080
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL3_FREQ_DISABLE_RDB_MACRO_SHIFT 7
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL3_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: DOCSIS_PLL_SYS1_CHANNEL1_FREQ_DISABLE_RDB_MACRO [06:06] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL1_FREQ_DISABLE_RDB_MACRO_MASK 0x00000040
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL1_FREQ_DISABLE_RDB_MACRO_SHIFT 6
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_DOCSIS_PLL_SYS1_CHANNEL1_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: CHANNEL4_FREQ [05:04] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL4_FREQ_MASK 0x00000030
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL4_FREQ_SHIFT 4
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL4_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: CHANNEL3_FREQ [03:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL3_FREQ_MASK 0x0000000c
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL3_FREQ_SHIFT 2
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL3_FREQ_DEFAULT 0x00000000

/* CLKGEN :: DOCSIS_PLL_SYS1_RDB_MACRO_CTRL :: CHANNEL1_FREQ [01:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL1_FREQ_MASK 0x00000003
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL1_FREQ_SHIFT 0
#define BCHP_CLKGEN_DOCSIS_PLL_SYS1_RDB_MACRO_CTRL_CHANNEL1_FREQ_DEFAULT 0x00000000

/***************************************************************************
 *DOCSIS_PLL_SYS2_PLL_RESET_STATUS - DOCSIS_PLL_SYS2 Reset Status
 ***************************************************************************/
/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_reserved0_SHIFT 2

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: DOCSIS_PLL_SYS2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DOCSIS_PLL_SYS2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *DS_TOPA_INST_CLOCK_ENABLE - Ds topa inst clock enable
 ***************************************************************************/
/* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_reserved0_SHIFT      1

/* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE :: DSA_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_DSA_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DS_TOPA_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_TOPA_INST_CLOCK_ENABLE_STATUS :: DSA_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_DSA_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPA_INST_CLOCK_ENABLE_STATUS_DSA_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DS_TOPB_INST_CLOCK_ENABLE - Ds topb inst clock enable
 ***************************************************************************/
/* CLKGEN :: DS_TOPB_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_reserved0_SHIFT      1

/* CLKGEN :: DS_TOPB_INST_CLOCK_ENABLE :: DSB_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_DSB_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_DSB_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_DSB_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DS_TOPB_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DS_TOPB_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_TOPB_INST_CLOCK_ENABLE_STATUS :: DSB_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS_DSB_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPB_INST_CLOCK_ENABLE_STATUS_DSB_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DS_TOPC_INST_CLOCK_ENABLE - Ds topc inst clock enable
 ***************************************************************************/
/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_reserved0_SHIFT      2

/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE :: DSC_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE :: DSC_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DS_TOPC_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE_STATUS :: DSC_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_DSC_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_DSC_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: DS_TOPC_INST_CLOCK_ENABLE_STATUS :: DSC_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_DSC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPC_INST_CLOCK_ENABLE_STATUS_DSC_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DS_TOPD_INST_CLOCK_ENABLE - Ds topd inst clock enable
 ***************************************************************************/
/* CLKGEN :: DS_TOPD_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_reserved0_SHIFT      1

/* CLKGEN :: DS_TOPD_INST_CLOCK_ENABLE :: DSC_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_DSC_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DS_TOPD_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DS_TOPD_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_TOPD_INST_CLOCK_ENABLE_STATUS :: DSC_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS_DSC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_TOPD_INST_CLOCK_ENABLE_STATUS_DSC_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DS_WFE_TOP_INST_CLOCK_ENABLE - Ds wfe top inst clock enable
 ***************************************************************************/
/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT   1

/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_ENABLE :: WFE_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_WFE_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_WFE_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_WFE_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS :: WFE_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS_WFE_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DS_WFE_TOP_INST_CLOCK_ENABLE_STATUS_WFE_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DTP_DFAP_TOP_INST_CLOCK_DISABLE - Disable DTP_DFAP_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 3

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DFAP_324_CLOCK [02:02] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_324_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_324_CLOCK_SHIFT 2
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_324_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_DFAP_216_CLOCK [01:01] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_216_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_216_CLOCK_SHIFT 1
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_DFAP_216_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_CG_TCK_SCAN_CLOCK [00:00] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DFAP_324_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_324_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_324_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_DFAP_216_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_216_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_DFAP_216_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CG_TCK_SCAN_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DTP_DFAP_TOP_INST_CLOCK_ENABLE - Dtp dfap top inst clock enable
 ***************************************************************************/
/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK  0xfffffffc
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE :: DFAP_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE :: DFAP_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_DFAP_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS :: DFAP_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS :: DFAP_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DTP_DFAP_TOP_INST_CLOCK_ENABLE_STATUS_DFAP_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DVP_HR_INST_CLOCK_DISABLE - Disable DVP_HR_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_reserved0_SHIFT      1

/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE :: DISABLE_DVPHR_ALWAYSON_CLOCK [00:00] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_DISABLE_DVPHR_ALWAYSON_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DVP_HR_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DVP_HR_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHR_ALWAYSON_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DVP_HR_INST_CLOCK_ENABLE - Dvp hr inst clock enable
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffff0
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_SHIFT       4

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_BVB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_BVB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_54_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_324_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_324_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_324_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_324_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DVP_HR_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_BVB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_BVB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_54_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_54_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_324_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_324_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_324_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE_STATUS :: DVPHR_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_STATUS_DVPHR_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DVP_HR_INST_ENABLE - Dvp hr inst enable
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HR_INST_ENABLE_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_DVP_HR_INST_ENABLE_reserved0_SHIFT             1

/* CLKGEN :: DVP_HR_INST_ENABLE :: DVPHR_SCAN_CLK_324_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HR_INST_ENABLE_DVPHR_SCAN_CLK_324_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HR_INST_ENABLE_DVPHR_SCAN_CLK_324_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HR_INST_ENABLE_DVPHR_SCAN_CLK_324_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *DVP_HR_INST_OBSERVE_CLOCK - Dvp hr inst observe clock
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_SHIFT      6

/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT      1

/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DVP_HT_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE_STATUS :: DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffff0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT       4

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_BVB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_BVB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_BVB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_BVB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_54_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_324_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_324_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_324_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_324_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DVP_HT_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_BVB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_BVB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_54_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_54_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_324_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_324_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_324_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE_STATUS :: DVPHT_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT      6

/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *EAGLET_TOP_CORE_INST_CLOCK_ENABLE - Eaglet top core inst clock enable
 ***************************************************************************/
/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_reserved0_SHIFT 4

/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE :: A15C_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE :: A15C_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE :: A15C_CPU_SECURE_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_CPU_SECURE_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_CPU_SECURE_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_CPU_SECURE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE :: A15C_CPU_C_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_CPU_C_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_CPU_C_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_A15C_CPU_C_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS :: A15C_SCB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_SCB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS :: A15C_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS :: A15C_CPU_SECURE_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_CPU_SECURE_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_CPU_SECURE_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS :: A15C_CPU_C_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_CPU_C_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_EAGLET_TOP_CORE_INST_CLOCK_ENABLE_STATUS_A15C_CPU_C_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE - Eaglet top router inst clock enable
 ***************************************************************************/
/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_reserved0_SHIFT 4

/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE :: A15R_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE :: A15R_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE :: A15R_CPU_SECURE_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_CPU_SECURE_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_CPU_SECURE_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_CPU_SECURE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE :: A15R_CPU_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_CPU_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_CPU_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_A15R_CPU_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: A15R_SCB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_SCB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: A15R_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: A15R_CPU_SECURE_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_CPU_SECURE_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_CPU_SECURE_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: A15R_CPU_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_CPU_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_A15R_CPU_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *EAGLET_TOP_ROUTER_INST_SELECT - Eaglet top router inst select
 ***************************************************************************/
/* CLKGEN :: EAGLET_TOP_ROUTER_INST_SELECT :: reserved0 [31:01] */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_SELECT_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_SELECT_reserved0_SHIFT  1

/* CLKGEN :: EAGLET_TOP_ROUTER_INST_SELECT :: ROUTER_CPU_PLL_CLOCK_SELECT [00:00] */
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_SELECT_ROUTER_CPU_PLL_CLOCK_SELECT_MASK 0x00000001
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_SELECT_ROUTER_CPU_PLL_CLOCK_SELECT_SHIFT 0
#define BCHP_CLKGEN_EAGLET_TOP_ROUTER_INST_SELECT_ROUTER_CPU_PLL_CLOCK_SELECT_DEFAULT 0x00000000

/***************************************************************************
 *EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT - Egphy28 4port 33v 90o fc inst clock select
 ***************************************************************************/
/* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: reserved0 [31:02] */
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_reserved0_SHIFT 2

/* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: EGPHY_PLL_CLOCK_SELECT [01:01] */
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_PLL_CLOCK_SELECT_MASK 0x00000002
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_PLL_CLOCK_SELECT_SHIFT 1
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_PLL_CLOCK_SELECT_DEFAULT 0x00000000

/* CLKGEN :: EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT :: EGPHY_25_50_CLOCK_SELECT [00:00] */
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_25_50_CLOCK_SELECT_MASK 0x00000001
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_25_50_CLOCK_SELECT_SHIFT 0
#define BCHP_CLKGEN_EGPHY28_4PORT_33V_90O_FC_INST_CLOCK_SELECT_EGPHY_25_50_CLOCK_SELECT_DEFAULT 0x00000000

/***************************************************************************
 *G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE - G2u u2u ubus mod ss inst clock enable
 ***************************************************************************/
/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE :: G2U_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE :: G2U_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_G2U_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS :: G2U_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS :: G2U_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_G2U_U2U_UBUS_MOD_SS_INST_CLOCK_ENABLE_STATUS_G2U_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *GFAP_TOP_INST_CLOCK_DISABLE - Disable GFAP_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff8
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    3

/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_GFAP_324_CLOCK [02:02] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_324_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_324_CLOCK_SHIFT 2
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_324_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_GFAP_25_CLOCK [01:01] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_25_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_25_CLOCK_SHIFT 1
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_GFAP_25_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE :: DISABLE_CG_TCK_SCAN_CLOCK [00:00] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_SHIFT 0
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *GFAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_GFAP_324_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_GFAP_324_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_GFAP_324_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_GFAP_25_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_GFAP_25_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_GFAP_25_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: GFAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CG_TCK_SCAN_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *GFAP_TOP_INST_CLOCK_ENABLE - Gfap top inst clock enable
 ***************************************************************************/
/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     2

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE :: GFAP_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE :: GFAP_324_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_324_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_324_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_GFAP_324_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *GFAP_TOP_INST_CLOCK_ENABLE0 - Gfap top inst clock enable0
 ***************************************************************************/
/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0 :: reserved0 [31:02] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_reserved0_SHIFT    2

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0 :: GFAP_SCB_CLOCK_ENABLE0 [01:01] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_SCB_CLOCK_ENABLE0_MASK 0x00000002
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_SCB_CLOCK_ENABLE0_SHIFT 1
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_SCB_CLOCK_ENABLE0_DEFAULT 0x00000001

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0 :: GFAP_M2MC0_GISB_CLOCK_ENABLE0 [00:00] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_M2MC0_GISB_CLOCK_ENABLE0_MASK 0x00000001
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_M2MC0_GISB_CLOCK_ENABLE0_SHIFT 0
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_GFAP_M2MC0_GISB_CLOCK_ENABLE0_DEFAULT 0x00000001

/***************************************************************************
 *GFAP_TOP_INST_CLOCK_ENABLE0_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_reserved0_SHIFT 2

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0_STATUS :: GFAP_SCB_CLOCK_ENABLE0_STATUS [01:01] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_GFAP_SCB_CLOCK_ENABLE0_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_GFAP_SCB_CLOCK_ENABLE0_STATUS_SHIFT 1

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE0_STATUS :: GFAP_M2MC0_GISB_CLOCK_ENABLE0_STATUS [00:00] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_GFAP_M2MC0_GISB_CLOCK_ENABLE0_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE0_STATUS_GFAP_M2MC0_GISB_CLOCK_ENABLE0_STATUS_SHIFT 0

/***************************************************************************
 *GFAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE_STATUS :: GFAP_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_GFAP_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_GFAP_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: GFAP_TOP_INST_CLOCK_ENABLE_STATUS :: GFAP_324_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_GFAP_324_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_GFAP_TOP_INST_CLOCK_ENABLE_STATUS_GFAP_324_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT     1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *GRAPHICS_INST_CLOCK_ENABLE0 - Graphics inst clock enable0
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0 :: reserved0 [31:02] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_reserved0_SHIFT    2

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0 :: GFX_M2MC0_SCB_CLOCK_ENABLE0 [01:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_SCB_CLOCK_ENABLE0_MASK 0x00000002
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_SCB_CLOCK_ENABLE0_SHIFT 1
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_SCB_CLOCK_ENABLE0_DEFAULT 0x00000001

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0 :: GFX_M2MC0_GISB_CLOCK_ENABLE0 [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_GISB_CLOCK_ENABLE0_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_GISB_CLOCK_ENABLE0_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_GFX_M2MC0_GISB_CLOCK_ENABLE0_DEFAULT 0x00000001

/***************************************************************************
 *GRAPHICS_INST_CLOCK_ENABLE0_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_reserved0_SHIFT 2

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0_STATUS :: GFX_M2MC0_SCB_CLOCK_ENABLE0_STATUS [01:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_GFX_M2MC0_SCB_CLOCK_ENABLE0_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_GFX_M2MC0_SCB_CLOCK_ENABLE0_STATUS_SHIFT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE0_STATUS :: GFX_M2MC0_GISB_CLOCK_ENABLE0_STATUS [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_GFX_M2MC0_GISB_CLOCK_ENABLE0_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE0_STATUS_GFX_M2MC0_GISB_CLOCK_ENABLE0_STATUS_SHIFT 0

/***************************************************************************
 *GRAPHICS_INST_CLOCK_ENABLE1 - Graphics inst clock enable1
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1 :: reserved0 [31:02] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_reserved0_SHIFT    2

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1 :: GFX_M2MC1_SCB_CLOCK_ENABLE1 [01:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_SCB_CLOCK_ENABLE1_MASK 0x00000002
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_SCB_CLOCK_ENABLE1_SHIFT 1
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_SCB_CLOCK_ENABLE1_DEFAULT 0x00000001

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1 :: GFX_M2MC1_GISB_CLOCK_ENABLE1 [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_GISB_CLOCK_ENABLE1_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_GISB_CLOCK_ENABLE1_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_GFX_M2MC1_GISB_CLOCK_ENABLE1_DEFAULT 0x00000001

/***************************************************************************
 *GRAPHICS_INST_CLOCK_ENABLE1_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_reserved0_SHIFT 2

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1_STATUS :: GFX_M2MC1_SCB_CLOCK_ENABLE1_STATUS [01:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_GFX_M2MC1_SCB_CLOCK_ENABLE1_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_GFX_M2MC1_SCB_CLOCK_ENABLE1_STATUS_SHIFT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE1_STATUS :: GFX_M2MC1_GISB_CLOCK_ENABLE1_STATUS [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_GFX_M2MC1_GISB_CLOCK_ENABLE1_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE1_STATUS_GFX_M2MC1_GISB_CLOCK_ENABLE1_STATUS_SHIFT 0

/***************************************************************************
 *GRAPHICS_INST_CLOCK_ENABLE_M2MC0 - Graphics inst clock enable m2mc0
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0 :: reserved0 [31:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_reserved0_SHIFT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0 :: GFX_M2MC0_CLOCK_ENABLE_M2MC0 [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_GFX_M2MC0_CLOCK_ENABLE_M2MC0_DEFAULT 0x00000001

/***************************************************************************
 *GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_reserved0_SHIFT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS :: GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC0_STATUS_GFX_M2MC0_CLOCK_ENABLE_M2MC0_STATUS_SHIFT 0

/***************************************************************************
 *GRAPHICS_INST_CLOCK_ENABLE_M2MC1 - Graphics inst clock enable m2mc1
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: reserved0 [31:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_reserved0_SHIFT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1 :: GFX_M2MC1_CLOCK_ENABLE_M2MC1 [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_GFX_M2MC1_CLOCK_ENABLE_M2MC1_DEFAULT 0x00000001

/***************************************************************************
 *GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_reserved0_SHIFT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS :: GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_M2MC1_STATUS_GFX_M2MC1_CLOCK_ENABLE_M2MC1_STATUS_SHIFT 0

/***************************************************************************
 *GRAPHICS_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE_STATUS :: GFX_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_STATUS_GFX_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks
 ***************************************************************************/
/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:06] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK          0xffffffc0
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT         6

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_EBI_CLOCK [05:05] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_SHIFT 5
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_NAND_DDR_CLOCK [04:04] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_SHIFT 4
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_NAND_DDR_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [03:03] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 3
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_EMMC_CLOCK [02:02] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_SHIFT 2
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_EMMC_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [01:01] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 1
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_ALWAYSON_CLOCK [00:00] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_SHIFT 0
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_ALWAYSON_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *HIF_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:06] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_MASK   0xffffffc0
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT  6

/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS [05:05] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_EBI_CLOCK_STATUS_SHIFT 5

/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_NAND_DDR_CLOCK_STATUS [04:04] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_NAND_DDR_CLOCK_STATUS_SHIFT 4

/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [03:03] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 3

/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_EMMC_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_CARD_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: HIF_INST_CLOCK_DISABLE_STATUS :: DISABLE_HIF_ALWAYSON_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_STATUS_DISABLE_HIF_ALWAYSON_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *HIF_INST_CLOCK_ENABLE - Hif inst clock enable
 ***************************************************************************/
/* CLKGEN :: HIF_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_reserved0_SHIFT          1

/* CLKGEN :: HIF_INST_CLOCK_ENABLE :: HIF_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_HIF_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *HIF_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: HIF_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT   1

/* CLKGEN :: HIF_INST_CLOCK_ENABLE_STATUS :: HIF_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_HIF_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_HIF_INST_CLOCK_ENABLE_STATUS_HIF_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *HIF_INST_OBSERVE_CLOCK - Hif inst observe clock
 ***************************************************************************/
/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_SHIFT         6

/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *HVD0_TOP_INST_CLOCK_ENABLE - Hvd0 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xffffffe0
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     5

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_SCB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_SCB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_SCB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_GISB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_GISB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_GISB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_CPU_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CPU_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CPU_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CPU_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_CORE_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CORE_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CORE_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE :: HVD0_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_HVD0_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *HVD0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_SCB_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_SCB_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_GISB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_GISB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_CPU_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_CPU_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_CORE_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_CORE_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: HVD0_TOP_INST_CLOCK_ENABLE_STATUS :: HVD0_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_HVD0_TOP_INST_CLOCK_ENABLE_STATUS_HVD0_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *HVD0_TOP_INST_OBSERVE_CLOCK - Hvd0 top inst observe clock
 ***************************************************************************/
/* CLKGEN :: HVD0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: HVD0_TOP_INST_OBSERVE_CLOCK :: HVD0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HVD0_TOP_INST_OBSERVE_CLOCK :: HVD0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HVD0_TOP_INST_OBSERVE_CLOCK :: HVD0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_HVD0_TOP_INST_OBSERVE_CLOCK_HVD0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
 ***************************************************************************/
/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:08] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xffffff00
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            8

/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO2_REFERENCE_CLOCK [07:06] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_MASK 0x000000c0
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_SHIFT 6
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [05:04] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000030
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [03:02] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x0000000c
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 2
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: INTERNAL_MUX_SELECT :: DOS_SYSTEM_TP_CLOCK [01:01] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_TP_CLOCK_MASK   0x00000002
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_TP_CLOCK_SHIFT  1
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_TP_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: INTERNAL_MUX_SELECT :: DOS_SYSTEM_BPCM_CLOCK [00:00] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_BPCM_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_BPCM_CLOCK_SHIFT 0
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_DOS_SYSTEM_BPCM_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *ITU656_0_MUX_SELECT - Mux selects for itu656_0 clocks
 ***************************************************************************/
/* CLKGEN :: ITU656_0_MUX_SELECT :: reserved0 [31:03] */
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_MASK             0xfffffff8
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_reserved0_SHIFT            3

/* CLKGEN :: ITU656_0_MUX_SELECT :: VEC_ITU656_0_CLOCK [02:01] */
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_MASK    0x00000006
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_SHIFT   1
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: ITU656_0_MUX_SELECT :: ENABLE_INVERT_VEC_ITU656_0_CLOCK [00:00] */
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_SHIFT 0
#define BCHP_CLKGEN_ITU656_0_MUX_SELECT_ENABLE_INVERT_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *LEAP_TOP_INST_CLOCK_DISABLE - Disable LEAP_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff0
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    4

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_LEAP_27_UART_CLOCK [03:03] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_UART_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_UART_CLOCK_SHIFT 3
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_27_UART_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_LEAP_216_CLOCK [02:02] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_216_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_216_CLOCK_SHIFT 2
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_LEAP_216_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [01:01] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT 1
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE :: DISABLE_AVSTOP_27_UART_CLOCK [00:00] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_SHIFT 0
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_DISABLE_AVSTOP_27_UART_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *LEAP_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_LEAP_27_UART_CLOCK_STATUS [03:03] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_UART_CLOCK_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_27_UART_CLOCK_STATUS_SHIFT 3

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_LEAP_216_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_216_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_LEAP_216_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVS_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: LEAP_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AVSTOP_27_UART_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AVSTOP_27_UART_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *LEAP_TOP_INST_CLOCK_ENABLE - Leap top inst clock enable
 ***************************************************************************/
/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff0
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     4

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_UNUSED_54_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_UNUSED_54_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_UNUSED_54_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_UNUSED_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_216_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE :: LEAP_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_LEAP_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *LEAP_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_UNUSED_54_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_UNUSED_54_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_UNUSED_54_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_216_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_216_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: LEAP_TOP_INST_CLOCK_ENABLE_STATUS :: LEAP_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_LEAP_TOP_INST_CLOCK_ENABLE_STATUS_LEAP_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *LEAP_TOP_INST_OBSERVE_CLOCK - Leap top inst observe clock
 ***************************************************************************/
/* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: LEAP_TOP_INST_OBSERVE_CLOCK :: AVS_TOP_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_LEAP_TOP_INST_OBSERVE_CLOCK_AVS_TOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE - Memsys 32 wrapper 0 inst clock enable
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_reserved0_SHIFT 3

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: MEMSYS0_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: MEMSYS0_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE :: MEMSYS0_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_MEMSYS0_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS :: MEMSYS0_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_CLOCK_ENABLE_STATUS_MEMSYS0_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK - Memsys 32 wrapper 0 inst observe clock
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK :: MEMSYS0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK :: MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK :: MEMSYS0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_OBSERVE_CLOCK_MEMSYS0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MEMSYS_32_WRAPPER_0_INST_STATUS - Memsys 32 wrapper 0 inst status
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS_reserved0_SHIFT 1

/* CLKGEN :: MEMSYS_32_WRAPPER_0_INST_STATUS :: MEMSYS0_PLL_LOCKED_STATUS [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS_MEMSYS0_PLL_LOCKED_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_0_INST_STATUS_MEMSYS0_PLL_LOCKED_STATUS_SHIFT 0

/***************************************************************************
 *MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE - Memsys 32 wrapper 1 inst clock enable
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_reserved0_SHIFT 3

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: MEMSYS1_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: MEMSYS1_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE :: MEMSYS1_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_MEMSYS1_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS :: MEMSYS1_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_CLOCK_ENABLE_STATUS_MEMSYS1_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK - Memsys 32 wrapper 1 inst observe clock
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK :: MEMSYS1_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK :: MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK :: MEMSYS1_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_OBSERVE_CLOCK_MEMSYS1_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MEMSYS_32_WRAPPER_1_INST_STATUS - Memsys 32 wrapper 1 inst status
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS_reserved0_SHIFT 1

/* CLKGEN :: MEMSYS_32_WRAPPER_1_INST_STATUS :: MEMSYS1_PLL_LOCKED_STATUS [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS_MEMSYS1_PLL_LOCKED_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_WRAPPER_1_INST_STATUS_MEMSYS1_PLL_LOCKED_STATUS_SHIFT 0

/***************************************************************************
 *MOCAMAC_TOP_INST_CLOCK_ENABLE - Mocamac top inst clock enable
 ***************************************************************************/
/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff8
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  3

/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE :: MOCAMAC_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_MOCAMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAMAC_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_CLOCK_ENABLE_STATUS_MOCAMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *MOCAMAC_TOP_INST_OBSERVE_CLOCK - Mocamac top inst observe clock
 ***************************************************************************/
/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MOCAMAC_TOP_INST_OBSERVE_CLOCK :: MOCAMAC_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MOCAMAC_TOP_INST_OBSERVE_CLOCK_MOCAMAC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MOCAPHY_TOP_INST_CLOCK_ENABLE - Mocaphy top inst clock enable
 ***************************************************************************/
/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  2

/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE :: MOCAPHY_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_MOCAPHY_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS :: MOCAPHY_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_CLOCK_ENABLE_STATUS_MOCAPHY_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *MOCAPHY_TOP_INST_OBSERVE_CLOCK - Mocaphy top inst observe clock
 ***************************************************************************/
/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MOCAPHY_TOP_INST_OBSERVE_CLOCK :: MOCAPHY_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MOCAPHY_TOP_INST_OBSERVE_CLOCK_MOCAPHY_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MULTI_CLOCK_DISABLE - Disable MULTI's clocks
 ***************************************************************************/
/* CLKGEN :: MULTI_CLOCK_DISABLE :: reserved0 [31:07] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_reserved0_MASK             0xffffff80
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_reserved0_SHIFT            7

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_US_54_CLOCK [06:06] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_US_54_CLOCK_MASK   0x00000040
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_US_54_CLOCK_SHIFT  6
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_US_54_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_UCB_DI_CLOCK [05:05] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_UCB_CLOCK [04:04] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_UCB_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_TP_CLOCK [03:03] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_TP_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_TP_CLOCK_SHIFT 3
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_TP_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_SMISB_CLOCK [02:02] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_SMISB_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_SMISB_CLOCK_SHIFT 2
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_SMISB_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_REQ_CLOCK [01:01] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_REQ_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_REQ_CLOCK_SHIFT 1
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_REQ_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MULTI_CLOCK_DISABLE :: DISABLE_DOS_SYSTEM_BPCM_CLOCK [00:00] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_DISABLE_DOS_SYSTEM_BPCM_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MULTI_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: reserved0 [31:07] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_reserved0_MASK      0xffffff80
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_reserved0_SHIFT     7

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_US_54_CLOCK_STATUS [06:06] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_US_54_CLOCK_STATUS_MASK 0x00000040
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_US_54_CLOCK_STATUS_SHIFT 6

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_STATUS [05:05] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_DI_CLOCK_STATUS_SHIFT 5

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_UCB_CLOCK_STATUS [04:04] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_CLOCK_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_UCB_CLOCK_STATUS_SHIFT 4

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_TP_CLOCK_STATUS [03:03] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_TP_CLOCK_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_TP_CLOCK_STATUS_SHIFT 3

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_SMISB_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_SMISB_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_SMISB_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_REQ_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_REQ_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_REQ_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: MULTI_CLOCK_DISABLE_STATUS :: DISABLE_DOS_SYSTEM_BPCM_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_BPCM_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MULTI_CLOCK_DISABLE_STATUS_DISABLE_DOS_SYSTEM_BPCM_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *PAD_CLK_OUT0_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: reserved0 [31:09] */
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_reserved0_MASK        0xfffffe00
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_reserved0_SHIFT       9

/* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OUT0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CLK_OUT0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PAD_CLK_OUT1_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: reserved0 [31:09] */
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_reserved0_MASK        0xfffffe00
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_reserved0_SHIFT       9

/* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OUT1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CLK_OUT1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PAD_CLOCK_DISABLE - Disable PAD's clocks
 ***************************************************************************/
/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              2

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK [01:01] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK [00:00] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT1_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK_OUT0_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *PAD_MUX_SELECT - Mux selects for Pad clocks
 ***************************************************************************/
/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffff8
#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 3

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_SC_CLOCK [02:02] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_MASK        0x00000004
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_SHIFT       2
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_SC_CLOCK_DEFAULT     0x00000000

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK_OUT1_CLOCK [01:01] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT1_CLOCK_MASK  0x00000002
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT1_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT1_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK_OUT0_CLOCK [00:00] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT0_CLOCK_MASK  0x00000001
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT0_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK_OUT0_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *PCIE_X2_TOP_INST_CLOCK_DISABLE - Disable PCIE_X2_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE :: DISABLE_PCIE_ALWAYSON_CLOCK [00:00] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_DISABLE_PCIE_ALWAYSON_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_PCIE_ALWAYSON_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_PCIE_ALWAYSON_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *PCIE_X2_TOP_INST_CLOCK_ENABLE - Pcie x2 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffff0
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  4

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE :: PCIE_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_PCIE_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_SCB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_SCB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS :: PCIE_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_CLOCK_ENABLE_STATUS_PCIE_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *PCIE_X2_TOP_INST_OBSERVE_CLOCK - Pcie x2 top inst observe clock
 ***************************************************************************/
/* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PCIE_X2_TOP_INST_OBSERVE_CLOCK :: PCIE_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PCIE_X2_TOP_INST_OBSERVE_CLOCK_PCIE_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2

/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2

/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_AUDIO2_PLL_RESET_STATUS - PLL_AUDIO2 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_SHIFT    2

/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_AVD_PLL_RESET_STATUS - PLL_AVD Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_AVD_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_MASK          0xfffffff0
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_SHIFT         4

/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: PLL_AVD_OPTIONS_DISABLE_RDB_MACRO [03:03] */
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: OPTIONS [02:00] */
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_MASK            0x00000007
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000

/***************************************************************************
 *PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST - PLL_CPU_CORE Glitchless Clock Switching
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9

/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f

/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000

/***************************************************************************
 *PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS - PLL_CPU_CORE Glitchless Switching
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4

/* CLKGEN :: PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
#define BCHP_CLKGEN_PLL_CPU_CORE_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0

/***************************************************************************
 *PLL_CPU_CORE_PLL_RESET_STATUS - PLL_CPU_CORE Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_reserved0_SHIFT  2

/* CLKGEN :: PLL_CPU_CORE_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_CPU_CORE_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_CORE_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_CPU_CORE_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_CORE_RDB_MACRO_CTRL :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_reserved0_MASK     0xfffffff0
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_reserved0_SHIFT    4

/* CLKGEN :: PLL_CPU_CORE_RDB_MACRO_CTRL :: PLL_CPU_CORE_OPTIONS_DISABLE_RDB_MACRO [03:03] */
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_PLL_CPU_CORE_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_PLL_CPU_CORE_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_PLL_CPU_CORE_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_CORE_RDB_MACRO_CTRL :: OPTIONS [02:00] */
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_OPTIONS_MASK       0x00000007
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_OPTIONS_SHIFT      0
#define BCHP_CLKGEN_PLL_CPU_CORE_RDB_MACRO_CTRL_OPTIONS_DEFAULT    0x00000000

/***************************************************************************
 *PLL_CPU_ROUTER_PLL_RESET_STATUS - PLL_CPU_ROUTER Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS_reserved0_SHIFT 2

/* CLKGEN :: PLL_CPU_ROUTER_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_CPU_ROUTER_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_CPU_ROUTER_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_CPU_ROUTER_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_CPU_ROUTER_RDB_MACRO_CTRL :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_reserved0_MASK   0xfffffff0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_reserved0_SHIFT  4

/* CLKGEN :: PLL_CPU_ROUTER_RDB_MACRO_CTRL :: PLL_CPU_ROUTER_OPTIONS_DISABLE_RDB_MACRO [03:03] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_PLL_CPU_ROUTER_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_PLL_CPU_ROUTER_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_PLL_CPU_ROUTER_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_CPU_ROUTER_RDB_MACRO_CTRL :: OPTIONS [02:00] */
#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_OPTIONS_MASK     0x00000007
#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_OPTIONS_SHIFT    0
#define BCHP_CLKGEN_PLL_CPU_ROUTER_RDB_MACRO_CTRL_OPTIONS_DEFAULT  0x00000000

/***************************************************************************
 *PLL_LC_PLL_RESET_STATUS - PLL_LC Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_LC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_LC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_LC_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_LC_RDB_MACRO_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_reserved0_MASK           0xfffffffc
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_reserved0_SHIFT          2

/* CLKGEN :: PLL_LC_RDB_MACRO_CTRL :: PLL_LC_CHANNEL0_FREQ_DISABLE_RDB_MACRO [01:01] */
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_PLL_LC_CHANNEL0_FREQ_DISABLE_RDB_MACRO_MASK 0x00000002
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_PLL_LC_CHANNEL0_FREQ_DISABLE_RDB_MACRO_SHIFT 1
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_PLL_LC_CHANNEL0_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_LC_RDB_MACRO_CTRL :: CHANNEL0_FREQ [00:00] */
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_CHANNEL0_FREQ_MASK       0x00000001
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_CHANNEL0_FREQ_SHIFT      0
#define BCHP_CLKGEN_PLL_LC_RDB_MACRO_CTRL_CHANNEL0_FREQ_DEFAULT    0x00000000

/***************************************************************************
 *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_MOCA_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: reserved0 [31:08] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_MASK         0xffffff00
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_SHIFT        8

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_CHANNEL3_FREQ_DISABLE_RDB_MACRO [07:07] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL3_FREQ_DISABLE_RDB_MACRO_MASK 0x00000080
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL3_FREQ_DISABLE_RDB_MACRO_SHIFT 7
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL3_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_CHANNEL1_FREQ_DISABLE_RDB_MACRO [06:06] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL1_FREQ_DISABLE_RDB_MACRO_MASK 0x00000040
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL1_FREQ_DISABLE_RDB_MACRO_SHIFT 6
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL1_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_CHANNEL0_FREQ_DISABLE_RDB_MACRO [05:05] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL0_FREQ_DISABLE_RDB_MACRO_MASK 0x00000020
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL0_FREQ_DISABLE_RDB_MACRO_SHIFT 5
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_CHANNEL0_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: CHANNEL3_FREQ [04:04] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL3_FREQ_MASK     0x00000010
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL3_FREQ_SHIFT    4
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL3_FREQ_DEFAULT  0x00000000

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: CHANNEL1_FREQ [03:02] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL1_FREQ_MASK     0x0000000c
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL1_FREQ_SHIFT    2
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL1_FREQ_DEFAULT  0x00000000

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: CHANNEL0_FREQ [01:00] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL0_FREQ_MASK     0x00000003
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL0_FREQ_SHIFT    0
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_CHANNEL0_FREQ_DEFAULT  0x00000000

/***************************************************************************
 *PLL_RAAGA_PLL_RESET_STATUS - PLL_RAAGA Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_RAAGA_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_MASK        0xfffffff0
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_SHIFT       4

/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO [03:03] */
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: OPTIONS [02:00] */
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_MASK          0x00000007
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_SHIFT         0
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_DEFAULT       0x00000000

/***************************************************************************
 *PLL_SC0_PLL_RESET_STATUS - PLL_SC0 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_SC0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_SC0_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: reserved0 [31:05] */
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_MASK          0xffffffe0
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_reserved0_SHIFT         5

/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: PLL_SC0_OPTIONS_DISABLE_RDB_MACRO [04:04] */
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_PLL_SC0_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC0_RDB_MACRO_CTRL :: OPTIONS [03:00] */
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_MASK            0x0000000f
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
#define BCHP_CLKGEN_PLL_SC0_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000

/***************************************************************************
 *PLL_SC1_PLL_RESET_STATUS - PLL_SC1 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_SC1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_SC1_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: reserved0 [31:05] */
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_MASK          0xffffffe0
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_reserved0_SHIFT         5

/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: PLL_SC1_OPTIONS_DISABLE_RDB_MACRO [04:04] */
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_PLL_SC1_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_SC1_RDB_MACRO_CTRL :: OPTIONS [03:00] */
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_MASK            0x0000000f
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
#define BCHP_CLKGEN_PLL_SC1_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0x00000000

/***************************************************************************
 *PLL_STRAP_OVERRIDE - Disable
 ***************************************************************************/
/* CLKGEN :: PLL_STRAP_OVERRIDE :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_SHIFT             2

/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_HIFSPI_DISABLE [01:01] */
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_MASK   0x00000002
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_SHIFT  1
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_HIFSPI_DISABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLMIPS_DISABLE [00:00] */
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SWITCH_PLL_RESET_STATUS - PLL_SWITCH Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_SWITCH_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_reserved0_SHIFT    2

/* CLKGEN :: PLL_SWITCH_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_SWITCH_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SWITCH_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_SYS0_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_reserved0_MASK         0xfffffff8
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_reserved0_SHIFT        3

/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: PLL_SYS0_CHANNEL1_FREQ_DISABLE_RDB_MACRO [02:02] */
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_CHANNEL1_FREQ_DISABLE_RDB_MACRO_MASK 0x00000004
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_CHANNEL1_FREQ_DISABLE_RDB_MACRO_SHIFT 2
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_CHANNEL1_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: CHANNEL1_FREQ [01:00] */
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL1_FREQ_MASK     0x00000003
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL1_FREQ_SHIFT    0
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_CHANNEL1_FREQ_DEFAULT  0x00000000

/***************************************************************************
 *PLL_VCXO0_PLL_RESET_STATUS - PLL_VCXO0 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_VCXO1_PLL_RESET_STATUS - PLL_VCXO1 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_VCXO2_PLL_RESET_STATUS - PLL_VCXO2 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_XPT_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: reserved0 [31:05] */
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_reserved0_MASK          0xffffffe0
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_reserved0_SHIFT         5

/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: PLL_XPT_CHANNEL1_FREQ_DISABLE_RDB_MACRO [04:04] */
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL1_FREQ_DISABLE_RDB_MACRO_MASK 0x00000010
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL1_FREQ_DISABLE_RDB_MACRO_SHIFT 4
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL1_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: PLL_XPT_CHANNEL0_FREQ_DISABLE_RDB_MACRO [03:03] */
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL0_FREQ_DISABLE_RDB_MACRO_MASK 0x00000008
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL0_FREQ_DISABLE_RDB_MACRO_SHIFT 3
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_PLL_XPT_CHANNEL0_FREQ_DISABLE_RDB_MACRO_DEFAULT 0x00000000

/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: CHANNEL1_FREQ [02:02] */
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL1_FREQ_MASK      0x00000004
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL1_FREQ_SHIFT     2
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL1_FREQ_DEFAULT   0x00000000

/* CLKGEN :: PLL_XPT_RDB_MACRO_CTRL :: CHANNEL0_FREQ [01:00] */
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL0_FREQ_MASK      0x00000003
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL0_FREQ_SHIFT     0
#define BCHP_CLKGEN_PLL_XPT_RDB_MACRO_CTRL_CHANNEL0_FREQ_DEFAULT   0x00000000

/***************************************************************************
 *PM_CLOCK_Async_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
 ***************************************************************************/
/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_reserved0_SHIFT       1

/* CLKGEN :: PM_CLOCK_Async_ALIVE_SEL :: CLOCK_Async_CG_XPT [00:00] */
#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_MASK 0x00000001
#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_SHIFT 0
#define BCHP_CLKGEN_PM_CLOCK_Async_ALIVE_SEL_CLOCK_Async_CG_XPT_DEFAULT 0x00000000

/***************************************************************************
 *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
 ***************************************************************************/
/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:07] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xffffff80
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               7

/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys1_PLL [06:06] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_MASK              0x00000040
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_SHIFT             6
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys1_PLL_DEFAULT           0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys0_PLL [05:05] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_MASK              0x00000020
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_SHIFT             5
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys0_PLL_DEFAULT           0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_XPT [04:04] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_MASK                  0x00000010
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_SHIFT                 4
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_XPT_DEFAULT               0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [03:03] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000008
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                3
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_CPU_CORE [02:02] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_CORE_MASK             0x00000004
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_CORE_SHIFT            2
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_CPU_CORE_DEFAULT          0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: DOCSIS_PLL_SYS1 [01:01] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS1_MASK          0x00000002
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS1_SHIFT         1
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS1_DEFAULT       0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: DOCSIS_PLL_SYS0 [00:00] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS0_MASK          0x00000001
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS0_SHIFT         0
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DOCSIS_PLL_SYS0_DEFAULT       0x00000000

/***************************************************************************
 *PM_PLL_LDO_POWERUP - Power management LDO PLL
 ***************************************************************************/
/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:15] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xffff8000
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             15

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO2 [14:14] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO2_MASK    0x00004000
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO2_SHIFT   14
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO2_DEFAULT 0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO1 [13:13] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_MASK    0x00002000
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_SHIFT   13
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO1_DEFAULT 0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_VCXO0 [12:12] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_MASK    0x00001000
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_SHIFT   12
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_VCXO0_DEFAULT 0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SWITCH [11:11] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SWITCH_MASK   0x00000800
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SWITCH_SHIFT  11
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SWITCH_DEFAULT 0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SC1 [10:10] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_MASK      0x00000400
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_SHIFT     10
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC1_DEFAULT   0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SC0 [09:09] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_MASK      0x00000200
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_SHIFT     9
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SC0_DEFAULT   0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [08:08] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK    0x00000100
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT   8
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [07:07] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK     0x00000080
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT    7
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT  0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_LC [06:06] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_MASK       0x00000040
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_SHIFT      6
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_LC_DEFAULT    0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_CPU_ROUTER [05:05] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_CPU_ROUTER_MASK 0x00000020
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_CPU_ROUTER_SHIFT 5
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_CPU_ROUTER_DEFAULT 0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [04:04] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK      0x00000010
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT     4
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT   0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AUDIO2 [03:03] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO2_MASK   0x00000008
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO2_SHIFT  3
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO2_DEFAULT 0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AUDIO1 [02:02] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO1_MASK   0x00000004
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO1_SHIFT  2
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO1_DEFAULT 0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AUDIO0 [01:01] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO0_MASK   0x00000002
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO0_SHIFT  1
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AUDIO0_DEFAULT 0x00000001

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_DOCSIS_PLL_SYS2 [00:00] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_DOCSIS_PLL_SYS2_MASK 0x00000001
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_DOCSIS_PLL_SYS2_SHIFT 0
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_DOCSIS_PLL_SYS2_DEFAULT 0x00000001

/***************************************************************************
 *PROD_OTP_INST_CLOCK_DISABLE - Disable PROD_OTP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_reserved0_SHIFT    2

/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_JTAGOTP_CLOCK [01:01] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_JTAGOTP_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE :: DISABLE_POTP_ALWAYSON_CLOCK [00:00] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_DISABLE_POTP_ALWAYSON_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *PROD_OTP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_JTAGOTP_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_JTAGOTP_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: PROD_OTP_INST_CLOCK_DISABLE_STATUS :: DISABLE_POTP_ALWAYSON_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_DISABLE_STATUS_DISABLE_POTP_ALWAYSON_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *PROD_OTP_INST_CLOCK_ENABLE - Prod otp inst clock enable
 ***************************************************************************/
/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_reserved0_SHIFT     2

/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE :: POTP_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_POTP_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *PROD_OTP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: PROD_OTP_INST_CLOCK_ENABLE_STATUS :: POTP_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PROD_OTP_INST_CLOCK_ENABLE_STATUS_POTP_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE - Raaga dsp top 0 inst clock enable
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_reserved0_SHIFT 5

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_SCB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_GISB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_GISB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_GISB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_DSP_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_DSP_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE :: RAAGA0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_RAAGA0_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_SCB_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_SCB_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_GISB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_GISB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_DSP_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_DSP_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS :: RAAGA0_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_CLOCK_ENABLE_STATUS_RAAGA0_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK - Raaga dsp top 0 inst observe clock
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 2

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA0_ENABLE_OBSERVE_CLOCK [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_SHIFT 1
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK :: RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_0_INST_OBSERVE_CLOCK_RAAGA0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE - Raaga dsp top 1 inst clock enable
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_reserved0_SHIFT 5

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_SCB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_GISB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_GISB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_GISB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_DSP_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_DSP_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE :: RAAGA1_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_RAAGA1_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 5

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_SCB_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_SCB_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_GISB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_GISB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_DSP_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_DSP_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_DSP_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS :: RAAGA1_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_CLOCK_ENABLE_STATUS_RAAGA1_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK - Raaga dsp top 1 inst observe clock
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 2

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: RAAGA1_ENABLE_OBSERVE_CLOCK [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_SHIFT 1
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK :: RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_1_INST_OBSERVE_CLOCK_RAAGA1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *RFM_TOP_INST_CLOCK_ENABLE - Rfm top inst clock enable
 ***************************************************************************/
/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3

/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *RFM_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: RFM_TOP_INST_CLOCK_ENABLE_STATUS :: RFM_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_RFM_TOP_INST_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *RFM_TOP_INST_OBSERVE_CLOCK - Rfm top inst observe clock
 ***************************************************************************/
/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT     6

/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: RFM_TOP_INST_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_RFM_TOP_INST_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SATA3_TOP_INST_CLOCK_DISABLE - Disable SATA3_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT   1

/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SATA3_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: SATA3_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_SATA3_AT_SPEED_SCAN_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *SATA3_TOP_INST_CLOCK_ENABLE - Sata3 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffff8
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT    3

/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *SATA3_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE_STATUS :: SATA3_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_STATUS_SATA3_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *SATA3_TOP_INST_CLOCK_SELECT - Sata3 top inst clock select
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: reserved0 [31:03] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_MASK     0xfffffff8
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_SHIFT    3

/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [02:00] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000007
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 0x00000000

/***************************************************************************
 *SATA3_TOP_INST_OBSERVE_CLOCK - Sata3 top inst observe clock
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT   6

/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SECTOP_INST_CLOCK_ENABLE - Sectop inst clock enable
 ***************************************************************************/
/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_reserved0_SHIFT       2

/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SECTOP_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE :: SECTOP_27_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_27_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_27_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_SECTOP_27_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *SECTOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_STATUS :: SECTOP_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SECTOP_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SECTOP_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_STATUS :: SECTOP_27_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SECTOP_27_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_STATUS_SECTOP_27_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
 ***************************************************************************/
/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6

/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
 ***************************************************************************/
/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:02] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           2

/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [01:01] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x00000002
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           1
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0x00000000

/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [00:00] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x00000001
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           0
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0x00000000

/***************************************************************************
 *SPARE - Spares
 ***************************************************************************/
/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0x00000000

/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0x00000000

/***************************************************************************
 *SWITCH_TOP_INST_CLOCK_DISABLE - Disable SWITCH_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_reserved0_MASK   0xfffffff8
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT  3

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: DISABLE_EGPHY_25_CLOCK [02:02] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_25_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_25_CLOCK_SHIFT 2
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_25_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: DISABLE_EGPHY_200_CLOCK [01:01] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_200_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_200_CLOCK_SHIFT 1
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_200_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE :: DISABLE_EGPHY_125_CLOCK [00:00] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_125_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_125_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_DISABLE_EGPHY_125_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SWITCH_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_EGPHY_25_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_25_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_25_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_EGPHY_200_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_200_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_200_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_EGPHY_125_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_125_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_EGPHY_125_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *SWITCH_TOP_INST_CLOCK_ENABLE - Switch top inst clock enable
 ***************************************************************************/
/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: reserved0 [31:06] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_reserved0_MASK    0xffffffc0
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT   6

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SWCH_SYS_CLOCK_ENABLE [05:05] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_SYS_CLOCK_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_SYS_CLOCK_ENABLE_SHIFT 5
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_SYS_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SWCH_SCB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_SCB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_SCB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SWCH_RGMII_250_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_RGMII_250_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_RGMII_250_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_RGMII_250_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SWCH_54_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_54_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_54_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SWCH_250_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_250_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_250_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_250_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE :: SWCH_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_SWCH_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *SWITCH_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SWCH_SYS_CLOCK_ENABLE_STATUS [05:05] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_SYS_CLOCK_ENABLE_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_SYS_CLOCK_ENABLE_STATUS_SHIFT 5

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SWCH_SCB_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_SCB_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SWCH_RGMII_250_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_RGMII_250_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_RGMII_250_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SWCH_54_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_54_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SWCH_250_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_250_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_250_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: SWITCH_TOP_INST_CLOCK_ENABLE_STATUS :: SWCH_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SWITCH_TOP_INST_CLOCK_ENABLE_STATUS_SWCH_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *SWITCH_TOP_INST_OBSERVE_CLOCK - Switch top inst observe clock
 ***************************************************************************/
/* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_reserved0_MASK   0xffffffc0
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT  6

/* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: SWCH_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: SWCH_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SWITCH_TOP_INST_OBSERVE_CLOCK :: SWCH_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SWITCH_TOP_INST_OBSERVE_CLOCK_SWCH_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff8
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT    3

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [02:02] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 2
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SYS_CTRL_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC1_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC1_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *TESTPORT - Special Testport Controls
 ***************************************************************************/
/* CLKGEN :: TESTPORT :: reserved0 [31:05] */
#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xffffffe0
#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       5

/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [04:00] */
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x0000001f
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0x00000000

/***************************************************************************
 *UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE - Disable UBUS_MOD_PERIPH_FPM_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: reserved0 [31:06] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_reserved0_SHIFT 6

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_SYSTEM_27_CLOCK [05:05] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_SYSTEM_27_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_SYSTEM_27_CLOCK_SHIFT 5
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_SYSTEM_27_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_XTAL_CLOCK [04:04] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_XTAL_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_XTAL_CLOCK_SHIFT 4
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_XTAL_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_SPIM_100_CLOCK [03:03] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_SPIM_100_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_SPIM_100_CLOCK_SHIFT 3
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_SPIM_100_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_HSPI_CLOCK [02:02] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_HSPI_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_HSPI_CLOCK_SHIFT 2
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_HSPI_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_PER_DEV_216_CLOCK [01:01] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_DEV_216_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_DEV_216_CLOCK_SHIFT 1
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_PER_DEV_216_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE :: DISABLE_FPM_DEV_216_CLOCK [00:00] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_FPM_DEV_216_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_FPM_DEV_216_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_DISABLE_FPM_DEV_216_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:06] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 6

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_SYSTEM_27_CLOCK_STATUS [05:05] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_27_CLOCK_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_SYSTEM_27_CLOCK_STATUS_SHIFT 5

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_XTAL_CLOCK_STATUS [04:04] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_XTAL_CLOCK_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_XTAL_CLOCK_STATUS_SHIFT 4

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_SPIM_100_CLOCK_STATUS [03:03] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_SPIM_100_CLOCK_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_SPIM_100_CLOCK_STATUS_SHIFT 3

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_HSPI_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_HSPI_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_HSPI_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_PER_DEV_216_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_DEV_216_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_PER_DEV_216_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS :: DISABLE_FPM_DEV_216_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_FPM_DEV_216_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_DISABLE_STATUS_DISABLE_FPM_DEV_216_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE - Ubus mod periph fpm inst clock enable
 ***************************************************************************/
/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_reserved0_SHIFT 3

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE :: PER_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE :: PER_GISB_2ND_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_GISB_2ND_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_GISB_2ND_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_GISB_2ND_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE :: PER_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_PER_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS :: PER_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS :: PER_GISB_2ND_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_GISB_2ND_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_GISB_2ND_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS :: PER_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UBUS_MOD_PERIPH_FPM_INST_CLOCK_ENABLE_STATUS_PER_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_ROUTER_1_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE - Unimac mbdma top router 1 inst clock enable
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE :: UNIMAC_H2_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE :: UNIMAC_H2_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_UNIMAC_H2_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H2_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_UNIMAC_H2_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_UNIMAC_H2_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H2_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_UNIMAC_H2_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_1_INST_CLOCK_ENABLE_STATUS_UNIMAC_H2_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_ROUTER_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE - Unimac mbdma top router inst clock enable
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE :: UNIMAC_H1_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE :: UNIMAC_H1_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_UNIMAC_H1_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H1_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_UNIMAC_H1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_UNIMAC_H1_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H1_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_UNIMAC_H1_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_ROUTER_INST_CLOCK_ENABLE_STATUS_UNIMAC_H1_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_STB_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE - Unimac mbdma top stb inst clock enable
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE :: UNIMAC_H_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE :: UNIMAC_H_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_UNIMAC_H_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_UNIMAC_H_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_UNIMAC_H_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS :: UNIMAC_H_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_UNIMAC_H_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_STB_INST_CLOCK_ENABLE_STATUS_UNIMAC_H_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE - Disable UNIMAC_MBDMA_TOP_WAN_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_250_CLOCK [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_250_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE :: DISABLE_UNIMAC_108_CLOCK [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_DISABLE_UNIMAC_108_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_250_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_250_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS :: DISABLE_UNIMAC_108_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_DISABLE_STATUS_DISABLE_UNIMAC_108_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE - Unimac mbdma top wan inst clock enable
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE :: UNIMAC_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE :: UNIMAC_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_UNIMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS :: UNIMAC_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS :: UNIMAC_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UNIMAC_MBDMA_TOP_WAN_INST_CLOCK_ENABLE_STATUS_UNIMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *USB0_TOP_INST_CLOCK_DISABLE - Disable USB0_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    2

/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: DISABLE_USB0_FREERUN_CLOCK [01:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_SHIFT 1
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_FREERUN_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE :: DISABLE_USB0_54_MDIO_CLOCK [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *USB0_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_FREERUN_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_FREERUN_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: USB0_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USB0_54_MDIO_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_54_MDIO_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USB0_54_MDIO_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *USB0_TOP_INST_CLOCK_ENABLE - Usb0 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     3

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_GISB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE :: USB0_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_USB0_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *USB0_TOP_INST_CLOCK_ENABLE_AHB - Usb0 top inst clock enable ahb
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_reserved0_SHIFT 1

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB :: USB0_108_CLOCK_ENABLE_AHB [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_SHIFT 0
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_USB0_108_CLOCK_ENABLE_AHB_DEFAULT 0x00000001

/***************************************************************************
 *USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_reserved0_SHIFT 1

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS :: USB0_108_CLOCK_ENABLE_AHB_STATUS [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AHB_STATUS_USB0_108_CLOCK_ENABLE_AHB_STATUS_SHIFT 0

/***************************************************************************
 *USB0_TOP_INST_CLOCK_ENABLE_AXI - Usb0 top inst clock enable axi
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_reserved0_SHIFT 1

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI :: USB0_108_CLOCK_ENABLE_AXI [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_SHIFT 0
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_USB0_108_CLOCK_ENABLE_AXI_DEFAULT 0x00000001

/***************************************************************************
 *USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_reserved0_SHIFT 1

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS :: USB0_108_CLOCK_ENABLE_AXI_STATUS [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_AXI_STATUS_USB0_108_CLOCK_ENABLE_AXI_STATUS_SHIFT 0

/***************************************************************************
 *USB0_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_GISB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_GISB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: USB0_TOP_INST_CLOCK_ENABLE_STATUS :: USB0_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USB0_TOP_INST_CLOCK_ENABLE_STATUS_USB0_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *USB0_TOP_INST_OBSERVE_CLOCK - Usb0 top inst observe clock
 ***************************************************************************/
/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: USB0_TOP_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB0_TOP_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE - Disable USMAC_TC8X_DAVIC_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 3

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE :: DISABLE_USMAC_TX_CLOCK [02:02] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_TX_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_TX_CLOCK_SHIFT 2
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_TX_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE :: DISABLE_USMAC_RX_CLOCK [01:01] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_RX_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_RX_CLOCK_SHIFT 1
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_RX_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE :: DISABLE_USMAC_216_CLOCK [00:00] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_216_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_216_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_DISABLE_USMAC_216_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USMAC_TX_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_TX_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_TX_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USMAC_RX_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_RX_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_RX_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_USMAC_216_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_216_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_USMAC_216_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE - Usmac tc8x davic top inst clock enable
 ***************************************************************************/
/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE :: USMAC_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_USMAC_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_USMAC_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_USMAC_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS :: USMAC_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_USMAC_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USMAC_TC8X_DAVIC_TOP_INST_CLOCK_ENABLE_STATUS_USMAC_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *US_TOP_INST_CLOCK_ENABLE - Us top inst clock enable
 ***************************************************************************/
/* CLKGEN :: US_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT       1

/* CLKGEN :: US_TOP_INST_CLOCK_ENABLE :: US_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_US_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_US_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_US_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *US_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: US_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: US_TOP_INST_CLOCK_ENABLE_STATUS :: US_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_US_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_US_TOP_INST_CLOCK_ENABLE_STATUS_US_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE - Disable UTP_CRYPTO_SEGDMA_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 4

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_USM_54_CLOCK [03:03] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_USM_54_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_USM_54_CLOCK_SHIFT 3
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_USM_54_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_278_CLOCK [02:02] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_278_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_278_CLOCK_SHIFT 2
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_278_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_UTP_25_CLOCK [01:01] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_25_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_25_CLOCK_SHIFT 1
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_UTP_25_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE :: DISABLE_CG_TCK_SCAN_CLOCK [00:00] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_DISABLE_CG_TCK_SCAN_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_USM_54_CLOCK_STATUS [03:03] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_USM_54_CLOCK_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_USM_54_CLOCK_STATUS_SHIFT 3

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_278_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_278_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_278_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_UTP_25_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_25_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_UTP_25_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_CG_TCK_SCAN_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_CG_TCK_SCAN_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE - Utp crypto segdma top inst clock enable
 ***************************************************************************/
/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE :: UTP_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_UTP_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_UTP_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_UTP_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS :: UTP_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_UTP_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_UTP_CRYPTO_SEGDMA_TOP_INST_CLOCK_ENABLE_STATUS_UTP_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *V3D_TOP_INST_CLOCK_ENABLE - V3d top inst clock enable
 ***************************************************************************/
/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff0
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      4

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_54_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_54_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *V3D_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 4

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_SCB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_SCB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_GISB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_GISB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE_STATUS :: V3D_54_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_54_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_STATUS_V3D_54_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xffffffe0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 5

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_0_CLOCK [04:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_SHIFT 4
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [03:03] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 3
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK [02:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_SHIFT 2
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_reserved0_SHIFT 5

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_ITU656_0_CLOCK_STATUS [04:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_ITU656_0_CLOCK_STATUS_SHIFT 4

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [03:03] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 3

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_DIV8_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_DIV2_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS :: DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_STATUS_DISABLE_AUDIO_DAC_DSM_DEM_27_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:09] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffe00
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  9

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_SCB_CLOCK_ENABLE [08:08] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_MASK 0x00000100
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_SHIFT 8
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_QDAC_BVB_CLOCK_ENABLE [07:07] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_BVB_CLOCK_ENABLE_MASK 0x00000080
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_BVB_CLOCK_ENABLE_SHIFT 7
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_BVB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_BVB_CLOCK_ENABLE [06:06] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_BVB_CLOCK_ENABLE_MASK 0x00000040
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_BVB_CLOCK_ENABLE_SHIFT 6
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_BVB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_54_CLOCK_ENABLE [05:05] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_SHIFT 5
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_324_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_324_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_324_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_324_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_108_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_108_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: AIO_ALTERNATE_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: AIO_ALTERNATE_108_3_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_108_3_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_108_3_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_108_3_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: AIO_ALTERNATE_108_2_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_108_2_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_108_2_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_ALTERNATE_108_2_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:09] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffe00
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 9

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_SCB_CLOCK_ENABLE_STATUS [08:08] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000100
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_SCB_CLOCK_ENABLE_STATUS_SHIFT 8

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_QDAC_BVB_CLOCK_ENABLE_STATUS [07:07] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_QDAC_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000080
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_QDAC_BVB_CLOCK_ENABLE_STATUS_SHIFT 7

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_BVB_CLOCK_ENABLE_STATUS [06:06] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000040
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_BVB_CLOCK_ENABLE_STATUS_SHIFT 6

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_AIO_54_CLOCK_ENABLE_STATUS [05:05] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_AIO_54_CLOCK_ENABLE_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_AIO_54_CLOCK_ENABLE_STATUS_SHIFT 5

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_324_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_324_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_324_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: VEC_108_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_108_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_VEC_108_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_AIO_ALTERNATE_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: AIO_ALTERNATE_108_3_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_AIO_ALTERNATE_108_3_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_AIO_ALTERNATE_108_3_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS :: AIO_ALTERNATE_108_2_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_AIO_ALTERNATE_108_2_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_STATUS_AIO_ALTERNATE_108_2_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF - Vec aio top inst clock enable vec qdac intf
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF :: VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF_DEFAULT 0x00000001

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS :: VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_VEC_ALTERNATE_BVB_CLOCK_ENABLE_VEC_QDAC_INTF_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xfffff000
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 12

/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_ENABLE_OBSERVE_CLOCK [11:11] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_SHIFT 11
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_CONTROL_OBSERVE_CLOCK [09:06] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_SHIFT 6
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *VICE2_0_INST_CLOCK_ENABLE - Vice2 0 inst clock enable
 ***************************************************************************/
/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: reserved0 [31:06] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_reserved0_SHIFT      6

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_SCB_CLOCK_ENABLE [05:05] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_SHIFT 5
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_GISB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_CORE_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_BVB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_BVB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_BVB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_BVB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE :: VICE2_0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_VICE2_0_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *VICE2_0_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_SCB_CLOCK_ENABLE_STATUS [05:05] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_SCB_CLOCK_ENABLE_STATUS_SHIFT 5

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_GISB_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_GISB_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_CORE_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_CORE_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_BVB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_BVB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: VICE2_0_INST_CLOCK_ENABLE_STATUS :: VICE2_0_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VICE2_0_INST_CLOCK_ENABLE_STATUS_VICE2_0_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *VICE2_1_INST_CLOCK_ENABLE - Vice2 1 inst clock enable
 ***************************************************************************/
/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: reserved0 [31:06] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_reserved0_SHIFT      6

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_SCB_CLOCK_ENABLE [05:05] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_SCB_CLOCK_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_SCB_CLOCK_ENABLE_SHIFT 5
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_GISB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_GISB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_CORE_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_CORE_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_CORE_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_CORE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_BVB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_BVB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_BVB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_BVB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_54_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_54_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_54_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE :: VICE2_1_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_VICE2_1_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *VICE2_1_INST_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: reserved0 [31:06] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_reserved0_SHIFT 6

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_SCB_CLOCK_ENABLE_STATUS [05:05] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000020
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_SCB_CLOCK_ENABLE_STATUS_SHIFT 5

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_GISB_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_GISB_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_GISB_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_CORE_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_CORE_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_BVB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_BVB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_BVB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_54_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_54_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_54_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: VICE2_1_INST_CLOCK_ENABLE_STATUS :: VICE2_1_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VICE2_1_INST_CLOCK_ENABLE_STATUS_VICE2_1_108_CLOCK_ENABLE_STATUS_SHIFT 0

#endif /* #ifndef BCHP_CLKGEN_H__ */

/* End of File */