/***************************************************************************
 *     Copyright (c) 1999-2014, Broadcom Corporation
 *     All Rights Reserved
 *     Confidential Property of Broadcom Corporation
 *
 *
 * THIS SOFTWARE MAY ONLY BE USED SUBJECT TO AN EXECUTED SOFTWARE LICENSE
 * AGREEMENT  BETWEEN THE USER AND BROADCOM.  YOU HAVE NO RIGHT TO USE OR
 * EXPLOIT THIS MATERIAL EXCEPT SUBJECT TO THE TERMS OF SUCH AN AGREEMENT.
 *
 * $brcm_Workfile: $
 * $brcm_Revision: $
 * $brcm_Date: $
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on              Tue Dec  2 03:18:41 2014
 *                 Full Compile MD5 Checksum 3461841ff250f7118305e1f1650424cf
 *                   (minus title and desc)  
 *                 MD5 Checksum              92044aba65695bbffdeefc8d096b8587
 *
 * Compiled with:  RDB Utility               combo_header.pl
 *                 RDB Parser                3.0
 *                 unknown                   unknown
 *                 Perl Interpreter          5.008008
 *                 Operating System          linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_HIF_SPI_INTR2_H__
#define BCHP_HIF_SPI_INTR2_H__

/***************************************************************************
 *HIF_SPI_INTR2 - HIF Level 2 Interrupt Controller Registers for SPI
 ***************************************************************************/
#define BCHP_HIF_SPI_INTR2_CPU_STATUS            0x00441a00 /* CPU interrupt Status Register */
#define BCHP_HIF_SPI_INTR2_CPU_SET               0x00441a04 /* CPU interrupt Set Register */
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR             0x00441a08 /* CPU interrupt Clear Register */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS       0x00441a0c /* CPU interrupt Mask Status Register */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET          0x00441a10 /* CPU interrupt Mask Set Register */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR        0x00441a14 /* CPU interrupt Mask Clear Register */
#define BCHP_HIF_SPI_INTR2_PCI_STATUS            0x00441a18 /* PCI interrupt Status Register */
#define BCHP_HIF_SPI_INTR2_PCI_SET               0x00441a1c /* PCI interrupt Set Register */
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR             0x00441a20 /* PCI interrupt Clear Register */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS       0x00441a24 /* PCI interrupt Mask Status Register */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET          0x00441a28 /* PCI interrupt Mask Set Register */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR        0x00441a2c /* PCI interrupt Mask Clear Register */

/***************************************************************************
 *CPU_STATUS - CPU interrupt Status Register
 ***************************************************************************/
/* HIF_SPI_INTR2 :: CPU_STATUS :: reserved0 [31:07] */
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_MASK               0xffffff80
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_reserved0_SHIFT              7

/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_HALTED [06:06] */
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_MASK             0x00000040
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_SHIFT            6
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_HALTED_DEFAULT          0x00000000

/* HIF_SPI_INTR2 :: CPU_STATUS :: MSPI_DONE [05:05] */
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_MASK               0x00000020
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_SHIFT              5
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_MSPI_DONE_DEFAULT            0x00000000

/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_OVERREAD [04:04] */
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_SHIFT        4
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000

/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_DONE [03:03] */
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000

/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_IMPATIENT [02:02] */
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_SHIFT       2
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000

/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: CPU_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
#define BCHP_HIF_SPI_INTR2_CPU_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000

/***************************************************************************
 *CPU_SET - CPU interrupt Set Register
 ***************************************************************************/
/* HIF_SPI_INTR2 :: CPU_SET :: reserved0 [31:07] */
#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_MASK                  0xffffff80
#define BCHP_HIF_SPI_INTR2_CPU_SET_reserved0_SHIFT                 7

/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_HALTED [06:06] */
#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_MASK                0x00000040
#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_SHIFT               6
#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_HALTED_DEFAULT             0x00000000

/* HIF_SPI_INTR2 :: CPU_SET :: MSPI_DONE [05:05] */
#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_MASK                  0x00000020
#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_SHIFT                 5
#define BCHP_HIF_SPI_INTR2_CPU_SET_MSPI_DONE_DEFAULT               0x00000000

/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_OVERREAD [04:04] */
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_MASK            0x00000010
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_SHIFT           4
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000

/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_DONE [03:03] */
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_SHIFT       3
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000

/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_IMPATIENT [02:02] */
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_MASK           0x00000004
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_SHIFT          2
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000

/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_SESSION_ABORTED [01:01] */
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000

/* HIF_SPI_INTR2 :: CPU_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
#define BCHP_HIF_SPI_INTR2_CPU_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000

/***************************************************************************
 *CPU_CLEAR - CPU interrupt Clear Register
 ***************************************************************************/
/* HIF_SPI_INTR2 :: CPU_CLEAR :: reserved0 [31:07] */
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_MASK                0xffffff80
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_reserved0_SHIFT               7

/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_HALTED [06:06] */
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_MASK              0x00000040
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_SHIFT             6
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_HALTED_DEFAULT           0x00000000

/* HIF_SPI_INTR2 :: CPU_CLEAR :: MSPI_DONE [05:05] */
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_MASK                0x00000020
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_SHIFT               5
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_MSPI_DONE_DEFAULT             0x00000000

/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_OVERREAD [04:04] */
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_SHIFT         4
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000

/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000

/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_IMPATIENT [02:02] */
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000

/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: CPU_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
#define BCHP_HIF_SPI_INTR2_CPU_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000

/***************************************************************************
 *CPU_MASK_STATUS - CPU interrupt Mask Status Register
 ***************************************************************************/
/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:07] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_MASK          0xffffff80
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_reserved0_SHIFT         7

/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_HALTED [06:06] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_SHIFT       6
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: MSPI_DONE [05:05] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_MASK          0x00000020
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_SHIFT         5
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
#define BCHP_HIF_SPI_INTR2_CPU_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000

/***************************************************************************
 *CPU_MASK_SET - CPU interrupt Mask Set Register
 ***************************************************************************/
/* HIF_SPI_INTR2 :: CPU_MASK_SET :: reserved0 [31:07] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_MASK             0xffffff80
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_reserved0_SHIFT            7

/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_HALTED [06:06] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_MASK           0x00000040
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_SHIFT          6
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_SET :: MSPI_DONE [05:05] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_MASK             0x00000020
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_SHIFT            5
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_MSPI_DONE_DEFAULT          0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_OVERREAD [04:04] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
#define BCHP_HIF_SPI_INTR2_CPU_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000

/***************************************************************************
 *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register
 ***************************************************************************/
/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:07] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_MASK           0xffffff80
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT          7

/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_HALTED [06:06] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_SHIFT        6
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: MSPI_DONE [05:05] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_SHIFT          5
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: CPU_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
#define BCHP_HIF_SPI_INTR2_CPU_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000

/***************************************************************************
 *PCI_STATUS - PCI interrupt Status Register
 ***************************************************************************/
/* HIF_SPI_INTR2 :: PCI_STATUS :: reserved0 [31:07] */
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_MASK               0xffffff80
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_reserved0_SHIFT              7

/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_HALTED [06:06] */
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_MASK             0x00000040
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_SHIFT            6
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_HALTED_DEFAULT          0x00000000

/* HIF_SPI_INTR2 :: PCI_STATUS :: MSPI_DONE [05:05] */
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_MASK               0x00000020
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_SHIFT              5
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_MSPI_DONE_DEFAULT            0x00000000

/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_OVERREAD [04:04] */
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_MASK         0x00000010
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_SHIFT        4
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_OVERREAD_DEFAULT      0x00000000

/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_DONE [03:03] */
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_MASK     0x00000008
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_SHIFT    3
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_DONE_DEFAULT  0x00000000

/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_IMPATIENT [02:02] */
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_MASK        0x00000004
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_SHIFT       2
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_IMPATIENT_DEFAULT     0x00000000

/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_MASK  0x00000002
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: PCI_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
#define BCHP_HIF_SPI_INTR2_PCI_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000

/***************************************************************************
 *PCI_SET - PCI interrupt Set Register
 ***************************************************************************/
/* HIF_SPI_INTR2 :: PCI_SET :: reserved0 [31:07] */
#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_MASK                  0xffffff80
#define BCHP_HIF_SPI_INTR2_PCI_SET_reserved0_SHIFT                 7

/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_HALTED [06:06] */
#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_MASK                0x00000040
#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_SHIFT               6
#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_HALTED_DEFAULT             0x00000000

/* HIF_SPI_INTR2 :: PCI_SET :: MSPI_DONE [05:05] */
#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_MASK                  0x00000020
#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_SHIFT                 5
#define BCHP_HIF_SPI_INTR2_PCI_SET_MSPI_DONE_DEFAULT               0x00000000

/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_OVERREAD [04:04] */
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_MASK            0x00000010
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_SHIFT           4
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_OVERREAD_DEFAULT         0x00000000

/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_DONE [03:03] */
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_MASK        0x00000008
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_SHIFT       3
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_DONE_DEFAULT     0x00000000

/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_IMPATIENT [02:02] */
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_MASK           0x00000004
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_SHIFT          2
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_IMPATIENT_DEFAULT        0x00000000

/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_SESSION_ABORTED [01:01] */
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_MASK     0x00000002
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_SHIFT    1
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_SESSION_ABORTED_DEFAULT  0x00000000

/* HIF_SPI_INTR2 :: PCI_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_MASK    0x00000001
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_SHIFT   0
#define BCHP_HIF_SPI_INTR2_PCI_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000

/***************************************************************************
 *PCI_CLEAR - PCI interrupt Clear Register
 ***************************************************************************/
/* HIF_SPI_INTR2 :: PCI_CLEAR :: reserved0 [31:07] */
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_MASK                0xffffff80
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_reserved0_SHIFT               7

/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_HALTED [06:06] */
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_MASK              0x00000040
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_SHIFT             6
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_HALTED_DEFAULT           0x00000000

/* HIF_SPI_INTR2 :: PCI_CLEAR :: MSPI_DONE [05:05] */
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_MASK                0x00000020
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_SHIFT               5
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_MSPI_DONE_DEFAULT             0x00000000

/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_OVERREAD [04:04] */
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_MASK          0x00000010
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_SHIFT         4
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_OVERREAD_DEFAULT       0x00000000

/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_MASK      0x00000008
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_SHIFT     3
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_DONE_DEFAULT   0x00000000

/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_IMPATIENT [02:02] */
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_MASK         0x00000004
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_SHIFT        2
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_IMPATIENT_DEFAULT      0x00000000

/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_MASK   0x00000002
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT  1
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: PCI_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_MASK  0x00000001
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
#define BCHP_HIF_SPI_INTR2_PCI_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000

/***************************************************************************
 *PCI_MASK_STATUS - PCI interrupt Mask Status Register
 ***************************************************************************/
/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:07] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_MASK          0xffffff80
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_reserved0_SHIFT         7

/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_HALTED [06:06] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_MASK        0x00000040
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_SHIFT       6
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_HALTED_DEFAULT     0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: MSPI_DONE [05:05] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_MASK          0x00000020
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_SHIFT         5
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_MSPI_DONE_DEFAULT       0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_OVERREAD [04:04] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_MASK    0x00000010
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_SHIFT   4
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_OVERREAD_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_DONE [03:03] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_MASK 0x00000008
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_SHIFT 3
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_DONE_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_IMPATIENT [02:02] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_MASK   0x00000004
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_SHIFT  2
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_IMPATIENT_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_SESSION_ABORTED [01:01] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_MASK 0x00000002
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_SHIFT 1
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_STATUS :: SPI_LR_FULLNESS_REACHED [00:00] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_SHIFT 0
#define BCHP_HIF_SPI_INTR2_PCI_MASK_STATUS_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000

/***************************************************************************
 *PCI_MASK_SET - PCI interrupt Mask Set Register
 ***************************************************************************/
/* HIF_SPI_INTR2 :: PCI_MASK_SET :: reserved0 [31:07] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_MASK             0xffffff80
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_reserved0_SHIFT            7

/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_HALTED [06:06] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_MASK           0x00000040
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_SHIFT          6
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_HALTED_DEFAULT        0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_SET :: MSPI_DONE [05:05] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_MASK             0x00000020
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_SHIFT            5
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_MSPI_DONE_DEFAULT          0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_OVERREAD [04:04] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_MASK       0x00000010
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_SHIFT      4
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_OVERREAD_DEFAULT    0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_DONE [03:03] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_MASK   0x00000008
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_SHIFT  3
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_DONE_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_IMPATIENT [02:02] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_MASK      0x00000004
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_SHIFT     2
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_IMPATIENT_DEFAULT   0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_SESSION_ABORTED [01:01] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_MASK 0x00000002
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_SHIFT 1
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_SET :: SPI_LR_FULLNESS_REACHED [00:00] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_SHIFT 0
#define BCHP_HIF_SPI_INTR2_PCI_MASK_SET_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000

/***************************************************************************
 *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register
 ***************************************************************************/
/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:07] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_MASK           0xffffff80
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT          7

/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_HALTED [06:06] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_MASK         0x00000040
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_SHIFT        6
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_HALTED_DEFAULT      0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: MSPI_DONE [05:05] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_MASK           0x00000020
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_SHIFT          5
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_MSPI_DONE_DEFAULT        0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_OVERREAD [04:04] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_MASK     0x00000010
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_SHIFT    4
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_OVERREAD_DEFAULT  0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_DONE [03:03] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_MASK 0x00000008
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_SHIFT 3
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_DONE_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_IMPATIENT [02:02] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_MASK    0x00000004
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_SHIFT   2
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_IMPATIENT_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_SESSION_ABORTED [01:01] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_MASK 0x00000002
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_SHIFT 1
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_SESSION_ABORTED_DEFAULT 0x00000000

/* HIF_SPI_INTR2 :: PCI_MASK_CLEAR :: SPI_LR_FULLNESS_REACHED [00:00] */
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_MASK 0x00000001
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_SHIFT 0
#define BCHP_HIF_SPI_INTR2_PCI_MASK_CLEAR_SPI_LR_FULLNESS_REACHED_DEFAULT 0x00000000

#endif /* #ifndef BCHP_HIF_SPI_INTR2_H__ */

/* End of File */