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/* cx25840 - Conexant CX25840 audio/video decoder driver
*
* Copyright (C) 2004 Ulf Eklund
*
* Based on the saa7115 driver and on the first version of Chris Kennedy's
* cx25840 driver.
*
* Changes by Tyler Trafford <tatrafford@comcast.net>
* - cleanup/rewrite for V4L2 API (2005)
*
* VBI support by Hans Verkuil <hverkuil@xs4all.nl>.
*
* NTSC sliced VBI support by Christopher Neufeld <television@cneufeld.ca>
* with additional fixes by Hans Verkuil <hverkuil@xs4all.nl>.
*
* CX23885 support by Steven Toth <stoth@linuxtv.org>.
*
* CX2388[578] IRQ handling, IO Pin mux configuration and other small fixes are
* Copyright (C) 2010 Andy Walls <awalls@md.metrocast.net>
*
* CX23888 DIF support for the HVR1850
* Copyright (C) 2011 Steven Toth <stoth@kernellabs.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
*/
#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/videodev2.h>
#include <linux/i2c.h>
#include <linux/delay.h>
#include <linux/math64.h>
#include <media/v4l2-common.h>
#include <media/cx25840.h>
#include "cx25840-core.h"
MODULE_DESCRIPTION("Conexant CX25840 audio/video decoder driver");
MODULE_AUTHOR("Ulf Eklund, Chris Kennedy, Hans Verkuil, Tyler Trafford");
MODULE_LICENSE("GPL");
#define CX25840_VID_INT_STAT_REG 0x410
#define CX25840_VID_INT_STAT_BITS 0x0000ffff
#define CX25840_VID_INT_MASK_BITS 0xffff0000
#define CX25840_VID_INT_MASK_SHFT 16
#define CX25840_VID_INT_MASK_REG 0x412
#define CX23885_AUD_MC_INT_MASK_REG 0x80c
#define CX23885_AUD_MC_INT_STAT_BITS 0xffff0000
#define CX23885_AUD_MC_INT_CTRL_BITS 0x0000ffff
#define CX23885_AUD_MC_INT_STAT_SHFT 16
#define CX25840_AUD_INT_CTRL_REG 0x812
#define CX25840_AUD_INT_STAT_REG 0x813
#define CX23885_PIN_CTRL_IRQ_REG 0x123
#define CX23885_PIN_CTRL_IRQ_IR_STAT 0x40
#define CX23885_PIN_CTRL_IRQ_AUD_STAT 0x20
#define CX23885_PIN_CTRL_IRQ_VID_STAT 0x10
#define CX25840_IR_STATS_REG 0x210
#define CX25840_IR_IRQEN_REG 0x214
static int cx25840_debug;
module_param_named(debug,cx25840_debug, int, 0644);
MODULE_PARM_DESC(debug, "Debugging messages [0=Off (default) 1=On]");
/* ----------------------------------------------------------------------- */
static void cx23888_std_setup(struct i2c_client *client);
int cx25840_write(struct i2c_client *client, u16 addr, u8 value)
{
u8 buffer[3];
buffer[0] = addr >> 8;
buffer[1] = addr & 0xff;
buffer[2] = value;
return i2c_master_send(client, buffer, 3);
}
int cx25840_write4(struct i2c_client *client, u16 addr, u32 value)
{
u8 buffer[6];
buffer[0] = addr >> 8;
buffer[1] = addr & 0xff;
buffer[2] = value & 0xff;
buffer[3] = (value >> 8) & 0xff;
buffer[4] = (value >> 16) & 0xff;
buffer[5] = value >> 24;
return i2c_master_send(client, buffer, 6);
}
u8 cx25840_read(struct i2c_client * client, u16 addr)
{
struct i2c_msg msgs[2];
u8 tx_buf[2], rx_buf[1];
/* Write register address */
tx_buf[0] = addr >> 8;
tx_buf[1] = addr & 0xff;
msgs[0].addr = client->addr;
msgs[0].flags = 0;
msgs[0].len = 2;
msgs[0].buf = (char *) tx_buf;
/* Read data from register */
msgs[1].addr = client->addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = 1;
msgs[1].buf = (char *) rx_buf;
if (i2c_transfer(client->adapter, msgs, 2) < 2)
return 0;
return rx_buf[0];
}
u32 cx25840_read4(struct i2c_client * client, u16 addr)
{
struct i2c_msg msgs[2];
u8 tx_buf[2], rx_buf[4];
/* Write register address */
tx_buf[0] = addr >> 8;
tx_buf[1] = addr & 0xff;
msgs[0].addr = client->addr;
msgs[0].flags = 0;
msgs[0].len = 2;
msgs[0].buf = (char *) tx_buf;
/* Read data from registers */
msgs[1].addr = client->addr;
msgs[1].flags = I2C_M_RD;
msgs[1].len = 4;
msgs[1].buf = (char *) rx_buf;
if (i2c_transfer(client->adapter, msgs, 2) < 2)
return 0;
return (rx_buf[3] << 24) | (rx_buf[2] << 16) | (rx_buf[1] << 8) |
rx_buf[0];
}
int cx25840_and_or(struct i2c_client *client, u16 addr, unsigned and_mask,
u8 or_value)
{
return cx25840_write(client, addr,
(cx25840_read(client, addr) & and_mask) |
or_value);
}
int cx25840_and_or4(struct i2c_client *client, u16 addr, u32 and_mask,
u32 or_value)
{
return cx25840_write4(client, addr,
(cx25840_read4(client, addr) & and_mask) |
or_value);
}
/* ----------------------------------------------------------------------- */
static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
enum cx25840_audio_input aud_input);
/* ----------------------------------------------------------------------- */
static int cx23885_s_io_pin_config(struct v4l2_subdev *sd, size_t n,
struct v4l2_subdev_io_pin_config *p)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
int i;
u32 pin_ctrl;
u8 gpio_oe, gpio_data, strength;
pin_ctrl = cx25840_read4(client, 0x120);
gpio_oe = cx25840_read(client, 0x160);
gpio_data = cx25840_read(client, 0x164);
for (i = 0; i < n; i++) {
strength = p[i].strength;
if (strength > CX25840_PIN_DRIVE_FAST)
strength = CX25840_PIN_DRIVE_FAST;
switch (p[i].pin) {
case CX23885_PIN_IRQ_N_GPIO16:
if (p[i].function != CX23885_PAD_IRQ_N) {
/* GPIO16 */
pin_ctrl &= ~(0x1 << 25);
} else {
/* IRQ_N */
if (p[i].flags &
(V4L2_SUBDEV_IO_PIN_DISABLE |
V4L2_SUBDEV_IO_PIN_INPUT)) {
pin_ctrl &= ~(0x1 << 25);
} else {
pin_ctrl |= (0x1 << 25);
}
if (p[i].flags &
V4L2_SUBDEV_IO_PIN_ACTIVE_LOW) {
pin_ctrl &= ~(0x1 << 24);
} else {
pin_ctrl |= (0x1 << 24);
}
}
break;
case CX23885_PIN_IR_RX_GPIO19:
if (p[i].function != CX23885_PAD_GPIO19) {
/* IR_RX */
gpio_oe |= (0x1 << 0);
pin_ctrl &= ~(0x3 << 18);
pin_ctrl |= (strength << 18);
} else {
/* GPIO19 */
gpio_oe &= ~(0x1 << 0);
if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
gpio_data &= ~(0x1 << 0);
gpio_data |= ((p[i].value & 0x1) << 0);
}
pin_ctrl &= ~(0x3 << 12);
pin_ctrl |= (strength << 12);
}
break;
case CX23885_PIN_IR_TX_GPIO20:
if (p[i].function != CX23885_PAD_GPIO20) {
/* IR_TX */
gpio_oe |= (0x1 << 1);
if (p[i].flags & V4L2_SUBDEV_IO_PIN_DISABLE)
pin_ctrl &= ~(0x1 << 10);
else
pin_ctrl |= (0x1 << 10);
pin_ctrl &= ~(0x3 << 18);
pin_ctrl |= (strength << 18);
} else {
/* GPIO20 */
gpio_oe &= ~(0x1 << 1);
if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
gpio_data &= ~(0x1 << 1);
gpio_data |= ((p[i].value & 0x1) << 1);
}
pin_ctrl &= ~(0x3 << 12);
pin_ctrl |= (strength << 12);
}
break;
case CX23885_PIN_I2S_SDAT_GPIO21:
if (p[i].function != CX23885_PAD_GPIO21) {
/* I2S_SDAT */
/* TODO: Input or Output config */
gpio_oe |= (0x1 << 2);
pin_ctrl &= ~(0x3 << 22);
pin_ctrl |= (strength << 22);
} else {
/* GPIO21 */
gpio_oe &= ~(0x1 << 2);
if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
gpio_data &= ~(0x1 << 2);
gpio_data |= ((p[i].value & 0x1) << 2);
}
pin_ctrl &= ~(0x3 << 12);
pin_ctrl |= (strength << 12);
}
break;
case CX23885_PIN_I2S_WCLK_GPIO22:
if (p[i].function != CX23885_PAD_GPIO22) {
/* I2S_WCLK */
/* TODO: Input or Output config */
gpio_oe |= (0x1 << 3);
pin_ctrl &= ~(0x3 << 22);
pin_ctrl |= (strength << 22);
} else {
/* GPIO22 */
gpio_oe &= ~(0x1 << 3);
if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
gpio_data &= ~(0x1 << 3);
gpio_data |= ((p[i].value & 0x1) << 3);
}
pin_ctrl &= ~(0x3 << 12);
pin_ctrl |= (strength << 12);
}
break;
case CX23885_PIN_I2S_BCLK_GPIO23:
if (p[i].function != CX23885_PAD_GPIO23) {
/* I2S_BCLK */
/* TODO: Input or Output config */
gpio_oe |= (0x1 << 4);
pin_ctrl &= ~(0x3 << 22);
pin_ctrl |= (strength << 22);
} else {
/* GPIO23 */
gpio_oe &= ~(0x1 << 4);
if (p[i].flags & V4L2_SUBDEV_IO_PIN_SET_VALUE) {
gpio_data &= ~(0x1 << 4);
gpio_data |= ((p[i].value & 0x1) << 4);
}
pin_ctrl &= ~(0x3 << 12);
pin_ctrl |= (strength << 12);
}
break;
}
}
cx25840_write(client, 0x164, gpio_data);
cx25840_write(client, 0x160, gpio_oe);
cx25840_write4(client, 0x120, pin_ctrl);
return 0;
}
static int common_s_io_pin_config(struct v4l2_subdev *sd, size_t n,
struct v4l2_subdev_io_pin_config *pincfg)
{
struct cx25840_state *state = to_state(sd);
if (is_cx2388x(state))
return cx23885_s_io_pin_config(sd, n, pincfg);
return 0;
}
/* ----------------------------------------------------------------------- */
static void init_dll1(struct i2c_client *client)
{
/* This is the Hauppauge sequence used to
* initialize the Delay Lock Loop 1 (ADC DLL). */
cx25840_write(client, 0x159, 0x23);
cx25840_write(client, 0x15a, 0x87);
cx25840_write(client, 0x15b, 0x06);
udelay(10);
cx25840_write(client, 0x159, 0xe1);
udelay(10);
cx25840_write(client, 0x15a, 0x86);
cx25840_write(client, 0x159, 0xe0);
cx25840_write(client, 0x159, 0xe1);
cx25840_write(client, 0x15b, 0x10);
}
static void init_dll2(struct i2c_client *client)
{
/* This is the Hauppauge sequence used to
* initialize the Delay Lock Loop 2 (ADC DLL). */
cx25840_write(client, 0x15d, 0xe3);
cx25840_write(client, 0x15e, 0x86);
cx25840_write(client, 0x15f, 0x06);
udelay(10);
cx25840_write(client, 0x15d, 0xe1);
cx25840_write(client, 0x15d, 0xe0);
cx25840_write(client, 0x15d, 0xe1);
}
static void cx25836_initialize(struct i2c_client *client)
{
/* reset configuration is described on page 3-77 of the CX25836 datasheet */
/* 2. */
cx25840_and_or(client, 0x000, ~0x01, 0x01);
cx25840_and_or(client, 0x000, ~0x01, 0x00);
/* 3a. */
cx25840_and_or(client, 0x15a, ~0x70, 0x00);
/* 3b. */
cx25840_and_or(client, 0x15b, ~0x1e, 0x06);
/* 3c. */
cx25840_and_or(client, 0x159, ~0x02, 0x02);
/* 3d. */
udelay(10);
/* 3e. */
cx25840_and_or(client, 0x159, ~0x02, 0x00);
/* 3f. */
cx25840_and_or(client, 0x159, ~0xc0, 0xc0);
/* 3g. */
cx25840_and_or(client, 0x159, ~0x01, 0x00);
cx25840_and_or(client, 0x159, ~0x01, 0x01);
/* 3h. */
cx25840_and_or(client, 0x15b, ~0x1e, 0x10);
}
static void cx25840_work_handler(struct work_struct *work)
{
struct cx25840_state *state = container_of(work, struct cx25840_state, fw_work);
cx25840_loadfw(state->c);
wake_up(&state->fw_wait);
}
static void cx25840_initialize(struct i2c_client *client)
{
DEFINE_WAIT(wait);
struct cx25840_state *state = to_state(i2c_get_clientdata(client));
struct workqueue_struct *q;
/* datasheet startup in numbered steps, refer to page 3-77 */
/* 2. */
cx25840_and_or(client, 0x803, ~0x10, 0x00);
/* The default of this register should be 4, but I get 0 instead.
* Set this register to 4 manually. */
cx25840_write(client, 0x000, 0x04);
/* 3. */
init_dll1(client);
init_dll2(client);
cx25840_write(client, 0x136, 0x0a);
/* 4. */
cx25840_write(client, 0x13c, 0x01);
cx25840_write(client, 0x13c, 0x00);
/* 5. */
/* Do the firmware load in a work handler to prevent.
Otherwise the kernel is blocked waiting for the
bit-banging i2c interface to finish uploading the
firmware. */
INIT_WORK(&state->fw_work, cx25840_work_handler);
init_waitqueue_head(&state->fw_wait);
q = create_singlethread_workqueue("cx25840_fw");
prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
queue_work(q, &state->fw_work);
schedule();
finish_wait(&state->fw_wait, &wait);
destroy_workqueue(q);
/* 6. */
cx25840_write(client, 0x115, 0x8c);
cx25840_write(client, 0x116, 0x07);
cx25840_write(client, 0x118, 0x02);
/* 7. */
cx25840_write(client, 0x4a5, 0x80);
cx25840_write(client, 0x4a5, 0x00);
cx25840_write(client, 0x402, 0x00);
/* 8. */
cx25840_and_or(client, 0x401, ~0x18, 0);
cx25840_and_or(client, 0x4a2, ~0x10, 0x10);
/* steps 8c and 8d are done in change_input() */
/* 10. */
cx25840_write(client, 0x8d3, 0x1f);
cx25840_write(client, 0x8e3, 0x03);
cx25840_std_setup(client);
/* trial and error says these are needed to get audio */
cx25840_write(client, 0x914, 0xa0);
cx25840_write(client, 0x918, 0xa0);
cx25840_write(client, 0x919, 0x01);
/* stereo preferred */
cx25840_write(client, 0x809, 0x04);
/* AC97 shift */
cx25840_write(client, 0x8cf, 0x0f);
/* (re)set input */
set_input(client, state->vid_input, state->aud_input);
/* start microcontroller */
cx25840_and_or(client, 0x803, ~0x10, 0x10);
}
static void cx23885_initialize(struct i2c_client *client)
{
DEFINE_WAIT(wait);
struct cx25840_state *state = to_state(i2c_get_clientdata(client));
struct workqueue_struct *q;
/*
* Come out of digital power down
* The CX23888, at least, needs this, otherwise registers aside from
* 0x0-0x2 can't be read or written.
*/
cx25840_write(client, 0x000, 0);
/* Internal Reset */
cx25840_and_or(client, 0x102, ~0x01, 0x01);
cx25840_and_or(client, 0x102, ~0x01, 0x00);
/* Stop microcontroller */
cx25840_and_or(client, 0x803, ~0x10, 0x00);
/* DIF in reset? */
cx25840_write(client, 0x398, 0);
/*
* Trust the default xtal, no division
* '885: 28.636363... MHz
* '887: 25.000000 MHz
* '888: 50.000000 MHz
*/
cx25840_write(client, 0x2, 0x76);
/* Power up all the PLL's and DLL */
cx25840_write(client, 0x1, 0x40);
/* Sys PLL */
switch (state->id) {
case CX23888_AV:
/*
* 50.0 MHz * (0xb + 0xe8ba26/0x2000000)/4 = 5 * 28.636363 MHz
* 572.73 MHz before post divide
*/
/* HVR1850 or 50MHz xtal */
cx25840_write(client, 0x2, 0x71);
cx25840_write4(client, 0x11c, 0x01d1744c);
cx25840_write4(client, 0x118, 0x00000416);
cx25840_write4(client, 0x404, 0x0010253e);
cx25840_write4(client, 0x42c, 0x42600000);
cx25840_write4(client, 0x44c, 0x161f1000);
break;
case CX23887_AV:
/*
* 25.0 MHz * (0x16 + 0x1d1744c/0x2000000)/4 = 5 * 28.636363 MHz
* 572.73 MHz before post divide
*/
cx25840_write4(client, 0x11c, 0x01d1744c);
cx25840_write4(client, 0x118, 0x00000416);
break;
case CX23885_AV:
default:
/*
* 28.636363 MHz * (0x14 + 0x0/0x2000000)/4 = 5 * 28.636363 MHz
* 572.73 MHz before post divide
*/
cx25840_write4(client, 0x11c, 0x00000000);
cx25840_write4(client, 0x118, 0x00000414);
break;
}
/* Disable DIF bypass */
cx25840_write4(client, 0x33c, 0x00000001);
/* DIF Src phase inc */
cx25840_write4(client, 0x340, 0x0df7df83);
/*
* Vid PLL
* Setup for a BT.656 pixel clock of 13.5 Mpixels/second
*
* 28.636363 MHz * (0xf + 0x02be2c9/0x2000000)/4 = 8 * 13.5 MHz
* 432.0 MHz before post divide
*/
/* HVR1850 */
switch (state->id) {
case CX23888_AV:
/* 888/HVR1250 specific */
cx25840_write4(client, 0x10c, 0x13333333);
cx25840_write4(client, 0x108, 0x00000515);
break;
default:
cx25840_write4(client, 0x10c, 0x002be2c9);
cx25840_write4(client, 0x108, 0x0000040f);
}
/* Luma */
cx25840_write4(client, 0x414, 0x00107d12);
/* Chroma */
cx25840_write4(client, 0x420, 0x3d008282);
/*
* Aux PLL
* Initial setup for audio sample clock:
* 48 ksps, 16 bits/sample, x160 multiplier = 122.88 MHz
* Initial I2S output/master clock(?):
* 48 ksps, 16 bits/sample, x16 multiplier = 12.288 MHz
*/
switch (state->id) {
case CX23888_AV:
/*
* 50.0 MHz * (0x7 + 0x0bedfa4/0x2000000)/3 = 122.88 MHz
* 368.64 MHz before post divide
* 122.88 MHz / 0xa = 12.288 MHz
*/
/* HVR1850 or 50MHz xtal */
cx25840_write4(client, 0x114, 0x017dbf48);
cx25840_write4(client, 0x110, 0x000a030e);
break;
case CX23887_AV:
/*
* 25.0 MHz * (0xe + 0x17dbf48/0x2000000)/3 = 122.88 MHz
* 368.64 MHz before post divide
* 122.88 MHz / 0xa = 12.288 MHz
*/
cx25840_write4(client, 0x114, 0x017dbf48);
cx25840_write4(client, 0x110, 0x000a030e);
break;
case CX23885_AV:
default:
/*
* 28.636363 MHz * (0xc + 0x1bf0c9e/0x2000000)/3 = 122.88 MHz
* 368.64 MHz before post divide
* 122.88 MHz / 0xa = 12.288 MHz
*/
cx25840_write4(client, 0x114, 0x01bf0c9e);
cx25840_write4(client, 0x110, 0x000a030c);
break;
}
/* ADC2 input select */
cx25840_write(client, 0x102, 0x10);
/* VIN1 & VIN5 */
cx25840_write(client, 0x103, 0x11);
/* Enable format auto detect */
cx25840_write(client, 0x400, 0);
/* Fast subchroma lock */
/* White crush, Chroma AGC & Chroma Killer enabled */
cx25840_write(client, 0x401, 0xe8);
/* Select AFE clock pad output source */
cx25840_write(client, 0x144, 0x05);
/* Drive GPIO2 direction and values for HVR1700
* where an onboard mux selects the output of demodulator
* vs the 417. Failure to set this results in no DTV.
* It's safe to set this across all Hauppauge boards
* currently, regardless of the board type.
*/
cx25840_write(client, 0x160, 0x1d);
cx25840_write(client, 0x164, 0x00);
/* Do the firmware load in a work handler to prevent.
Otherwise the kernel is blocked waiting for the
bit-banging i2c interface to finish uploading the
firmware. */
INIT_WORK(&state->fw_work, cx25840_work_handler);
init_waitqueue_head(&state->fw_wait);
q = create_singlethread_workqueue("cx25840_fw");
prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
queue_work(q, &state->fw_work);
schedule();
finish_wait(&state->fw_wait, &wait);
destroy_workqueue(q);
/* Call the cx23888 specific std setup func, we no longer rely on
* the generic cx24840 func.
*/
if (is_cx23888(state))
cx23888_std_setup(client);
else
cx25840_std_setup(client);
/* (re)set input */
set_input(client, state->vid_input, state->aud_input);
/* start microcontroller */
cx25840_and_or(client, 0x803, ~0x10, 0x10);
/* Disable and clear video interrupts - we don't use them */
cx25840_write4(client, CX25840_VID_INT_STAT_REG, 0xffffffff);
/* Disable and clear audio interrupts - we don't use them */
cx25840_write(client, CX25840_AUD_INT_CTRL_REG, 0xff);
cx25840_write(client, CX25840_AUD_INT_STAT_REG, 0xff);
/* CC raw enable */
/* - VIP 1.1 control codes - 10bit, blue field enable.
* - enable raw data during vertical blanking.
* - enable ancillary Data insertion for 656 or VIP.
*/
cx25840_write4(client, 0x404, 0x0010253e);
/* CC on - Undocumented Register */
cx25840_write(client, 0x42f, 0x66);
/* HVR-1250 / HVR1850 DIF related */
/* Power everything up */
cx25840_write4(client, 0x130, 0x0);
/* Undocumented */
cx25840_write4(client, 0x478, 0x6628021F);
/* AFE_CLK_OUT_CTRL - Select the clock output source as output */
cx25840_write4(client, 0x144, 0x5);
/* I2C_OUT_CTL - I2S output configuration as
* Master, Sony, Left justified, left sample on WS=1
*/
cx25840_write4(client, 0x918, 0x1a0);
/* AFE_DIAG_CTRL1 */
cx25840_write4(client, 0x134, 0x000a1800);
/* AFE_DIAG_CTRL3 - Inverted Polarity for Audio and Video */
cx25840_write4(client, 0x13c, 0x00310000);
}
/* ----------------------------------------------------------------------- */
static void cx231xx_initialize(struct i2c_client *client)
{
DEFINE_WAIT(wait);
struct cx25840_state *state = to_state(i2c_get_clientdata(client));
struct workqueue_struct *q;
/* Internal Reset */
cx25840_and_or(client, 0x102, ~0x01, 0x01);
cx25840_and_or(client, 0x102, ~0x01, 0x00);
/* Stop microcontroller */
cx25840_and_or(client, 0x803, ~0x10, 0x00);
/* DIF in reset? */
cx25840_write(client, 0x398, 0);
/* Trust the default xtal, no division */
/* This changes for the cx23888 products */
cx25840_write(client, 0x2, 0x76);
/* Bring down the regulator for AUX clk */
cx25840_write(client, 0x1, 0x40);
/* Disable DIF bypass */
cx25840_write4(client, 0x33c, 0x00000001);
/* DIF Src phase inc */
cx25840_write4(client, 0x340, 0x0df7df83);
/* Luma */
cx25840_write4(client, 0x414, 0x00107d12);
/* Chroma */
cx25840_write4(client, 0x420, 0x3d008282);
/* ADC2 input select */
cx25840_write(client, 0x102, 0x10);
/* VIN1 & VIN5 */
cx25840_write(client, 0x103, 0x11);
/* Enable format auto detect */
cx25840_write(client, 0x400, 0);
/* Fast subchroma lock */
/* White crush, Chroma AGC & Chroma Killer enabled */
cx25840_write(client, 0x401, 0xe8);
/* Do the firmware load in a work handler to prevent.
Otherwise the kernel is blocked waiting for the
bit-banging i2c interface to finish uploading the
firmware. */
INIT_WORK(&state->fw_work, cx25840_work_handler);
init_waitqueue_head(&state->fw_wait);
q = create_singlethread_workqueue("cx25840_fw");
prepare_to_wait(&state->fw_wait, &wait, TASK_UNINTERRUPTIBLE);
queue_work(q, &state->fw_work);
schedule();
finish_wait(&state->fw_wait, &wait);
destroy_workqueue(q);
cx25840_std_setup(client);
/* (re)set input */
set_input(client, state->vid_input, state->aud_input);
/* start microcontroller */
cx25840_and_or(client, 0x803, ~0x10, 0x10);
/* CC raw enable */
cx25840_write(client, 0x404, 0x0b);
/* CC on */
cx25840_write(client, 0x42f, 0x66);
cx25840_write4(client, 0x474, 0x1e1e601a);
}
/* ----------------------------------------------------------------------- */
void cx25840_std_setup(struct i2c_client *client)
{
struct cx25840_state *state = to_state(i2c_get_clientdata(client));
v4l2_std_id std = state->std;
int hblank, hactive, burst, vblank, vactive, sc;
int vblank656, src_decimation;
int luma_lpf, uv_lpf, comb;
u32 pll_int, pll_frac, pll_post;
/* datasheet startup, step 8d */
if (std & ~V4L2_STD_NTSC)
cx25840_write(client, 0x49f, 0x11);
else
cx25840_write(client, 0x49f, 0x14);
if (std & V4L2_STD_625_50) {
hblank = 132;
hactive = 720;
burst = 93;
vblank = 36;
vactive = 580;
vblank656 = 40;
src_decimation = 0x21f;
luma_lpf = 2;
if (std & V4L2_STD_SECAM) {
uv_lpf = 0;
comb = 0;
sc = 0x0a425f;
} else if (std == V4L2_STD_PAL_Nc) {
uv_lpf = 1;
comb = 0x20;
sc = 556453;
} else {
uv_lpf = 1;
comb = 0x20;
sc = 688739;
}
} else {
hactive = 720;
hblank = 122;
vactive = 487;
luma_lpf = 1;
uv_lpf = 1;
src_decimation = 0x21f;
if (std == V4L2_STD_PAL_60) {
vblank = 26;
vblank656 = 26;
burst = 0x5b;
luma_lpf = 2;
comb = 0x20;
sc = 688739;
} else if (std == V4L2_STD_PAL_M) {
vblank = 20;
vblank656 = 24;
burst = 0x61;
comb = 0x20;
sc = 555452;
} else {
vblank = 26;
vblank656 = 26;
burst = 0x5b;
comb = 0x66;
sc = 556063;
}
}
/* DEBUG: Displays configured PLL frequency */
if (!is_cx231xx(state)) {
pll_int = cx25840_read(client, 0x108);
pll_frac = cx25840_read4(client, 0x10c) & 0x1ffffff;
pll_post = cx25840_read(client, 0x109);
v4l_dbg(1, cx25840_debug, client,
"PLL regs = int: %u, frac: %u, post: %u\n",
pll_int, pll_frac, pll_post);
if (pll_post) {
int fin, fsc;
int pll = (28636363L * ((((u64)pll_int) << 25L) + pll_frac)) >> 25L;
pll /= pll_post;
v4l_dbg(1, cx25840_debug, client, "PLL = %d.%06d MHz\n",
pll / 1000000, pll % 1000000);
v4l_dbg(1, cx25840_debug, client, "PLL/8 = %d.%06d MHz\n",
pll / 8000000, (pll / 8) % 1000000);
fin = ((u64)src_decimation * pll) >> 12;
v4l_dbg(1, cx25840_debug, client,
"ADC Sampling freq = %d.%06d MHz\n",
fin / 1000000, fin % 1000000);
fsc = (((u64)sc) * pll) >> 24L;
v4l_dbg(1, cx25840_debug, client,
"Chroma sub-carrier freq = %d.%06d MHz\n",
fsc / 1000000, fsc % 1000000);
v4l_dbg(1, cx25840_debug, client, "hblank %i, hactive %i, "
"vblank %i, vactive %i, vblank656 %i, src_dec %i, "
"burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, "
"sc 0x%06x\n",
hblank, hactive, vblank, vactive, vblank656,
src_decimation, burst, luma_lpf, uv_lpf, comb, sc);
}
}
/* Sets horizontal blanking delay and active lines */
cx25840_write(client, 0x470, hblank);
cx25840_write(client, 0x471,
(((hblank >> 8) & 0x3) | (hactive << 4)) & 0xff);
cx25840_write(client, 0x472, hactive >> 4);
/* Sets burst gate delay */
cx25840_write(client, 0x473, burst);
/* Sets vertical blanking delay and active duration */
cx25840_write(client, 0x474, vblank);
cx25840_write(client, 0x475,
(((vblank >> 8) & 0x3) | (vactive << 4)) & 0xff);
cx25840_write(client, 0x476, vactive >> 4);
cx25840_write(client, 0x477, vblank656);
/* Sets src decimation rate */
cx25840_write(client, 0x478, src_decimation & 0xff);
cx25840_write(client, 0x479, (src_decimation >> 8) & 0xff);
/* Sets Luma and UV Low pass filters */
cx25840_write(client, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30));
/* Enables comb filters */
cx25840_write(client, 0x47b, comb);
/* Sets SC Step*/
cx25840_write(client, 0x47c, sc);
cx25840_write(client, 0x47d, (sc >> 8) & 0xff);
cx25840_write(client, 0x47e, (sc >> 16) & 0xff);
/* Sets VBI parameters */
if (std & V4L2_STD_625_50) {
cx25840_write(client, 0x47f, 0x01);
state->vbi_line_offset = 5;
} else {
cx25840_write(client, 0x47f, 0x00);
state->vbi_line_offset = 8;
}
}
/* ----------------------------------------------------------------------- */
static void input_change(struct i2c_client *client)
{
struct cx25840_state *state = to_state(i2c_get_clientdata(client));
v4l2_std_id std = state->std;
/* Follow step 8c and 8d of section 3.16 in the cx25840 datasheet */
if (std & V4L2_STD_SECAM) {
cx25840_write(client, 0x402, 0);
}
else {
cx25840_write(client, 0x402, 0x04);
cx25840_write(client, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11);
}
cx25840_and_or(client, 0x401, ~0x60, 0);
cx25840_and_or(client, 0x401, ~0x60, 0x60);
/* Don't write into audio registers on cx2583x chips */
if (is_cx2583x(state))
return;
cx25840_and_or(client, 0x810, ~0x01, 1);
if (state->radio) {
cx25840_write(client, 0x808, 0xf9);
cx25840_write(client, 0x80b, 0x00);
}
else if (std & V4L2_STD_525_60) {
/* Certain Hauppauge PVR150 models have a hardware bug
that causes audio to drop out. For these models the
audio standard must be set explicitly.
To be precise: it affects cards with tuner models
85, 99 and 112 (model numbers from tveeprom). */
int hw_fix = state->pvr150_workaround;
if (std == V4L2_STD_NTSC_M_JP) {
/* Japan uses EIAJ audio standard */
cx25840_write(client, 0x808, hw_fix ? 0x2f : 0xf7);
} else if (std == V4L2_STD_NTSC_M_KR) {
/* South Korea uses A2 audio standard */
cx25840_write(client, 0x808, hw_fix ? 0x3f : 0xf8);
} else {
/* Others use the BTSC audio standard */
cx25840_write(client, 0x808, hw_fix ? 0x1f : 0xf6);
}
cx25840_write(client, 0x80b, 0x00);
} else if (std & V4L2_STD_PAL) {
/* Autodetect audio standard and audio system */
cx25840_write(client, 0x808, 0xff);
/* Since system PAL-L is pretty much non-existent and
not used by any public broadcast network, force
6.5 MHz carrier to be interpreted as System DK,
this avoids DK audio detection instability */
cx25840_write(client, 0x80b, 0x00);
} else if (std & V4L2_STD_SECAM) {
/* Autodetect audio standard and audio system */
cx25840_write(client, 0x808, 0xff);
/* If only one of SECAM-DK / SECAM-L is required, then force
6.5MHz carrier, else autodetect it */
if ((std & V4L2_STD_SECAM_DK) &&
!(std & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))) {
/* 6.5 MHz carrier to be interpreted as System DK */
cx25840_write(client, 0x80b, 0x00);
} else if (!(std & V4L2_STD_SECAM_DK) &&
(std & (V4L2_STD_SECAM_L | V4L2_STD_SECAM_LC))) {
/* 6.5 MHz carrier to be interpreted as System L */
cx25840_write(client, 0x80b, 0x08);
} else {
/* 6.5 MHz carrier to be autodetected */
cx25840_write(client, 0x80b, 0x10);
}
}
cx25840_and_or(client, 0x810, ~0x01, 0);
}
static int set_input(struct i2c_client *client, enum cx25840_video_input vid_input,
enum cx25840_audio_input aud_input)
{
struct cx25840_state *state = to_state(i2c_get_clientdata(client));
u8 is_composite = (vid_input >= CX25840_COMPOSITE1 &&
vid_input <= CX25840_COMPOSITE8);
u8 is_component = (vid_input & CX25840_COMPONENT_ON) ==
CX25840_COMPONENT_ON;
u8 is_dif = (vid_input & CX25840_DIF_ON) ==
CX25840_DIF_ON;
u8 is_svideo = (vid_input & CX25840_SVIDEO_ON) ==
CX25840_SVIDEO_ON;
int luma = vid_input & 0xf0;
int chroma = vid_input & 0xf00;
u8 reg;
u32 val;
v4l_dbg(1, cx25840_debug, client,
"decoder set video input %d, audio input %d\n",
vid_input, aud_input);
if (vid_input >= CX25840_VIN1_CH1) {
v4l_dbg(1, cx25840_debug, client, "vid_input 0x%x\n",
vid_input);
reg = vid_input & 0xff;
is_composite = !is_component &&
((vid_input & CX25840_SVIDEO_ON) != CX25840_SVIDEO_ON);
v4l_dbg(1, cx25840_debug, client, "mux cfg 0x%x comp=%d\n",
reg, is_composite);
} else if (is_composite) {
reg = 0xf0 + (vid_input - CX25840_COMPOSITE1);
} else {
if ((vid_input & ~0xff0) ||
luma < CX25840_SVIDEO_LUMA1 || luma > CX25840_SVIDEO_LUMA8 ||
chroma < CX25840_SVIDEO_CHROMA4 || chroma > CX25840_SVIDEO_CHROMA8) {
v4l_err(client, "0x%04x is not a valid video input!\n",
vid_input);
return -EINVAL;
}
reg = 0xf0 + ((luma - CX25840_SVIDEO_LUMA1) >> 4);
if (chroma >= CX25840_SVIDEO_CHROMA7) {
reg &= 0x3f;
reg |= (chroma - CX25840_SVIDEO_CHROMA7) >> 2;
} else {
reg &= 0xcf;
reg |= (chroma - CX25840_SVIDEO_CHROMA4) >> 4;
}
}
/* The caller has previously prepared the correct routing
* configuration in reg (for the cx23885) so we have no
* need to attempt to flip bits for earlier av decoders.
*/
if (!is_cx2388x(state) && !is_cx231xx(state)) {
switch (aud_input) {
case CX25840_AUDIO_SERIAL:
/* do nothing, use serial audio input */
break;
case CX25840_AUDIO4: reg &= ~0x30; break;
case CX25840_AUDIO5: reg &= ~0x30; reg |= 0x10; break;
case CX25840_AUDIO6: reg &= ~0x30; reg |= 0x20; break;
case CX25840_AUDIO7: reg &= ~0xc0; break;
case CX25840_AUDIO8: reg &= ~0xc0; reg |= 0x40; break;
default:
v4l_err(client, "0x%04x is not a valid audio input!\n",
aud_input);
return -EINVAL;
}
}
cx25840_write(client, 0x103, reg);
/* Set INPUT_MODE to Composite, S-Video or Component */
if (is_component)
cx25840_and_or(client, 0x401, ~0x6, 0x6);
else
cx25840_and_or(client, 0x401, ~0x6, is_composite ? 0 : 0x02);
if (is_cx2388x(state)) {
/* Enable or disable the DIF for tuner use */
if (is_dif) {
cx25840_and_or(client, 0x102, ~0x80, 0x80);
/* Set of defaults for NTSC and PAL */
cx25840_write4(client, 0x31c, 0xc2262600);
cx25840_write4(client, 0x320, 0xc2262600);
/* 18271 IF - Nobody else yet uses a different
* tuner with the DIF, so these are reasonable
* assumptions (HVR1250 and HVR1850 specific).
*/
cx25840_write4(client, 0x318, 0xda262600);
cx25840_write4(client, 0x33c, 0x2a24c800);
cx25840_write4(client, 0x104, 0x0704dd00);
} else {
cx25840_write4(client, 0x300, 0x015c28f5);
cx25840_and_or(client, 0x102, ~0x80, 0);
cx25840_write4(client, 0x340, 0xdf7df83);
cx25840_write4(client, 0x104, 0x0704dd80);
cx25840_write4(client, 0x314, 0x22400600);
cx25840_write4(client, 0x318, 0x40002600);
cx25840_write4(client, 0x324, 0x40002600);
cx25840_write4(client, 0x32c, 0x0250e620);
cx25840_write4(client, 0x39c, 0x01FF0B00);
cx25840_write4(client, 0x410, 0xffff0dbf);
cx25840_write4(client, 0x414, 0x00137d03);
/* on the 887, 0x418 is HSCALE_CTRL, on the 888 it is
CHROMA_CTRL */
if (is_cx23888(state))
cx25840_write4(client, 0x418, 0x01008080);
else
cx25840_write4(client, 0x418, 0x01000000);
cx25840_write4(client, 0x41c, 0x00000000);
/* on the 887, 0x420 is CHROMA_CTRL, on the 888 it is
CRUSH_CTRL */
if (is_cx23888(state))
cx25840_write4(client, 0x420, 0x001c3e0f);
else
cx25840_write4(client, 0x420, 0x001c8282);
cx25840_write4(client, 0x42c, 0x42600000);
cx25840_write4(client, 0x430, 0x0000039b);
cx25840_write4(client, 0x438, 0x00000000);
cx25840_write4(client, 0x440, 0xF8E3E824);
cx25840_write4(client, 0x444, 0x401040dc);
cx25840_write4(client, 0x448, 0xcd3f02a0);
cx25840_write4(client, 0x44c, 0x161f1000);
cx25840_write4(client, 0x450, 0x00000802);
cx25840_write4(client, 0x91c, 0x01000000);
cx25840_write4(client, 0x8e0, 0x03063870);
cx25840_write4(client, 0x8d4, 0x7FFF0024);
cx25840_write4(client, 0x8d0, 0x00063073);
cx25840_write4(client, 0x8c8, 0x00010000);
cx25840_write4(client, 0x8cc, 0x00080023);
/* DIF BYPASS */
cx25840_write4(client, 0x33c, 0x2a04c800);
}
/* Reset the DIF */
cx25840_write4(client, 0x398, 0);
}
if (!is_cx2388x(state) && !is_cx231xx(state)) {
/* Set CH_SEL_ADC2 to 1 if input comes from CH3 */
cx25840_and_or(client, 0x102, ~0x2, (reg & 0x80) == 0 ? 2 : 0);
/* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2&CH3 */
if ((reg & 0xc0) != 0xc0 && (reg & 0x30) != 0x30)
cx25840_and_or(client, 0x102, ~0x4, 4);
else
cx25840_and_or(client, 0x102, ~0x4, 0);
} else {
/* Set DUAL_MODE_ADC2 to 1 if component*/
cx25840_and_or(client, 0x102, ~0x4, is_component ? 0x4 : 0x0);
if (is_composite) {
/* ADC2 input select channel 2 */
cx25840_and_or(client, 0x102, ~0x2, 0);
} else if (!is_component) {
/* S-Video */
if (chroma >= CX25840_SVIDEO_CHROMA7) {
/* ADC2 input select channel 3 */
cx25840_and_or(client, 0x102, ~0x2, 2);
} else {
/* ADC2 input select channel 2 */
cx25840_and_or(client, 0x102, ~0x2, 0);
}
}
/* cx23885 / SVIDEO */
if (is_cx2388x(state) && is_svideo) {
#define AFE_CTRL (0x104)
#define MODE_CTRL (0x400)
cx25840_and_or(client, 0x102, ~0x2, 0x2);
val = cx25840_read4(client, MODE_CTRL);
val &= 0xFFFFF9FF;
/* YC */
val |= 0x00000200;
val &= ~0x2000;
cx25840_write4(client, MODE_CTRL, val);
val = cx25840_read4(client, AFE_CTRL);
/* Chroma in select */
val |= 0x00001000;
val &= 0xfffffe7f;
/* Clear VGA_SEL_CH2 and VGA_SEL_CH3 (bits 7 and 8).
* This sets them to use video rather than audio.
* Only one of the two will be in use.
*/
cx25840_write4(client, AFE_CTRL, val);
} else
cx25840_and_or(client, 0x102, ~0x2, 0);
}
state->vid_input = vid_input;
state->aud_input = aud_input;
cx25840_audio_set_path(client);
input_change(client);
if (is_cx2388x(state)) {
/* Audio channel 1 src : Parallel 1 */
cx25840_write(client, 0x124, 0x03);
/* Select AFE clock pad output source */
cx25840_write(client, 0x144, 0x05);
/* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
cx25840_write(client, 0x914, 0xa0);
/* I2S_OUT_CTL:
* I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
* I2S_OUT_MASTER_MODE = Master
*/
cx25840_write(client, 0x918, 0xa0);
cx25840_write(client, 0x919, 0x01);
} else if (is_cx231xx(state)) {
/* Audio channel 1 src : Parallel 1 */
cx25840_write(client, 0x124, 0x03);
/* I2S_IN_CTL: I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1 */
cx25840_write(client, 0x914, 0xa0);
/* I2S_OUT_CTL:
* I2S_IN_SONY_MODE, LEFT SAMPLE on WS=1
* I2S_OUT_MASTER_MODE = Master
*/
cx25840_write(client, 0x918, 0xa0);
cx25840_write(client, 0x919, 0x01);
}
if (is_cx2388x(state) && ((aud_input == CX25840_AUDIO7) ||
(aud_input == CX25840_AUDIO6))) {
/* Configure audio from LR1 or LR2 input */
cx25840_write4(client, 0x910, 0);
cx25840_write4(client, 0x8d0, 0x63073);
} else
if (is_cx2388x(state) && (aud_input == CX25840_AUDIO8)) {
/* Configure audio from tuner/sif input */
cx25840_write4(client, 0x910, 0x12b000c9);
cx25840_write4(client, 0x8d0, 0x1f063870);
}
if (is_cx23888(state)) {
/* HVR1850 */
/* AUD_IO_CTRL - I2S Input, Parallel1*/
/* - Channel 1 src - Parallel1 (Merlin out) */
/* - Channel 2 src - Parallel2 (Merlin out) */
/* - Channel 3 src - Parallel3 (Merlin AC97 out) */
/* - I2S source and dir - Merlin, output */
cx25840_write4(client, 0x124, 0x100);
if (!is_dif) {
/* Stop microcontroller if we don't need it
* to avoid audio popping on svideo/composite use.
*/
cx25840_and_or(client, 0x803, ~0x10, 0x00);
}
}
return 0;
}
/* ----------------------------------------------------------------------- */
static int set_v4lstd(struct i2c_client *client)
{
struct cx25840_state *state = to_state(i2c_get_clientdata(client));
u8 fmt = 0; /* zero is autodetect */
u8 pal_m = 0;
/* First tests should be against specific std */
if (state->std == V4L2_STD_NTSC_M_JP) {
fmt = 0x2;
} else if (state->std == V4L2_STD_NTSC_443) {
fmt = 0x3;
} else if (state->std == V4L2_STD_PAL_M) {
pal_m = 1;
fmt = 0x5;
} else if (state->std == V4L2_STD_PAL_N) {
fmt = 0x6;
} else if (state->std == V4L2_STD_PAL_Nc) {
fmt = 0x7;
} else if (state->std == V4L2_STD_PAL_60) {
fmt = 0x8;
} else {
/* Then, test against generic ones */
if (state->std & V4L2_STD_NTSC)
fmt = 0x1;
else if (state->std & V4L2_STD_PAL)
fmt = 0x4;
else if (state->std & V4L2_STD_SECAM)
fmt = 0xc;
}
v4l_dbg(1, cx25840_debug, client, "changing video std to fmt %i\n",fmt);
/* Follow step 9 of section 3.16 in the cx25840 datasheet.
Without this PAL may display a vertical ghosting effect.
This happens for example with the Yuan MPC622. */
if (fmt >= 4 && fmt < 8) {
/* Set format to NTSC-M */
cx25840_and_or(client, 0x400, ~0xf, 1);
/* Turn off LCOMB */
cx25840_and_or(client, 0x47b, ~6, 0);
}
cx25840_and_or(client, 0x400, ~0xf, fmt);
cx25840_and_or(client, 0x403, ~0x3, pal_m);
if (is_cx23888(state))
cx23888_std_setup(client);
else
cx25840_std_setup(client);
if (!is_cx2583x(state))
input_change(client);
return 0;
}
/* ----------------------------------------------------------------------- */
static int cx25840_s_ctrl(struct v4l2_ctrl *ctrl)
{
struct v4l2_subdev *sd = to_sd(ctrl);
struct cx25840_state *state = to_state(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
switch (ctrl->id) {
case V4L2_CID_BRIGHTNESS:
cx25840_write(client, 0x414, ctrl->val - 128);
break;
case V4L2_CID_CONTRAST:
cx25840_write(client, 0x415, ctrl->val << 1);
break;
case V4L2_CID_SATURATION:
if (is_cx23888(state)) {
cx25840_write(client, 0x418, ctrl->val << 1);
cx25840_write(client, 0x419, ctrl->val << 1);
} else {
cx25840_write(client, 0x420, ctrl->val << 1);
cx25840_write(client, 0x421, ctrl->val << 1);
}
break;
case V4L2_CID_HUE:
if (is_cx23888(state))
cx25840_write(client, 0x41a, ctrl->val);
else
cx25840_write(client, 0x422, ctrl->val);
break;
default:
return -EINVAL;
}
return 0;
}
/* ----------------------------------------------------------------------- */
static int cx25840_s_mbus_fmt(struct v4l2_subdev *sd, struct v4l2_mbus_framefmt *fmt)
{
struct cx25840_state *state = to_state(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
int HSC, VSC, Vsrc, Hsrc, filter, Vlines;
int is_50Hz = !(state->std & V4L2_STD_525_60);
if (fmt->code != MEDIA_BUS_FMT_FIXED)
return -EINVAL;
fmt->field = V4L2_FIELD_INTERLACED;
fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
if (is_cx23888(state)) {
Vsrc = (cx25840_read(client, 0x42a) & 0x3f) << 4;
Vsrc |= (cx25840_read(client, 0x429) & 0xf0) >> 4;
} else {
Vsrc = (cx25840_read(client, 0x476) & 0x3f) << 4;
Vsrc |= (cx25840_read(client, 0x475) & 0xf0) >> 4;
}
if (is_cx23888(state)) {
Hsrc = (cx25840_read(client, 0x426) & 0x3f) << 4;
Hsrc |= (cx25840_read(client, 0x425) & 0xf0) >> 4;
} else {
Hsrc = (cx25840_read(client, 0x472) & 0x3f) << 4;
Hsrc |= (cx25840_read(client, 0x471) & 0xf0) >> 4;
}
Vlines = fmt->height + (is_50Hz ? 4 : 7);
if ((fmt->width * 16 < Hsrc) || (Hsrc < fmt->width) ||
(Vlines * 8 < Vsrc) || (Vsrc < Vlines)) {
v4l_err(client, "%dx%d is not a valid size!\n",
fmt->width, fmt->height);
return -ERANGE;
}
HSC = (Hsrc * (1 << 20)) / fmt->width - (1 << 20);
VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9));
VSC &= 0x1fff;
if (fmt->width >= 385)
filter = 0;
else if (fmt->width > 192)
filter = 1;
else if (fmt->width > 96)
filter = 2;
else
filter = 3;
v4l_dbg(1, cx25840_debug, client, "decoder set size %dx%d -> scale %ux%u\n",
fmt->width, fmt->height, HSC, VSC);
/* HSCALE=HSC */
cx25840_write(client, 0x418, HSC & 0xff);
cx25840_write(client, 0x419, (HSC >> 8) & 0xff);
cx25840_write(client, 0x41a, HSC >> 16);
/* VSCALE=VSC */
cx25840_write(client, 0x41c, VSC & 0xff);
cx25840_write(client, 0x41d, VSC >> 8);
/* VS_INTRLACE=1 VFILT=filter */
cx25840_write(client, 0x41e, 0x8 | filter);
return 0;
}
/* ----------------------------------------------------------------------- */
static void log_video_status(struct i2c_client *client)
{
static const char *const fmt_strs[] = {
"0x0",
"NTSC-M", "NTSC-J", "NTSC-4.43",
"PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60",
"0x9", "0xA", "0xB",
"SECAM",
"0xD", "0xE", "0xF"
};
struct cx25840_state *state = to_state(i2c_get_clientdata(client));
u8 vidfmt_sel = cx25840_read(client, 0x400) & 0xf;
u8 gen_stat1 = cx25840_read(client, 0x40d);
u8 gen_stat2 = cx25840_read(client, 0x40e);
int vid_input = state->vid_input;
v4l_info(client, "Video signal: %spresent\n",
(gen_stat2 & 0x20) ? "" : "not ");
v4l_info(client, "Detected format: %s\n",
fmt_strs[gen_stat1 & 0xf]);
v4l_info(client, "Specified standard: %s\n",
vidfmt_sel ? fmt_strs[vidfmt_sel] : "automatic detection");
if (vid_input >= CX25840_COMPOSITE1 &&
vid_input <= CX25840_COMPOSITE8) {
v4l_info(client, "Specified video input: Composite %d\n",
vid_input - CX25840_COMPOSITE1 + 1);
} else {
v4l_info(client, "Specified video input: S-Video (Luma In%d, Chroma In%d)\n",
(vid_input & 0xf0) >> 4, (vid_input & 0xf00) >> 8);
}
v4l_info(client, "Specified audioclock freq: %d Hz\n", state->audclk_freq);
}
/* ----------------------------------------------------------------------- */
static void log_audio_status(struct i2c_client *client)
{
struct cx25840_state *state = to_state(i2c_get_clientdata(client));
u8 download_ctl = cx25840_read(client, 0x803);
u8 mod_det_stat0 = cx25840_read(client, 0x804);
u8 mod_det_stat1 = cx25840_read(client, 0x805);
u8 audio_config = cx25840_read(client, 0x808);
u8 pref_mode = cx25840_read(client, 0x809);
u8 afc0 = cx25840_read(client, 0x80b);
u8 mute_ctl = cx25840_read(client, 0x8d3);
int aud_input = state->aud_input;
char *p;
switch (mod_det_stat0) {
case 0x00: p = "mono"; break;
case 0x01: p = "stereo"; break;
case 0x02: p = "dual"; break;
case 0x04: p = "tri"; break;
case 0x10: p = "mono with SAP"; break;
case 0x11: p = "stereo with SAP"; break;
case 0x12: p = "dual with SAP"; break;
case 0x14: p = "tri with SAP"; break;
case 0xfe: p = "forced mode"; break;
default: p = "not defined";
}
v4l_info(client, "Detected audio mode: %s\n", p);
switch (mod_det_stat1) {
case 0x00: p = "not defined"; break;
case 0x01: p = "EIAJ"; break;
case 0x02: p = "A2-M"; break;
case 0x03: p = "A2-BG"; break;
case 0x04: p = "A2-DK1"; break;
case 0x05: p = "A2-DK2"; break;
case 0x06: p = "A2-DK3"; break;
case 0x07: p = "A1 (6.0 MHz FM Mono)"; break;
case 0x08: p = "AM-L"; break;
case 0x09: p = "NICAM-BG"; break;
case 0x0a: p = "NICAM-DK"; break;
case 0x0b: p = "NICAM-I"; break;
case 0x0c: p = "NICAM-L"; break;
case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break;
case 0x0e: p = "IF FM Radio"; break;
case 0x0f: p = "BTSC"; break;
case 0x10: p = "high-deviation FM"; break;
case 0x11: p = "very high-deviation FM"; break;
case 0xfd: p = "unknown audio standard"; break;
case 0xfe: p = "forced audio standard"; break;
case 0xff: p = "no detected audio standard"; break;
default: p = "not defined";
}
v4l_info(client, "Detected audio standard: %s\n", p);
v4l_info(client, "Audio microcontroller: %s\n",
(download_ctl & 0x10) ?
((mute_ctl & 0x2) ? "detecting" : "running") : "stopped");
switch (audio_config >> 4) {
case 0x00: p = "undefined"; break;
case 0x01: p = "BTSC"; break;
case 0x02: p = "EIAJ"; break;
case 0x03: p = "A2-M"; break;
case 0x04: p = "A2-BG"; break;
case 0x05: p = "A2-DK1"; break;
case 0x06: p = "A2-DK2"; break;
case 0x07: p = "A2-DK3"; break;
case 0x08: p = "A1 (6.0 MHz FM Mono)"; break;
case 0x09: p = "AM-L"; break;
case 0x0a: p = "NICAM-BG"; break;
case 0x0b: p = "NICAM-DK"; break;
case 0x0c: p = "NICAM-I"; break;
case 0x0d: p = "NICAM-L"; break;
case 0x0e: p = "FM radio"; break;
case 0x0f: p = "automatic detection"; break;
default: p = "undefined";
}
v4l_info(client, "Configured audio standard: %s\n", p);
if ((audio_config >> 4) < 0xF) {
switch (audio_config & 0xF) {
case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break;
case 0x01: p = "MONO2 (LANGUAGE B)"; break;
case 0x02: p = "MONO3 (STEREO forced MONO)"; break;
case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break;
case 0x04: p = "STEREO"; break;
case 0x05: p = "DUAL1 (AB)"; break;
case 0x06: p = "DUAL2 (AC) (FM)"; break;
case 0x07: p = "DUAL3 (BC) (FM)"; break;
case 0x08: p = "DUAL4 (AC) (AM)"; break;
case 0x09: p = "DUAL5 (BC) (AM)"; break;
case 0x0a: p = "SAP"; break;
default: p = "undefined";
}
v4l_info(client, "Configured audio mode: %s\n", p);
} else {
switch (audio_config & 0xF) {
case 0x00: p = "BG"; break;
case 0x01: p = "DK1"; break;
case 0x02: p = "DK2"; break;
case 0x03: p = "DK3"; break;
case 0x04: p = "I"; break;
case 0x05: p = "L"; break;
case 0x06: p = "BTSC"; break;
case 0x07: p = "EIAJ"; break;
case 0x08: p = "A2-M"; break;
case 0x09: p = "FM Radio"; break;
case 0x0f: p = "automatic standard and mode detection"; break;
default: p = "undefined";
}
v4l_info(client, "Configured audio system: %s\n", p);
}
if (aud_input) {
v4l_info(client, "Specified audio input: Tuner (In%d)\n", aud_input);
} else {
v4l_info(client, "Specified audio input: External\n");
}
switch (pref_mode & 0xf) {
case 0: p = "mono/language A"; break;
case 1: p = "language B"; break;
case 2: p = "language C"; break;
case 3: p = "analog fallback"; break;
case 4: p = "stereo"; break;
case 5: p = "language AC"; break;
case 6: p = "language BC"; break;
case 7: p = "language AB"; break;
default: p = "undefined";
}
v4l_info(client, "Preferred audio mode: %s\n", p);
if ((audio_config & 0xf) == 0xf) {
switch ((afc0 >> 3) & 0x3) {
case 0: p = "system DK"; break;
case 1: p = "system L"; break;
case 2: p = "autodetect"; break;
default: p = "undefined";
}
v4l_info(client, "Selected 65 MHz format: %s\n", p);
switch (afc0 & 0x7) {
case 0: p = "chroma"; break;
case 1: p = "BTSC"; break;
case 2: p = "EIAJ"; break;
case 3: p = "A2-M"; break;
case 4: p = "autodetect"; break;
default: p = "undefined";
}
v4l_info(client, "Selected 45 MHz format: %s\n", p);
}
}
/* ----------------------------------------------------------------------- */
/* This load_fw operation must be called to load the driver's firmware.
Without this the audio standard detection will fail and you will
only get mono.
Since loading the firmware is often problematic when the driver is
compiled into the kernel I recommend postponing calling this function
until the first open of the video device. Another reason for
postponing it is that loading this firmware takes a long time (seconds)
due to the slow i2c bus speed. So it will speed up the boot process if
you can avoid loading the fw as long as the video device isn't used. */
static int cx25840_load_fw(struct v4l2_subdev *sd)
{
struct cx25840_state *state = to_state(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
if (!state->is_initialized) {
/* initialize and load firmware */
state->is_initialized = 1;
if (is_cx2583x(state))
cx25836_initialize(client);
else if (is_cx2388x(state))
cx23885_initialize(client);
else if (is_cx231xx(state))
cx231xx_initialize(client);
else
cx25840_initialize(client);
}
return 0;
}
#ifdef CONFIG_VIDEO_ADV_DEBUG
static int cx25840_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
reg->size = 1;
reg->val = cx25840_read(client, reg->reg & 0x0fff);
return 0;
}
static int cx25840_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
cx25840_write(client, reg->reg & 0x0fff, reg->val & 0xff);
return 0;
}
#endif
static int cx25840_s_audio_stream(struct v4l2_subdev *sd, int enable)
{
struct cx25840_state *state = to_state(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
u8 v;
if (is_cx2583x(state) || is_cx2388x(state) || is_cx231xx(state))
return 0;
v4l_dbg(1, cx25840_debug, client, "%s audio output\n",
enable ? "enable" : "disable");
if (enable) {
v = cx25840_read(client, 0x115) | 0x80;
cx25840_write(client, 0x115, v);
v = cx25840_read(client, 0x116) | 0x03;
cx25840_write(client, 0x116, v);
} else {
v = cx25840_read(client, 0x115) & ~(0x80);
cx25840_write(client, 0x115, v);
v = cx25840_read(client, 0x116) & ~(0x03);
cx25840_write(client, 0x116, v);
}
return 0;
}
static int cx25840_s_stream(struct v4l2_subdev *sd, int enable)
{
struct cx25840_state *state = to_state(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
u8 v;
v4l_dbg(1, cx25840_debug, client, "%s video output\n",
enable ? "enable" : "disable");
if (enable) {
if (is_cx2388x(state) || is_cx231xx(state)) {
v = cx25840_read(client, 0x421) | 0x0b;
cx25840_write(client, 0x421, v);
} else {
v = cx25840_read(client, 0x115) | 0x0c;
cx25840_write(client, 0x115, v);
v = cx25840_read(client, 0x116) | 0x04;
cx25840_write(client, 0x116, v);
}
} else {
if (is_cx2388x(state) || is_cx231xx(state)) {
v = cx25840_read(client, 0x421) & ~(0x0b);
cx25840_write(client, 0x421, v);
} else {
v = cx25840_read(client, 0x115) & ~(0x0c);
cx25840_write(client, 0x115, v);
v = cx25840_read(client, 0x116) & ~(0x04);
cx25840_write(client, 0x116, v);
}
}
return 0;
}
/* Query the current detected video format */
static int cx25840_g_std(struct v4l2_subdev *sd, v4l2_std_id *std)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
v4l2_std_id stds[] = {
/* 0000 */ V4L2_STD_UNKNOWN,
/* 0001 */ V4L2_STD_NTSC_M,
/* 0010 */ V4L2_STD_NTSC_M_JP,
/* 0011 */ V4L2_STD_NTSC_443,
/* 0100 */ V4L2_STD_PAL,
/* 0101 */ V4L2_STD_PAL_M,
/* 0110 */ V4L2_STD_PAL_N,
/* 0111 */ V4L2_STD_PAL_Nc,
/* 1000 */ V4L2_STD_PAL_60,
/* 1001 */ V4L2_STD_UNKNOWN,
/* 1010 */ V4L2_STD_UNKNOWN,
/* 1001 */ V4L2_STD_UNKNOWN,
/* 1010 */ V4L2_STD_UNKNOWN,
/* 1011 */ V4L2_STD_UNKNOWN,
/* 1110 */ V4L2_STD_UNKNOWN,
/* 1111 */ V4L2_STD_UNKNOWN
};
u32 fmt = (cx25840_read4(client, 0x40c) >> 8) & 0xf;
*std = stds[ fmt ];
v4l_dbg(1, cx25840_debug, client, "g_std fmt = %x, v4l2_std_id = 0x%x\n",
fmt, (unsigned int)stds[ fmt ]);
return 0;
}
static int cx25840_g_input_status(struct v4l2_subdev *sd, u32 *status)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
/* A limited function that checks for signal status and returns
* the state.
*/
/* Check for status of Horizontal lock (SRC lock isn't reliable) */
if ((cx25840_read4(client, 0x40c) & 0x00010000) == 0)
*status |= V4L2_IN_ST_NO_SIGNAL;
return 0;
}
static int cx25840_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
{
struct cx25840_state *state = to_state(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
if (state->radio == 0 && state->std == std)
return 0;
state->radio = 0;
state->std = std;
return set_v4lstd(client);
}
static int cx25840_s_radio(struct v4l2_subdev *sd)
{
struct cx25840_state *state = to_state(sd);
state->radio = 1;
return 0;
}
static int cx25840_s_video_routing(struct v4l2_subdev *sd,
u32 input, u32 output, u32 config)
{
struct cx25840_state *state = to_state(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
if (is_cx23888(state))
cx23888_std_setup(client);
return set_input(client, input, state->aud_input);
}
static int cx25840_s_audio_routing(struct v4l2_subdev *sd,
u32 input, u32 output, u32 config)
{
struct cx25840_state *state = to_state(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
if (is_cx23888(state))
cx23888_std_setup(client);
return set_input(client, state->vid_input, input);
}
static int cx25840_s_frequency(struct v4l2_subdev *sd, const struct v4l2_frequency *freq)
{
struct i2c_client *client = v4l2_get_subdevdata(sd);
input_change(client);
return 0;
}
static int cx25840_g_tuner(struct v4l2_subdev *sd, struct v4l2_tuner *vt)
{
struct cx25840_state *state = to_state(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
u8 vpres = cx25840_read(client, 0x40e) & 0x20;
u8 mode;
int val = 0;
if (state->radio)
return 0;
vt->signal = vpres ? 0xffff : 0x0;
if (is_cx2583x(state))
return 0;
vt->capability |=
V4L2_TUNER_CAP_STEREO | V4L2_TUNER_CAP_LANG1 |
V4L2_TUNER_CAP_LANG2 | V4L2_TUNER_CAP_SAP;
mode = cx25840_read(client, 0x804);
/* get rxsubchans and audmode */
if ((mode & 0xf) == 1)
val |= V4L2_TUNER_SUB_STEREO;
else
val |= V4L2_TUNER_SUB_MONO;
if (mode == 2 || mode == 4)
val = V4L2_TUNER_SUB_LANG1 | V4L2_TUNER_SUB_LANG2;
if (mode & 0x10)
val |= V4L2_TUNER_SUB_SAP;
vt->rxsubchans = val;
vt->audmode = state->audmode;
return 0;
}
static int cx25840_s_tuner(struct v4l2_subdev *sd, const struct v4l2_tuner *vt)
{
struct cx25840_state *state = to_state(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
if (state->radio || is_cx2583x(state))
return 0;
switch (vt->audmode) {
case V4L2_TUNER_MODE_MONO:
/* mono -> mono
stereo -> mono
bilingual -> lang1 */
cx25840_and_or(client, 0x809, ~0xf, 0x00);
break;
case V4L2_TUNER_MODE_STEREO:
case V4L2_TUNER_MODE_LANG1:
/* mono -> mono
stereo -> stereo
bilingual -> lang1 */
cx25840_and_or(client, 0x809, ~0xf, 0x04);
break;
case V4L2_TUNER_MODE_LANG1_LANG2:
/* mono -> mono
stereo -> stereo
bilingual -> lang1/lang2 */
cx25840_and_or(client, 0x809, ~0xf, 0x07);
break;
case V4L2_TUNER_MODE_LANG2:
/* mono -> mono
stereo -> stereo
bilingual -> lang2 */
cx25840_and_or(client, 0x809, ~0xf, 0x01);
break;
default:
return -EINVAL;
}
state->audmode = vt->audmode;
return 0;
}
static int cx25840_reset(struct v4l2_subdev *sd, u32 val)
{
struct cx25840_state *state = to_state(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
if (is_cx2583x(state))
cx25836_initialize(client);
else if (is_cx2388x(state))
cx23885_initialize(client);
else if (is_cx231xx(state))
cx231xx_initialize(client);
else
cx25840_initialize(client);
return 0;
}
static int cx25840_log_status(struct v4l2_subdev *sd)
{
struct cx25840_state *state = to_state(sd);
struct i2c_client *client = v4l2_get_subdevdata(sd);
log_video_status(client);
if (!is_cx2583x(state))
log_audio_status(client);
cx25840_ir_log_status(sd);
v4l2_ctrl_handler_log_status(&state->hdl, sd->name);
return 0;
}
static int cx23885_irq_handler(struct v4l2_subdev *sd, u32 status,
bool *handled)
{
struct cx25840_state *state = to_state(sd);
struct i2c_client *c = v4l2_get_subdevdata(sd);
u8 irq_stat, aud_stat, aud_en, ir_stat, ir_en;
u32 vid_stat, aud_mc_stat;
bool block_handled;
int ret = 0;
irq_stat = cx25840_read(c, CX23885_PIN_CTRL_IRQ_REG);
v4l_dbg(2, cx25840_debug, c, "AV Core IRQ status (entry): %s %s %s\n",
irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT ? "ir" : " ",
irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT ? "aud" : " ",
irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT ? "vid" : " ");
if ((is_cx23885(state) || is_cx23887(state))) {
ir_stat = cx25840_read(c, CX25840_IR_STATS_REG);
ir_en = cx25840_read(c, CX25840_IR_IRQEN_REG);
v4l_dbg(2, cx25840_debug, c,
"AV Core ir IRQ status: %#04x disables: %#04x\n",
ir_stat, ir_en);
if (irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT) {
block_handled = false;
ret = cx25840_ir_irq_handler(sd,
status, &block_handled);
if (block_handled)
*handled = true;
}
}
aud_stat = cx25840_read(c, CX25840_AUD_INT_STAT_REG);
aud_en = cx25840_read(c, CX25840_AUD_INT_CTRL_REG);
v4l_dbg(2, cx25840_debug, c,
"AV Core audio IRQ status: %#04x disables: %#04x\n",
aud_stat, aud_en);
aud_mc_stat = cx25840_read4(c, CX23885_AUD_MC_INT_MASK_REG);
v4l_dbg(2, cx25840_debug, c,
"AV Core audio MC IRQ status: %#06x enables: %#06x\n",
aud_mc_stat >> CX23885_AUD_MC_INT_STAT_SHFT,
aud_mc_stat & CX23885_AUD_MC_INT_CTRL_BITS);
if (irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT) {
if (aud_stat) {
cx25840_write(c, CX25840_AUD_INT_STAT_REG, aud_stat);
*handled = true;
}
}
vid_stat = cx25840_read4(c, CX25840_VID_INT_STAT_REG);
v4l_dbg(2, cx25840_debug, c,
"AV Core video IRQ status: %#06x disables: %#06x\n",
vid_stat & CX25840_VID_INT_STAT_BITS,
vid_stat >> CX25840_VID_INT_MASK_SHFT);
if (irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT) {
if (vid_stat & CX25840_VID_INT_STAT_BITS) {
cx25840_write4(c, CX25840_VID_INT_STAT_REG, vid_stat);
*handled = true;
}
}
irq_stat = cx25840_read(c, CX23885_PIN_CTRL_IRQ_REG);
v4l_dbg(2, cx25840_debug, c, "AV Core IRQ status (exit): %s %s %s\n",
irq_stat & CX23885_PIN_CTRL_IRQ_IR_STAT ? "ir" : " ",
irq_stat & CX23885_PIN_CTRL_IRQ_AUD_STAT ? "aud" : " ",
irq_stat & CX23885_PIN_CTRL_IRQ_VID_STAT ? "vid" : " ");
return ret;
}
static int cx25840_irq_handler(struct v4l2_subdev *sd, u32 status,
bool *handled)
{
struct cx25840_state *state = to_state(sd);
*handled = false;
/* Only support the CX2388[578] AV Core for now */
if (is_cx2388x(state))
return cx23885_irq_handler(sd, status, handled);
return -ENODEV;
}
/* ----------------------------------------------------------------------- */
#define DIF_PLL_FREQ_WORD (0x300)
#define DIF_BPF_COEFF01 (0x348)
#define DIF_BPF_COEFF23 (0x34c)
#define DIF_BPF_COEFF45 (0x350)
#define DIF_BPF_COEFF67 (0x354)
#define DIF_BPF_COEFF89 (0x358)
#define DIF_BPF_COEFF1011 (0x35c)
#define DIF_BPF_COEFF1213 (0x360)
#define DIF_BPF_COEFF1415 (0x364)
#define DIF_BPF_COEFF1617 (0x368)
#define DIF_BPF_COEFF1819 (0x36c)
#define DIF_BPF_COEFF2021 (0x370)
#define DIF_BPF_COEFF2223 (0x374)
#define DIF_BPF_COEFF2425 (0x378)
#define DIF_BPF_COEFF2627 (0x37c)
#define DIF_BPF_COEFF2829 (0x380)
#define DIF_BPF_COEFF3031 (0x384)
#define DIF_BPF_COEFF3233 (0x388)
#define DIF_BPF_COEFF3435 (0x38c)
#define DIF_BPF_COEFF36 (0x390)
static void cx23885_dif_setup(struct i2c_client *client, u32 ifHz)
{
u64 pll_freq;
u32 pll_freq_word;
v4l_dbg(1, cx25840_debug, client, "%s(%d)\n", __func__, ifHz);
/* Assuming TV */
/* Calculate the PLL frequency word based on the adjusted ifHz */
pll_freq = div_u64((u64)ifHz * 268435456, 50000000);
pll_freq_word = (u32)pll_freq;
cx25840_write4(client, DIF_PLL_FREQ_WORD, pll_freq_word);
/* Round down to the nearest 100KHz */
ifHz = (ifHz / 100000) * 100000;
if (ifHz < 3000000)
ifHz = 3000000;
if (ifHz > 16000000)
ifHz = 16000000;
v4l_dbg(1, cx25840_debug, client, "%s(%d) again\n", __func__, ifHz);
switch (ifHz) {
case 3000000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
cx25840_write4(client, DIF_BPF_COEFF23, 0x00080012);
cx25840_write4(client, DIF_BPF_COEFF45, 0x001e0024);
cx25840_write4(client, DIF_BPF_COEFF67, 0x001bfff8);
cx25840_write4(client, DIF_BPF_COEFF89, 0xffb4ff50);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xfed8fe68);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe24fe34);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfebaffc7);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x014d031f);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x04f0065d);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x07010688);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x04c901d6);
cx25840_write4(client, DIF_BPF_COEFF2425, 0xfe00f9d3);
cx25840_write4(client, DIF_BPF_COEFF2627, 0xf600f342);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf235f337);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf64efb22);
cx25840_write4(client, DIF_BPF_COEFF3233, 0x0105070f);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x0c460fce);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 3100000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00000001);
cx25840_write4(client, DIF_BPF_COEFF23, 0x00070012);
cx25840_write4(client, DIF_BPF_COEFF45, 0x00220032);
cx25840_write4(client, DIF_BPF_COEFF67, 0x00370026);
cx25840_write4(client, DIF_BPF_COEFF89, 0xfff0ff91);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xff0efe7c);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe01fdcc);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe0afedb);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x00440224);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x0434060c);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x0738074e);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x06090361);
cx25840_write4(client, DIF_BPF_COEFF2425, 0xff99fb39);
cx25840_write4(client, DIF_BPF_COEFF2627, 0xf6fef3b6);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf21af2a5);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf573fa33);
cx25840_write4(client, DIF_BPF_COEFF3233, 0x0034067d);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x0bfb0fb9);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 3200000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00000000);
cx25840_write4(client, DIF_BPF_COEFF23, 0x0004000e);
cx25840_write4(client, DIF_BPF_COEFF45, 0x00200038);
cx25840_write4(client, DIF_BPF_COEFF67, 0x004c004f);
cx25840_write4(client, DIF_BPF_COEFF89, 0x002fffdf);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xff5cfeb6);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe0dfd92);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd7ffe03);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xff36010a);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x03410575);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x072607d2);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x071804d5);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x0134fcb7);
cx25840_write4(client, DIF_BPF_COEFF2627, 0xf81ff451);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf223f22e);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf4a7f94b);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xff6405e8);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x0bae0fa4);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 3300000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x0000ffff);
cx25840_write4(client, DIF_BPF_COEFF23, 0x00000008);
cx25840_write4(client, DIF_BPF_COEFF45, 0x001a0036);
cx25840_write4(client, DIF_BPF_COEFF67, 0x0056006d);
cx25840_write4(client, DIF_BPF_COEFF89, 0x00670030);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xffbdff10);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe46fd8d);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd25fd4f);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe35ffe0);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x0224049f);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x06c9080e);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x07ef0627);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x02c9fe45);
cx25840_write4(client, DIF_BPF_COEFF2627, 0xf961f513);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf250f1d2);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf3ecf869);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xfe930552);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x0b5f0f8f);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 3400000:
cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffe);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfffd0001);
cx25840_write4(client, DIF_BPF_COEFF45, 0x000f002c);
cx25840_write4(client, DIF_BPF_COEFF67, 0x0054007d);
cx25840_write4(client, DIF_BPF_COEFF89, 0x0093007c);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x0024ff82);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xfea6fdbb);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd03fcca);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd51feb9);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x00eb0392);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x06270802);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x08880750);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x044dffdb);
cx25840_write4(client, DIF_BPF_COEFF2627, 0xfabdf5f8);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf2a0f193);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf342f78f);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xfdc404b9);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x0b0e0f78);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 3500000:
cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffd);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfffafff9);
cx25840_write4(client, DIF_BPF_COEFF45, 0x0002001b);
cx25840_write4(client, DIF_BPF_COEFF67, 0x0046007d);
cx25840_write4(client, DIF_BPF_COEFF89, 0x00ad00ba);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x00870000);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xff26fe1a);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd1bfc7e);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc99fda4);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xffa5025c);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x054507ad);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x08dd0847);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x05b80172);
cx25840_write4(client, DIF_BPF_COEFF2627, 0xfc2ef6ff);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf313f170);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf2abf6bd);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xfcf6041f);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x0abc0f61);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 3600000:
cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffd);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8fff3);
cx25840_write4(client, DIF_BPF_COEFF45, 0xfff50006);
cx25840_write4(client, DIF_BPF_COEFF67, 0x002f006c);
cx25840_write4(client, DIF_BPF_COEFF89, 0x00b200e3);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x00dc007e);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xffb9fea0);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd6bfc71);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc17fcb1);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xfe65010b);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x042d0713);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x08ec0906);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x07020302);
cx25840_write4(client, DIF_BPF_COEFF2627, 0xfdaff823);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf3a7f16a);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf228f5f5);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xfc2a0384);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x0a670f4a);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 3700000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfff7ffef);
cx25840_write4(client, DIF_BPF_COEFF45, 0xffe9fff1);
cx25840_write4(client, DIF_BPF_COEFF67, 0x0010004d);
cx25840_write4(client, DIF_BPF_COEFF89, 0x00a100f2);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x011a00f0);
cx25840_write4(client, DIF_BPF_COEFF1213, 0x0053ff44);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfdedfca2);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xfbd3fbef);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xfd39ffae);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x02ea0638);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x08b50987);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x08230483);
cx25840_write4(client, DIF_BPF_COEFF2627, 0xff39f960);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf45bf180);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf1b8f537);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xfb6102e7);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x0a110f32);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 3800000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffe);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfff9ffee);
cx25840_write4(client, DIF_BPF_COEFF45, 0xffe1ffdd);
cx25840_write4(client, DIF_BPF_COEFF67, 0xfff00024);
cx25840_write4(client, DIF_BPF_COEFF89, 0x007c00e5);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x013a014a);
cx25840_write4(client, DIF_BPF_COEFF1213, 0x00e6fff8);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe98fd0f);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xfbd3fb67);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xfc32fe54);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x01880525);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x083909c7);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x091505ee);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x00c7fab3);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf52df1b4);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf15df484);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xfa9b0249);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x09ba0f19);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 3900000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00000000);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfffbfff0);
cx25840_write4(client, DIF_BPF_COEFF45, 0xffdeffcf);
cx25840_write4(client, DIF_BPF_COEFF67, 0xffd1fff6);
cx25840_write4(client, DIF_BPF_COEFF89, 0x004800be);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x01390184);
cx25840_write4(client, DIF_BPF_COEFF1213, 0x016300ac);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xff5efdb1);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc17fb23);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xfb5cfd0d);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x001703e4);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x077b09c4);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x09d2073c);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0251fc18);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf61cf203);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf118f3dc);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf9d801aa);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x09600eff);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 4000000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00000001);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfffefff4);
cx25840_write4(client, DIF_BPF_COEFF45, 0xffe1ffc8);
cx25840_write4(client, DIF_BPF_COEFF67, 0xffbaffca);
cx25840_write4(client, DIF_BPF_COEFF89, 0x000b0082);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x01170198);
cx25840_write4(client, DIF_BPF_COEFF1213, 0x01c10152);
cx25840_write4(client, DIF_BPF_COEFF1415, 0x0030fe7b);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xfc99fb24);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xfac3fbe9);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xfea5027f);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x0683097f);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a560867);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x03d2fd89);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf723f26f);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0e8f341);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf919010a);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x09060ee5);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 4100000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00010002);
cx25840_write4(client, DIF_BPF_COEFF23, 0x0002fffb);
cx25840_write4(client, DIF_BPF_COEFF45, 0xffe8ffca);
cx25840_write4(client, DIF_BPF_COEFF67, 0xffacffa4);
cx25840_write4(client, DIF_BPF_COEFF89, 0xffcd0036);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x00d70184);
cx25840_write4(client, DIF_BPF_COEFF1213, 0x01f601dc);
cx25840_write4(client, DIF_BPF_COEFF1415, 0x00ffff60);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xfd51fb6d);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa6efaf5);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xfd410103);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x055708f9);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a9e0969);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0543ff02);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf842f2f5);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0cef2b2);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf85e006b);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x08aa0ecb);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 4200000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00010003);
cx25840_write4(client, DIF_BPF_COEFF23, 0x00050003);
cx25840_write4(client, DIF_BPF_COEFF45, 0xfff3ffd3);
cx25840_write4(client, DIF_BPF_COEFF67, 0xffaaff8b);
cx25840_write4(client, DIF_BPF_COEFF89, 0xff95ffe5);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x0080014a);
cx25840_write4(client, DIF_BPF_COEFF1213, 0x01fe023f);
cx25840_write4(client, DIF_BPF_COEFF1415, 0x01ba0050);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe35fbf8);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa62fa3b);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xfbf9ff7e);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x04010836);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x0aa90a3d);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x069f007f);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xf975f395);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0cbf231);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf7a9ffcb);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x084c0eaf);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 4300000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00010003);
cx25840_write4(client, DIF_BPF_COEFF23, 0x0008000a);
cx25840_write4(client, DIF_BPF_COEFF45, 0x0000ffe4);
cx25840_write4(client, DIF_BPF_COEFF67, 0xffb4ff81);
cx25840_write4(client, DIF_BPF_COEFF89, 0xff6aff96);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x001c00f0);
cx25840_write4(client, DIF_BPF_COEFF1213, 0x01d70271);
cx25840_write4(client, DIF_BPF_COEFF1415, 0x0254013b);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xff36fcbd);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xfa9ff9c5);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xfadbfdfe);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x028c073b);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a750adf);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x07e101fa);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xfab8f44e);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf0ddf1be);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf6f9ff2b);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x07ed0e94);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 4400000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
cx25840_write4(client, DIF_BPF_COEFF23, 0x0009000f);
cx25840_write4(client, DIF_BPF_COEFF45, 0x000efff8);
cx25840_write4(client, DIF_BPF_COEFF67, 0xffc9ff87);
cx25840_write4(client, DIF_BPF_COEFF89, 0xff52ff54);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xffb5007e);
cx25840_write4(client, DIF_BPF_COEFF1213, 0x01860270);
cx25840_write4(client, DIF_BPF_COEFF1415, 0x02c00210);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x0044fdb2);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xfb22f997);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xf9f2fc90);
cx25840_write4(client, DIF_BPF_COEFF2223, 0x0102060f);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x0a050b4c);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0902036e);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xfc0af51e);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf106f15a);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf64efe8b);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x078d0e77);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 4500000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
cx25840_write4(client, DIF_BPF_COEFF23, 0x00080012);
cx25840_write4(client, DIF_BPF_COEFF45, 0x0019000e);
cx25840_write4(client, DIF_BPF_COEFF67, 0xffe5ff9e);
cx25840_write4(client, DIF_BPF_COEFF89, 0xff4fff25);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xff560000);
cx25840_write4(client, DIF_BPF_COEFF1213, 0x0112023b);
cx25840_write4(client, DIF_BPF_COEFF1415, 0x02f702c0);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x014dfec8);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xfbe5f9b3);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xf947fb41);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xff7004b9);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x095a0b81);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0a0004d8);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xfd65f603);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf144f104);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf5aafdec);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x072b0e5a);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 4600000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00000001);
cx25840_write4(client, DIF_BPF_COEFF23, 0x00060012);
cx25840_write4(client, DIF_BPF_COEFF45, 0x00200022);
cx25840_write4(client, DIF_BPF_COEFF67, 0x0005ffc1);
cx25840_write4(client, DIF_BPF_COEFF89, 0xff61ff10);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xff09ff82);
cx25840_write4(client, DIF_BPF_COEFF1213, 0x008601d7);
cx25840_write4(client, DIF_BPF_COEFF1415, 0x02f50340);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x0241fff0);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xfcddfa19);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8e2fa1e);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xfde30343);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x08790b7f);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0ad50631);
cx25840_write4(client, DIF_BPF_COEFF2829, 0xfec7f6fc);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf198f0bd);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf50dfd4e);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x06c90e3d);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 4700000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x0000ffff);
cx25840_write4(client, DIF_BPF_COEFF23, 0x0003000f);
cx25840_write4(client, DIF_BPF_COEFF45, 0x00220030);
cx25840_write4(client, DIF_BPF_COEFF67, 0x0025ffed);
cx25840_write4(client, DIF_BPF_COEFF89, 0xff87ff15);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xfed6ff10);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xffed014c);
cx25840_write4(client, DIF_BPF_COEFF1415, 0x02b90386);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x03110119);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xfdfefac4);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8c6f92f);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xfc6701b7);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x07670b44);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0b7e0776);
cx25840_write4(client, DIF_BPF_COEFF2829, 0x002df807);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf200f086);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf477fcb1);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x06650e1e);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 4800000:
cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffe);
cx25840_write4(client, DIF_BPF_COEFF23, 0xffff0009);
cx25840_write4(client, DIF_BPF_COEFF45, 0x001e0038);
cx25840_write4(client, DIF_BPF_COEFF67, 0x003f001b);
cx25840_write4(client, DIF_BPF_COEFF89, 0xffbcff36);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xfec2feb6);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xff5600a5);
cx25840_write4(client, DIF_BPF_COEFF1415, 0x0248038d);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x03b00232);
cx25840_write4(client, DIF_BPF_COEFF1819, 0xff39fbab);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xf8f4f87f);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xfb060020);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x062a0ad2);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0bf908a3);
cx25840_write4(client, DIF_BPF_COEFF2829, 0x0192f922);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf27df05e);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf3e8fc14);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x06000e00);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 4900000:
cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffd);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfffc0002);
cx25840_write4(client, DIF_BPF_COEFF45, 0x00160037);
cx25840_write4(client, DIF_BPF_COEFF67, 0x00510046);
cx25840_write4(client, DIF_BPF_COEFF89, 0xfff9ff6d);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xfed0fe7c);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xfecefff0);
cx25840_write4(client, DIF_BPF_COEFF1415, 0x01aa0356);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x0413032b);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x007ffcc5);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xf96cf812);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xf9cefe87);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x04c90a2c);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0c4309b4);
cx25840_write4(client, DIF_BPF_COEFF2829, 0x02f3fa4a);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf30ef046);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf361fb7a);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x059b0de0);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 5000000:
cx25840_write4(client, DIF_BPF_COEFF01, 0xfffffffd);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfff9fffa);
cx25840_write4(client, DIF_BPF_COEFF45, 0x000a002d);
cx25840_write4(client, DIF_BPF_COEFF67, 0x00570067);
cx25840_write4(client, DIF_BPF_COEFF89, 0x0037ffb5);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xfefffe68);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe62ff3d);
cx25840_write4(client, DIF_BPF_COEFF1415, 0x00ec02e3);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x043503f6);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x01befe05);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xfa27f7ee);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xf8c6fcf8);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x034c0954);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0c5c0aa4);
cx25840_write4(client, DIF_BPF_COEFF2829, 0x044cfb7e);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf3b1f03f);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf2e2fae1);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x05340dc0);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 5100000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffd);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8fff4);
cx25840_write4(client, DIF_BPF_COEFF45, 0xfffd001e);
cx25840_write4(client, DIF_BPF_COEFF67, 0x0051007b);
cx25840_write4(client, DIF_BPF_COEFF89, 0x006e0006);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xff48fe7c);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe1bfe9a);
cx25840_write4(client, DIF_BPF_COEFF1415, 0x001d023e);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x04130488);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x02e6ff5b);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xfb1ef812);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xf7f7fb7f);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x01bc084e);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0c430b72);
cx25840_write4(client, DIF_BPF_COEFF2829, 0x059afcba);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf467f046);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf26cfa4a);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x04cd0da0);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 5200000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x0000fffe);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfff8ffef);
cx25840_write4(client, DIF_BPF_COEFF45, 0xfff00009);
cx25840_write4(client, DIF_BPF_COEFF67, 0x003f007f);
cx25840_write4(client, DIF_BPF_COEFF89, 0x00980056);
cx25840_write4(client, DIF_BPF_COEFF1011, 0xffa5feb6);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe00fe15);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xff4b0170);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x03b004d7);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x03e800b9);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xfc48f87f);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xf768fa23);
cx25840_write4(client, DIF_BPF_COEFF2425, 0x0022071f);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0bf90c1b);
cx25840_write4(client, DIF_BPF_COEFF2829, 0x06dafdfd);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf52df05e);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf1fef9b5);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x04640d7f);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 5300000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x0000ffff);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfff9ffee);
cx25840_write4(client, DIF_BPF_COEFF45, 0xffe6fff3);
cx25840_write4(client, DIF_BPF_COEFF67, 0x00250072);
cx25840_write4(client, DIF_BPF_COEFF89, 0x00af009c);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x000cff10);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe13fdb8);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfe870089);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x031104e1);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x04b8020f);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xfd98f92f);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xf71df8f0);
cx25840_write4(client, DIF_BPF_COEFF2425, 0xfe8805ce);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0b7e0c9c);
cx25840_write4(client, DIF_BPF_COEFF2829, 0x0808ff44);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf603f086);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf19af922);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x03fb0d5e);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 5400000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00000001);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfffcffef);
cx25840_write4(client, DIF_BPF_COEFF45, 0xffe0ffe0);
cx25840_write4(client, DIF_BPF_COEFF67, 0x00050056);
cx25840_write4(client, DIF_BPF_COEFF89, 0x00b000d1);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x0071ff82);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xfe53fd8c);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfddfff99);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x024104a3);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x054a034d);
cx25840_write4(client, DIF_BPF_COEFF2021, 0xff01fa1e);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xf717f7ed);
cx25840_write4(client, DIF_BPF_COEFF2425, 0xfcf50461);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0ad50cf4);
cx25840_write4(client, DIF_BPF_COEFF2829, 0x0921008d);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf6e7f0bd);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf13ff891);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x03920d3b);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 5500000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00010002);
cx25840_write4(client, DIF_BPF_COEFF23, 0xfffffff3);
cx25840_write4(client, DIF_BPF_COEFF45, 0xffdeffd1);
cx25840_write4(client, DIF_BPF_COEFF67, 0xffe5002f);
cx25840_write4(client, DIF_BPF_COEFF89, 0x009c00ed);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x00cb0000);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xfebafd94);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd61feb0);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x014d0422);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x05970464);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x0074fb41);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xf759f721);
cx25840_write4(client, DIF_BPF_COEFF2425, 0xfb7502de);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x0a000d21);
cx25840_write4(client, DIF_BPF_COEFF2829, 0x0a2201d4);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf7d9f104);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf0edf804);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x03280d19);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 5600000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00010003);
cx25840_write4(client, DIF_BPF_COEFF23, 0x0003fffa);
cx25840_write4(client, DIF_BPF_COEFF45, 0xffe3ffc9);
cx25840_write4(client, DIF_BPF_COEFF67, 0xffc90002);
cx25840_write4(client, DIF_BPF_COEFF89, 0x007500ef);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x010e007e);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xff3dfdcf);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd16fddd);
cx25840_write4(client, DIF_BPF_COEFF1617, 0x00440365);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x059b0548);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x01e3fc90);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xf7dff691);
cx25840_write4(client, DIF_BPF_COEFF2425, 0xfa0f014d);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x09020d23);
cx25840_write4(client, DIF_BPF_COEFF2829, 0x0b0a0318);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf8d7f15a);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf0a5f779);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x02bd0cf6);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 5700000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00010003);
cx25840_write4(client, DIF_BPF_COEFF23, 0x00060001);
cx25840_write4(client, DIF_BPF_COEFF45, 0xffecffc9);
cx25840_write4(client, DIF_BPF_COEFF67, 0xffb4ffd4);
cx25840_write4(client, DIF_BPF_COEFF89, 0x004000d5);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x013600f0);
cx25840_write4(client, DIF_BPF_COEFF1213, 0xffd3fe39);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd04fd31);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xff360277);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x055605ef);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x033efdfe);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xf8a5f642);
cx25840_write4(client, DIF_BPF_COEFF2425, 0xf8cbffb6);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x07e10cfb);
cx25840_write4(client, DIF_BPF_COEFF2829, 0x0bd50456);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xf9dff1be);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf067f6f2);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x02520cd2);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 5800000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00000003);
cx25840_write4(client, DIF_BPF_COEFF23, 0x00080009);
cx25840_write4(client, DIF_BPF_COEFF45, 0xfff8ffd2);
cx25840_write4(client, DIF_BPF_COEFF67, 0xffaaffac);
cx25840_write4(client, DIF_BPF_COEFF89, 0x000200a3);
cx25840_write4(client, DIF_BPF_COEFF1011, 0x013c014a);
cx25840_write4(client, DIF_BPF_COEFF1213, 0x006dfec9);
cx25840_write4(client, DIF_BPF_COEFF1415, 0xfd2bfcb7);
cx25840_write4(client, DIF_BPF_COEFF1617, 0xfe350165);
cx25840_write4(client, DIF_BPF_COEFF1819, 0x04cb0651);
cx25840_write4(client, DIF_BPF_COEFF2021, 0x0477ff7e);
cx25840_write4(client, DIF_BPF_COEFF2223, 0xf9a5f635);
cx25840_write4(client, DIF_BPF_COEFF2425, 0xf7b1fe20);
cx25840_write4(client, DIF_BPF_COEFF2627, 0x069f0ca8);
cx25840_write4(client, DIF_BPF_COEFF2829, 0x0c81058b);
cx25840_write4(client, DIF_BPF_COEFF3031, 0xfaf0f231);
cx25840_write4(client, DIF_BPF_COEFF3233, 0xf033f66d);
cx25840_write4(client, DIF_BPF_COEFF3435, 0x01e60cae);
cx25840_write4(client, DIF_BPF_COEFF36, 0x110d0000);
break;
case 5900000:
cx25840_write4(client, DIF_BPF_COEFF01, 0x00000002);
cx25840_write4(client, DIF_BPF_COEFF23, 0x0009000e);
cx25840_write4(client, DIF_BPF_COEFF45, 0x0005ffe1);