/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Thu Jan 29 15:29:44 2009
 *                 MD5 Checksum         0a9f974b7551a1ff1e1f6c0bddfbd2ab
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7405/rdb/d0/bchp_sun_top_ctrl.h $
 * 
 * Hydra_Software_Devel/1   1/29/09 11:02p albertl
 * PR51716: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_SUN_TOP_CTRL_H__
#define BCHP_SUN_TOP_CTRL_H__

/***************************************************************************
 *SUN_TOP_CTRL - Top Control registers
 ***************************************************************************/
#define BCHP_SUN_TOP_CTRL_PROD_REVISION          0x00404000 /* Product Revision ID */
#define BCHP_SUN_TOP_CTRL_SUN_REVISION           0x00404004 /* Sundry Revision ID */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404008 /* Reset control */
#define BCHP_SUN_TOP_CTRL_SW_RESET               0x00404014 /* Software reset register */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404018 /* Reset history */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST        0x00404028 /* OTP option test register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS      0x0040402c /* OTP option status register */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404030 /* Semaphore channel 0 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x00404034 /* Semaphore channel 1 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404038 /* Semaphore channel 2 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x0040403c /* Semaphore channel 3 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404040 /* Semaphore channel 4 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x00404044 /* Semaphore channel 5 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404048 /* Semaphore channel 6 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x0040404c /* Semaphore channel 7 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404050 /* Semaphore channel 8 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x00404054 /* Semaphore channel 9 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404058 /* Semaphore channel 10 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x0040405c /* Semaphore channel 11 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404060 /* Semaphore channel 12 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x00404064 /* Semaphore channel 13 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404068 /* Semaphore channel 14 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x0040406c /* Semaphore channel 15 */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404070 /* General watchdog timer 0 */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x00404074 /* General watchdog timer 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404078 /* General control register 0 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x0040407c /* General control register 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404080 /* General control register 2 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404084 /* General status register 0 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x00404088 /* General status register 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x0040408c /* General status register 2 */
#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x00404090 /* Scratch register */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pin mux control register 0 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pin mux control register 1 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pin mux control register 2 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pin mux control register 3 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pin mux control register 4 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pin mux control register 5 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pin mux control register 6 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pin mux control register 7 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pin mux control register 8 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pin mux control register 9 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pin mux control register 10 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pin mux control register 11 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pin mux control register 12 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pin mux control register 13 */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404200 /* Test port control */
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404208 /* EJTAG input bus enables */
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x0040420c /* EJTAG output select */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x00404210 /* UART Router select */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x0040421c /* Serial Slave Port configuration register */
#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404220 /* SERS Revision Register */
#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404224 /* SERS Configuration Register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404280 /* Testport peek register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404284 /* Testport poke register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x00404288 /* Testport peek register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x0040428c /* Testport poke register */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x00404300 /* Spare control bits reserved for future use */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404400 /* Block select for RO testmode */
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL          0x00404404 /* Simultaneous switching testmode control */
#define BCHP_SUN_TOP_CTRL_TEST_MODE              0x00404408 /* Testmode register */

/***************************************************************************
 *PROD_REVISION - Product Revision ID
 ***************************************************************************/
/* SUN_TOP_CTRL :: PROD_REVISION :: product_revision [31:00] */
#define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_MASK      0xffffffff
#define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_SHIFT     0

/***************************************************************************
 *SUN_REVISION - Sundry Revision ID
 ***************************************************************************/
/* SUN_TOP_CTRL :: SUN_REVISION :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_MASK              0xffff0000
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_SHIFT             16

/* SUN_TOP_CTRL :: SUN_REVISION :: sundry_revision [15:00] */
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_MASK        0x0000ffff
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_SHIFT       0

/***************************************************************************
 *RESET_CTRL - Reset control
 ***************************************************************************/
/* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_monitor [31:31] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_MASK       0x80000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_SHIFT      31

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_monitor [30:30] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_MASK 0x40000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_SHIFT 30

/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [29:12] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0x3ffff000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               12

/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [11:11] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000800
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     11

/* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable_lock [10:10] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_SHIFT 10

/* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable [09:09] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_SHIFT 9

/* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable_lock [08:08] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_SHIFT 8

/* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable [07:07] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_MASK    0x00000080
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_SHIFT   7

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [06:06] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 6

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable [05:05] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT 5

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_polarity [04:04] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT 4

/* SUN_TOP_CTRL :: RESET_CTRL :: master_reset_en [03:03] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_MASK          0x00000008
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_SHIFT         3

/* SUN_TOP_CTRL :: RESET_CTRL :: reserved1 [02:02] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_MASK                0x00000004
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_SHIFT               2

/* SUN_TOP_CTRL :: RESET_CTRL :: sc_insert_reset_en [01:00] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_MASK       0x00000003
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_SHIFT      0

/***************************************************************************
 *SW_RESET - Software reset register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SW_RESET :: chip_master_reset [31:31] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_MASK          0x80000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_SHIFT         31

/* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_1shot [30:30] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_MASK         0x40000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_SHIFT        30

/* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_1shot [29:29] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_MASK        0x20000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_SHIFT       29

/* SUN_TOP_CTRL :: SW_RESET :: pci_rstb_out_sw_reset [28:28] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_pci_rstb_out_sw_reset_MASK      0x10000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_pci_rstb_out_sw_reset_SHIFT     28

/* SUN_TOP_CTRL :: SW_RESET :: reserved0 [27:26] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_MASK                  0x0c000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_SHIFT                 26

/* SUN_TOP_CTRL :: SW_RESET :: avd0_sw_reset [25:25] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_MASK              0x02000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_SHIFT             25

/* SUN_TOP_CTRL :: SW_RESET :: aio_sw_reset [24:24] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_aio_sw_reset_MASK               0x01000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_aio_sw_reset_SHIFT              24

/* SUN_TOP_CTRL :: SW_RESET :: rptd_sw_reset [23:23] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_rptd_sw_reset_MASK              0x00800000
#define BCHP_SUN_TOP_CTRL_SW_RESET_rptd_sw_reset_SHIFT             23

/* SUN_TOP_CTRL :: SW_RESET :: bvnm_sw_reset [22:22] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_bvnm_sw_reset_MASK              0x00400000
#define BCHP_SUN_TOP_CTRL_SW_RESET_bvnm_sw_reset_SHIFT             22

/* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_level [21:21] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_MASK        0x00200000
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_SHIFT       21

/* SUN_TOP_CTRL :: SW_RESET :: usb_sw_reset [20:20] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_usb_sw_reset_MASK               0x00100000
#define BCHP_SUN_TOP_CTRL_SW_RESET_usb_sw_reset_SHIFT              20

/* SUN_TOP_CTRL :: SW_RESET :: reserved1 [19:19] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved1_MASK                  0x00080000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved1_SHIFT                 19

/* SUN_TOP_CTRL :: SW_RESET :: sata_sw_reset [18:18] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_sata_sw_reset_MASK              0x00040000
#define BCHP_SUN_TOP_CTRL_SW_RESET_sata_sw_reset_SHIFT             18

/* SUN_TOP_CTRL :: SW_RESET :: memc_gfx_sw_reset [17:17] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_memc_gfx_sw_reset_MASK          0x00020000
#define BCHP_SUN_TOP_CTRL_SW_RESET_memc_gfx_sw_reset_SHIFT         17

/* SUN_TOP_CTRL :: SW_RESET :: reserved2 [16:15] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved2_MASK                  0x00018000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved2_SHIFT                 15

/* SUN_TOP_CTRL :: SW_RESET :: bvn_mad_sw_reset [14:14] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_mad_sw_reset_MASK           0x00004000
#define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_mad_sw_reset_SHIFT          14

/* SUN_TOP_CTRL :: SW_RESET :: xpt_sw_reset [13:13] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_MASK               0x00002000
#define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_SHIFT              13

/* SUN_TOP_CTRL :: SW_RESET :: reserved3 [12:12] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved3_MASK                  0x00001000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved3_SHIFT                 12

/* SUN_TOP_CTRL :: SW_RESET :: vec_sw_reset [11:11] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_vec_sw_reset_MASK               0x00000800
#define BCHP_SUN_TOP_CTRL_SW_RESET_vec_sw_reset_SHIFT              11

/* SUN_TOP_CTRL :: SW_RESET :: bvn_edge_sw_reset [10:10] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_edge_sw_reset_MASK          0x00000400
#define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_edge_sw_reset_SHIFT         10

/* SUN_TOP_CTRL :: SW_RESET :: hdmi_sw_reset [09:09] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_hdmi_sw_reset_MASK              0x00000200
#define BCHP_SUN_TOP_CTRL_SW_RESET_hdmi_sw_reset_SHIFT             9

/* SUN_TOP_CTRL :: SW_RESET :: reserved4 [08:07] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved4_MASK                  0x00000180
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved4_SHIFT                 7

/* SUN_TOP_CTRL :: SW_RESET :: rfm_sw_reset [06:06] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_rfm_sw_reset_MASK               0x00000040
#define BCHP_SUN_TOP_CTRL_SW_RESET_rfm_sw_reset_SHIFT              6

/* SUN_TOP_CTRL :: SW_RESET :: jtag_otp_sw_reset [05:05] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_MASK          0x00000020
#define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_SHIFT         5

/* SUN_TOP_CTRL :: SW_RESET :: enet_sw_reset [04:04] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_enet_sw_reset_MASK              0x00000010
#define BCHP_SUN_TOP_CTRL_SW_RESET_enet_sw_reset_SHIFT             4

/* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_level [03:03] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_MASK         0x00000008
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_SHIFT        3

/* SUN_TOP_CTRL :: SW_RESET :: ebi_sw_reset [02:02] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ebi_sw_reset_MASK               0x00000004
#define BCHP_SUN_TOP_CTRL_SW_RESET_ebi_sw_reset_SHIFT              2

/* SUN_TOP_CTRL :: SW_RESET :: pci_sw_reset [01:01] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_pci_sw_reset_MASK               0x00000002
#define BCHP_SUN_TOP_CTRL_SW_RESET_pci_sw_reset_SHIFT              1

/* SUN_TOP_CTRL :: SW_RESET :: sundry_sw_reset [00:00] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_MASK            0x00000001
#define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_SHIFT           0

/***************************************************************************
 *RESET_HISTORY - Reset history
 ***************************************************************************/
/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:12] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffff000
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            12

/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset [11:11] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_MASK   0x00000800
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_SHIFT  11

/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_sft_sft_rst_b [10:10] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_SHIFT 10

/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_hrd_sft_rst_b [09:09] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_SHIFT 9

/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [08:08] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 8

/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset [07:07] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_MASK  0x00000080
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_SHIFT 7

/* SUN_TOP_CTRL :: RESET_HISTORY :: special_sw_reset [06:06] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_MASK      0x00000040
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_SHIFT     6

/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved1 [05:05] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_MASK             0x00000020
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_SHIFT            5

/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [04:04] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000010
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 4

/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [03:03] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 3

/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [02:02] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 2

/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1

/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0

/***************************************************************************
 *STRAP_VALUE_0 - Strapping values
 ***************************************************************************/
/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_bch_enable [31:31] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_bch_enable_MASK      0x80000000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_bch_enable_SHIFT     31

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_external_mpi_arbiter [30:30] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_external_mpi_arbiter_MASK 0x40000000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_external_mpi_arbiter_SHIFT 30

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [29:29] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x20000000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 29

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_test_debug_en [28:27] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_test_debug_en_MASK   0x18000000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_test_debug_en_SHIFT  27

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_nmi_polarity [26:26] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_nmi_polarity_MASK    0x04000000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_nmi_polarity_SHIFT   26

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_sel_33_27_mhz_clock [25:25] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_sel_33_27_mhz_clock_MASK 0x02000000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_sel_33_27_mhz_clock_SHIFT 25

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ddr1_device_config [24:23] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ddr1_device_config_MASK 0x01800000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ddr1_device_config_SHIFT 23

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ddr0_device_config [22:21] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ddr0_device_config_MASK 0x00600000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ddr0_device_config_SHIFT 21

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_rom_size [20:19] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_rom_size_MASK    0x00180000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_rom_size_SHIFT   19

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_invert_addr [18:18] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_invert_addr_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_invert_addr_SHIFT 18

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_boot_memory [17:17] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_boot_memory_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_boot_memory_SHIFT 17

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_usb_mode [16:16] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_usb_mode_MASK        0x00010000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_usb_mode_SHIFT       16

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ddr_configuration [15:13] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ddr_configuration_MASK 0x0000e000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ddr_configuration_SHIFT 13

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [12:12] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 12

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_cs_swap [11:11] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_cs_swap_MASK     0x00000800
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_cs_swap_SHIFT    11

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_spi_slave_enable [10:10] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spi_slave_enable_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_spi_slave_enable_SHIFT 10

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pci_memwin_size [09:08] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_memwin_size_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_memwin_size_SHIFT 8

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pci_memwin2_en [07:07] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_memwin2_en_MASK  0x00000080
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_memwin2_en_SHIFT 7

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pci_memwin1_en [06:06] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_memwin1_en_MASK  0x00000040
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_memwin1_en_SHIFT 6

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pci_client [05:05] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_client_MASK      0x00000020
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_client_SHIFT     5

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_cpu_freq [04:02] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_cpu_freq_MASK        0x0000001c
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_cpu_freq_SHIFT       2

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_rom_type [01:01] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_rom_type_MASK   0x00000002
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_rom_type_SHIFT  1

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_ext_mode [00:00] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_ext_mode_MASK  0x00000001
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_ext_mode_SHIFT 0

/***************************************************************************
 *STRAP_VALUE_1 - Strapping values
 ***************************************************************************/
/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:03] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff8
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            3

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_2 [02:02] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_SHIFT 2

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_1_SHIFT 1

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_0_SHIFT 0

/***************************************************************************
 *BOND_STATUS - Bond option value register
 ***************************************************************************/
/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1

/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0

/***************************************************************************
 *OTP_OPTION_TEST - OTP option test register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: reserved0 [31:29] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_reserved0_MASK           0xe0000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_reserved0_SHIFT          29

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_3d_disable [28:28] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_3d_disable_MASK 0x10000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_3d_disable_SHIFT 28

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_spare_jtag_otp_8 [27:27] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_8_MASK 0x08000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_8_SHIFT 27

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_spare_jtag_otp_7 [26:26] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_7_MASK 0x04000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_7_SHIFT 26

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_spare_jtag_otp_6 [25:25] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_6_MASK 0x02000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_6_SHIFT 25

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_spare_jtag_otp_5 [24:24] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_5_MASK 0x01000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_5_SHIFT 24

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_spare_jtag_otp_4 [23:23] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_4_MASK 0x00800000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_4_SHIFT 23

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_spare_jtag_otp_3 [22:22] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_3_MASK 0x00400000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_3_SHIFT 22

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_spare_jtag_otp_2 [21:21] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_2_MASK 0x00200000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_2_SHIFT 21

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_spare_jtag_otp_1 [20:20] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_1_MASK 0x00100000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_1_SHIFT 20

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_spare_jtag_otp_0 [19:19] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_0_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_spare_jtag_otp_0_SHIFT 19

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_bsp_spare_3 [18:18] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_bsp_spare_3_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_bsp_spare_3_SHIFT 18

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_bsp_spare_2 [17:17] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_bsp_spare_2_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_bsp_spare_2_SHIFT 17

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_bsp_spare_1 [16:16] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_bsp_spare_1_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_bsp_spare_1_SHIFT 16

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_bsp_spare_0 [15:15] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_bsp_spare_0_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_bsp_spare_0_SHIFT 15

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_sata_disable [14:14] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_sata_disable_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_sata_disable_SHIFT 14

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_audio_spdif_disable [13:13] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_audio_spdif_disable_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_audio_spdif_disable_SHIFT 13

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_en_cr [12:11] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_en_cr_MASK    0x00001800
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_en_cr_SHIFT   11

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_en_pci_ebi [10:10] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_en_pci_ebi_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_en_pci_ebi_SHIFT 10

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_en_testport [09:09] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_en_testport_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_en_testport_SHIFT 9

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_en_hd_display [08:08] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_en_hd_display_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_en_hd_display_SHIFT 8

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_ebi_cs_swap_ovrd [07:07] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_ebi_cs_swap_ovrd_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_ebi_cs_swap_ovrd_SHIFT 7

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_int_daa_disable [06:06] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_int_daa_disable_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_int_daa_disable_SHIFT 6

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_hdcp_disable [05:05] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_hdcp_disable_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_hdcp_disable_SHIFT 5

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_macrovision_enable [04:04] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_macrovision_enable_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_macrovision_enable_SHIFT 4

/* SUN_TOP_CTRL :: OTP_OPTION_TEST :: otp_option_product_id [03:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_product_id_MASK 0x0000000f
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_otp_option_product_id_SHIFT 0

/***************************************************************************
 *OTP_OPTION_STATUS - OTP option status register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: reserved0 [31:29] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_reserved0_MASK         0xe0000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_reserved0_SHIFT        29

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_3d_disable [28:28] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_3d_disable_MASK 0x10000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_3d_disable_SHIFT 28

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_spare_jtag_otp_8 [27:27] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_8_MASK 0x08000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_8_SHIFT 27

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_spare_jtag_otp_7 [26:26] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_7_MASK 0x04000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_7_SHIFT 26

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_spare_jtag_otp_6 [25:25] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_6_MASK 0x02000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_6_SHIFT 25

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_spare_jtag_otp_5 [24:24] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_5_MASK 0x01000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_5_SHIFT 24

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_spare_jtag_otp_4 [23:23] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_4_MASK 0x00800000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_4_SHIFT 23

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_spare_jtag_otp_3 [22:22] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_3_MASK 0x00400000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_3_SHIFT 22

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_spare_jtag_otp_2 [21:21] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_2_MASK 0x00200000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_2_SHIFT 21

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_spare_jtag_otp_1 [20:20] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_1_MASK 0x00100000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_1_SHIFT 20

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_spare_jtag_otp_0 [19:19] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_0_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_spare_jtag_otp_0_SHIFT 19

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_bsp_spare_3 [18:18] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_bsp_spare_3_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_bsp_spare_3_SHIFT 18

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_bsp_spare_2 [17:17] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_bsp_spare_2_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_bsp_spare_2_SHIFT 17

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_bsp_spare_1 [16:16] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_bsp_spare_1_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_bsp_spare_1_SHIFT 16

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_bsp_spare_0 [15:15] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_bsp_spare_0_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_bsp_spare_0_SHIFT 15

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_sata_disable [14:14] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_sata_disable_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_sata_disable_SHIFT 14

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_audio_spdif_disable [13:13] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_audio_spdif_disable_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_audio_spdif_disable_SHIFT 13

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_en_cr [12:11] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_en_cr_MASK  0x00001800
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_en_cr_SHIFT 11

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_en_pci_ebi [10:10] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_en_pci_ebi_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_en_pci_ebi_SHIFT 10

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_en_testport [09:09] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_en_testport_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_en_testport_SHIFT 9

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_en_hd_display [08:08] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_en_hd_display_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_en_hd_display_SHIFT 8

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_ebi_cs_swap_ovrd [07:07] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_ebi_cs_swap_ovrd_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_ebi_cs_swap_ovrd_SHIFT 7

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_int_daa_disable [06:06] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_int_daa_disable_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_int_daa_disable_SHIFT 6

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_hdcp_disable [05:05] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_hdcp_disable_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_hdcp_disable_SHIFT 5

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_macrovision_enable [04:04] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_macrovision_enable_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_macrovision_enable_SHIFT 4

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS :: otp_option_product_id [03:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_product_id_MASK 0x0000000f
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_otp_option_product_id_SHIFT 0

/***************************************************************************
 *SEMAPHORE_0 - Semaphore channel 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_1 - Semaphore channel 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_2 - Semaphore channel 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_3 - Semaphore channel 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_4 - Semaphore channel 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_5 - Semaphore channel 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_6 - Semaphore channel 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_7 - Semaphore channel 7
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_8 - Semaphore channel 8
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_9 - Semaphore channel 9
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_10 - Semaphore channel 10
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_11 - Semaphore channel 11
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_12 - Semaphore channel 12
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_13 - Semaphore channel 13
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_14 - Semaphore channel 14
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_15 - Semaphore channel 15
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *GEN_WATCHDOG_0 - General watchdog timer 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0

/***************************************************************************
 *GEN_WATCHDOG_1 - General watchdog timer 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_0 - General control register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_reserved [31:25] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_reserved_MASK    0xfe000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_reserved_SHIFT   25

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_burst_stat_sel [24:24] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_burst_stat_sel_MASK 0x01000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_burst_stat_sel_SHIFT 24

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_access_mode [23:22] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_access_mode_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_access_mode_SHIFT 22

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_otp_prog_en [21:21] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_prog_en_MASK 0x00200000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_prog_en_SHIFT 21

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_otp_debug_mode [20:20] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_debug_mode_MASK 0x00100000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_debug_mode_SHIFT 20

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_continue_on_fail [19:19] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_continue_on_fail_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_continue_on_fail_SHIFT 19

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_time_margin [18:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_time_margin_MASK 0x00070000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_time_margin_SHIFT 16

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_sadbyp [15:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_sadbyp_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_sadbyp_SHIFT 15

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_unused [14:14] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_unused_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_unused_SHIFT 14

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_pbyp [13:13] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pbyp_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pbyp_SHIFT 13

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_pcount [12:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pcount_MASK 0x00001c00
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pcount_SHIFT 10

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_vsel [09:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_vsel_MASK 0x000003c0
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_vsel_SHIFT 6

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_prog_sel [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_prog_sel_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_prog_sel_SHIFT 5

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_command [04:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_command_MASK 0x0000001e
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_command_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_start [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_start_MASK  0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_start_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_1 - General control register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: jtag_otp_cpu_addr [31:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_addr_MASK    0xffff0000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_addr_SHIFT   16

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_11 [11:11] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_MASK     0x00000800
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_11_SHIFT    11

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: daa_testmode [10:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_testmode_MASK         0x00000400
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_testmode_SHIFT        10

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: daa_iddq [09:09] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_iddq_MASK             0x00000200
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_iddq_SHIFT            9

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: daa_bypass [08:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_bypass_MASK           0x00000100
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_bypass_SHIFT          8

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_ana_pwrdn [07:07] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_ana_pwrdn_MASK       0x00000080
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_ana_pwrdn_SHIFT      7

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_force_sata_mode [06:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_force_sata_mode_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_force_sata_mode_SHIFT 6

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_3g_mode [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_3g_mode_MASK         0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_3g_mode_SHIFT        5

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_pll_seq_start [04:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_pll_seq_start_MASK   0x00000010
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_pll_seq_start_SHIFT  4

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_stb_oob [03:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_stb_oob_MASK         0x00000008
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_stb_oob_SHIFT        3

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_pll_int_ref_clk_sel [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_pll_int_ref_clk_sel_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_pll_int_ref_clk_sel_SHIFT 2

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: sata_ext_mdio_en [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_ext_mdio_en_MASK     0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_sata_ext_mdio_en_SHIFT    1

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: jtag_otp_cpu_mode [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_mode_MASK    0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_mode_SHIFT   0

/***************************************************************************
 *GENERAL_CTRL_2 - General control register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: spare_general_ctrl_2 [31:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_spare_general_ctrl_2_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_spare_general_ctrl_2_SHIFT 0

/***************************************************************************
 *GENERAL_STATUS_0 - General status register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: jtag_otp_data_out [31:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_jtag_otp_data_out_MASK  0xffffffff
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_jtag_otp_data_out_SHIFT 0

/***************************************************************************
 *GENERAL_STATUS_1 - General status register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xffffff00
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         8

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: jtag_otp_status [07:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_jtag_otp_status_MASK    0x000000ff
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_jtag_otp_status_SHIFT   0

/***************************************************************************
 *GENERAL_STATUS_2 - General status register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xffff0000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         16

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_15 [15:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_15_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_15_SHIFT 15

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_14 [14:14] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_14_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_14_SHIFT 14

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_13 [13:13] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_13_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_13_SHIFT 13

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_12 [12:12] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_12_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_12_SHIFT 12

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_11 [11:11] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_11_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_11_SHIFT 11

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_10 [10:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_10_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_10_SHIFT 10

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_09 [09:09] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_09_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_09_SHIFT 9

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_08 [08:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_08_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_08_SHIFT 8

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_07 [07:07] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_07_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_07_SHIFT 7

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_06 [06:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_06_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_06_SHIFT 6

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_05 [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_05_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_05_SHIFT 5

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_04 [04:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_04_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_04_SHIFT 4

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_03 [03:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_03_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_03_SHIFT 3

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_02 [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_02_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_02_SHIFT 2

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_01 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_01_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_01_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_00 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_00_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_00_SHIFT 0

/***************************************************************************
 *UNCLEARED_SCRATCH - Scratch register
 ***************************************************************************/
/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0

/***************************************************************************
 *PIN_MUX_CTRL_0 - Pin mux control register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad06 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad06_MASK             0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad06_SHIFT            30

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad05 [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad05_MASK             0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad05_SHIFT            28

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad04 [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad04_MASK             0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad04_SHIFT            26

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad03 [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad03_MASK             0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad03_SHIFT            24

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad02 [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad02_MASK             0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad02_SHIFT            22

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad01 [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad01_MASK             0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad01_SHIFT            20

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad00 [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad00_MASK             0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad00_SHIFT            18

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: vo_656_clk [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_clk_MASK           0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_clk_SHIFT          16

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: vo_656_7 [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_7_MASK             0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_7_SHIFT            14

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: vo_656_6 [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_6_MASK             0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_6_SHIFT            12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: vo_656_5 [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_5_MASK             0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_5_SHIFT            10

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: vo_656_4 [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_4_MASK             0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_4_SHIFT            8

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: vo_656_3 [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_3_MASK             0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_3_SHIFT            6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: vo_656_2 [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_2_MASK             0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_2_SHIFT            4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: vo_656_1 [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_1_MASK             0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_1_SHIFT            2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: vo_656_0 [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_0_MASK             0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_vo_656_0_SHIFT            0

/***************************************************************************
 *PIN_MUX_CTRL_1 - Pin mux control register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad22 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad22_MASK             0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad22_SHIFT            30

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad21 [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad21_MASK             0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad21_SHIFT            28

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad20 [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad20_MASK             0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad20_SHIFT            26

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad19 [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad19_MASK             0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad19_SHIFT            24

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad18 [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad18_MASK             0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad18_SHIFT            22

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad17 [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad17_MASK             0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad17_SHIFT            20

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad16 [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad16_MASK             0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad16_SHIFT            18

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad15 [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad15_MASK             0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad15_SHIFT            16

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad14 [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad14_MASK             0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad14_SHIFT            14

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad13 [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad13_MASK             0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad13_SHIFT            12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad12 [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad12_MASK             0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad12_SHIFT            10

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad11 [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad11_MASK             0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad11_SHIFT            8

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad10 [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad10_MASK             0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad10_SHIFT            6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad09 [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad09_MASK             0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad09_SHIFT            4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad08 [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad08_MASK             0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad08_SHIFT            2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad07 [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad07_MASK             0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad07_SHIFT            0

/***************************************************************************
 *PIN_MUX_CTRL_2 - Pin mux control register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_003 [31:29] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_MASK             0xe0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_003_SHIFT            29

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_002 [28:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_MASK             0x1c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_002_SHIFT            26

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_001 [25:23] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_MASK             0x03800000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_001_SHIFT            23

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_000 [22:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_MASK             0x00700000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_000_SHIFT            20

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: daa_aout [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_daa_aout_MASK             0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_daa_aout_SHIFT            18

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad31 [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad31_MASK             0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad31_SHIFT            16

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad30 [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad30_MASK             0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad30_SHIFT            14

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad29 [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad29_MASK             0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad29_SHIFT            12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad28 [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad28_MASK             0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad28_SHIFT            10

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad27 [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad27_MASK             0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad27_SHIFT            8

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad26 [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad26_MASK             0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad26_SHIFT            6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad25 [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad25_MASK             0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad25_SHIFT            4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad24 [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad24_MASK             0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad24_SHIFT            2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad23 [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad23_MASK             0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad23_SHIFT            0

/***************************************************************************
 *PIN_MUX_CTRL_3 - Pin mux control register 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_reserved0_MASK            0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT           30

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_013 [29:27] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_MASK             0x38000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_013_SHIFT            27

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_012 [26:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_MASK             0x07000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_012_SHIFT            24

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_011 [23:21] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_MASK             0x00e00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_011_SHIFT            21

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_010 [20:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_MASK             0x001c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_010_SHIFT            18

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_009 [17:15] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_MASK             0x00038000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_009_SHIFT            15

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_008 [14:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_MASK             0x00007000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_008_SHIFT            12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_007 [11:09] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_MASK             0x00000e00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_007_SHIFT            9

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_006 [08:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_MASK             0x000001c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_006_SHIFT            6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_005 [05:03] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_MASK             0x00000038
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_005_SHIFT            3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_004 [02:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_MASK             0x00000007
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_004_SHIFT            0

/***************************************************************************
 *PIN_MUX_CTRL_4 - Pin mux control register 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: reserved0 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_reserved0_MASK            0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_reserved0_SHIFT           30

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_023 [29:27] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_MASK             0x38000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_023_SHIFT            27

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_022 [26:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_MASK             0x07000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_022_SHIFT            24

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_021 [23:21] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_MASK             0x00e00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_021_SHIFT            21

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_020 [20:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_MASK             0x001c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_020_SHIFT            18

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_019 [17:15] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_MASK             0x00038000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_019_SHIFT            15

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_018 [14:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_MASK             0x00007000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_018_SHIFT            12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_017 [11:09] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_MASK             0x00000e00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_017_SHIFT            9

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_016 [08:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_016_MASK             0x000001c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_016_SHIFT            6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_015 [05:03] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_015_MASK             0x00000038
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_015_SHIFT            3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_014 [02:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_014_MASK             0x00000007
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_014_SHIFT            0

/***************************************************************************
 *PIN_MUX_CTRL_5 - Pin mux control register 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: reserved0 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_reserved0_MASK            0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_reserved0_SHIFT           30

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_033 [29:27] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_033_MASK             0x38000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_033_SHIFT            27

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_032 [26:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_MASK             0x07000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_032_SHIFT            24

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_031 [23:21] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_MASK             0x00e00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_031_SHIFT            21

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_030 [20:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_MASK             0x001c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_030_SHIFT            18

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_029 [17:15] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_MASK             0x00038000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_029_SHIFT            15

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_028 [14:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_MASK             0x00007000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_028_SHIFT            12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_027 [11:09] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_MASK             0x00000e00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_027_SHIFT            9

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_026 [08:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_MASK             0x000001c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_026_SHIFT            6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_025 [05:03] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_MASK             0x00000038
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_025_SHIFT            3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_024 [02:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_024_MASK             0x00000007
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_024_SHIFT            0

/***************************************************************************
 *PIN_MUX_CTRL_6 - Pin mux control register 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: reserved0 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_reserved0_MASK            0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_reserved0_SHIFT           30

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_043 [29:27] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_043_MASK             0x38000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_043_SHIFT            27

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_042 [26:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_042_MASK             0x07000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_042_SHIFT            24

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_041 [23:21] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_041_MASK             0x00e00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_041_SHIFT            21

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_040 [20:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_MASK             0x001c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_040_SHIFT            18

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_039 [17:15] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_MASK             0x00038000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_039_SHIFT            15

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_038 [14:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_MASK             0x00007000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_038_SHIFT            12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_037 [11:09] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_MASK             0x00000e00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_037_SHIFT            9

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_036 [08:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_MASK             0x000001c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_036_SHIFT            6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_035 [05:03] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_MASK             0x00000038
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_035_SHIFT            3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_034 [02:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_MASK             0x00000007
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_034_SHIFT            0

/***************************************************************************
 *PIN_MUX_CTRL_7 - Pin mux control register 7
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: reserved0 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_reserved0_MASK            0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_reserved0_SHIFT           30

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_053 [29:27] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_053_MASK             0x38000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_053_SHIFT            27

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_052 [26:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_052_MASK             0x07000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_052_SHIFT            24

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_051 [23:21] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_051_MASK             0x00e00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_051_SHIFT            21

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_050 [20:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_050_MASK             0x001c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_050_SHIFT            18

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_049 [17:15] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_049_MASK             0x00038000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_049_SHIFT            15

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_048 [14:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_MASK             0x00007000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_048_SHIFT            12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_047 [11:09] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_MASK             0x00000e00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_047_SHIFT            9

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_046 [08:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_MASK             0x000001c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_046_SHIFT            6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_045 [05:03] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_MASK             0x00000038
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_045_SHIFT            3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_044 [02:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_MASK             0x00000007
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_044_SHIFT            0

/***************************************************************************
 *PIN_MUX_CTRL_8 - Pin mux control register 8
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: reserved0 [31:31] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_reserved0_MASK            0x80000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_reserved0_SHIFT           31

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_064 [30:29] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_064_MASK             0x60000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_064_SHIFT            29

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_063 [28:27] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_063_MASK             0x18000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_063_SHIFT            27

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_062 [26:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_062_MASK             0x07000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_062_SHIFT            24

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_061 [23:21] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_061_MASK             0x00e00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_061_SHIFT            21

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_060 [20:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_060_MASK             0x001c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_060_SHIFT            18

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_059 [17:15] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_059_MASK             0x00038000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_059_SHIFT            15

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_058 [14:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_058_MASK             0x00007000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_058_SHIFT            12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_057 [11:09] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_057_MASK             0x00000e00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_057_SHIFT            9

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_056 [08:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_MASK             0x000001c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_056_SHIFT            6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_055 [05:03] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_MASK             0x00000038
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_055_SHIFT            3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_054 [02:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_MASK             0x00000007
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_054_SHIFT            0

/***************************************************************************
 *PIN_MUX_CTRL_9 - Pin mux control register 9
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_076 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_076_MASK             0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_076_SHIFT            30

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_075 [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_075_MASK             0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_075_SHIFT            28

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_074 [27:25] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_074_MASK             0x0e000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_074_SHIFT            25

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_073 [24:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_073_MASK             0x01c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_073_SHIFT            22

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_072 [21:19] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_MASK             0x00380000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_072_SHIFT            19

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_071 [18:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_071_MASK             0x00070000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_071_SHIFT            16

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_070 [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_070_MASK             0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_070_SHIFT            14

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_069 [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_069_MASK             0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_069_SHIFT            12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_068 [11:09] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_068_MASK             0x00000e00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_068_SHIFT            9

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_067 [08:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_067_MASK             0x000001c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_067_SHIFT            6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_066 [05:03] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_066_MASK             0x00000038
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_066_SHIFT            3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_065 [02:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_065_MASK             0x00000007
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_065_SHIFT            0

/***************************************************************************
 *PIN_MUX_CTRL_10 - Pin mux control register 10
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_087 [31:29] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_087_MASK            0xe0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_087_SHIFT           29

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_086 [28:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_086_MASK            0x1c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_086_SHIFT           26

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_085 [25:23] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_085_MASK            0x03800000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_085_SHIFT           23

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_084 [22:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_084_MASK            0x00700000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_084_SHIFT           20

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_083 [19:17] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_083_MASK            0x000e0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_083_SHIFT           17

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_082 [16:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_082_MASK            0x0001c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_082_SHIFT           14

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_081 [13:11] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_081_MASK            0x00003800
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_081_SHIFT           11

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_080 [10:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_080_MASK            0x00000700
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_080_SHIFT           8

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_079 [07:05] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_079_MASK            0x000000e0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_079_SHIFT           5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_078 [04:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_078_MASK            0x0000001c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_078_SHIFT           2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_077 [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_077_MASK            0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_077_SHIFT           0

/***************************************************************************
 *PIN_MUX_CTRL_11 - Pin mux control register 11
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: reserved0 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_reserved0_MASK           0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_reserved0_SHIFT          30

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_097 [29:27] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_097_MASK            0x38000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_097_SHIFT           27

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_096 [26:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_096_MASK            0x07000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_096_SHIFT           24

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_095 [23:21] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_095_MASK            0x00e00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_095_SHIFT           21

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_094 [20:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_094_MASK            0x001c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_094_SHIFT           18

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_093 [17:15] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_MASK            0x00038000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_093_SHIFT           15

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_092 [14:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_MASK            0x00007000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_092_SHIFT           12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_091 [11:09] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_091_MASK            0x00000e00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_091_SHIFT           9

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_090 [08:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_090_MASK            0x000001c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_090_SHIFT           6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_089 [05:03] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_089_MASK            0x00000038
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_089_SHIFT           3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_088 [02:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_088_MASK            0x00000007
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_088_SHIFT           0

/***************************************************************************
 *PIN_MUX_CTRL_12 - Pin mux control register 12
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_108 [31:29] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_108_MASK            0xe0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_108_SHIFT           29

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_107 [28:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_107_MASK            0x1c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_107_SHIFT           26

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_106 [25:23] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_MASK            0x03800000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_106_SHIFT           23

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_105 [22:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_MASK            0x00700000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_105_SHIFT           20

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_104 [19:17] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_MASK            0x000e0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_SHIFT           17

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_103 [16:15] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_MASK            0x00018000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_SHIFT           15

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_102 [14:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_MASK            0x00007000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_SHIFT           12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [11:09] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK            0x00000e00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT           9

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_100 [08:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK            0x000001c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT           6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_099 [05:03] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_MASK            0x00000038
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_099_SHIFT           3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_098 [02:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_MASK            0x00000007
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_098_SHIFT           0

/***************************************************************************
 *PIN_MUX_CTRL_13 - Pin mux control register 13
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: reserved0 [31:29] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_reserved0_MASK           0xe0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_reserved0_SHIFT          29

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: byp_sys9_clk [28:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_byp_sys9_clk_MASK        0x10000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_byp_sys9_clk_SHIFT       28

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: sgpio_07 [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_07_MASK            0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_07_SHIFT           26

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: sgpio_06 [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_06_MASK            0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_06_SHIFT           24

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: sgpio_05 [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_05_MASK            0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_05_SHIFT           22

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: sgpio_04 [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_04_MASK            0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_04_SHIFT           20

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: sgpio_03 [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_03_MASK            0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_03_SHIFT           18

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: sgpio_02 [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_02_MASK            0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_02_SHIFT           16

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: sgpio_01 [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_01_MASK            0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_01_SHIFT           14

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: sgpio_00 [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_00_MASK            0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_00_SHIFT           12

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_112 [11:09] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_MASK            0x00000e00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_112_SHIFT           9

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_111 [08:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_MASK            0x000001c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_111_SHIFT           6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_110 [05:03] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK            0x00000038
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT           3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_109 [02:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK            0x00000007
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT           0

/***************************************************************************
 *TEST_PORT_CTRL - Test port control
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sundry_local_tp_out_sel [31:28] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MASK 0xf0000000
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SHIFT 28
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_0 0
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_1 1
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_FP_RST_CNT 2
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MISC_TEST 3
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SSP 4
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_OUT_POKE_REG 5
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_IN 6
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UHFR_TP 7
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_DAA_TP 8
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SOFT_MODEM_TP 9
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_NOT_USED_AUX3 10

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:08] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0fffff00
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           8

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [07:07] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000080
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 7

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [06:05] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000060
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           5

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [04:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000001f
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_ENET    0
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     1
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM     2
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA    3
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    4
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HDMI    6
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    7
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     8
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFX     14
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     15
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB     16
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SUN     17
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MAD     18
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     21
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RPTD    22
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     23
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    24
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     25

/***************************************************************************
 *EJTAG_INPUT_EN - EJTAG input bus enables
 ***************************************************************************/
/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:05] */
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xffffffe0
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           5

/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [04:00] */
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x0000001f
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AUDIO_ZSP_CPU_ONE_HOT 4
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AVD0_OL_CPU_ONE_HOT 8
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AVD0_IL_CPU_ONE_HOT 16

/***************************************************************************
 *EJTAG_OUTPUT_SEL - EJTAG output select
 ***************************************************************************/
/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3

/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AUDIO_ZSP_CPU 2
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AVD0_OL_CPU 3
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AVD0_IL_CPU 4

/***************************************************************************
 *UART_ROUTER_SEL - UART Router select
 ***************************************************************************/
/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15

/***************************************************************************
 *SSP_CONFIG - Serial Slave Port configuration register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11

/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7

/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3

/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2

/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1

/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0

/***************************************************************************
 *SERS_REV - SERS Revision Register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16

/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8

/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0

/***************************************************************************
 *SERS_CFG - SERS Configuration Register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29

/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1

/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27

/* union - case mapped_buffer_mode [26:08] */
/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8

/* union - case cmd_fifo_mode [26:08] */
/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: reserved0 [11:10] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_reserved0_MASK    0x00000c00
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_reserved0_SHIFT   10

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8

/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1

/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0

/***************************************************************************
 *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
 ***************************************************************************/
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404228
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32

/***************************************************************************
 *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0


/***************************************************************************
 *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
 ***************************************************************************/
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404248
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32

/***************************************************************************
 *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0


/***************************************************************************
 *TEST_PORT_OUT_PEEK - Testport peek register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_peek_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_peek_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_peek_value_SHIFT 0

/***************************************************************************
 *TEST_PORT_OUT_POKE - Testport poke register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_poke_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_poke_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_poke_value_SHIFT 0

/***************************************************************************
 *TEST_PORT_IN_PEEK - Testport peek register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_peek_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_peek_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_peek_value_SHIFT 0

/***************************************************************************
 *TEST_PORT_IN_POKE - Testport poke register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_poke_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_poke_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_poke_value_SHIFT 0

/***************************************************************************
 *SPARE_CTRL - Spare control bits reserved for future use
 ***************************************************************************/
/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0

/***************************************************************************
 *RO_TEST_BLOCK_SEL - Block select for RO testmode
 ***************************************************************************/
/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5

/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [04:03] */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x00000018
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 3

/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [02:00] */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000007
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_XPT_RO_TEST_ID 1
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SUN_RO_TEST_ID 2
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 3
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 4
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_VEC_RO_TEST_ID 5
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_RPTD_RO_TEST_ID 6
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MIPS_RO_TEST_ID 7

/***************************************************************************
 *SS_TMODE_CTRL - Simultaneous switching testmode control
 ***************************************************************************/
/* SUN_TOP_CTRL :: SS_TMODE_CTRL :: scb_ss_tmode_enables [31:00] */
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_MASK  0xffffffff
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_SHIFT 0
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_BVN_EDGE 0
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_BVN_MAD 1
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_BVN_MID 2
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_HIF   3
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_USB   4
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_SUN   5
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_GFX   6
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_ENET  7
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_XPT   8
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_SATA  9
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_RPTD  10
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_AIO   11
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_AVD0  12
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_MC1   13
#define BCHP_SUN_TOP_CTRL_SS_TMODE_CTRL_scb_ss_tmode_enables_MC2   14

/***************************************************************************
 *TEST_MODE - Testmode register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_MODE :: reserved0 [31:24] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_MASK                 0xff000000
#define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_SHIFT                24

/* SUN_TOP_CTRL :: TEST_MODE :: live_test_mode [23:20] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_live_test_mode_MASK            0x00f00000
#define BCHP_SUN_TOP_CTRL_TEST_MODE_live_test_mode_SHIFT           20

/* SUN_TOP_CTRL :: TEST_MODE :: latched_test_mode [19:16] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_latched_test_mode_MASK         0x000f0000
#define BCHP_SUN_TOP_CTRL_TEST_MODE_latched_test_mode_SHIFT        16

/* SUN_TOP_CTRL :: TEST_MODE :: reserved1 [15:12] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved1_MASK                 0x0000f000
#define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved1_SHIFT                12

/* SUN_TOP_CTRL :: TEST_MODE :: test_mode_register [11:08] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_MASK        0x00000f00
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_SHIFT       8
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_FUNCT_TM0   0
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_FUNCT_TM1   1
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_FUNCT_TM2   2
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_FUNCT_TM3   3
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_SCAN_TM0    4
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_SCAN_TM1    5
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_MBIST_TM0   6
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_MBIST_TM1   7
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_ANALOG_TM   8
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_OVST_TM     9
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_EXT_TP_TM0  10
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_EXT_TP_TM1  11
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_EXT_TP_TM2  12
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_EXT_TP_TM3  13
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_EXT_TP_TM4  14
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_register_EXT_TP_TM5  15

/* SUN_TOP_CTRL :: TEST_MODE :: test_mode_tap [07:04] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_SHIFT            4
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_FUNCT_TM0        0
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_FUNCT_TM1        1
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_FUNCT_TM2        2
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_FUNCT_TM3        3
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_SCAN_TM0         4
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_SCAN_TM1         5
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_MBIST_TM0        6
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_MBIST_TM1        7
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_ANALOG_TM        8
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_OVST_TM          9
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_EXT_TP_TM0       10
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_EXT_TP_TM1       11
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_EXT_TP_TM2       12
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_EXT_TP_TM3       13
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_EXT_TP_TM4       14
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_tap_EXT_TP_TM5       15

/* SUN_TOP_CTRL :: TEST_MODE :: test_mode_pins [03:00] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_MASK            0x0000000f
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_SHIFT           0
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_FUNCT_TM0       0
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_FUNCT_TM1       1
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_FUNCT_TM2       2
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_FUNCT_TM3       3
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_SCAN_TM0        4
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_SCAN_TM1        5
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_MBIST_TM0       6
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_MBIST_TM1       7
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_ANALOG_TM       8
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_OVST_TM         9
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_EXT_TP_TM0      10
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_EXT_TP_TM1      11
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_EXT_TP_TM2      12
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_EXT_TP_TM3      13
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_EXT_TP_TM4      14
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_pins_EXT_TP_TM5      15

#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */

/* End of File */