/***************************************************************************
 *     Copyright (c) 1999-2010, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri Jan 22 20:13:12 2010
 *                 MD5 Checksum         a2d1f2163f65e87d228a0fb491cb442d
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7125/rdb/c0/bchp_sata_mdio.h $
 * 
 * Hydra_Software_Devel/1   1/25/10 9:42p albertl
 * SW7125-177: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_SATA_MDIO_H__
#define BCHP_SATA_MDIO_H__

/***************************************************************************
 *SATA_MDIO - MDIO Address mapping
 ***************************************************************************/
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG            0x1a0a00 /* PLL_CTRL_0_REG */
#define BCHP_SATA_MDIO_PLL_CTRL_1_REG            0x1a0a02 /* PLL_CTRL_1_REG */
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG            0x1a0a04 /* PLL_CTRL_2_REG */
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG            0x1a0a06 /* PLL_CTRL_3_REG */
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG           0x1a0a08 /* MISC_CTRL_1_REG */
#define BCHP_SATA_MDIO_TB_CTRL_REG               0x1a0a0a /* TB_CTRL_REG */
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG           0x1a0a0c /* MISC_CTRL_2_REG */
#define BCHP_SATA_MDIO_PORT_SELECT_REG           0x1a0a0e /* PORT_SELECT_REG */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG        0x1a0a10 /* PORT_RX_CTRL_0_REG */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG        0x1a0a12 /* PORT_RX_CTRL_1_REG */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG        0x1a0a1c /* PORT_RX_CTRL_2_REG */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG        0x1a0a1e /* PORT_RX_CTRL_3_REG */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG        0x1a0a14 /* PORT_TX_CTRL_0_REG */
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG        0x1a0a16 /* PORT_PRBS_CTRL_REG */
#define BCHP_SATA_MDIO_PORT_PRBS_STAT_REG        0x1a0a18 /* PORT_PRBS_STAT_REG */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG         0x1a0a1a /* PORT_DIG_CTRL_REG */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG        0x1a0a20 /* PORT_TX_CTRL_1_REG */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_2_REG        0x1a0a22 /* PORT_TX_Control_2_REG */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG            0x1a0a24 /* PLL_CTRL_4_REG */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG            0x1a0a26 /* PLL_CTRL_5_REG */
#define BCHP_SATA_MDIO_PLL_CTRL_6_REG            0x1a0a28 /* PLL_CTRL_6_REG */
#define BCHP_SATA_MDIO_PLL_CTRL_7_REG            0x1a0a2a /* PLL_CTRL_7_REG */
#define BCHP_SATA_MDIO_PLL_STAT_0_REG            0x1a0a36 /* PLL_STAT_0_REG */
#define BCHP_SATA_MDIO_PLL_STAT_1_REG            0x1a0a38 /* PLL_STAT_1_REG */
#define BCHP_SATA_MDIO_CORE_ID                   0x1a0a3e /* CORE_ID */

/***************************************************************************
 *PLL_CTRL_0_REG - PLL_CTRL_0_REG
 ***************************************************************************/
/* SATA_MDIO :: PLL_CTRL_0_REG :: VCO_OUTPUT_SWING [15:14] */
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_VCO_OUTPUT_SWING_MASK        0xc000
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_VCO_OUTPUT_SWING_SHIFT       14

/* SATA_MDIO :: PLL_CTRL_0_REG :: FDBK_DIVIDER_RATIO [13:10] */
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_FDBK_DIVIDER_RATIO_MASK      0x3c00
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_FDBK_DIVIDER_RATIO_SHIFT     10

/* SATA_MDIO :: PLL_CTRL_0_REG :: CHARGE_PUMP_CURR [09:08] */
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_CHARGE_PUMP_CURR_MASK        0x0300
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_CHARGE_PUMP_CURR_SHIFT       8

/* SATA_MDIO :: PLL_CTRL_0_REG :: CHARGE_PUMP_CURR_2X [07:07] */
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_CHARGE_PUMP_CURR_2X_MASK     0x0080
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_CHARGE_PUMP_CURR_2X_SHIFT    7

/* SATA_MDIO :: PLL_CTRL_0_REG :: AUTO_PLL_BW_ADJ [06:06] */
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_AUTO_PLL_BW_ADJ_MASK         0x0040
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_AUTO_PLL_BW_ADJ_SHIFT        6

/* SATA_MDIO :: PLL_CTRL_0_REG :: LOW_LF_0_RESIS [05:05] */
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_LOW_LF_0_RESIS_MASK          0x0020
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_LOW_LF_0_RESIS_SHIFT         5

/* SATA_MDIO :: PLL_CTRL_0_REG :: EN_HIGH_KVCO_MODE [04:04] */
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_EN_HIGH_KVCO_MODE_MASK       0x0010
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_EN_HIGH_KVCO_MODE_SHIFT      4

/* SATA_MDIO :: PLL_CTRL_0_REG :: RAISE_VC_THRESHOLD [03:03] */
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_RAISE_VC_THRESHOLD_MASK      0x0008
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_RAISE_VC_THRESHOLD_SHIFT     3

/* SATA_MDIO :: PLL_CTRL_0_REG :: AUTO_VCORANGE_SEL [02:02] */
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_AUTO_VCORANGE_SEL_MASK       0x0004
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_AUTO_VCORANGE_SEL_SHIFT      2

/* SATA_MDIO :: PLL_CTRL_0_REG :: PLL_RESET [01:01] */
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_PLL_RESET_MASK               0x0002
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_PLL_RESET_SHIFT              1

/* SATA_MDIO :: PLL_CTRL_0_REG :: PLL_PWRDN [00:00] */
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_PLL_PWRDN_MASK               0x0001
#define BCHP_SATA_MDIO_PLL_CTRL_0_REG_PLL_PWRDN_SHIFT              0

/***************************************************************************
 *PLL_CTRL_1_REG - PLL_CTRL_1_REG
 ***************************************************************************/
/* SATA_MDIO :: PLL_CTRL_1_REG :: CTAT_ADJ [15:15] */
#define BCHP_SATA_MDIO_PLL_CTRL_1_REG_CTAT_ADJ_MASK                0x8000
#define BCHP_SATA_MDIO_PLL_CTRL_1_REG_CTAT_ADJ_SHIFT               15

/* SATA_MDIO :: PLL_CTRL_1_REG :: PTAT_ADJ [14:11] */
#define BCHP_SATA_MDIO_PLL_CTRL_1_REG_PTAT_ADJ_MASK                0x7800
#define BCHP_SATA_MDIO_PLL_CTRL_1_REG_PTAT_ADJ_SHIFT               11

/* SATA_MDIO :: PLL_CTRL_1_REG :: G_65NM_PROCESS [10:10] */
#define BCHP_SATA_MDIO_PLL_CTRL_1_REG_G_65NM_PROCESS_MASK          0x0400
#define BCHP_SATA_MDIO_PLL_CTRL_1_REG_G_65NM_PROCESS_SHIFT         10

/* SATA_MDIO :: PLL_CTRL_1_REG :: KVCO_65NMLP_PROCESS [09:09] */
#define BCHP_SATA_MDIO_PLL_CTRL_1_REG_KVCO_65NMLP_PROCESS_MASK     0x0200
#define BCHP_SATA_MDIO_PLL_CTRL_1_REG_KVCO_65NMLP_PROCESS_SHIFT    9

/* SATA_MDIO :: PLL_CTRL_1_REG :: reserved0 [08:00] */
#define BCHP_SATA_MDIO_PLL_CTRL_1_REG_reserved0_MASK               0x01ff
#define BCHP_SATA_MDIO_PLL_CTRL_1_REG_reserved0_SHIFT              0

/***************************************************************************
 *PLL_CTRL_2_REG - PLL_CTRL_2_REG
 ***************************************************************************/
/* SATA_MDIO :: PLL_CTRL_2_REG :: INREF_BUFFBIAS [15:13] */
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_INREF_BUFFBIAS_MASK          0xe000
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_INREF_BUFFBIAS_SHIFT         13

/* SATA_MDIO :: PLL_CTRL_2_REG :: CHARGE_PUMP_BIAS_CURR [12:10] */
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_CHARGE_PUMP_BIAS_CURR_MASK   0x1c00
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_CHARGE_PUMP_BIAS_CURR_SHIFT  10

/* SATA_MDIO :: PLL_CTRL_2_REG :: PLL_GLOB_CURR [09:07] */
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_PLL_GLOB_CURR_MASK           0x0380
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_PLL_GLOB_CURR_SHIFT          7

/* SATA_MDIO :: PLL_CTRL_2_REG :: BIAS_GEN_REFH [06:06] */
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_BIAS_GEN_REFH_MASK           0x0040
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_BIAS_GEN_REFH_SHIFT          6

/* SATA_MDIO :: PLL_CTRL_2_REG :: BIAS_GEN_REFL [05:05] */
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_BIAS_GEN_REFL_MASK           0x0020
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_BIAS_GEN_REFL_SHIFT          5

/* SATA_MDIO :: PLL_CTRL_2_REG :: BANDGAP_BIAS [04:04] */
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_BANDGAP_BIAS_MASK            0x0010
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_BANDGAP_BIAS_SHIFT           4

/* SATA_MDIO :: PLL_CTRL_2_REG :: BANDGAP_PWRDN [03:03] */
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_BANDGAP_PWRDN_MASK           0x0008
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_BANDGAP_PWRDN_SHIFT          3

/* SATA_MDIO :: PLL_CTRL_2_REG :: CTAT_ADJ [02:00] */
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_CTAT_ADJ_MASK                0x0007
#define BCHP_SATA_MDIO_PLL_CTRL_2_REG_CTAT_ADJ_SHIFT               0

/***************************************************************************
 *PLL_CTRL_3_REG - PLL_CTRL_3_REG
 ***************************************************************************/
/* SATA_MDIO :: PLL_CTRL_3_REG :: PLL_TEST_CTRL_2 [15:14] */
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG_PLL_TEST_CTRL_2_MASK         0xc000
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG_PLL_TEST_CTRL_2_SHIFT        14

/* SATA_MDIO :: PLL_CTRL_3_REG :: PLL_TEST_CTRL_1 [13:12] */
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG_PLL_TEST_CTRL_1_MASK         0x3000
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG_PLL_TEST_CTRL_1_SHIFT        12

/* SATA_MDIO :: PLL_CTRL_3_REG :: VCOVC_OUT_BUFFBIAS [11:09] */
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG_VCOVC_OUT_BUFFBIAS_MASK      0x0e00
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG_VCOVC_OUT_BUFFBIAS_SHIFT     9

/* SATA_MDIO :: PLL_CTRL_3_REG :: VCOVC_COMP_BIAS [08:06] */
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG_VCOVC_COMP_BIAS_MASK         0x01c0
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG_VCOVC_COMP_BIAS_SHIFT        6

/* SATA_MDIO :: PLL_CTRL_3_REG :: VCO_BUFFBIAS_CURR [05:03] */
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG_VCO_BUFFBIAS_CURR_MASK       0x0038
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG_VCO_BUFFBIAS_CURR_SHIFT      3

/* SATA_MDIO :: PLL_CTRL_3_REG :: PLL_VCOBIAS_CURR [02:00] */
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG_PLL_VCOBIAS_CURR_MASK        0x0007
#define BCHP_SATA_MDIO_PLL_CTRL_3_REG_PLL_VCOBIAS_CURR_SHIFT       0

/***************************************************************************
 *MISC_CTRL_1_REG - MISC_CTRL_1_REG
 ***************************************************************************/
/* SATA_MDIO :: MISC_CTRL_1_REG :: reserved0 [15:09] */
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG_reserved0_MASK              0xfe00
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG_reserved0_SHIFT             9

/* SATA_MDIO :: MISC_CTRL_1_REG :: EN_TEST_MDIO_SPACE [08:08] */
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG_EN_TEST_MDIO_SPACE_MASK     0x0100
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG_EN_TEST_MDIO_SPACE_SHIFT    8

/* SATA_MDIO :: MISC_CTRL_1_REG :: reserved1 [07:04] */
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG_reserved1_MASK              0x00f0
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG_reserved1_SHIFT             4

/* SATA_MDIO :: MISC_CTRL_1_REG :: ANALOG_RESET [03:03] */
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG_ANALOG_RESET_MASK           0x0008
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG_ANALOG_RESET_SHIFT          3

/* SATA_MDIO :: MISC_CTRL_1_REG :: reserved2 [02:01] */
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG_reserved2_MASK              0x0006
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG_reserved2_SHIFT             1

/* SATA_MDIO :: MISC_CTRL_1_REG :: ANALOG_PWRN [00:00] */
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG_ANALOG_PWRN_MASK            0x0001
#define BCHP_SATA_MDIO_MISC_CTRL_1_REG_ANALOG_PWRN_SHIFT           0

/***************************************************************************
 *TB_CTRL_REG - TB_CTRL_REG
 ***************************************************************************/
/* union - case MDIO_FUNC_SPACE [15:00] */
/* SATA_MDIO :: TB_CTRL_REG :: MDIO_FUNC_SPACE :: reserved0 [15:00] */
#define BCHP_SATA_MDIO_TB_CTRL_REG_MDIO_FUNC_SPACE_reserved0_MASK  0xffff
#define BCHP_SATA_MDIO_TB_CTRL_REG_MDIO_FUNC_SPACE_reserved0_SHIFT 0

/* union - case MDIO_TEST_SPACE [15:00] */
/* SATA_MDIO :: TB_CTRL_REG :: MDIO_TEST_SPACE :: reserved0 [15:13] */
#define BCHP_SATA_MDIO_TB_CTRL_REG_MDIO_TEST_SPACE_reserved0_MASK  0xe000
#define BCHP_SATA_MDIO_TB_CTRL_REG_MDIO_TEST_SPACE_reserved0_SHIFT 13

/* SATA_MDIO :: TB_CTRL_REG :: MDIO_TEST_SPACE :: TB_TYPE_SEL [12:11] */
#define BCHP_SATA_MDIO_TB_CTRL_REG_MDIO_TEST_SPACE_TB_TYPE_SEL_MASK 0x1800
#define BCHP_SATA_MDIO_TB_CTRL_REG_MDIO_TEST_SPACE_TB_TYPE_SEL_SHIFT 11

/* SATA_MDIO :: TB_CTRL_REG :: MDIO_TEST_SPACE :: TB_PORT_SEL [10:08] */
#define BCHP_SATA_MDIO_TB_CTRL_REG_MDIO_TEST_SPACE_TB_PORT_SEL_MASK 0x0700
#define BCHP_SATA_MDIO_TB_CTRL_REG_MDIO_TEST_SPACE_TB_PORT_SEL_SHIFT 8

/* SATA_MDIO :: TB_CTRL_REG :: MDIO_TEST_SPACE :: TEST_MUX_SEL [07:00] */
#define BCHP_SATA_MDIO_TB_CTRL_REG_MDIO_TEST_SPACE_TEST_MUX_SEL_MASK 0x00ff
#define BCHP_SATA_MDIO_TB_CTRL_REG_MDIO_TEST_SPACE_TEST_MUX_SEL_SHIFT 0

/***************************************************************************
 *MISC_CTRL_2_REG - MISC_CTRL_2_REG
 ***************************************************************************/
/* union - case MDIO_FUNC_SPACE [15:00] */
/* SATA_MDIO :: MISC_CTRL_2_REG :: MDIO_FUNC_SPACE :: reserved0 [15:10] */
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_FUNC_SPACE_reserved0_MASK 0xfc00
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_FUNC_SPACE_reserved0_SHIFT 10

/* SATA_MDIO :: MISC_CTRL_2_REG :: MDIO_FUNC_SPACE :: EN_FAST_MDIO_CYCLES [09:09] */
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_FUNC_SPACE_EN_FAST_MDIO_CYCLES_MASK 0x0200
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_FUNC_SPACE_EN_FAST_MDIO_CYCLES_SHIFT 9

/* SATA_MDIO :: MISC_CTRL_2_REG :: MDIO_FUNC_SPACE :: RESET_PCI_BLOCK [08:08] */
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_FUNC_SPACE_RESET_PCI_BLOCK_MASK 0x0100
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_FUNC_SPACE_RESET_PCI_BLOCK_SHIFT 8

/* SATA_MDIO :: MISC_CTRL_2_REG :: MDIO_FUNC_SPACE :: reserved1 [07:02] */
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_FUNC_SPACE_reserved1_MASK 0x00fc
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_FUNC_SPACE_reserved1_SHIFT 2

/* SATA_MDIO :: MISC_CTRL_2_REG :: MDIO_FUNC_SPACE :: RESET_PORT_1 [01:01] */
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_FUNC_SPACE_RESET_PORT_1_MASK 0x0002
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_FUNC_SPACE_RESET_PORT_1_SHIFT 1

/* SATA_MDIO :: MISC_CTRL_2_REG :: MDIO_FUNC_SPACE :: RESET_PORT_0 [00:00] */
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_FUNC_SPACE_RESET_PORT_0_MASK 0x0001
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_FUNC_SPACE_RESET_PORT_0_SHIFT 0

/* union - case MDIO_TEST_SPACE [15:00] */
/* SATA_MDIO :: MISC_CTRL_2_REG :: MDIO_TEST_SPACE :: reserved0 [15:08] */
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_TEST_SPACE_reserved0_MASK 0xff00
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_TEST_SPACE_reserved0_SHIFT 8

/* SATA_MDIO :: MISC_CTRL_2_REG :: MDIO_TEST_SPACE :: PHY_TEST_SEL [07:04] */
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_TEST_SPACE_PHY_TEST_SEL_MASK 0x00f0
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_TEST_SPACE_PHY_TEST_SEL_SHIFT 4

/* SATA_MDIO :: MISC_CTRL_2_REG :: MDIO_TEST_SPACE :: SEL_LF_FOR_TB [03:00] */
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_TEST_SPACE_SEL_LF_FOR_TB_MASK 0x000f
#define BCHP_SATA_MDIO_MISC_CTRL_2_REG_MDIO_TEST_SPACE_SEL_LF_FOR_TB_SHIFT 0

/***************************************************************************
 *PORT_SELECT_REG - PORT_SELECT_REG
 ***************************************************************************/
/* SATA_MDIO :: PORT_SELECT_REG :: FREQ_LOCK [15:15] */
#define BCHP_SATA_MDIO_PORT_SELECT_REG_FREQ_LOCK_MASK              0x8000
#define BCHP_SATA_MDIO_PORT_SELECT_REG_FREQ_LOCK_SHIFT             15

/* SATA_MDIO :: PORT_SELECT_REG :: reserved0 [14:02] */
#define BCHP_SATA_MDIO_PORT_SELECT_REG_reserved0_MASK              0x7ffc
#define BCHP_SATA_MDIO_PORT_SELECT_REG_reserved0_SHIFT             2

/* SATA_MDIO :: PORT_SELECT_REG :: SEL_PORT1 [01:01] */
#define BCHP_SATA_MDIO_PORT_SELECT_REG_SEL_PORT1_MASK              0x0002
#define BCHP_SATA_MDIO_PORT_SELECT_REG_SEL_PORT1_SHIFT             1

/* SATA_MDIO :: PORT_SELECT_REG :: SEL_PORT0 [00:00] */
#define BCHP_SATA_MDIO_PORT_SELECT_REG_SEL_PORT0_MASK              0x0001
#define BCHP_SATA_MDIO_PORT_SELECT_REG_SEL_PORT0_SHIFT             0

/***************************************************************************
 *PORT_RX_CTRL_0_REG - PORT_RX_CTRL_0_REG
 ***************************************************************************/
/* union - case MDIO_FUNC_SPACE [15:00] */
/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_FUNC_SPACE :: SIG_DETECT_BIAS [15:14] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_SIG_DETECT_BIAS_MASK 0xc000
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_SIG_DETECT_BIAS_SHIFT 14

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_FUNC_SPACE :: SIG_THRESHOLD_SCALING [13:11] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_SIG_THRESHOLD_SCALING_MASK 0x3800
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_SIG_THRESHOLD_SCALING_SHIFT 11

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_FUNC_SPACE :: GRAY_SIGNAL_THRESHOLD [10:08] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_GRAY_SIGNAL_THRESHOLD_MASK 0x0700
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_GRAY_SIGNAL_THRESHOLD_SHIFT 8

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_FUNC_SPACE :: BIAS_GEN_REFH [07:07] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_BIAS_GEN_REFH_MASK 0x0080
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_BIAS_GEN_REFH_SHIFT 7

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_FUNC_SPACE :: BIAS_GEN_REFL [06:06] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_BIAS_GEN_REFL_MASK 0x0040
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_BIAS_GEN_REFL_SHIFT 6

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_FUNC_SPACE :: BAND_GAP_BIAS [05:05] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_BAND_GAP_BIAS_MASK 0x0020
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_BAND_GAP_BIAS_SHIFT 5

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_FUNC_SPACE :: LOW_SPD_EN [04:04] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_LOW_SPD_EN_MASK 0x0010
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_LOW_SPD_EN_SHIFT 4

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_FUNC_SPACE :: SIGDET_PWRDN [03:03] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_SIGDET_PWRDN_MASK 0x0008
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_SIGDET_PWRDN_SHIFT 3

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_FUNC_SPACE :: LPBK_MODE_EN [02:02] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_LPBK_MODE_EN_MASK 0x0004
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_LPBK_MODE_EN_SHIFT 2

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_FUNC_SPACE :: RX_RESET [01:01] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_RX_RESET_MASK 0x0002
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_RX_RESET_SHIFT 1

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_FUNC_SPACE :: RX_PWRDN [00:00] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_RX_PWRDN_MASK 0x0001
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_FUNC_SPACE_RX_PWRDN_SHIFT 0

/* union - case MDIO_TEST_SPACE [15:00] */
/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_TEST_SPACE :: reserved0 [15:11] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_TEST_SPACE_reserved0_MASK 0xf800
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_TEST_SPACE_reserved0_SHIFT 11

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_TEST_SPACE :: en_auto_inc_fix [10:10] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_TEST_SPACE_en_auto_inc_fix_MASK 0x0400
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_TEST_SPACE_en_auto_inc_fix_SHIFT 10

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_TEST_SPACE :: fix_align_pattern [09:09] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_TEST_SPACE_fix_align_pattern_MASK 0x0200
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_TEST_SPACE_fix_align_pattern_SHIFT 9

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_TEST_SPACE :: disable_align_fix [08:08] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_TEST_SPACE_disable_align_fix_MASK 0x0100
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_TEST_SPACE_disable_align_fix_SHIFT 8

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_TEST_SPACE :: reserved1 [07:06] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_TEST_SPACE_reserved1_MASK 0x00c0
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_TEST_SPACE_reserved1_SHIFT 6

/* SATA_MDIO :: PORT_RX_CTRL_0_REG :: MDIO_TEST_SPACE :: RAM_WR_ADDR [05:00] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_TEST_SPACE_RAM_WR_ADDR_MASK 0x003f
#define BCHP_SATA_MDIO_PORT_RX_CTRL_0_REG_MDIO_TEST_SPACE_RAM_WR_ADDR_SHIFT 0

/***************************************************************************
 *PORT_RX_CTRL_1_REG - PORT_RX_CTRL_1_REG
 ***************************************************************************/
/* union - case MDIO_FUNC_SPACE [15:00] */
/* SATA_MDIO :: PORT_RX_CTRL_1_REG :: MDIO_FUNC_SPACE :: SSC_MOD_FREQ [15:15] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_SSC_MOD_FREQ_MASK 0x8000
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_SSC_MOD_FREQ_SHIFT 15

/* SATA_MDIO :: PORT_RX_CTRL_1_REG :: MDIO_FUNC_SPACE :: EN_SSC [14:14] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_EN_SSC_MASK 0x4000
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_EN_SSC_SHIFT 14

/* SATA_MDIO :: PORT_RX_CTRL_1_REG :: MDIO_FUNC_SPACE :: EN_RXWCLK1_TESTPORT [13:13] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_EN_RXWCLK1_TESTPORT_MASK 0x2000
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_EN_RXWCLK1_TESTPORT_SHIFT 13

/* SATA_MDIO :: PORT_RX_CTRL_1_REG :: MDIO_FUNC_SPACE :: DATA_SLICER_BIAS [12:10] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_DATA_SLICER_BIAS_MASK 0x1c00
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_DATA_SLICER_BIAS_SHIFT 10

/* SATA_MDIO :: PORT_RX_CTRL_1_REG :: MDIO_FUNC_SPACE :: CLK_BUFF_BIAS [09:07] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_CLK_BUFF_BIAS_MASK 0x0380
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_CLK_BUFF_BIAS_SHIFT 7

/* SATA_MDIO :: PORT_RX_CTRL_1_REG :: MDIO_FUNC_SPACE :: DIVBY2_CLK_BIAS [06:04] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_DIVBY2_CLK_BIAS_MASK 0x0070
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_DIVBY2_CLK_BIAS_SHIFT 4

/* SATA_MDIO :: PORT_RX_CTRL_1_REG :: MDIO_FUNC_SPACE :: PHASE_INTRPOL_BIAS [03:01] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_PHASE_INTRPOL_BIAS_MASK 0x000e
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_PHASE_INTRPOL_BIAS_SHIFT 1

/* SATA_MDIO :: PORT_RX_CTRL_1_REG :: MDIO_FUNC_SPACE :: SIG_DET_BIAS_2 [00:00] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_SIG_DET_BIAS_2_MASK 0x0001
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_FUNC_SPACE_SIG_DET_BIAS_2_SHIFT 0

/* union - case MDIO_TEST_SPACE [15:00] */
/* SATA_MDIO :: PORT_RX_CTRL_1_REG :: MDIO_TEST_SPACE :: RAM_WR_DATA [15:00] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_TEST_SPACE_RAM_WR_DATA_MASK 0xffff
#define BCHP_SATA_MDIO_PORT_RX_CTRL_1_REG_MDIO_TEST_SPACE_RAM_WR_DATA_SHIFT 0

/***************************************************************************
 *PORT_RX_CTRL_2_REG - PORT_RX_CTRL_2_REG
 ***************************************************************************/
/* union - case MDIO_FUNC_SPACE [15:00] */
/* SATA_MDIO :: PORT_RX_CTRL_2_REG :: MDIO_FUNC_SPACE :: EQ_LEVEL [15:13] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG_MDIO_FUNC_SPACE_EQ_LEVEL_MASK 0xe000
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG_MDIO_FUNC_SPACE_EQ_LEVEL_SHIFT 13

/* SATA_MDIO :: PORT_RX_CTRL_2_REG :: MDIO_FUNC_SPACE :: EQ_BIAS [12:10] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG_MDIO_FUNC_SPACE_EQ_BIAS_MASK 0x1c00
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG_MDIO_FUNC_SPACE_EQ_BIAS_SHIFT 10

/* SATA_MDIO :: PORT_RX_CTRL_2_REG :: MDIO_FUNC_SPACE :: EQ_BUFF_BIAS [09:07] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG_MDIO_FUNC_SPACE_EQ_BUFF_BIAS_MASK 0x0380
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG_MDIO_FUNC_SPACE_EQ_BUFF_BIAS_SHIFT 7

/* SATA_MDIO :: PORT_RX_CTRL_2_REG :: MDIO_FUNC_SPACE :: SSC_MAX_SPREAD [06:03] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG_MDIO_FUNC_SPACE_SSC_MAX_SPREAD_MASK 0x0078
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG_MDIO_FUNC_SPACE_SSC_MAX_SPREAD_SHIFT 3

/* SATA_MDIO :: PORT_RX_CTRL_2_REG :: MDIO_FUNC_SPACE :: SSC_MOD_FREQ [02:00] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG_MDIO_FUNC_SPACE_SSC_MOD_FREQ_MASK 0x0007
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG_MDIO_FUNC_SPACE_SSC_MOD_FREQ_SHIFT 0

/* union - case MDIO_TEST_SPACE [15:00] */
/* SATA_MDIO :: PORT_RX_CTRL_2_REG :: MDIO_TEST_SPACE :: reserved0 [15:00] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG_MDIO_TEST_SPACE_reserved0_MASK 0xffff
#define BCHP_SATA_MDIO_PORT_RX_CTRL_2_REG_MDIO_TEST_SPACE_reserved0_SHIFT 0

/***************************************************************************
 *PORT_RX_CTRL_3_REG - PORT_RX_CTRL_3_REG
 ***************************************************************************/
/* SATA_MDIO :: PORT_RX_CTRL_3_REG :: PROP_BW [15:14] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_PROP_BW_MASK             0xc000
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_PROP_BW_SHIFT            14

/* SATA_MDIO :: PORT_RX_CTRL_3_REG :: INTEG_BW [13:12] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_INTEG_BW_MASK            0x3000
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_INTEG_BW_SHIFT           12

/* SATA_MDIO :: PORT_RX_CTRL_3_REG :: PDET_INVERT_EN [11:11] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_PDET_INVERT_EN_MASK      0x0800
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_PDET_INVERT_EN_SHIFT     11

/* SATA_MDIO :: PORT_RX_CTRL_3_REG :: LF_INPUT_OFFSET [10:08] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_LF_INPUT_OFFSET_MASK     0x0700
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_LF_INPUT_OFFSET_SHIFT    8

/* SATA_MDIO :: PORT_RX_CTRL_3_REG :: PH_ROT_TRIGGER [07:07] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_PH_ROT_TRIGGER_MASK      0x0080
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_PH_ROT_TRIGGER_SHIFT     7

/* SATA_MDIO :: PORT_RX_CTRL_3_REG :: PH_ROT_DIR [06:06] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_PH_ROT_DIR_MASK          0x0040
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_PH_ROT_DIR_SHIFT         6

/* SATA_MDIO :: PORT_RX_CTRL_3_REG :: PH_ROT_SIZE [05:05] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_PH_ROT_SIZE_MASK         0x0020
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_PH_ROT_SIZE_SHIFT        5

/* SATA_MDIO :: PORT_RX_CTRL_3_REG :: LF_TM_EN [04:03] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_LF_TM_EN_MASK            0x0018
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_LF_TM_EN_SHIFT           3

/* SATA_MDIO :: PORT_RX_CTRL_3_REG :: LF_TEST_SEL [02:02] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_LF_TEST_SEL_MASK         0x0004
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_LF_TEST_SEL_SHIFT        2

/* SATA_MDIO :: PORT_RX_CTRL_3_REG :: reserved0 [01:00] */
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_reserved0_MASK           0x0003
#define BCHP_SATA_MDIO_PORT_RX_CTRL_3_REG_reserved0_SHIFT          0

/***************************************************************************
 *PORT_TX_CTRL_0_REG - PORT_TX_CTRL_0_REG
 ***************************************************************************/
/* union - case MDIO_FUNC_SPACE [15:00] */
/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: CLK_DIV_5_BUFF_BIAS [15:15] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_CLK_DIV_5_BUFF_BIAS_MASK 0x8000
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_CLK_DIV_5_BUFF_BIAS_SHIFT 15

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: CLK_DIV_1_BUFF_BIAS [14:13] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_CLK_DIV_1_BUFF_BIAS_MASK 0x6000
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_CLK_DIV_1_BUFF_BIAS_SHIFT 13

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: BIAS_GEN_REFH [12:12] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_BIAS_GEN_REFH_MASK 0x1000
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_BIAS_GEN_REFH_SHIFT 12

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: BIAS_GEN_REFL [11:11] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_BIAS_GEN_REFL_MASK 0x0800
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_BIAS_GEN_REFL_SHIFT 11

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: DRAIN_REG_BIAS_EN [10:10] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_DRAIN_REG_BIAS_EN_MASK 0x0400
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_DRAIN_REG_BIAS_EN_SHIFT 10

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: SEL_BGAP_BIAS [09:09] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_SEL_BGAP_BIAS_MASK 0x0200
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_SEL_BGAP_BIAS_SHIFT 9

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: OUT_CM_ADJ [08:07] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_OUT_CM_ADJ_MASK 0x0180
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_OUT_CM_ADJ_SHIFT 7

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: OUT_LOWAMP_EN [06:06] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_OUT_LOWAMP_EN_MASK 0x0040
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_OUT_LOWAMP_EN_SHIFT 6

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: IN_DATA_LD_SKEW_ADJ [05:04] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_IN_DATA_LD_SKEW_ADJ_MASK 0x0030
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_IN_DATA_LD_SKEW_ADJ_SHIFT 4

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: TX_DRV_IDLE_EN [03:03] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_TX_DRV_IDLE_EN_MASK 0x0008
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_TX_DRV_IDLE_EN_SHIFT 3

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: REMOTE_LPBK_EN [02:02] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_REMOTE_LPBK_EN_MASK 0x0004
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_REMOTE_LPBK_EN_SHIFT 2

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: TX_RESET [01:01] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_TX_RESET_MASK 0x0002
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_TX_RESET_SHIFT 1

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_FUNC_SPACE :: TX_PWRDN [00:00] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_TX_PWRDN_MASK 0x0001
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_FUNC_SPACE_TX_PWRDN_SHIFT 0

/* union - case MDIO_TEST_SPACE [15:00] */
/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_TB_SEL [15:14] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_TB_SEL_MASK 0xc000
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_TB_SEL_SHIFT 14

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_EXT_PH_SEL [13:13] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_EXT_PH_SEL_MASK 0x2000
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_EXT_PH_SEL_SHIFT 13

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_CLR_ERRBITS [12:12] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_CLR_ERRBITS_MASK 0x1000
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_CLR_ERRBITS_SHIFT 12

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_ERR_SEL [11:09] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_ERR_SEL_MASK 0x0e00
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_ERR_SEL_SHIFT 9

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_FORCE_RXLOCK [08:08] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_FORCE_RXLOCK_MASK 0x0100
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_FORCE_RXLOCK_SHIFT 8

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_SPD_SEL [07:07] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_SPD_SEL_MASK 0x0080
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_SPD_SEL_SHIFT 7

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_EN_TX_ALIGN [06:06] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_EN_TX_ALIGN_MASK 0x0040
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_EN_TX_ALIGN_SHIFT 6

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_TRAINPAT_TYPE [05:05] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_TRAINPAT_TYPE_MASK 0x0020
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_TRAINPAT_TYPE_SHIFT 5

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_AUTO_INC [04:04] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_AUTO_INC_MASK 0x0010
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_AUTO_INC_SHIFT 4

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_EN_TXRAM_WR [03:03] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_EN_TXRAM_WR_MASK 0x0008
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_EN_TXRAM_WR_SHIFT 3

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_EN_RXRAM_WR [02:02] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_EN_RXRAM_WR_MASK 0x0004
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_EN_RXRAM_WR_SHIFT 2

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_SOFT_RESET [01:01] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_SOFT_RESET_MASK 0x0002
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_SOFT_RESET_SHIFT 1

/* SATA_MDIO :: PORT_TX_CTRL_0_REG :: MDIO_TEST_SPACE :: CJ_EN_BIT [00:00] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_EN_BIT_MASK 0x0001
#define BCHP_SATA_MDIO_PORT_TX_CTRL_0_REG_MDIO_TEST_SPACE_CJ_EN_BIT_SHIFT 0

/***************************************************************************
 *PORT_PRBS_CTRL_REG - PORT_PRBS_CTRL_REG
 ***************************************************************************/
/* union - case MDIO_FUNC_SPACE [15:00] */
/* SATA_MDIO :: PORT_PRBS_CTRL_REG :: MDIO_FUNC_SPACE :: reserved0 [15:06] */
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_FUNC_SPACE_reserved0_MASK 0xffc0
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_FUNC_SPACE_reserved0_SHIFT 6

/* SATA_MDIO :: PORT_PRBS_CTRL_REG :: MDIO_FUNC_SPACE :: PRBS_SPD_SEL [05:05] */
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_FUNC_SPACE_PRBS_SPD_SEL_MASK 0x0020
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_FUNC_SPACE_PRBS_SPD_SEL_SHIFT 5

/* SATA_MDIO :: PORT_PRBS_CTRL_REG :: MDIO_FUNC_SPACE :: PRBS_EN [04:04] */
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_FUNC_SPACE_PRBS_EN_MASK 0x0010
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_FUNC_SPACE_PRBS_EN_SHIFT 4

/* SATA_MDIO :: PORT_PRBS_CTRL_REG :: MDIO_FUNC_SPACE :: PRBS_INVERT [03:03] */
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_FUNC_SPACE_PRBS_INVERT_MASK 0x0008
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_FUNC_SPACE_PRBS_INVERT_SHIFT 3

/* SATA_MDIO :: PORT_PRBS_CTRL_REG :: MDIO_FUNC_SPACE :: PRBS_ORDER [02:01] */
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_FUNC_SPACE_PRBS_ORDER_MASK 0x0006
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_FUNC_SPACE_PRBS_ORDER_SHIFT 1

/* SATA_MDIO :: PORT_PRBS_CTRL_REG :: MDIO_FUNC_SPACE :: PRBS_ERR_CLR [00:00] */
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_FUNC_SPACE_PRBS_ERR_CLR_MASK 0x0001
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_FUNC_SPACE_PRBS_ERR_CLR_SHIFT 0

/* union - case MDIO_TEST_SPACE [15:00] */
/* SATA_MDIO :: PORT_PRBS_CTRL_REG :: MDIO_TEST_SPACE :: CJ_TRAIN_PAT_L [15:00] */
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_TEST_SPACE_CJ_TRAIN_PAT_L_MASK 0xffff
#define BCHP_SATA_MDIO_PORT_PRBS_CTRL_REG_MDIO_TEST_SPACE_CJ_TRAIN_PAT_L_SHIFT 0

/***************************************************************************
 *PORT_PRBS_STAT_REG - PORT_PRBS_STAT_REG
 ***************************************************************************/
/* union - case MDIO_FUNC_SPACE [15:00] */
/* SATA_MDIO :: PORT_PRBS_STAT_REG :: MDIO_FUNC_SPACE :: PRBS_LOCK [15:15] */
#define BCHP_SATA_MDIO_PORT_PRBS_STAT_REG_MDIO_FUNC_SPACE_PRBS_LOCK_MASK 0x8000
#define BCHP_SATA_MDIO_PORT_PRBS_STAT_REG_MDIO_FUNC_SPACE_PRBS_LOCK_SHIFT 15

/* SATA_MDIO :: PORT_PRBS_STAT_REG :: MDIO_FUNC_SPACE :: PRBS_LOST_LOCK [14:14] */
#define BCHP_SATA_MDIO_PORT_PRBS_STAT_REG_MDIO_FUNC_SPACE_PRBS_LOST_LOCK_MASK 0x4000
#define BCHP_SATA_MDIO_PORT_PRBS_STAT_REG_MDIO_FUNC_SPACE_PRBS_LOST_LOCK_SHIFT 14

/* SATA_MDIO :: PORT_PRBS_STAT_REG :: MDIO_FUNC_SPACE :: PRBS_ERROR_CNT [13:00] */
#define BCHP_SATA_MDIO_PORT_PRBS_STAT_REG_MDIO_FUNC_SPACE_PRBS_ERROR_CNT_MASK 0x3fff
#define BCHP_SATA_MDIO_PORT_PRBS_STAT_REG_MDIO_FUNC_SPACE_PRBS_ERROR_CNT_SHIFT 0

/* union - case MDIO_TEST_SPACE [15:00] */
/* SATA_MDIO :: PORT_PRBS_STAT_REG :: MDIO_TEST_SPACE :: CJ_TRAIN_PAT_H [15:00] */
#define BCHP_SATA_MDIO_PORT_PRBS_STAT_REG_MDIO_TEST_SPACE_CJ_TRAIN_PAT_H_MASK 0xffff
#define BCHP_SATA_MDIO_PORT_PRBS_STAT_REG_MDIO_TEST_SPACE_CJ_TRAIN_PAT_H_SHIFT 0

/***************************************************************************
 *PORT_DIG_CTRL_REG - PORT_DIG_CTRL_REG
 ***************************************************************************/
/* union - case MDIO_FUNC_SPACE [15:00] */
/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: RESET_TXDSKEW_FIFO [15:15] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_RESET_TXDSKEW_FIFO_MASK 0x8000
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_RESET_TXDSKEW_FIFO_SHIFT 15

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: reserved0 [14:14] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_reserved0_MASK 0x4000
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_reserved0_SHIFT 14

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: EN_LPBK_FIFO [13:13] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_EN_LPBK_FIFO_MASK 0x2000
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_EN_LPBK_FIFO_SHIFT 13

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: reserved1 [12:12] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_reserved1_MASK 0x1000
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_reserved1_SHIFT 12

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: DIS_SMCTRL_SPD [11:11] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_DIS_SMCTRL_SPD_MASK 0x0800
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_DIS_SMCTRL_SPD_SHIFT 11

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: EN_OOB_DET_WIN [10:10] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_EN_OOB_DET_WIN_MASK 0x0400
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_EN_OOB_DET_WIN_SHIFT 10

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: COMWAKE_XMIT_EN [09:09] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_COMWAKE_XMIT_EN_MASK 0x0200
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_COMWAKE_XMIT_EN_SHIFT 9

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: COMRESET_XMIT_EN [08:08] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_COMRESET_XMIT_EN_MASK 0x0100
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_COMRESET_XMIT_EN_SHIFT 8

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: reserved2 [07:07] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_reserved2_MASK 0x0080
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_reserved2_SHIFT 7

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: DIS_SMCTRL_IDLE [06:06] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_DIS_SMCTRL_IDLE_MASK 0x0040
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_DIS_SMCTRL_IDLE_SHIFT 6

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: EN_TX_D10_2 [05:05] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_EN_TX_D10_2_MASK 0x0020
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_EN_TX_D10_2_SHIFT 5

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: EN_TBI_LPBK [04:04] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_EN_TBI_LPBK_MASK 0x0010
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_EN_TBI_LPBK_SHIFT 4

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: EN_RTIME_LPBK [03:03] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_EN_RTIME_LPBK_MASK 0x0008
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_EN_RTIME_LPBK_SHIFT 3

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: reserved3 [02:02] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_reserved3_MASK 0x0004
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_reserved3_SHIFT 2

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: PRBS_DATA_BITSEL [01:01] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_PRBS_DATA_BITSEL_MASK 0x0002
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_PRBS_DATA_BITSEL_SHIFT 1

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_FUNC_SPACE :: COMMA_EN [00:00] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_COMMA_EN_MASK 0x0001
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_FUNC_SPACE_COMMA_EN_SHIFT 0

/* union - case MDIO_TEST_SPACE [15:00] */
/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_TEST_SPACE :: CJ_RAM_DEPTH [15:10] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_TEST_SPACE_CJ_RAM_DEPTH_MASK 0xfc00
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_TEST_SPACE_CJ_RAM_DEPTH_SHIFT 10

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_TEST_SPACE :: CJ_ALIGN_INTVAL [09:06] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_TEST_SPACE_CJ_ALIGN_INTVAL_MASK 0x03c0
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_TEST_SPACE_CJ_ALIGN_INTVAL_SHIFT 6

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_TEST_SPACE :: CJ_NUM_ALIGN [05:03] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_TEST_SPACE_CJ_NUM_ALIGN_MASK 0x0038
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_TEST_SPACE_CJ_NUM_ALIGN_SHIFT 3

/* SATA_MDIO :: PORT_DIG_CTRL_REG :: MDIO_TEST_SPACE :: CJ_NUM_TRAIN_PAT [02:00] */
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_TEST_SPACE_CJ_NUM_TRAIN_PAT_MASK 0x0007
#define BCHP_SATA_MDIO_PORT_DIG_CTRL_REG_MDIO_TEST_SPACE_CJ_NUM_TRAIN_PAT_SHIFT 0

/***************************************************************************
 *PORT_TX_CTRL_1_REG - PORT_TX_CTRL_1_REG
 ***************************************************************************/
/* SATA_MDIO :: PORT_TX_CTRL_1_REG :: PRE_DRV_BIAS [15:14] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG_PRE_DRV_BIAS_MASK        0xc000
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG_PRE_DRV_BIAS_SHIFT       14

/* SATA_MDIO :: PORT_TX_CTRL_1_REG :: FULL_SPD_DATA_RTIMER_BIAS [13:11] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG_FULL_SPD_DATA_RTIMER_BIAS_MASK 0x3800
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG_FULL_SPD_DATA_RTIMER_BIAS_SHIFT 11

/* SATA_MDIO :: PORT_TX_CTRL_1_REG :: MUX21_CLKBUFF_BIAS [10:08] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG_MUX21_CLKBUFF_BIAS_MASK  0x0700
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG_MUX21_CLKBUFF_BIAS_SHIFT 8

/* SATA_MDIO :: PORT_TX_CTRL_1_REG :: MUX10_2_RTIMER_BUFF_BIAS [07:05] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG_MUX10_2_RTIMER_BUFF_BIAS_MASK 0x00e0
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG_MUX10_2_RTIMER_BUFF_BIAS_SHIFT 5

/* SATA_MDIO :: PORT_TX_CTRL_1_REG :: CLK_DIV_2_BUFF_BIAS [04:02] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG_CLK_DIV_2_BUFF_BIAS_MASK 0x001c
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG_CLK_DIV_2_BUFF_BIAS_SHIFT 2

/* SATA_MDIO :: PORT_TX_CTRL_1_REG :: CLK_DIV_5_BUFF_BIAS [01:00] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG_CLK_DIV_5_BUFF_BIAS_MASK 0x0003
#define BCHP_SATA_MDIO_PORT_TX_CTRL_1_REG_CLK_DIV_5_BUFF_BIAS_SHIFT 0

/***************************************************************************
 *PORT_TX_CTRL_2_REG - PORT_TX_Control_2_REG
 ***************************************************************************/
/* SATA_MDIO :: PORT_TX_CTRL_2_REG :: PRE_EMPH_LEVEL [15:12] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_2_REG_PRE_EMPH_LEVEL_MASK      0xf000
#define BCHP_SATA_MDIO_PORT_TX_CTRL_2_REG_PRE_EMPH_LEVEL_SHIFT     12

/* SATA_MDIO :: PORT_TX_CTRL_2_REG :: OUT_DRV_AMP [11:08] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_2_REG_OUT_DRV_AMP_MASK         0x0f00
#define BCHP_SATA_MDIO_PORT_TX_CTRL_2_REG_OUT_DRV_AMP_SHIFT        8

/* SATA_MDIO :: PORT_TX_CTRL_2_REG :: OUT_DRV_BIAS [07:05] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_2_REG_OUT_DRV_BIAS_MASK        0x00e0
#define BCHP_SATA_MDIO_PORT_TX_CTRL_2_REG_OUT_DRV_BIAS_SHIFT       5

/* SATA_MDIO :: PORT_TX_CTRL_2_REG :: PRE_DRV_AMP [04:01] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_2_REG_PRE_DRV_AMP_MASK         0x001e
#define BCHP_SATA_MDIO_PORT_TX_CTRL_2_REG_PRE_DRV_AMP_SHIFT        1

/* SATA_MDIO :: PORT_TX_CTRL_2_REG :: PRE_DRV_BIAS [00:00] */
#define BCHP_SATA_MDIO_PORT_TX_CTRL_2_REG_PRE_DRV_BIAS_MASK        0x0001
#define BCHP_SATA_MDIO_PORT_TX_CTRL_2_REG_PRE_DRV_BIAS_SHIFT       0

/***************************************************************************
 *PLL_CTRL_4_REG - PLL_CTRL_4_REG
 ***************************************************************************/
/* SATA_MDIO :: PLL_CTRL_4_REG :: reserved0 [15:15] */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_reserved0_MASK               0x8000
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_reserved0_SHIFT              15

/* SATA_MDIO :: PLL_CTRL_4_REG :: EN_PLLVCHIGH_CTRL [14:14] */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_EN_PLLVCHIGH_CTRL_MASK       0x4000
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_EN_PLLVCHIGH_CTRL_SHIFT      14

/* SATA_MDIO :: PLL_CTRL_4_REG :: PLLVCHIGH_VAL [13:13] */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_PLLVCHIGH_VAL_MASK           0x2000
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_PLLVCHIGH_VAL_SHIFT          13

/* SATA_MDIO :: PLL_CTRL_4_REG :: reserved1 [12:12] */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_reserved1_MASK               0x1000
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_reserved1_SHIFT              12

/* SATA_MDIO :: PLL_CTRL_4_REG :: EN_BYPASS_CAPDONE [11:11] */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_EN_BYPASS_CAPDONE_MASK       0x0800
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_EN_BYPASS_CAPDONE_SHIFT      11

/* SATA_MDIO :: PLL_CTRL_4_REG :: SET_CAPDONE [10:10] */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_SET_CAPDONE_MASK             0x0400
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_SET_CAPDONE_SHIFT            10

/* SATA_MDIO :: PLL_CTRL_4_REG :: EN_BYPASS_CAPSTAT [09:09] */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_EN_BYPASS_CAPSTAT_MASK       0x0200
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_EN_BYPASS_CAPSTAT_SHIFT      9

/* SATA_MDIO :: PLL_CTRL_4_REG :: SET_CAPSTAT [08:08] */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_SET_CAPSTAT_MASK             0x0100
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_SET_CAPSTAT_SHIFT            8

/* SATA_MDIO :: PLL_CTRL_4_REG :: reserved2 [07:07] */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_reserved2_MASK               0x0080
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_reserved2_SHIFT              7

/* SATA_MDIO :: PLL_CTRL_4_REG :: INVERT_PLLVCHIGH [06:06] */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_INVERT_PLLVCHIGH_MASK        0x0040
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_INVERT_PLLVCHIGH_SHIFT       6

/* SATA_MDIO :: PLL_CTRL_4_REG :: EN_PLLRANGE_CTRL [05:05] */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_EN_PLLRANGE_CTRL_MASK        0x0020
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_EN_PLLRANGE_CTRL_SHIFT       5

/* SATA_MDIO :: PLL_CTRL_4_REG :: FORCED_VCO_RANGE [04:00] */
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_FORCED_VCO_RANGE_MASK        0x001f
#define BCHP_SATA_MDIO_PLL_CTRL_4_REG_FORCED_VCO_RANGE_SHIFT       0

/***************************************************************************
 *PLL_CTRL_5_REG - PLL_CTRL_5_REG
 ***************************************************************************/
/* SATA_MDIO :: PLL_CTRL_5_REG :: reserved0 [15:15] */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_reserved0_MASK               0x8000
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_reserved0_SHIFT              15

/* SATA_MDIO :: PLL_CTRL_5_REG :: PLL_REFSEL [14:13] */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_PLL_REFSEL_MASK              0x6000
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_PLL_REFSEL_SHIFT             13

/* SATA_MDIO :: PLL_CTRL_5_REG :: VCO_STEP_SEL [12:10] */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_VCO_STEP_SEL_MASK            0x1c00
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_VCO_STEP_SEL_SHIFT           10

/* SATA_MDIO :: PLL_CTRL_5_REG :: START_PLL_TUNER [09:09] */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_START_PLL_TUNER_MASK         0x0200
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_START_PLL_TUNER_SHIFT        9

/* SATA_MDIO :: PLL_CTRL_5_REG :: reserved1 [08:08] */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_reserved1_MASK               0x0100
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_reserved1_SHIFT              8

/* SATA_MDIO :: PLL_CTRL_5_REG :: RESET_PLL_TUNER [07:07] */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_RESET_PLL_TUNER_MASK         0x0080
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_RESET_PLL_TUNER_SHIFT        7

/* SATA_MDIO :: PLL_CTRL_5_REG :: EN_FREQLOCK_BYPASS [06:06] */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_EN_FREQLOCK_BYPASS_MASK      0x0040
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_EN_FREQLOCK_BYPASS_SHIFT     6

/* SATA_MDIO :: PLL_CTRL_5_REG :: SET_FREQLOCK_DONE [05:05] */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_SET_FREQLOCK_DONE_MASK       0x0020
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_SET_FREQLOCK_DONE_SHIFT      5

/* SATA_MDIO :: PLL_CTRL_5_REG :: SET_FREQLOCK_PASS [04:04] */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_SET_FREQLOCK_PASS_MASK       0x0010
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_SET_FREQLOCK_PASS_SHIFT      4

/* SATA_MDIO :: PLL_CTRL_5_REG :: reserved2 [03:02] */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_reserved2_MASK               0x000c
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_reserved2_SHIFT              2

/* SATA_MDIO :: PLL_CTRL_5_REG :: EN_CONT_FREQLOCK_MON [01:01] */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_EN_CONT_FREQLOCK_MON_MASK    0x0002
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_EN_CONT_FREQLOCK_MON_SHIFT   1

/* SATA_MDIO :: PLL_CTRL_5_REG :: FORCE_FREQLOCK [00:00] */
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_FORCE_FREQLOCK_MASK          0x0001
#define BCHP_SATA_MDIO_PLL_CTRL_5_REG_FORCE_FREQLOCK_SHIFT         0

/***************************************************************************
 *PLL_CTRL_6_REG - PLL_CTRL_6_REG
 ***************************************************************************/
/* SATA_MDIO :: PLL_CTRL_6_REG :: MDIO_RES_VAL [15:08] */
#define BCHP_SATA_MDIO_PLL_CTRL_6_REG_MDIO_RES_VAL_MASK            0xff00
#define BCHP_SATA_MDIO_PLL_CTRL_6_REG_MDIO_RES_VAL_SHIFT           8

/* SATA_MDIO :: PLL_CTRL_6_REG :: MDIO_WIN_VAL [07:00] */
#define BCHP_SATA_MDIO_PLL_CTRL_6_REG_MDIO_WIN_VAL_MASK            0x00ff
#define BCHP_SATA_MDIO_PLL_CTRL_6_REG_MDIO_WIN_VAL_SHIFT           0

/***************************************************************************
 *PLL_CTRL_7_REG - PLL_CTRL_7_REG
 ***************************************************************************/
/* SATA_MDIO :: PLL_CTRL_7_REG :: reserved0 [15:04] */
#define BCHP_SATA_MDIO_PLL_CTRL_7_REG_reserved0_MASK               0xfff0
#define BCHP_SATA_MDIO_PLL_CTRL_7_REG_reserved0_SHIFT              4

/* SATA_MDIO :: PLL_CTRL_7_REG :: PLL_TUNER_CLKFREQ [03:02] */
#define BCHP_SATA_MDIO_PLL_CTRL_7_REG_PLL_TUNER_CLKFREQ_MASK       0x000c
#define BCHP_SATA_MDIO_PLL_CTRL_7_REG_PLL_TUNER_CLKFREQ_SHIFT      2

/* SATA_MDIO :: PLL_CTRL_7_REG :: reserved1 [01:00] */
#define BCHP_SATA_MDIO_PLL_CTRL_7_REG_reserved1_MASK               0x0003
#define BCHP_SATA_MDIO_PLL_CTRL_7_REG_reserved1_SHIFT              0

/***************************************************************************
 *PLL_STAT_0_REG - PLL_STAT_0_REG
 ***************************************************************************/
/* SATA_MDIO :: PLL_STAT_0_REG :: VCO_RANGE_CTL_BITS [15:12] */
#define BCHP_SATA_MDIO_PLL_STAT_0_REG_VCO_RANGE_CTL_BITS_MASK      0xf000
#define BCHP_SATA_MDIO_PLL_STAT_0_REG_VCO_RANGE_CTL_BITS_SHIFT     12

/* SATA_MDIO :: PLL_STAT_0_REG :: LT_REF_VOLT [11:11] */
#define BCHP_SATA_MDIO_PLL_STAT_0_REG_LT_REF_VOLT_MASK             0x0800
#define BCHP_SATA_MDIO_PLL_STAT_0_REG_LT_REF_VOLT_SHIFT            11

/* SATA_MDIO :: PLL_STAT_0_REG :: reserved0 [10:09] */
#define BCHP_SATA_MDIO_PLL_STAT_0_REG_reserved0_MASK               0x0600
#define BCHP_SATA_MDIO_PLL_STAT_0_REG_reserved0_SHIFT              9

/* SATA_MDIO :: PLL_STAT_0_REG :: PLL_DIG_ID [08:05] */
#define BCHP_SATA_MDIO_PLL_STAT_0_REG_PLL_DIG_ID_MASK              0x01e0
#define BCHP_SATA_MDIO_PLL_STAT_0_REG_PLL_DIG_ID_SHIFT             5

/* SATA_MDIO :: PLL_STAT_0_REG :: reserved1 [04:00] */
#define BCHP_SATA_MDIO_PLL_STAT_0_REG_reserved1_MASK               0x001f
#define BCHP_SATA_MDIO_PLL_STAT_0_REG_reserved1_SHIFT              0

/***************************************************************************
 *PLL_STAT_1_REG - PLL_STAT_1_REG
 ***************************************************************************/
/* SATA_MDIO :: PLL_STAT_1_REG :: reserved0 [15:15] */
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_reserved0_MASK               0x8000
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_reserved0_SHIFT              15

/* SATA_MDIO :: PLL_STAT_1_REG :: PLL_SEQSTART_BIT [14:14] */
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_SEQSTART_BIT_MASK        0x4000
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_SEQSTART_BIT_SHIFT       14

/* SATA_MDIO :: PLL_STAT_1_REG :: PLL_CAPSEQ_ST [13:11] */
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_CAPSEQ_ST_MASK           0x3800
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_CAPSEQ_ST_SHIFT          11

/* SATA_MDIO :: PLL_STAT_1_REG :: PLL_VCOSEQ_ST [10:08] */
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_VCOSEQ_ST_MASK           0x0700
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_VCOSEQ_ST_SHIFT          8

/* SATA_MDIO :: PLL_STAT_1_REG :: PLL_LOCK [07:07] */
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_LOCK_MASK                0x0080
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_LOCK_SHIFT               7

/* SATA_MDIO :: PLL_STAT_1_REG :: PLL_LOCKDET_DONE [06:06] */
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_LOCKDET_DONE_MASK        0x0040
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_LOCKDET_DONE_SHIFT       6

/* SATA_MDIO :: PLL_STAT_1_REG :: PLL_VCOSEQ_DONE [05:05] */
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_VCOSEQ_DONE_MASK         0x0020
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_VCOSEQ_DONE_SHIFT        5

/* SATA_MDIO :: PLL_STAT_1_REG :: PLL_VCOSEQ_PASS [04:04] */
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_VCOSEQ_PASS_MASK         0x0010
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_VCOSEQ_PASS_SHIFT        4

/* SATA_MDIO :: PLL_STAT_1_REG :: PLL_RANGE [03:00] */
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_RANGE_MASK               0x000f
#define BCHP_SATA_MDIO_PLL_STAT_1_REG_PLL_RANGE_SHIFT              0

/***************************************************************************
 *CORE_ID - CORE_ID
 ***************************************************************************/
/* SATA_MDIO :: CORE_ID :: CORE_ID [15:00] */
#define BCHP_SATA_MDIO_CORE_ID_CORE_ID_MASK                        0xffff
#define BCHP_SATA_MDIO_CORE_ID_CORE_ID_SHIFT                       0

#endif /* #ifndef BCHP_SATA_MDIO_H__ */

/* End of File */