| /*************************************************************************** |
| * Copyright (c) 1999-2013, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Tue Apr 16 03:20:12 2013 |
| * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_SUN_TOP_CTRL_H__ |
| #define BCHP_SUN_TOP_CTRL_H__ |
| |
| /*************************************************************************** |
| *SUN_TOP_CTRL - Top Control registers |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID 0x00404000 /* Chip family ID */ |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID 0x00404004 /* Product Revision ID */ |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR 0x00404008 /* BSP feature table address */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0 0x0040401c /* Strapping values */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1 0x00404020 /* Strapping values */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS 0x00404024 /* Bond option value register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0 0x00404028 /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1 0x0040402c /* OTP option test register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0 0x00404030 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1 0x00404034 /* OTP option status register */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0 0x00404038 /* Semaphore channel 0 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1 0x0040403c /* Semaphore channel 1 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2 0x00404040 /* Semaphore channel 2 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3 0x00404044 /* Semaphore channel 3 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4 0x00404048 /* Semaphore channel 4 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5 0x0040404c /* Semaphore channel 5 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6 0x00404050 /* Semaphore channel 6 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7 0x00404054 /* Semaphore channel 7 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8 0x00404058 /* Semaphore channel 8 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9 0x0040405c /* Semaphore channel 9 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10 0x00404060 /* Semaphore channel 10 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11 0x00404064 /* Semaphore channel 11 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12 0x00404068 /* Semaphore channel 12 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13 0x0040406c /* Semaphore channel 13 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14 0x00404070 /* Semaphore channel 14 */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15 0x00404074 /* Semaphore channel 15 */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0 0x00404078 /* General watchdog timer 0 */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1 0x0040407c /* General watchdog timer 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 0x00404080 /* General control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1 0x00404084 /* General control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2 0x00404088 /* General control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3 0x0040408c /* General control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4 0x00404090 /* General control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5 0x00404094 /* General control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0 0x00404098 /* General status register 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1 0x0040409c /* General status register 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2 0x004040a0 /* General status register 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x00404100 /* Pinmux control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1 0x00404104 /* Pinmux control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2 0x00404108 /* Pinmux control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3 0x0040410c /* Pinmux control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4 0x00404110 /* Pinmux control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5 0x00404114 /* Pinmux control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6 0x00404118 /* Pinmux control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7 0x0040411c /* Pinmux control register 7 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8 0x00404120 /* Pinmux control register 8 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9 0x00404124 /* Pinmux control register 9 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10 0x00404128 /* Pinmux control register 10 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11 0x0040412c /* Pinmux control register 11 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12 0x00404130 /* Pinmux control register 12 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13 0x00404134 /* Pinmux control register 13 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14 0x00404138 /* Pinmux control register 14 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15 0x0040413c /* Pinmux control register 15 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0 0x00404140 /* Pad pull-up/pull-down control register 0 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1 0x00404144 /* Pad pull-up/pull-down control register 1 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2 0x00404148 /* Pad pull-up/pull-down control register 2 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3 0x0040414c /* Pad pull-up/pull-down control register 3 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4 0x00404150 /* Pad pull-up/pull-down control register 4 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5 0x00404154 /* Pad pull-up/pull-down control register 5 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6 0x00404158 /* Pad pull-up/pull-down control register 6 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7 0x0040415c /* Pad pull-up/pull-down control register 7 */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8 0x00404160 /* Pad pull-up/pull-down control register 8 */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0 0x00404164 /* Bypass clock unselect register 0 */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL 0x00404300 /* Reset control */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE 0x00404304 /* Reset source enable */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET 0x00404308 /* Software master reset */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION 0x0040430c /* Hardware reset extension */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR 0x00404310 /* Reset Monitor */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY 0x00404314 /* Reset history */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET 0x00404318 /* Software init 0 set */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR 0x0040431c /* Software init 0 clear */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS 0x00404320 /* Software init 0 status */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR 0x00404324 /* Security software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR 0x00404328 /* Test configuration software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR 0x0040432c /* Final software init 0 monitor */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET 0x00404330 /* Software init 1 set */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR 0x00404334 /* Software init 1 clear */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS 0x00404338 /* Software init 1 status */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR 0x0040433c /* Security software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR 0x00404340 /* Test configuration software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR 0x00404344 /* Final software init 1 monitor */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER 0x00404348 /* Software init one-shot trigger */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH 0x0040434c /* One-shot 0 width */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK 0x00404350 /* One-shot 0 mask for software init 0 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK 0x00404354 /* One-shot 0 mask for software init 1 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH 0x00404358 /* One-shot 1 width */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK 0x0040435c /* One-shot 1 mask for software init 0 */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK 0x00404360 /* One-shot 1 mask for software init 1 */ |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH 0x00404364 /* Scratch register */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL 0x00404368 /* Spare control bits reserved for future use */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL 0x00404380 /* Test port control */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK 0x00404384 /* Testport peek register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE 0x00404388 /* Testport poke register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK 0x0040438c /* Testport peek register */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE 0x00404390 /* Testport poke register */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN 0x00404394 /* EJTAG input bus enables */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL 0x00404398 /* EJTAG output select */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL 0x0040439c /* UART Router select */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL 0x004043a0 /* VTRAP Control */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS 0x004043a4 /* VTRAP Status */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG 0x00404400 /* Serial Slave Port configuration register */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV 0x00404420 /* SERS Revision Register */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG 0x00404424 /* SERS Configuration Register */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL 0x00404514 /* Block select for RO testmode */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION 0x00404518 /* Test configuration */ |
| |
| /*************************************************************************** |
| *CHIP_FAMILY_ID - Chip family ID |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: CHIP_FAMILY_ID :: chip_family_id [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_CHIP_FAMILY_ID_chip_family_id_DEFAULT 0x75840000 |
| |
| /*************************************************************************** |
| *PRODUCT_ID - Product Revision ID |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PRODUCT_ID :: product_id [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PRODUCT_ID_product_id_DEFAULT 0x75840000 |
| |
| /*************************************************************************** |
| *BSP_FEATURE_TABLE_ADDR - BSP feature table address |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BSP_FEATURE_TABLE_ADDR :: bsp_feature_table_addr [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_BSP_FEATURE_TABLE_ADDR_bsp_feature_table_addr_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STRAP_VALUE_0 - Strapping values |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_shape [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_shape_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_rsvd [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_rsvd_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *STRAP_VALUE_1 - Strapping values |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_xcore_bias [03:01] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_MASK 0x0000000e |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_xcore_bias_DEFAULT 0x00000004 |
| |
| /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_hipass_xtal [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_hipass_xtal_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *BOND_STATUS - Bond option value register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_0 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_spare_0 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_spare_0_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ob_disable [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ob_disable_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ob_disable_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ob_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ds0_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ds0_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ds0_disable_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ds0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ds1_disable [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ds1_disable_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ds1_disable_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ds1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ds2_disable [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ds2_disable_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ds2_disable_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ds2_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_disable [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet1_disable [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet1_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_genet0_disable [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet0_disable_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet0_disable_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_genet0_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avc_disable [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avc_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_vc4_disable [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_vc4_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_directv_disable [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_directv_disable_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_directv_disable_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_directv_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sata_disable [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sata_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sds0_tuner_disable [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds0_tuner_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_disable [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ephy_disable [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ephy_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_disable [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_tfec_disable [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_tfec_disable_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_tfec_disable_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_tfec_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rsvd_ldpc_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ldpc_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ldpc_disable_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rsvd_ldpc_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ds3_disable [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ds3_disable_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ds3_disable_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ds3_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_if_dac_disable [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_if_dac_disable_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_if_dac_disable_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_if_dac_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_avs_disable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_avs_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [06:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK 0x00000060 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_DEFAULT 0x00000003 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_bsp_spares [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_bsp_spares_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_OPTION_TEST_1 - OTP option test register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_30 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_29 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_29_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_28 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_28_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_27 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_27_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_26 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_26_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_25 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_25_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_24 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_24_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_23 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_22 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_21 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_21_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_20 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_19 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_19_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_18 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_18_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_17 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_16 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_16_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_15 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_14 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_13 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_12 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_11 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_10 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_9 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_8 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_7 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_6 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_5 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_4 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_3 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_2 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_1 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_0 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_0_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_rv9_disable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_rv9_disable_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_0 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_spare_0 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_spare_0_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ob_disable [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ob_disable_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ob_disable_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ds0_disable [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ds0_disable_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ds0_disable_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ds1_disable [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ds1_disable_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ds1_disable_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ds2_disable [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ds2_disable_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ds2_disable_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_disable [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet1_disable [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet1_disable_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet1_disable_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_genet0_disable [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet0_disable_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_genet0_disable_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avc_disable [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avc_disable_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_vc4_disable [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_vc4_disable_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_directv_disable [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_directv_disable_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_directv_disable_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sata_disable [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sata_disable_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sds0_tuner_disable [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds0_tuner_disable_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_disable [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_disable_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ephy_disable [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ephy_disable_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_disable [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_disable_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_tfec_disable [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_tfec_disable_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_tfec_disable_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rsvd_ldpc_disable [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ldpc_disable_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rsvd_ldpc_disable_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ds3_disable [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ds3_disable_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ds3_disable_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_if_dac_disable [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_if_dac_disable_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_if_dac_disable_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_avs_disable [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_avs_disable_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [06:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000060 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_bsp_spares [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_bsp_spares_SHIFT 0 |
| |
| /*************************************************************************** |
| *OTP_OPTION_STATUS_1 - OTP option status register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_30 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_30_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_29 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_29_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_28 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_28_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_27 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_27_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_26 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_26_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_25 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_25_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_24 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_24_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_23 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_23_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_22 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_22_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_21 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_21_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_20 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_20_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_19 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_19_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_18 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_18_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_17 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_17_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_16 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_16_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_15 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_15_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_14 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_14_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_13 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_13_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_12 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_12_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_11 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_11_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_10 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_10_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_9 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_9_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_8 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_8_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_7 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_7_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_6 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_6_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_5 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_5_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_4 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_4_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_3 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_3_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_2 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_2_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_1 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_1_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_0 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_rv9_disable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_rv9_disable_SHIFT 0 |
| |
| /*************************************************************************** |
| *SEMAPHORE_0 - Semaphore channel 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_1 - Semaphore channel 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_2 - Semaphore channel 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_3 - Semaphore channel 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_4 - Semaphore channel 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_5 - Semaphore channel 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_6 - Semaphore channel 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_7 - Semaphore channel 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_8 - Semaphore channel 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_9 - Semaphore channel 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_10 - Semaphore channel 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_11 - Semaphore channel 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_12 - Semaphore channel 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_13 - Semaphore channel 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_14 - Semaphore channel 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEMAPHORE_15 - Semaphore channel 15 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GEN_WATCHDOG_0 - General watchdog timer 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GEN_WATCHDOG_1 - General watchdog timer 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_0 - General control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: usb0_mode [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_usb0_mode_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_1 - General control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_2 - General control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_2_disable [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_2_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: usb0_pwrflt_1_disable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_usb0_pwrflt_1_disable_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_3 - General control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_4 - General control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_5 - General control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_0 - General status register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_6 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_6_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_1 - General status register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_STATUS_2 - General status register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_1_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_0_SHIFT 0 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK 0xfffff000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_11_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_10_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_9 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_9_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_8 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_8_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_1_pad_mode [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_1_pad_mode_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: rgmii_0_pad_mode [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_rgmii_0_pad_mode_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK 0xfffffe00 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_8 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_8_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_8_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_8_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_7_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_6 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_6_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_6_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_6_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: host_cpu_backup_clk_sel [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_host_cpu_backup_clk_sel_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_host_cpu_backup_clk_sel_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_host_cpu_backup_clk_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: sdio_drive_src [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_src_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_src_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: sdio_drive_sel [03:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_sel_MASK 0x0000000e |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_sel_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_sdio_drive_sel_DRIVE_16MA 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: mtsif_hys_en [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_mtsif_hys_en_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_mtsif_hys_en_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_mtsif_hys_en_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK 0xfffffff8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved_for_padding1 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved_for_padding1_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved_for_padding1_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: wfe_force_daisy_up [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_wfe_force_daisy_up_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_wfe_force_daisy_up_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_wfe_force_daisy_up_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:20] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK 0xfff00000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_069 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_069_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_069_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_069_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_068 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_068_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_068_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_068_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_066 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_066_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_066_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_066_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_065 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_065_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_065_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_065_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_064 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_064_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_064_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_064_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_063 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_063_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_063_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_063_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_062 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_062_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_062_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_062_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_061 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_061_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_061_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_061_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_060 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_060_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_060_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_060_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_059 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_059_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_059_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_059_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_058 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_058_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_058_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_058_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_055 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_055_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_055_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_055_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_054 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_054_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_054_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_054_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_053 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_053_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_053_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_053_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_052 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_052_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_052_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_052_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_051 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_051_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_051_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_051_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_050 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_050_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_050_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_050_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_049 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_049_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_049_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_049_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_048 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_048_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_048_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_048_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: pad_mode_gpio_047 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_047_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_047_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_pad_mode_gpio_047_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:22] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK 0xffc00000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_pwrdn [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_pwrdn_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl [20:01] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_MASK 0x001ffffe |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: pnp_vregcntl_en [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_pnp_vregcntl_en_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:07] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK 0xffffff80 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_hys_en [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_hys_en_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_oeb [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_oeb_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_thp_do [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_thp_do_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_src [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_src_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: test_drive_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_2MA 0 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_4MA 1 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_6MA 2 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_8MA 3 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_10MA 4 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_12MA 5 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_14MA 6 |
| #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_test_drive_sel_DRIVE_16MA 7 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_0 - Pinmux control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_EBI_ADDR2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MII_TX_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_PM_GPIO_02 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_EBI_ADDR1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MII_RX_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_PM_GPIO_01 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_EBI_ADDR0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MII_RX_DV 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_PM_GPIO_00 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_sck [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SF_SCK 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_PM_SF_SCK 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_mosi [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SF_MOSI 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_PM_SF_MOSI 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_miso [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SF_MISO 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_PM_SF_MISO 1 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_24 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_GPIO_24 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_OOB_AGC_CTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_CC_DRX 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_24_PM_GPIO_24 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_23 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_GPIO_23 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_DS_AGC_CTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_CC_CRX 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_23_PM_GPIO_23 3 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_1 - Pinmux control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_EBI_ADDR10 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MII_TXD_00 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_PM_GPIO_10 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_EBI_ADDR9 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MII_TXD_01 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_PM_GPIO_09 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_EBI_ADDR8 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MII_TXD_02 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_PM_GPIO_08 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_07 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_GPIO_07 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_EBI_ADDR7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MII_TXD_03 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_PM_GPIO_07 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_06 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_GPIO_06 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_EBI_ADDR6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MII_RXD_00 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_PM_GPIO_06 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_05 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_GPIO_05 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_EBI_ADDR5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MII_RXD_01 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_PM_GPIO_05 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_04 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_GPIO_04 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_EBI_ADDR4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MII_RXD_02 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_PM_GPIO_04 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_03 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_GPIO_03 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_EBI_ADDR3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MII_RXD_03 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_PM_GPIO_03 3 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_2 - Pinmux control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_18 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_GPIO_18 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_EBI_CS0B 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_PM_GPIO_18 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_17 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_GPIO_17 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_EBI_RWB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_PM_GPIO_17 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_16 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_GPIO_16 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_EBI_WE1B 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_PM_GPIO_16 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_15 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_GPIO_15 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_EBI_WAITB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_PM_GPIO_15 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_14 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_GPIO_14 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_EBI_ADDR14 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MII_COL 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_PM_GPIO_14 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_13 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_GPIO_13 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_EBI_ADDR13 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MII_TX_ER 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_PM_GPIO_13 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_12 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_GPIO_12 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_EBI_ADDR12 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MII_RX_ER 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_PM_GPIO_12 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_11 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_GPIO_11 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_EBI_ADDR11 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MII_TX_EN 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_PM_GPIO_11 3 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_3 - Pinmux control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_28 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_GPIO_28 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_EBI_DATA3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_OUT_23 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_TP_IN_23 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_28_PM_GPIO_28 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_27 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_GPIO_27 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_EBI_DATA2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_OUT_22 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_TP_IN_22 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_27_PM_GPIO_27 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_26 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_GPIO_26 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_EBI_DATA1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_OUT_21 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_TP_IN_21 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_26_PM_GPIO_26 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_25 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_GPIO_25 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_EBI_DATA0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_OUT_20 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TEST_THP 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_TP_IN_20 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_25_PM_GPIO_25 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_22 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_GPIO_22 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_EBI_CS4B 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SPI_M_SS0B 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_PM_GPIO_22 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_21 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_GPIO_21 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_EBI_CS3B 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_PM_GPIO_21 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_20 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_GPIO_20 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_EBI_CS2B 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_TP_OUT_07 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_PM_GPIO_20 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_19 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_GPIO_19 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_EBI_CS1B 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_PM_GPIO_19 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_4 - Pinmux control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_36 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_GPIO_36 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_EBI_DATA11 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_SC1_IO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_36_PM_GPIO_36 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_35 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_GPIO_35 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_EBI_DATA10 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_SC1_RST 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_35_PM_GPIO_35 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_34 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_GPIO_34 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_EBI_DATA9 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_SC1_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_34_PM_GPIO_34 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_33 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_GPIO_33 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_EBI_DATA8 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_SC1_VCC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_33_PM_GPIO_33 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_32 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_GPIO_32 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_EBI_DATA7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_27 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_IN_27 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_TP_OUT_21 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_32_PM_GPIO_32 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_31 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_GPIO_31 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_EBI_DATA6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_26 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_IN_26 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_TP_OUT_20 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_31_PM_GPIO_31 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_30 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_GPIO_30 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_EBI_DATA5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_OUT_25 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_IN_25 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_PM_GPIO_30 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_29 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_GPIO_29 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_EBI_DATA4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_OUT_24 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_IN_24 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_PM_GPIO_29 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_5 - Pinmux control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_44 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_GPIO_44 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_EBI_TSB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_31 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_31 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_IN_19 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_TP_OUT_26 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_44_PM_GPIO_44 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_43 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_GPIO_43 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_EBI_DSB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_30 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_30 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_IN_18 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_TP_OUT_25 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_43_PM_GPIO_43 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_42 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_GPIO_42 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_EBI_WE0B 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_29 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_IN_29 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_TP_OUT_23 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_42_PM_GPIO_42 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_41 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_GPIO_41 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_EBI_RDB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_28 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_IN_28 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_TP_OUT_22 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_41_PM_GPIO_41 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_40 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_GPIO_40 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_EBI_DATA15 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SPI_M_SCK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_MII_COL 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_SC1_AUX2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_40_PM_GPIO_40 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_39 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_GPIO_39 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_EBI_DATA14 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SPI_M_MISO 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_MII_TX_ER 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_SC1_AUX1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_39_PM_GPIO_39 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_38 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_GPIO_38 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_EBI_DATA13 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SPI_M_MOSI 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_MII_RX_ER 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_SC1_VPP 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_38_PM_GPIO_38 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_37 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_GPIO_37 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_EBI_DATA12 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_SC1_PRES 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_37_PM_GPIO_37 3 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_6 - Pinmux control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_52 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_GPIO_52 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_POD2CHIP_MDI5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PPKT_I_DATA_5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_52_PM_GPIO_52 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_51 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_GPIO_51 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_POD2CHIP_MDI4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PPKT_I_DATA_4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_51_PM_GPIO_51 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_50 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_GPIO_50 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_POD2CHIP_MDI3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PPKT_I_DATA_3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_50_PM_GPIO_50 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_49 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_GPIO_49 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_POD2CHIP_MDI2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PPKT_I_DATA_2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_49_PM_GPIO_49 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_48 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_GPIO_48 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_POD2CHIP_MDI1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PPKT_I_DATA_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_48_PM_GPIO_48 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_47 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_GPIO_47 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_POD2CHIP_MDI0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PPKT_I_DATA_0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_47_PM_GPIO_47 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_46 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_GPIO_46 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_POD2CHIP_MCLKI 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PPKT_I_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_EBI_ADDR14 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_46_PM_GPIO_46 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_45 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_GPIO_45 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_NAND_RBB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_TP_OUT_16 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_45_PM_GPIO_45 3 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_7 - Pinmux control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_60 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_GPIO_60 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_CHIP2POD_MDO2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_RMXP_DATA2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_EBI_ADDR20 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_60_PM_GPIO_60 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_59 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_GPIO_59 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_CHIP2POD_MDO1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_RMXP_DATA1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_EBI_ADDR19 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_59_PM_GPIO_59 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_58 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_GPIO_58 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_CHIP2POD_MDO0 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_RMXP_DATA0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_EBI_ADDR18 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_58_PM_GPIO_58 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_57 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_GPIO_57 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_CHIP2POD_MCLKO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_RMXP_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_EBI_ADDR15 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_57_PM_GPIO_57 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_56 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_GPIO_56 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_POD2CHIP_MIVAL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PPKT_I_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_56_PM_GPIO_56 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_55 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_GPIO_55 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_POD2CHIP_MISTRT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PPKT_I_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_55_PM_GPIO_55 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_54 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_GPIO_54 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_POD2CHIP_MDI7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PPKT_I_DATA_7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_54_PM_GPIO_54 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_53 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_GPIO_53 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_POD2CHIP_MDI6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PPKT_I_DATA_6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_53_PM_GPIO_53 3 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_8 - Pinmux control register 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_68 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_GPIO_68 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_POD2CHIP_MICLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PPKT_I_ERROR 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_EBI_ADDR13 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_68_PM_GPIO_68 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_67 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_GPIO_67 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_CHIP2POD_MOVAL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_RMXP_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_EBI_ADDR16 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_67_PM_GPIO_67 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_66 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_GPIO_66 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_CHIP2POD_MOSTRT 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_RMXP_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_EBI_ADDR17 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_66_PM_GPIO_66 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_65 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_GPIO_65 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_CHIP2POD_MDO7 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_RMXP_DATA7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_EBI_ADDR25 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_65_PM_GPIO_65 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_64 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_GPIO_64 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_CHIP2POD_MDO6 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_RMXP_DATA6 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_EBI_ADDR24 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_64_PM_GPIO_64 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_63 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_GPIO_63 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_CHIP2POD_MDO5 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_RMXP_DATA5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_EBI_ADDR23 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_63_PM_GPIO_63 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_62 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_GPIO_62 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_CHIP2POD_MDO4 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_RMXP_DATA4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_EBI_ADDR22 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_62_PM_GPIO_62 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_61 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_GPIO_61 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_CHIP2POD_MDO3 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_RMXP_DATA3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_EBI_ADDR21 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_61_PM_GPIO_61 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_9 - Pinmux control register 9 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_76 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_GPIO_76 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_RMX0_SYNC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PKT1_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_MTSIF0_SYNC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_76_PM_GPIO_76 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_75 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_GPIO_75 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_RMX0_DATA 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PKT1_DATA 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_CLK_OBSRV3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_MTSIF0_DATA0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_75_PM_GPIO_75 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_74 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_GPIO_74 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_RMX0_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PKT1_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_CLK_OBSRV2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_MTSIF0_CLK 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_74_PM_GPIO_74 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_73 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_GPIO_73 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_MPOD_M_SDI 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_73_PM_GPIO_73 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_72 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_GPIO_72 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_MPOD_M_SDO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_EBI_ADDR0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_72_PM_GPIO_72 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_71 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_GPIO_71 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_MPOD_SCLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_EBI_ADDR1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_71_PM_GPIO_71 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_70 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_GPIO_70 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_MPOD_SCTL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_EBI_ADDR2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_70_PM_GPIO_70 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_69 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_DEFAULT 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_GPIO_69 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_CHIP2POD_MOCLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_RMXP_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_EBI_ADDR12 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_AUD_FS_CLK1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_69_PM_GPIO_69 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_10 - Pinmux control register 10 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_84 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_GPIO_84 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_SC0_AUX1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_I2S_DATA0_IN 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_TP_OUT_13 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_84_PM_GPIO_84 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_83 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_GPIO_83 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_SC0_PRES 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_I2S_CLK0_IN 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_TP_OUT_12 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_83_PM_GPIO_83 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_82 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_GPIO_82 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_SC0_IO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_TP_OUT_11 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_82_PM_GPIO_82 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_81 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_GPIO_81 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_SC0_RST 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_TP_OUT_10 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_81_PM_GPIO_81 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_80 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_GPIO_80 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_SC0_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_TP_OUT_09 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_80_PM_GPIO_80 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_79 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_GPIO_79 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_SC0_VCC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_TP_OUT_08 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_79_PM_GPIO_79 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_78 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_GPIO_78 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_RMX0_PAUSE 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT1_ERROR 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PKT3_DATA 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_I2S_LR0_IN 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_MTSIF0_DATA1 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_78_PM_GPIO_78 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_77 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_GPIO_77 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_RMX0_VALID 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT1_VALID 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PKT3_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_SPI_M_SS1B 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_77_PM_GPIO_77 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_11 - Pinmux control register 11 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_92 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_GPIO_92 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_UART_RX2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_IR_OUT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_ALT_TP_IN_02 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_POD2CHIP_MCLKI 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_92_PM_GPIO_92 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_91 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_GPIO_91 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_UART_TX2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PWM0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_ALT_TP_OUT_02 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_POD_EBI_DSB 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_91_PM_GPIO_91 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_90 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_GPIO_90 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_UART_RX1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_VEC_VSYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_ALT_TP_IN_01 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_POD_EBI_WE0B 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_90_PM_GPIO_90 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_89 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_GPIO_89 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_UART_TX1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_VEC_HSYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_ALT_TP_OUT_01 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_POD_EBI_RDB 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_89_PM_GPIO_89 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_88 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_GPIO_88 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_SPI_S_SSB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_UART_RX0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_ALT_TP_IN_00 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_88_PM_GPIO_88 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_87 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_GPIO_87 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_SPI_S_MISO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_UART_TX0 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_ALT_TP_OUT_00 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_87_PM_GPIO_87 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_86 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_GPIO_86 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_SC0_VPP 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_USB0_PWRFLT_1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_TP_OUT_15 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_86_PM_GPIO_86 4 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_85 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_GPIO_85 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_SC0_AUX2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_I2S_LR0_IN 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_TP_OUT_14 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_USB0_PWRFLT_2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_85_PM_GPIO_85 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_12 - Pinmux control register 12 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_GPIO_101 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_USB0_PWRON_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_RMX1_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_TP_OUT_17 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SDS0_RF_AGC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_ENET_ACTIVITY 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PM_GPIO_101 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_100 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_GPIO_100 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PKT2_ERROR 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_VPP 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_VEC_HSYNC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_UART_CTS2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_CODEC_FSYNCB 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SPI_M_SS1B 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SC1_PRES 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MTSIF0_DATA5 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PM_GPIO_100 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_99 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_GPIO_99 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT2_VALID 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PKT3_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_IR_OUT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_UART_RX2 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_CODEC_SDI 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SPI_M_MISO 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_SC1_IO 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_MTSIF_ATS_RST 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_99_PM_GPIO_99 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_98 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_GPIO_98 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PKT2_SYNC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_CODEC_MCLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SPI_M_SCK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_SC1_RST 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_MTSIF0_DATA4 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_98_PM_GPIO_98 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_97 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_GPIO_97 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PKT2_DATA 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_UART_RTS2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_CODEC_SDO 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SPI_M_SS0B 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_SC1_CLK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_MTSIF0_DATA3 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_97_PM_GPIO_97 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_96 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_GPIO_96 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PKT2_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_UART_TX2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_CODEC_SCLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SPI_M_MOSI 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_SC1_VCC 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_MTSIF0_DATA2 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_96_PM_GPIO_96 7 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_94 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_GPIO_94 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_SF_WPB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_EXT_IRQ3 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PWM0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_UART_RTS0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_I2S_DATA0_IN 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_94_PM_GPIO_94 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_93 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_GPIO_93 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_SF_HOLDB 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_EXT_IRQ2 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_VEC_VSYNC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_UART_CTS0 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_I2S_CLK0_IN 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_93_PM_GPIO_93 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_13 - Pinmux control register 13 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_110 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_GPIO_110 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_MII_CRS 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_EBI_ADDR15 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_110_PM_GPIO_110 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_109 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_GPIO_109 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MII_COL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PKT4_SYNC 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_IN 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR0_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_I2S_LR1_OUT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_SC1_AUX2 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_MTSIF0_DATA7 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_109_PM_GPIO_109 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_108 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_GPIO_108 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MII_TX_ER 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PKT4_DATA 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_IN 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA0_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_I2S_DATA1_OUT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_SC1_AUX1 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_TP_IN_31 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_MTSIF0_DATA6 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_108_PM_GPIO_108 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_107 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_GPIO_107 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MII_RX_ER 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PKT4_CLK 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_IN 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK0_OUT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_I2S_CLK1_OUT 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_SC1_VPP 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_TP_IN_30 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_MTSIF_ATS_INC 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_107_PM_GPIO_107 9 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_105 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_GPIO_105 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_ENET_ACTIVITY 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PWM1 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_OBSRV0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_CLK_27 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_AUD_FS_CLK0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_SC_CLK_OUT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_TP_OUT_19 7 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_105_PM_GPIO_105 8 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_104 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_GPIO_104 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_USB0_PWRFLT_2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_EXT_IRQ5 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_RMX1_SYNC 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_IR_INT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_SATA_MDCLK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_104_PM_GPIO_104 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_103 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_GPIO_103 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_USB0_PWRFLT_1 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_EXT_IRQ4 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_RMX1_PAUSE 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_P1_INTR_1 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_SATA_MDIO 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_103_PM_GPIO_103 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_102 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_GPIO_102 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_USB0_PWRON_2 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_RMX1_DATA 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_TP_OUT_18 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_SDS0_IF_AGC 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_ENET_LINK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_102_PM_GPIO_102 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_14 - Pinmux control register 14 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_118 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_GPIO_118 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_RGMII_TXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_EBI_ADDR23 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_SDIO0_DAT3 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_TP_OUT_27 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_VO0_656_4 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_118_PM_GPIO_118 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_117 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_GPIO_117 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_RGMII_RXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_EBI_ADDR22 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_SDIO0_LED 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_TP_OUT_26 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_VO0_656_3 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_117_PM_GPIO_117 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_116 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_GPIO_116 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_RGMII_RXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_EBI_ADDR21 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_SDIO0_CLK 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_TP_OUT_25 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_VO0_656_2 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_116_PM_GPIO_116 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_115 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_GPIO_115 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_RGMII_RXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_EBI_ADDR20 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_SDIO0_PWR0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_TP_OUT_24 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_VO0_656_1 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_115_PM_GPIO_115 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_114 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_GPIO_114 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_RGMII_RXD_03 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_EBI_ADDR19 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_SDIO0_WPROT 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_TP_OUT_23 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_VO0_656_0 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_114_PM_GPIO_114 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_113 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_GPIO_113 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_RGMII_TX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_EBI_ADDR18 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_SDIO0_PRES 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_TP_OUT_22 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_VO0_656_CLK 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_113_PM_GPIO_113 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_112 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_GPIO_112 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_RGMII_RX_CLK 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_EBI_ADDR17 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_SDIO_VCTL 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_TP_OUT_21 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_112_PM_GPIO_112 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: gpio_111 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_GPIO_111 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_RGMII_RX_DV 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_EBI_ADDR16 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_TP_OUT_20 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_gpio_111_PM_GPIO_111 4 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_15 - Pinmux control register 15 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_03 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_SGPIO_03 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_BSC_M1_SDA 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_EXT_IRQ7 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_03_P1_INTR_1 3 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: sgpio_02 [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_SGPIO_02 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_BSC_M1_SCL 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_sgpio_02_EXT_IRQ6 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_124 [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_GPIO_124 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_RGMII_MDIO 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_124_PM_GPIO_124 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_123 [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_GPIO_123 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_RGMII_MDC 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_123_PM_GPIO_123 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_122 [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_GPIO_122 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_RGMII_TX_EN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_EBI_ADDR27 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_SDIO0_CMD 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_TP_OUT_31 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_122_PM_GPIO_122 5 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_121 [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_GPIO_121 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_RGMII_TXD_00 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_EBI_ADDR26 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_SDIO0_DAT0 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_TP_OUT_30 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_VO0_656_7 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_121_PM_GPIO_121 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_120 [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_GPIO_120 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_RGMII_TXD_01 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_EBI_ADDR25 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_SDIO0_DAT1 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_TP_OUT_29 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_VO0_656_6 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_120_PM_GPIO_120 6 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: gpio_119 [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_GPIO_119 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_RGMII_TXD_02 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_EBI_ADDR24 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_SDIO0_DAT2 3 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_TP_OUT_28 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_VO0_656_5 5 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_gpio_119_PM_GPIO_119 6 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_08_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_08_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_07_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_07_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_06_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_06_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_05_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_05_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_04_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_04_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_03_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_03_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_02_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_02_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_01_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_01_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_00_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_00_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_24_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_24_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: gpio_23_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_gpio_23_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_25_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_25_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_22_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_22_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_21_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_21_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_20_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_20_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_19_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_19_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_18_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_18_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_17_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_17_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_16_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_16_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_15_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_15_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_14_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_14_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_13_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_13_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_12_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_12_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_11_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_11_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_10_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_10_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: gpio_09_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_gpio_09_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_40_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_40_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_39_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_39_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_38_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_38_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_37_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_37_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_36_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_36_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_35_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_35_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_34_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_34_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_33_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_33_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_32_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_32_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_31_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_31_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_30_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_30_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_29_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_29_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_28_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_28_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_27_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_27_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_26_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_26_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_55_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_55_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_54_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_54_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_53_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_53_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_52_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_52_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_51_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_51_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_50_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_50_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_49_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_49_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_48_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_48_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_47_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_47_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_46_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_46_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_45_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_45_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_44_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_44_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_43_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_43_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_42_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_42_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_41_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_41_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_70_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_70_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_69_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_69_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_68_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_68_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_67_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_67_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_66_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_66_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_65_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_65_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_64_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_64_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_63_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_63_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_62_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_62_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_61_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_61_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_60_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_60_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_59_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_59_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_58_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_58_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_57_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_57_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_56_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_56_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_85_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_85_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_84_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_84_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_83_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_83_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_82_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_82_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_81_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_81_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_80_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_80_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_79_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_79_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_78_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_78_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_77_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_77_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_76_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_76_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_75_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_75_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_74_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_74_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_73_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_73_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_72_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_72_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_71_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_71_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_101_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_101_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_100_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_100_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_99_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_99_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_98_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_98_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_97_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_97_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_96_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_96_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_94_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_94_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_93_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_93_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_92_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_92_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_91_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_91_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_90_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_90_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_89_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_89_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_88_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_88_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_87_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_87_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_86_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_86_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_117_pad_ctrl [29:28] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_MASK 0x30000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_117_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_116_pad_ctrl [27:26] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_116_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_115_pad_ctrl [25:24] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_MASK 0x03000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_115_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_114_pad_ctrl [23:22] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_114_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_113_pad_ctrl [21:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_MASK 0x00300000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_113_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_112_pad_ctrl [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_112_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_111_pad_ctrl [17:16] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_MASK 0x00030000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_111_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_110_pad_ctrl [15:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_110_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_109_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_109_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_108_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_108_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_107_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_107_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_105_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_105_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_104_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_104_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_103_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_103_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_102_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_102_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved0 [31:20] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_MASK 0xfff00000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved0_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [19:18] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0x000c0000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: reserved1 [17:14] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_MASK 0x0003c000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_reserved1_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_124_pad_ctrl [13:12] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_MASK 0x00003000 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_124_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_123_pad_ctrl [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_123_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_122_pad_ctrl [09:08] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_MASK 0x00000300 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_122_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_121_pad_ctrl [07:06] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_121_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_120_pad_ctrl [05:04] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_MASK 0x00000030 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_120_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_119_pad_ctrl [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_119_pad_ctrl_PULL_UP 2 |
| |
| /* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_118_pad_ctrl [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_NONE 0 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_118_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_24 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_24_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_23 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_23_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_CTRL - Reset control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_SOURCE_ENABLE - Reset source enable |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: reserved0 [31:10] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_MASK 0xfffffc00 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_en_lock [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_1_enable [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_1_enable_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_en_lock [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_level_reset_0_enable [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_level_reset_0_enable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_en_lock [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_1_enable [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_1_enable_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_en_lock [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: aux_chip_edge_reset_0_enable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_aux_chip_edge_reset_0_enable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_en_lock [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_en_lock_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: RESET_SOURCE_ENABLE :: sw_master_reset_enable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RESET_SOURCE_ENABLE_sw_master_reset_enable_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_MASTER_RESET - Software master reset |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_MASTER_RESET :: reserved0 [31:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_MASK 0xfffffffe |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_reserved0_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SW_MASTER_RESET :: chip_master_reset [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_MASTER_RESET_chip_master_reset_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *HW_RESET_EXTENSION - Hardware reset extension |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: HW_RESET_EXTENSION :: hw_reset_extension [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_HW_RESET_EXTENSION_hw_reset_extension_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET_MONITOR - Reset Monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reserved0 [31:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_MASK 0xffffff00 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reserved0_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: cpu_sw_init_def_val [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_cpu_sw_init_def_val_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_def_val [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_def_val_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: hold_cpu_in_reset_monitor [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_hold_cpu_in_reset_monitor_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_outb_monitor [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_outb_monitor_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: front_panel_reset_monitor [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_front_panel_reset_monitor_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: reset_ext_mode_monitor [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_reset_ext_mode_monitor_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: phase5_reset_timer_monitor [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase5_reset_timer_monitor_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_MONITOR :: phase4_reset_timer_monitor [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_MONITOR_phase4_reset_timer_monitor_SHIFT 0 |
| |
| /*************************************************************************** |
| *RESET_HISTORY - Reset history |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:18] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK 0xfffc0000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_1 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_1_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset_0 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_1 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_1_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset_0 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_0_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: undervoltage_reset [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_undervoltage_reset_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: overvoltage_reset [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overvoltage_reset_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: overtemp_reset [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_overtemp_reset_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: scpu_ejtag_reset [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_scpu_ejtag_reset_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_ejtag_reset [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_ejtag_reset_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: security_master_reset [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_security_master_reset_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_1_hot_boot_reset [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_1_hot_boot_reset_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: pcie_0_hot_boot_reset [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_pcie_0_hot_boot_reset_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_0_SET - Software init 0 set |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_rfm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sata_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_28_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_genet0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_25_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_raaga_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: avd0_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_avd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_dvp_ht_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_not_used_sw_init_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_ext_sys_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_cpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_SET :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_SET_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_0_CLEAR - Software init 0 clear |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_rfm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sata_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_28_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_genet0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_25_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_raaga_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: avd0_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_avd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_dvp_ht_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_not_used_sw_init_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_ext_sys_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_cpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_CLEAR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_CLEAR_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_0_STATUS - Software init 0 status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_rfm_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_30_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sata_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_28_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_genet0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_25_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_17_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_raaga_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_aio_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_gfx_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: avd0_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_avd0_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_12_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_dvp_ht_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_vec_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_bvn_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_not_used_sw_init_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_0_STATUS :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_0_STATUS_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SEC_SW_INIT_0_MONITOR - Security software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_CONFIG_SW_INIT_0_MONITOR - Test configuration software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *FINAL_SW_INIT_0_MONITOR - Final software init 0 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_rfm_sw_init_SHIFT 31 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_30_SHIFT 30 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sata_sw_init_SHIFT 29 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_28_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet1_sw_init_SHIFT 27 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_genet0_sw_init_SHIFT 26 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_25_SHIFT 25 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_usb0_sw_init_SHIFT 24 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_23_SHIFT 23 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_22_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ddr0_sw_init_SHIFT 21 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_20_SHIFT 20 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_memc0_sw_init_SHIFT 19 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_xpt_sw_init_SHIFT 18 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_17_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_raaga_sw_init_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_aio_sw_init_SHIFT 15 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_gfx_sw_init_SHIFT 14 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: avd0_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_avd0_sw_init_SHIFT 13 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_12_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_11_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_dvp_ht_sw_init_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_vec_sw_init_SHIFT 9 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_bvn_sw_init_SHIFT 8 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_7_SHIFT 7 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ebi_sw_init_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_5_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_4_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_not_used_sw_init_3_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_ext_sys_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_cpu_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_0_MONITOR :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_0_MONITOR_sys_ctrl_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_1_SET - Software init 1 set |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: reserved0 [31:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_MASK 0xffffffc0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_reserved0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare1_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: spare0_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: leap_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_leap_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: sid_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_sid_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: ds_wfe_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ds_wfe_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ds_wfe_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ds_wfe_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_SET :: ds_top0_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ds_top0_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ds_top0_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_SET_ds_top0_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_1_CLEAR - Software init 1 clear |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: reserved0 [31:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_MASK 0xffffffc0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_reserved0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare1_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: spare0_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: leap_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_leap_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: sid_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_sid_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ds_wfe_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ds_wfe_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ds_wfe_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ds_wfe_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_CLEAR :: ds_top0_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ds_top0_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ds_top0_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_CLEAR_ds_top0_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SW_INIT_1_STATUS - Software init 1 status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: reserved0 [31:06] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_MASK 0xffffffc0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_reserved0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare1_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare1_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: spare0_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: leap_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_leap_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: sid_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_sid_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ds_wfe_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ds_wfe_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ds_wfe_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ds_wfe_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_1_STATUS :: ds_top0_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ds_top0_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ds_top0_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_1_STATUS_ds_top0_sw_init_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SEC_SW_INIT_1_MONITOR - Security software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: reserved0 [31:06] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_MASK 0xffffffc0 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_reserved0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare1_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: spare0_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: leap_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: sid_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ds_wfe_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ds_wfe_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ds_wfe_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SEC_SW_INIT_1_MONITOR :: ds_top0_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ds_top0_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SEC_SW_INIT_1_MONITOR_ds_top0_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_CONFIG_SW_INIT_1_MONITOR - Test configuration software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: reserved0 [31:06] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_MASK 0xffffffc0 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_reserved0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare1_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: spare0_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: leap_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: sid_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ds_wfe_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ds_wfe_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ds_wfe_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIG_SW_INIT_1_MONITOR :: ds_top0_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ds_top0_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIG_SW_INIT_1_MONITOR_ds_top0_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *FINAL_SW_INIT_1_MONITOR - Final software init 1 monitor |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: reserved0 [31:06] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_MASK 0xffffffc0 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_reserved0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare1_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare1_sw_init_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: spare0_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_spare0_sw_init_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: leap_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_leap_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_leap_sw_init_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: sid_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_sid_sw_init_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ds_wfe_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ds_wfe_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ds_wfe_sw_init_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: FINAL_SW_INIT_1_MONITOR :: ds_top0_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ds_top0_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_FINAL_SW_INIT_1_MONITOR_ds_top0_sw_init_SHIFT 0 |
| |
| /*************************************************************************** |
| *SW_INIT_ONE_SHOT_TRIGGER - Software init one-shot trigger |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: reserved0 [31:02] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_MASK 0xfffffffc |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_reserved0_SHIFT 2 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_1 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SW_INIT_ONE_SHOT_TRIGGER :: trigger_one_shot_0 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SW_INIT_ONE_SHOT_TRIGGER_trigger_one_shot_0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_WIDTH - One-shot 0 width |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_WIDTH :: one_shot_0_width [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_WIDTH_one_shot_0_width_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_0_MASK - One-shot 0 mask for software init 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: avd0_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_0_SW_INIT_1_MASK - One-shot 0 mask for software init 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: reserved0 [31:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_MASK 0xffffffc0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_reserved0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare1_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: spare0_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: leap_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_leap_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: sid_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ds_wfe_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ds_wfe_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ds_wfe_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ds_wfe_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_0_SW_INIT_1_MASK :: ds_top0_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ds_top0_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ds_top0_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_0_SW_INIT_1_MASK_ds_top0_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_WIDTH - One-shot 1 width |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: reserved0 [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_reserved0_SHIFT 28 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_WIDTH :: one_shot_1_width [27:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_MASK 0x0fffffff |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_WIDTH_one_shot_1_width_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_0_MASK - One-shot 1 mask for software init 0 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: rfm_sw_init [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_rfm_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_30_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sata_sw_init [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sata_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_28_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet1_sw_init [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: genet0_sw_init [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_genet0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_25_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: usb0_sw_init [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_usb0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ddr0_sw_init [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ddr0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: memc0_sw_init [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_memc0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: xpt_sw_init [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_xpt_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: raaga_sw_init [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_raaga_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: aio_sw_init [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_aio_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: gfx_sw_init [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_gfx_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: avd0_sw_init [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_avd0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: dvp_ht_sw_init [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_dvp_ht_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: vec_sw_init [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_vec_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: bvn_sw_init [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_bvn_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_7 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_7_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ebi_sw_init [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ebi_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_5 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_5_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_4 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: not_used_sw_init_3 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_not_used_sw_init_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: ext_sys_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_ext_sys_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: cpu_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_cpu_sw_init_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_0_MASK :: sys_ctrl_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_0_MASK_sys_ctrl_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *ONE_SHOT_1_SW_INIT_1_MASK - One-shot 1 mask for software init 1 |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: reserved0 [31:06] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_MASK 0xffffffc0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_reserved0_SHIFT 6 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare1_sw_init [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare1_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: spare0_sw_init [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_spare0_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: leap_sw_init [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_leap_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: sid_sw_init [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_sid_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ds_wfe_sw_init [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ds_wfe_sw_init_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ds_wfe_sw_init_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ds_wfe_sw_init_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: ONE_SHOT_1_SW_INIT_1_MASK :: ds_top0_sw_init [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ds_top0_sw_init_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ds_top0_sw_init_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_ONE_SHOT_1_SW_INIT_1_MASK_ds_top0_sw_init_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *UNCLEARED_SCRATCH - Scratch register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPARE_CTRL - Spare control bits reserved for future use |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK 0x80000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT 31 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK 0x40000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT 30 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK 0x20000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK 0x04000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT 26 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK 0x02000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT 25 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK 0x01000000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK 0x00800000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT 23 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK 0x00400000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK 0x00200000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT 21 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK 0x00100000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK 0x00080000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT 19 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK 0x00040000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT 18 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK 0x00020000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK 0x00010000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK 0x00008000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT 15 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK 0x00004000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT 14 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK 0x00002000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT 13 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK 0x00001000 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK 0x00000080 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK 0x00000040 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT 6 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK 0x00000020 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT 5 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK 0x00000008 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TEST_PORT_CTRL - Test port control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sys_ctrl_local_tp_out_sel [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_0 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SEMAPHORE_1 1 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_02 2 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_MISC_TEST 3 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SSP 4 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_OUT_POKE_REG 5 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TP_IN 6 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_SOFT_MODEM_TP 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UPG_TP_OUT 12 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_ICID_TP_OUT 14 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sys_ctrl_local_tp_out_sel_TOP_AUX_TP_OUT 15 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK 0x0ffffc00 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT 10 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK 0x00000180 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK 0x0000007f |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DEFAULT 0x0000007f |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET0 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GENET1 1 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU 2 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DS_TOP0 3 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SATA 4 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RFM 5 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SCPU 6 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SYS 16 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK 17 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AON 18 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF 20 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP 21 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE 22 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM 23 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC 25 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0 27 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFX 29 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO 30 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RAAGA 31 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT 33 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0 35 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB0 45 |
| |
| /*************************************************************************** |
| *TEST_PORT_OUT_PEEK - Testport peek register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_OUT_POKE - Testport poke register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TEST_PORT_IN_PEEK - Testport peek register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0 |
| |
| /*************************************************************************** |
| *TEST_PORT_IN_POKE - Testport poke register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EJTAG_INPUT_EN - EJTAG input bus enables |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:05] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK 0xffffffe0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [04:00] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK 0x0000001f |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DEFAULT 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_LEAP_CPU_ONE_HOT 4 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SCPU_CPU_ONE_HOT 8 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_CPU_ONE_HOT 16 |
| |
| /*************************************************************************** |
| *EJTAG_OUTPUT_SEL - EJTAG output select |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK 0xfffffff8 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */ |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK 0x00000007 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_LEAP_CPU 2 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SCPU_CPU 3 |
| #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_CPU 4 |
| |
| /*************************************************************************** |
| *UART_ROUTER_SEL - UART Router select |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK 0xf0000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK 0x0f000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT 24 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK 0x00f00000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT 20 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK 0x000f0000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT 16 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK 0x0000f000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK 0x00000f00 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_FP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_LEAP_CPU 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK 0x000000f0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_FP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_LEAP_CPU 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15 |
| |
| /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU 0 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_FP 1 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL 2 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL 3 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SID 4 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_LEAP_CPU 5 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14 |
| #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15 |
| |
| /*************************************************************************** |
| *VTRAP_CTRL - VTRAP Control |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: reserved0 [31:12] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_MASK 0xfffff000 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_reserved0_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_max_threshold [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_max_threshold_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_min_threshold [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_min_threshold_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_enable_warning_threshold [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_enable_warning_threshold_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_vddcmon_test_trim_code [08:03] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_MASK 0x000001f8 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_vddcmon_test_trim_code_DEFAULT 0x00000018 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_warning_status_clear [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_warning_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_min_status_clear [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_min_status_clear_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_CTRL :: vtrap_threshold_max_status_clear [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_CTRL_vtrap_threshold_max_status_clear_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VTRAP_STATUS - VTRAP Status |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: reserved0 [31:03] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_MASK 0xfffffff8 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_reserved0_SHIFT 3 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_warning_status [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_warning_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_min_status [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_min_status_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: VTRAP_STATUS :: vtrap_threshold_max_status [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_VTRAP_STATUS_vtrap_threshold_max_status_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SSP_CONFIG - Serial Slave Port configuration register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK 0xfffff800 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT 11 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK 0x00000780 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT 7 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_DEFAULT 0x00000004 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK 0x00000078 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT 3 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK 0x00000004 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK 0x00000002 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT 1 |
| |
| /* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SERS_REV - SERS Revision Register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK 0xffff0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT 16 |
| |
| /* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK 0x0000ff00 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK 0x000000ff |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SERS_CFG - SERS Configuration Register |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK 0xe0000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT 29 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK 0x10000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT 28 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode 1 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK 0x08000000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT 27 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_DEFAULT 0x00000000 |
| |
| /* union - case mapped_buffer_mode [26:08] */ |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_DEFAULT 0x00000000 |
| |
| /* union - case cmd_fifo_mode [26:08] */ |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK 0x07c00000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT 22 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK 0x003e0000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT 17 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_DEFAULT 0x0000001f |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_DEFAULT 0x00000010 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK 0x00000c00 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT 10 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK 0x00000200 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK 0x00000100 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT 8 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_DEFAULT 0x00000001 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK 0x000000fe |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT 1 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_DEFAULT 0x00000000 |
| |
| /* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SERS_CMD_BUF_%i - Host Serial Write Command Buffer |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE 0x00404428 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END 7 |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *SERS_CMD_BUF_%i - Host Serial Write Command Buffer |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT 0 |
| |
| |
| /*************************************************************************** |
| *SERS_STAT_BUF_%i - Host Serial Read Status Buffer |
| ***************************************************************************/ |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE 0x00404448 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START 0 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END 1 |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE 32 |
| |
| /*************************************************************************** |
| *SERS_STAT_BUF_%i - Host Serial Read Status Buffer |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */ |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK 0xffffffff |
| #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT 0 |
| |
| |
| /*************************************************************************** |
| *RO_TEST_BLOCK_SEL - Block select for RO testmode |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK 0xffffffe0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT 5 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_pwenb [04:04] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_MASK 0x00000010 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_SHIFT 4 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DEFAULT 0x00000001 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_ENABLED 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_pwenb_DISABLED 1 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [03:02] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x0000000c |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MIN_LOAD 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MED_LOAD 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_HVT_MAX_LOAD 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SVT_MIN_LOAD 3 |
| |
| /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [01:00] */ |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000003 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DEFAULT 0x00000000 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 1 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 2 |
| #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_UNUSED_3_RO_TEST_ID 3 |
| |
| /*************************************************************************** |
| *TEST_CONFIGURATION - Test configuration |
| ***************************************************************************/ |
| /* SUN_TOP_CTRL :: TEST_CONFIGURATION :: reserved0 [31:04] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_MASK 0xfffffff0 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_reserved0_SHIFT 4 |
| |
| /* SUN_TOP_CTRL :: TEST_CONFIGURATION :: test_configuration [03:00] */ |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_MASK 0x0000000f |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_SHIFT 0 |
| #define BCHP_SUN_TOP_CTRL_TEST_CONFIGURATION_test_configuration_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */ |
| |
| /* End of File */ |
