| /*************************************************************************** |
| * Copyright (c) 1999-2012, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Mon May 7 03:06:14 2012 |
| * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008005 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_AON_PIN_CTRL_H__ |
| #define BCHP_AON_PIN_CTRL_H__ |
| |
| /*************************************************************************** |
| *AON_PIN_CTRL - AON Pinmux Control Registers |
| ***************************************************************************/ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0 0x00408500 /* Pinmux control register 0 */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1 0x00408504 /* Pinmux control register 1 */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2 0x00408508 /* Pinmux control register 2 */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3 0x0040850c /* Pinmux control register 3 */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0 0x00408510 /* Pad pull-up/pull-down control register 0 */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1 0x00408514 /* Pad pull-up/pull-down control register 1 */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2 0x00408518 /* Pad pull-up/pull-down control register 2 */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0 0x0040851c /* Bypass clock unselect register 0 */ |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_0 - Pinmux control register 0 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_05 [31:28] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MASK 0xf0000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SHIFT 28 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_AON_GPIO_05 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_LED_LD1 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PKT5_DATA 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_I2S_DATA0_OUT 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC_CLK_OUT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_MTSIF_ATS_RST 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_SC1_AUX1 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_TP_IN_05 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_05_PM_AON_GPIO_05 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_04 [27:24] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_MASK 0x0f000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SHIFT 24 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_AON_GPIO_04 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_LED_LD0 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PKT5_CLK 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_I2S_CLK0_OUT 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_EXT_IRQ1 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_IR_OUT 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SDS0_TNR_SDA 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_SC1_VPP 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_TP_IN_04 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_04_PM_AON_GPIO_04 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_03 [23:20] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_MASK 0x00f00000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SHIFT 20 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_AON_GPIO_03 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_LED_OUT 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PWR_BUTTON 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_FP_4SEC_RESETB 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_EXT_IRQ0 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_IR_OUT 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDS0_TNR_SCL 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_SDIO0_PRES 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_TP_IN_03 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_03_PM_AON_GPIO_03 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_01 [19:16] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_MASK 0x000f0000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SHIFT 16 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_AON_GPIO_01 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_LINK 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_PWM0 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_ENET_ACTIVITY 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_IR_OUT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_VEC_HSYNC 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_RMX1_VALID 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_SDS0_TNR_SCL 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_01_TP_OUT_01 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_gpio_00 [15:12] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_MASK 0x0000f000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_SHIFT 12 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AON_GPIO_00 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_AUD_SPDIF 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_CLK_OBSRV1 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_gpio_00_TP_OUT_00 3 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_hdmi_htplg [11:08] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_MASK 0x00000f00 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_SHIFT 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_AON_HDMI_HTPLG 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_hdmi_htplg_TP_IN_02 1 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_s3_standbyb [07:04] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_MASK 0x000000f0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_SHIFT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_AON_S3_STANDBYB 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_s3_standbyb_TP_IN_01 1 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_0 :: aon_ir_in0 [03:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_MASK 0x0000000f |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_SHIFT 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_AON_IR_IN0 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_0_aon_ir_in0_TP_IN_00 1 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_1 - Pinmux control register 1 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_13 [31:28] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MASK 0xf0000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SHIFT 28 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_AON_GPIO_13 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_LED_LS1 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PKT2_DATA 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_I2S_DATA0_OUT 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PWM0 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_SDIO0_CLK 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_USB0_PWRFLT_1 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_MTSIF0_DATA0 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_TP_OUT_05 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_13_PM_AON_GPIO_13 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_12 [27:24] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MASK 0x0f000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SHIFT 24 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_AON_GPIO_12 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_LS0 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PKT2_CLK 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_I2S_CLK0_OUT 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_LED_OUT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_SDIO0_PWR0 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_MTSIF0_CLK 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_TP_OUT_04 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_12_PM_AON_GPIO_12 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_11 [23:20] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_MASK 0x00f00000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SHIFT 20 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_GPIO_11 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_LED_LD7 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SC1_CLK 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_CODEC_MCLK 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_AON_CLK_27 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_SPI_M_SCK 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_11_TP_OUT_03 6 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_10 [19:16] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_MASK 0x000f0000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SHIFT 16 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_AON_GPIO_10 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_LED_LD6 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SC1_VCC 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_CODEC_SDO 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_UART_RTS2 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_SPI_M_SS0B 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_10_TP_OUT_02 6 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_09 [15:12] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MASK 0x0000f000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SHIFT 12 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_AON_GPIO_09 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_LED_LD5 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SC1_RST 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_CODEC_SCLK 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_UART_TX2 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_SPI_M_MOSI 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_MTSIF0_DATA5 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_TP_IN_09 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_09_PM_AON_GPIO_09 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_08 [11:08] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MASK 0x00000f00 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SHIFT 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_AON_GPIO_08 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_LED_LD4 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SC1_IO 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_CODEC_FSYNCB 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_UART_CTS2 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SPI_M_SS1B 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_SDIO0_PRES 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_MTSIF0_DATA1 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_TP_IN_08 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_08_PM_AON_GPIO_08 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_07 [07:04] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MASK 0x000000f0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SHIFT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_AON_GPIO_07 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_LED_LD3 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SC1_PRES 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_CODEC_SDI 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_UART_RX2 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_SPI_M_MISO 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_MTSIF0_VALID 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_TP_IN_07 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_07_PM_AON_GPIO_07 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_1 :: aon_gpio_06 [03:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_MASK 0x0000000f |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SHIFT 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_AON_GPIO_06 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_LED_LD2 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PKT5_SYNC 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_I2S_LR0_OUT 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC_EXT_CLK 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_VEC_VSYNC 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_SC1_AUX2 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_TP_IN_06 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_1_aon_gpio_06_PM_AON_GPIO_06 8 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_2 - Pinmux control register 2 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_sgpio_00 [31:28] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_MASK 0xf0000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SHIFT 28 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_AON_SGPIO_00 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_BSC_M3_SCL 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_USB0_PWRFLT_1 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_EXT_IRQ2 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_SDS0_TNR_SCL 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_sgpio_00_TP_IN_16 5 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_20 [27:24] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MASK 0x0f000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SHIFT 24 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_GPIO_20 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_LED_KD3 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PKT4_SYNC 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_CLK_OBSRV0 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_AON_CLK_27 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_SDIO0_WPROT 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_RO_OBSRV 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_MTSIF0_DATA7 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_TP_IN_15 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_20_PM_AON_GPIO_20 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_19 [23:20] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MASK 0x00f00000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SHIFT 20 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_AON_GPIO_19 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_LED_KD2 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PKT4_DATA 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SC1_PRES 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SPI_M_MISO 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_SDIO0_CMD 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_MTSIF0_DATA6 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_TP_IN_14 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_19_PM_AON_GPIO_19 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_18 [19:16] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MASK 0x000f0000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SHIFT 16 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_AON_GPIO_18 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_LED_KD1 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PKT4_CLK 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SC1_IO 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SPI_M_SS1B 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_SDIO0_DAT3 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_MTSIF_ATS_INC 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_TP_IN_13 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_18_PM_AON_GPIO_18 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_17 [15:12] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MASK 0x0000f000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SHIFT 12 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_AON_GPIO_17 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_LED_KD0 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PKT3_SYNC 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SC1_RST 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SPI_M_MOSI 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_SDIO0_DAT2 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PWR_BUTTON 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_MTSIF0_DATA4 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_TP_IN_12 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_17_PM_AON_GPIO_17 9 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_16 [11:08] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MASK 0x00000f00 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SHIFT 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_AON_GPIO_16 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_LED_LS4 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PKT3_DATA 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SC1_CLK 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SPI_M_SCK 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_SDIO0_DAT1 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_MTSIF0_DATA3 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_TP_IN_11 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_16_PM_AON_GPIO_16 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_15 [07:04] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MASK 0x000000f0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SHIFT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_AON_GPIO_15 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_LED_LS3 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PKT3_CLK 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SC1_VCC 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SPI_M_SS0B 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_SDIO0_DAT0 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_MTSIF0_DATA2 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_TP_IN_10 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_15_PM_AON_GPIO_15 8 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_2 :: aon_gpio_14 [03:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MASK 0x0000000f |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SHIFT 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_AON_GPIO_14 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_LED_LS2 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PKT2_SYNC 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_I2S_LR0_OUT 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_SDIO0_LED 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_USB0_PWRFLT_2 5 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_MTSIF0_SYNC 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_TP_OUT_06 7 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_2_aon_gpio_14_PM_AON_GPIO_14 8 |
| |
| /*************************************************************************** |
| *PIN_MUX_CTRL_3 - Pinmux control register 3 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: reserved0 [31:12] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_MASK 0xfffff000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_reserved0_SHIFT 12 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_01 [11:08] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_MASK 0x00000f00 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SHIFT 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_SGPIO_01 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_BSC_M0_SDA 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_01_HDMI_TX_BSC_SDA 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: sgpio_00 [07:04] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_MASK 0x000000f0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SHIFT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_SGPIO_00 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_BSC_M0_SCL 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_sgpio_00_HDMI_TX_BSC_SCL 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_CTRL_3 :: aon_sgpio_01 [03:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_MASK 0x0000000f |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SHIFT 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_AON_SGPIO_01 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_BSC_M3_SDA 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_USB0_PWRFLT_2 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_EXT_IRQ3 3 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_SDS0_TNR_SDA 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_CTRL_3_aon_sgpio_01_TP_IN_17 5 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_07_pad_ctrl [29:28] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_MASK 0x30000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_SHIFT 28 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_07_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_06_pad_ctrl [27:26] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_MASK 0x0c000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_SHIFT 26 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_06_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_05_pad_ctrl [25:24] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_MASK 0x03000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_SHIFT 24 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_05_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_04_pad_ctrl [23:22] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_SHIFT 22 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_04_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_03_pad_ctrl [21:20] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_MASK 0x00300000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_SHIFT 20 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_03_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_01_pad_ctrl [19:18] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_SHIFT 18 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_01_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: aon_gpio_00_pad_ctrl [17:16] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_MASK 0x00030000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_SHIFT 16 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_aon_gpio_00_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [15:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK 0x0000ffff |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT 0 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:26] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK 0x3c000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT 26 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_20_pad_ctrl [25:24] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_MASK 0x03000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_SHIFT 24 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_20_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_19_pad_ctrl [23:22] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_MASK 0x00c00000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_SHIFT 22 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_19_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_18_pad_ctrl [21:20] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_MASK 0x00300000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_SHIFT 20 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_18_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_17_pad_ctrl [19:18] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_MASK 0x000c0000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_SHIFT 18 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_17_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_16_pad_ctrl [17:16] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_MASK 0x00030000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_SHIFT 16 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_16_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_15_pad_ctrl [15:14] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_MASK 0x0000c000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_SHIFT 14 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_15_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_14_pad_ctrl [13:12] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_MASK 0x00003000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_SHIFT 12 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_14_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_13_pad_ctrl [11:10] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_MASK 0x00000c00 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_SHIFT 10 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_13_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_12_pad_ctrl [09:08] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_MASK 0x00000300 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_SHIFT 8 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_12_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_11_pad_ctrl [07:06] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_MASK 0x000000c0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_SHIFT 6 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_11_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_10_pad_ctrl [05:04] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_MASK 0x00000030 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_SHIFT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_10_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_09_pad_ctrl [03:02] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_MASK 0x0000000c |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_SHIFT 2 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_09_pad_ctrl_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_1 :: aon_gpio_08_pad_ctrl [01:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_MASK 0x00000003 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_SHIFT 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_DEFAULT 0x00000001 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_1_aon_gpio_08_pad_ctrl_PULL_UP 2 |
| |
| /*************************************************************************** |
| *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [31:06] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK 0xffffffc0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT 6 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [05:04] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0x00000030 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 4 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_DEFAULT 0x00000000 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1 |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2 |
| |
| /* AON_PIN_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved1 [03:00] */ |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_MASK 0x0000000f |
| #define BCHP_AON_PIN_CTRL_PIN_MUX_PAD_CTRL_2_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0 |
| ***************************************************************************/ |
| /* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xfffffff0 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 4 |
| |
| /* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_01 [03:03] */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_MASK 0x00000008 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_SHIFT 3 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_DEFAULT 0x00000000 |
| |
| /* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_00 [02:02] */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_MASK 0x00000004 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_SHIFT 2 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_00_DEFAULT 0x00000000 |
| |
| /* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_nmib [01:01] */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_MASK 0x00000002 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_SHIFT 1 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_nmib_DEFAULT 0x00000000 |
| |
| /* AON_PIN_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_aon_reset_outb [00:00] */ |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_MASK 0x00000001 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_SHIFT 0 |
| #define BCHP_AON_PIN_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_aon_reset_outb_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_AON_PIN_CTRL_H__ */ |
| |
| /* End of File */ |
