/***************************************************************************
 *     Copyright (c) 1999-2011, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Thu Aug  4 13:41:10 2011
 *                 MD5 Checksum         83f408cc25eb2d099cc58e22e4e239e9
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7552/rdb/b0/bchp_ddr40_phy_control_regs_0.h $
 * 
 * Hydra_Software_Devel/1   8/5/11 9:35p albertl
 * SW7552-89: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__
#define BCHP_DDR40_PHY_CONTROL_REGS_0_H__

/***************************************************************************
 *DDR40_PHY_CONTROL_REGS_0 - DDR40 DDR40 physical interface control registers 0
 ***************************************************************************/
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION   0x003b6000 /* Address & Control revision register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL 0x003b6004 /* PHY clock power management control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS 0x003b6010 /* PHY PLL status register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG 0x003b6014 /* PHY PLL configuration register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL 0x003b6018 /* PHY PLL control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS 0x003b601c /* PHY PLL dividers control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL 0x003b6020 /* Aux Control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL 0x003b6030 /* Address & Control coarse VDL static override control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL 0x003b6034 /* Address & Control fine VDL static override control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL 0x003b6038 /* Idle mode SSTL pad control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL 0x003b603c /* PVT Compensation control and status register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL 0x003b6040 /* SSTL pad drive characteristics control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS 0x003b6044 /* PHY Auto Init rd_data_dly result register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE 0x003b6048 /* PHY VDL calibration control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS 0x003b604c /* PHY VDL calibration status register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS 0x003b6050 /* PHY DQ VDL calibration status register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS 0x003b6054 /* PHY Write Channel VDL calibration status register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS 0x003b6058 /* PHY Read Enable VDL calibration status register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL 0x003b605c /* Virtual VTT Control and Status register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS 0x003b6060 /* Virtual VTT Control and Status register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS 0x003b6064 /* Virtual VTT Connections register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE 0x003b6068 /* Virtual VTT Override register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL 0x003b606c /* VREF DAC Control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL 0x003b6070 /* PhyBist Control Register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED 0x003b6074 /* PhyBist Seed Register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS 0x003b6078 /* PhyBist General Status Register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS 0x003b607c /* PhyBist Per-Bit Control Pad Status Register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS 0x003b6080 /* PhyBist Per-Bit DQ Pad Status Register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS 0x003b6084 /* PhyBist Per-Bit DM and CK Pad Status Register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG 0x003b6090 /* DRAM Command Register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0  0x003b6094 /* Mode Register 0 */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1  0x003b6098 /* Mode Register 1 */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2  0x003b609c /* Mode Register 2 */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3  0x003b60a0 /* Mode Register 3 */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL 0x003b60a4 /* Standby Control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL 0x003b60b0 /* Strap Control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2 0x003b60b4 /* Strap Control register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS 0x003b60b8 /* Strap Status register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2 0x003b60bc /* Strap Status register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE 0x003b60c0 /* Freeze-on-error enable register */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK 0x003b60c4 /* Datapth Loopback control register */

/***************************************************************************
 *REVISION - Address & Control revision register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: reserved0 [31:23] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_MASK      0xff800000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_reserved0_SHIFT     23

/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: TECHNOLOGY [22:20] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_MASK     0x00700000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_TECHNOLOGY_SHIFT    20

/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: WB [19:19] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_WB_MASK             0x00080000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_WB_SHIFT            19

/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: BITS [18:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_BITS_MASK           0x00070000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_BITS_SHIFT          16

/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MAJOR [15:08] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_MASK          0x0000ff00
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_SHIFT         8
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MAJOR_DEFAULT       64

/* DDR40_PHY_CONTROL_REGS_0 :: REVISION :: MINOR [07:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_MASK          0x000000ff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_SHIFT         0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_REVISION_MINOR_DEFAULT       6

/***************************************************************************
 *CLK_PM_CTRL - PHY clock power management control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_MASK   0xfffffffe
#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_reserved0_SHIFT  1

/* DDR40_PHY_CONTROL_REGS_0 :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_CLK_PM_CTRL_DIS_DDR_CLK_DEFAULT 0

/***************************************************************************
 *PLL_STATUS - PHY PLL status register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: reserved0 [31:27] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_MASK    0xf8000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_reserved0_SHIFT   27

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK_LOST [26:26] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_MASK    0x04000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_LOST_SHIFT   26

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: DDR_MHZ [25:14] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_MASK      0x03ffc000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_DDR_MHZ_SHIFT     14

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: CLOCKING_4X [13:13] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_MASK  0x00002000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_CLOCKING_4X_SHIFT 13

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: STATUS [12:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_MASK       0x00001ffe
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_STATUS_SHIFT      1

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_STATUS :: LOCK [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_MASK         0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS_LOCK_SHIFT        0

/***************************************************************************
 *PLL_CONFIG - PHY PLL configuration register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved0 [31:07] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_MASK    0xffffff80
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved0_SHIFT   7

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LP40_PLL_POST_RESET [06:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_MASK 0x00000040
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_SHIFT 6
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LP40_PLL_POST_RESET_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET_POST_DIV [05:05] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_MASK 0x00000020
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_SHIFT 5
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_POST_DIV_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: LDO_CTRL [04:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_MASK     0x00000018
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_SHIFT    3
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_LDO_CTRL_DEFAULT  2

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: reserved1 [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_MASK    0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_reserved1_SHIFT   2

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: RESET [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_MASK        0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_SHIFT       1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_RESET_DEFAULT     1

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONFIG :: PWRDN [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_MASK        0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_SHIFT       0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONFIG_PWRDN_DEFAULT     0

/***************************************************************************
 *PLL_CONTROL - PHY PLL control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: reserved0 [31:31] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_MASK   0x80000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_reserved0_SHIFT  31

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_kp [30:27] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_MASK        0x78000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_SHIFT       27
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_kp_DEFAULT     10

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ki [26:24] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_MASK        0x07000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_SHIFT       24
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ki_DEFAULT     3

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: i_ka [23:21] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_MASK        0x00e00000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_SHIFT       21
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_i_ka_DEFAULT     3

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_CONTROL :: PLL_CONTROL [20:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_MASK 0x001fffff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_CONTROL_PLL_CONTROL_DEFAULT 0

/***************************************************************************
 *PLL_DIVIDERS - PHY PLL dividers control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: reserved0 [31:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_MASK  0xffff0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_reserved0_SHIFT 16

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_HI [15:15] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_MASK 0x00008000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_SHIFT 15
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_HI_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV_40LP_LO [14:14] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_MASK 0x00004000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_SHIFT 14
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_40LP_LO_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: POST_DIV [13:11] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_MASK   0x00003800
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_SHIFT  11
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_POST_DIV_DEFAULT 2

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: PDIV [10:08] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_MASK       0x00000700
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_SHIFT      8
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_PDIV_DEFAULT    4

/* DDR40_PHY_CONTROL_REGS_0 :: PLL_DIVIDERS :: NDIV [07:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_MASK       0x000000ff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_SHIFT      0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_DIVIDERS_NDIV_DEFAULT    32

/***************************************************************************
 *AUX_CONTROL - Aux Control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: reserved0 [31:10] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_MASK   0xfffffc00
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_reserved0_SHIFT  10

/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_cs [09:07] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_MASK       0x00000380
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_SHIFT      7
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_cs_DEFAULT    0

/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_ad [06:04] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_MASK       0x00000070
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_SHIFT      4
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_ad_DEFAULT    0

/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: is_odt [03:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_MASK      0x0000000e
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_SHIFT     1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_is_odt_DEFAULT   0

/* DDR40_PHY_CONTROL_REGS_0 :: AUX_CONTROL :: override [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_MASK    0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_SHIFT   0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_AUX_CONTROL_override_DEFAULT 0

/***************************************************************************
 *VDL_OVRIDE_BYTE_CTL - Address & Control coarse VDL static override control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: busy [31:31] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_MASK 0x80000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_SHIFT 31
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_busy_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved0 [30:17] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_MASK 0x7ffe0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved0_SHIFT 17

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_en [16:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_MASK 0x00010000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_SHIFT 16
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_en_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved1 [15:09] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_MASK 0x0000fe00
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved1_SHIFT 9

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: byte_sel [08:08] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_MASK 0x00000100
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_SHIFT 8
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_byte_sel_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: reserved2 [07:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_MASK 0x000000c0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_reserved2_SHIFT 6

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BYTE_CTL :: ovr_step [05:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_MASK 0x0000003f
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BYTE_CTL_ovr_step_DEFAULT 0

/***************************************************************************
 *VDL_OVRIDE_BIT_CTL - Address & Control fine VDL static override control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: busy [31:31] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_MASK 0x80000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_SHIFT 31
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_busy_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved0 [30:17] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_MASK 0x7ffe0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved0_SHIFT 17

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_en [16:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_MASK 0x00010000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_SHIFT 16
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_en_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved1 [15:09] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_MASK 0x0000fe00
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved1_SHIFT 9

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: byte_sel [08:08] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_MASK 0x00000100
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_SHIFT 8
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_byte_sel_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: reserved2 [07:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_MASK 0x000000c0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_reserved2_SHIFT 6

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_OVRIDE_BIT_CTL :: ovr_step [05:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_MASK 0x0000003f
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_OVRIDE_BIT_CTL_ovr_step_DEFAULT 0

/***************************************************************************
 *IDLE_PAD_CONTROL - Idle mode SSTL pad control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: idle [31:31] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_MASK   0x80000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_SHIFT  31
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_idle_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved0 [30:09] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved0_SHIFT 9

/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: rxenb [08:08] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_MASK  0x00000100
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_SHIFT 8
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_rxenb_DEFAULT 1

/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved1 [07:07] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved1_SHIFT 7

/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_iddq_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_reb_DEFAULT 1

/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_ctl_oeb_DEFAULT 1

/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: reserved2 [03:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_reserved2_SHIFT 3

/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_iddq_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_reb [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_reb_DEFAULT 1

/* DDR40_PHY_CONTROL_REGS_0 :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_IDLE_PAD_CONTROL_cke_oeb_DEFAULT 0

/***************************************************************************
 *ZQ_PVT_COMP_CTL - PVT Compensation control and status register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: reserved0 [31:26] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_MASK 0xfc000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_reserved0_SHIFT 26

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: update_mode [25:25] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_MASK 0x02000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_SHIFT 25
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_update_mode_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_done [24:24] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_MASK 0x01000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_SHIFT 24
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_done_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_done [23:23] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_MASK 0x00800000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_SHIFT 23
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_done_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_done [22:22] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_MASK 0x00400000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_SHIFT 22
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_done_DEFAULT 1

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: auto_sample_en [21:21] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x00200000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 21
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_auto_sample_en_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: sample_en [20:20] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_MASK 0x00100000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_SHIFT 20
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_sample_en_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_ovr_en [19:19] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x00080000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 19
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_ovr_en_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_ovr_en [18:18] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x00040000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 18
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_ovr_en_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: pd_comp [17:15] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00038000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 15
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_pd_comp_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: nd_comp [14:12] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x00007000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 12
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_nd_comp_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [11:09] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x00000e00
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 9
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_pd_override_val_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [08:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x000001c0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 6
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_addr_nd_override_val_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [05:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x00000038
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 3
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_pd_override_val_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [02:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x00000007
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_ZQ_PVT_COMP_CTL_dq_nd_override_val_DEFAULT 0

/***************************************************************************
 *DRIVE_PAD_CTL - SSTL pad drive characteristics control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: reserved0 [31:14] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffc000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_reserved0_SHIFT 14

/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: auto_oeb [13:13] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_MASK  0x00002000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_SHIFT 13
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_auto_oeb_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a15 [12:12] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_MASK  0x00001000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_SHIFT 12
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a15_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a14 [11:11] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_MASK  0x00000800
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_SHIFT 11
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a14_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_a13 [10:10] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_MASK  0x00000400
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_SHIFT 10
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_a13_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: iddq_aux [09:07] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_MASK  0x00000380
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_SHIFT 7
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_iddq_aux_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: half_strength [06:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_MASK 0x00000040
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_SHIFT 6
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_half_strength_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: gddr_symmetry [05:05] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_MASK 0x00000020
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_SHIFT 5
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_gddr_symmetry_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: vddo_volts [04:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_MASK 0x00000018
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_SHIFT 3
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_vddo_volts_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt60b [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_MASK     0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_SHIFT    2
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt60b_DEFAULT  0

/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: rt120b_g [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_MASK  0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_rt120b_g_DEFAULT 1

/* DDR40_PHY_CONTROL_REGS_0 :: DRIVE_PAD_CTL :: g_ddr [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_MASK     0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_SHIFT    0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DRIVE_PAD_CTL_g_ddr_DEFAULT  0

/***************************************************************************
 *VDL_RD_DATA_DLY_STATUS - PHY Auto Init rd_data_dly result register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: reserved0 [31:12] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_MASK 0xfffff000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_reserved0_SHIFT 12

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: auto_init_state [11:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_MASK 0x00000fc0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_SHIFT 6
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_auto_init_state_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_max [05:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_MASK 0x00000038
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_SHIFT 3
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_max_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_DATA_DLY_STATUS :: rd_data_dly_min [02:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_MASK 0x00000007
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_DATA_DLY_STATUS_rd_data_dly_min_DEFAULT 7

/***************************************************************************
 *VDL_CALIBRATE - PHY VDL calibration control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: reserved0 [31:30] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_MASK 0xc0000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_reserved0_SHIFT 30

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: single_cycle [29:29] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_MASK 0x20000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_SHIFT 29
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_single_cycle_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: use_straps [28:28] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_MASK 0x10000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_SHIFT 28
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_use_straps_DEFAULT 1

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: auto_init [27:27] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_MASK 0x08000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_SHIFT 27
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_auto_init_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: skip_rst [26:26] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_MASK  0x04000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_SHIFT 26
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_skip_rst_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: exit_in_sr [25:25] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_MASK 0x02000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_SHIFT 25
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_exit_in_sr_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_dly_cal [24:24] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_MASK 0x01000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_SHIFT 24
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_dly_cal_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_refresh [23:23] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_MASK 0x00800000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_SHIFT 23
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_refresh_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_wr_dq [22:22] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_MASK 0x00400000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_SHIFT 22
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_wr_dq_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: dq0_only [21:21] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_MASK  0x00200000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_SHIFT 21
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_dq0_only_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: set_mr_mpr [20:20] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_MASK 0x00100000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_SHIFT 20
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_set_mr_mpr_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: bit_cal [19:19] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_MASK   0x00080000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_SHIFT  19
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_bit_cal_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: rd_en_cal [18:18] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_MASK 0x00040000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_SHIFT 18
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_rd_en_cal_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_bit_offset [17:12] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_MASK 0x0003f000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_SHIFT 12
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_bit_offset_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_clocks [11:11] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_MASK 0x00000800
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_SHIFT 11
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_clocks_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_dqs_pair [10:10] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_MASK 0x00000400
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_SHIFT 10
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_dqs_pair_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_steps [09:09] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_MASK 0x00000200
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_SHIFT 9
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_steps_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_auto [08:08] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_MASK 0x00000100
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_SHIFT 8
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_auto_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_ftm [07:07] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_MASK 0x00000080
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_SHIFT 7
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_ftm_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_phybist [06:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_MASK 0x00000040
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_SHIFT 6
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_phybist_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_byte [05:05] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_MASK 0x00000020
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_SHIFT 5
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_byte_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_clocks [04:04] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_SHIFT 4
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_clocks_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_test [03:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_MASK 0x00000008
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_SHIFT 3
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_test_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_always [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_MASK 0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_SHIFT 2
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_always_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_once [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_MASK 0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_once_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIBRATE :: calib_fast [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIBRATE_calib_fast_DEFAULT 0

/***************************************************************************
 *VDL_CALIB_STATUS - PHY VDL calibration status register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: reserved0 [31:30] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_MASK 0xc0000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_reserved0_SHIFT 30

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_fail [29:29] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_MASK 0x20000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_SHIFT 29
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_fail_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: auto_init_done [28:28] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_MASK 0x10000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_SHIFT 28
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_auto_init_done_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_rd_data_dly_error [27:27] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_MASK 0x08000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_SHIFT 27
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_rd_data_dly_error_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_read_en_error [26:23] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_MASK 0x07800000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_SHIFT 23
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_read_en_error_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_error [22:19] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_MASK 0x00780000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_SHIFT 19
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_error_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_byte_sel [18:18] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_MASK 0x00040000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_SHIFT 18
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_byte_sel_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_bit_offset [17:12] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_MASK 0x0003f000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_SHIFT 12
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_bit_offset_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_total [11:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_MASK 0x00000ffc
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_SHIFT 2
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_total_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_lock [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_MASK 0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_lock_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_CALIB_STATUS :: calib_idle [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_CALIB_STATUS_calib_idle_DEFAULT 1

/***************************************************************************
 *VDL_DQ_CALIB_STATUS - PHY DQ VDL calibration status register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved0 [31:26] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_MASK 0xfc000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved0_SHIFT 26

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_total [25:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_MASK 0x03ff0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_SHIFT 16
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_total_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: reserved1 [15:14] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_MASK 0x0000c000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_reserved1_SHIFT 14

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_total [13:04] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_MASK 0x00003ff0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_SHIFT 4
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_total_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_clocks [03:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_MASK 0x00000008
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_SHIFT 3
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_clocks_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_mode [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_MASK 0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_SHIFT 2
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_mode_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dqs_calib_lock [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_MASK 0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dqs_calib_lock_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_DQ_CALIB_STATUS :: dq_calib_lock [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_DQ_CALIB_STATUS_dq_calib_lock_DEFAULT 0

/***************************************************************************
 *VDL_WR_CHAN_CALIB_STATUS - PHY Write Channel VDL calibration status register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved0 [31:22] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_MASK 0xffc00000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved0_SHIFT 22

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_bit_offset [21:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_MASK 0x003f0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_SHIFT 16
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_bit_offset_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved1 [15:14] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_MASK 0x0000c000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved1_SHIFT 14

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_total [13:04] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_MASK 0x00003ff0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_SHIFT 4
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_total_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: reserved2 [03:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_MASK 0x00000008
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_reserved2_SHIFT 3

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_clocks [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_MASK 0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_SHIFT 2
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_clocks_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_byte_sel [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_MASK 0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_byte_sel_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_WR_CHAN_CALIB_STATUS :: wr_chan_calib_lock [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_WR_CHAN_CALIB_STATUS_wr_chan_calib_lock_DEFAULT 0

/***************************************************************************
 *VDL_RD_EN_CALIB_STATUS - PHY Read Enable VDL calibration status register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved0 [31:22] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_MASK 0xffc00000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved0_SHIFT 22

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_bit_offset [21:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_MASK 0x003f0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_SHIFT 16
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_bit_offset_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved1 [15:14] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_MASK 0x0000c000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved1_SHIFT 14

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_total [13:04] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_MASK 0x00003ff0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_SHIFT 4
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_total_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: reserved2 [03:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_MASK 0x00000008
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_reserved2_SHIFT 3

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_clocks [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_MASK 0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_SHIFT 2
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_clocks_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_byte_sel [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_MASK 0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_byte_sel_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VDL_RD_EN_CALIB_STATUS :: rd_en_calib_lock [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VDL_RD_EN_CALIB_STATUS_rd_en_calib_lock_DEFAULT 0

/***************************************************************************
 *VIRTUAL_VTT_CONTROL - Virtual VTT Control and Status register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: reserved0 [31:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_MASK 0xffffffc0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_reserved0_SHIFT 6

/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: low_vtt [05:05] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_MASK 0x00000020
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_SHIFT 5
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_low_vtt_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: high_vtt [04:04] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_MASK 0x00000010
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_SHIFT 4
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_high_vtt_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: error_reset [03:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_MASK 0x00000008
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_SHIFT 3
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_error_reset_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_ctl_idle [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_MASK 0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_SHIFT 2
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_ctl_idle_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cs_idle [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_MASK 0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cs_idle_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONTROL :: enable_cke_idle [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONTROL_enable_cke_idle_DEFAULT 0

/***************************************************************************
 *VIRTUAL_VTT_STATUS - Virtual VTT Control and Status register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: reserved0 [31:19] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_MASK 0xfff80000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_reserved0_SHIFT 19

/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error [18:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_MASK 0x0007fff8
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_SHIFT 3
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_low [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_MASK 0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_SHIFT 2
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_low_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: error_high [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_MASK 0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_error_high_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_STATUS :: ready [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_STATUS_ready_DEFAULT 0

/***************************************************************************
 *VIRTUAL_VTT_CONNECTIONS - Virtual VTT Connections register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: reserved0 [31:27] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_MASK 0xf8000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_reserved0_SHIFT 27

/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_CONNECTIONS :: mask [26:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_MASK 0x07ffffff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_CONNECTIONS_mask_DEFAULT 16777215

/***************************************************************************
 *VIRTUAL_VTT_OVERRIDE - Virtual VTT Override register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: reserved0 [31:27] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_MASK 0xf8000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_reserved0_SHIFT 27

/* DDR40_PHY_CONTROL_REGS_0 :: VIRTUAL_VTT_OVERRIDE :: mask [26:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_MASK 0x07ffffff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VIRTUAL_VTT_OVERRIDE_mask_DEFAULT 262143

/***************************************************************************
 *VREF_DAC_CONTROL - VREF DAC Control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: reserved0 [31:21] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_MASK 0xffe00000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_reserved0_SHIFT 21

/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK1_GT_INT [20:20] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_MASK 0x00100000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_SHIFT 20
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK1_GT_INT_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_CK0_GT_INT [19:19] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_MASK 0x00080000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_SHIFT 19
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_CK0_GT_INT_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_GT_INT [18:18] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_MASK 0x00040000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_SHIFT 18
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_GT_INT_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: EXT_GT_INT [17:17] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_MASK 0x00020000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_SHIFT 17
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_EXT_GT_INT_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: LDO_TESTOUT_MUX_CTL [16:15] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_MASK 0x00018000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_SHIFT 15
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_LDO_TESTOUT_MUX_CTL_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: TEST [14:14] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_MASK   0x00004000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_SHIFT  14
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_TEST_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN1 [13:13] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_MASK   0x00002000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_SHIFT  13
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN1_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: PDN0 [12:12] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_MASK   0x00001000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_SHIFT  12
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_PDN0_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC1 [11:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_MASK   0x00000fc0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_SHIFT  6
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC1_DEFAULT 32

/* DDR40_PHY_CONTROL_REGS_0 :: VREF_DAC_CONTROL :: DAC0 [05:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_MASK   0x0000003f
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_SHIFT  0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_VREF_DAC_CONTROL_DAC0_DEFAULT 32

/***************************************************************************
 *PHYBIST_CNTRL - PhyBist Control Register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:14] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xffffc000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 14

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_error_sel_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [07:05] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x000000e0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 5

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: bench_mode [04:04] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_MASK 0x00000010
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_SHIFT 4
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_bench_mode_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [03:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000008
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 3
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_dat_error_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 2
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_force_ctl_error_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: int_loopback [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_MASK 0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_int_loopback_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_MASK    0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_SHIFT   0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CNTRL_enable_DEFAULT 0

/***************************************************************************
 *PHYBIST_SEED - PhyBist Seed Register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_MASK       0xffffffff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_SHIFT      0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_SEED_seed_DEFAULT    621693686

/***************************************************************************
 *PHYBIST_STATUS - PhyBist General Status Register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: reserved0 [31:04] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_reserved0_SHIFT 4

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_pass [03:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_MASK 0x00000008
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_pass_SHIFT 3

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_pass [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_MASK 0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_pass_SHIFT 2

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: dat_done [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_MASK 0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_dat_done_SHIFT 1

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_STATUS :: ctl_done [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_STATUS_ctl_done_SHIFT 0

/***************************************************************************
 *PHYBIST_CTL_STATUS - PhyBist Per-Bit Control Pad Status Register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_CTL_STATUS :: ctl_errors [26:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_MASK 0x07ffffff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_CTL_STATUS_ctl_errors_SHIFT 0

/***************************************************************************
 *PHYBIST_DQ_STATUS - PhyBist Per-Bit DQ Pad Status Register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_DQ_STATUS :: dat_errors [31:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_MASK 0xffffffff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_DQ_STATUS_dat_errors_SHIFT 0

/***************************************************************************
 *PHYBIST_MISC_STATUS - PhyBist Per-Bit DM and CK Pad Status Register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [31:08] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0xffffff00
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: ck_errors [07:04] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_MASK 0x000000f0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_ck_errors_SHIFT 4

/* DDR40_PHY_CONTROL_REGS_0 :: PHYBIST_MISC_STATUS :: dm_errors [03:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_MASK 0x0000000f
#define BCHP_DDR40_PHY_CONTROL_REGS_0_PHYBIST_MISC_STATUS_dm_errors_SHIFT 0

/***************************************************************************
 *COMMAND_REG - DRAM Command Register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved0 [31:29] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_MASK   0xe0000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved0_SHIFT  29

/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: mpr_mode [28:28] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_MASK    0x10000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_SHIFT   28
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_mpr_mode_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: reserved1 [27:25] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved1_MASK   0x0e000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_reserved1_SHIFT  25

/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: aux [24:22] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_MASK         0x01c00000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_SHIFT        22
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_aux_DEFAULT      0

/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: we [21:21] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_MASK          0x00200000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_SHIFT         21
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_we_DEFAULT       0

/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: cas [20:20] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_MASK         0x00100000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_SHIFT        20
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_cas_DEFAULT      0

/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ras [19:19] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_MASK         0x00080000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_SHIFT        19
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ras_DEFAULT      0

/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ba [18:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_MASK          0x00070000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_SHIFT         16
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ba_DEFAULT       0

/* DDR40_PHY_CONTROL_REGS_0 :: COMMAND_REG :: ad [15:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_MASK          0x0000ffff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_SHIFT         0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_COMMAND_REG_ad_DEFAULT       0

/***************************************************************************
 *MODE_REG0 - Mode Register 0
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: reserved0 [31:17] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_MASK     0xfffe0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_reserved0_SHIFT    17

/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: valid [16:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_MASK         0x00010000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_SHIFT        16
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_valid_DEFAULT      0

/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG0 :: ad [15:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_MASK            0x0000ffff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_SHIFT           0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG0_ad_DEFAULT         0

/***************************************************************************
 *MODE_REG1 - Mode Register 1
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: reserved0 [31:17] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_MASK     0xfffe0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_reserved0_SHIFT    17

/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: valid [16:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_MASK         0x00010000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_SHIFT        16
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_valid_DEFAULT      0

/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG1 :: ad [15:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_MASK            0x0000ffff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_SHIFT           0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG1_ad_DEFAULT         0

/***************************************************************************
 *MODE_REG2 - Mode Register 2
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: reserved0 [31:17] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_MASK     0xfffe0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_reserved0_SHIFT    17

/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: valid [16:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_MASK         0x00010000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_SHIFT        16
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_valid_DEFAULT      0

/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG2 :: ad [15:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_MASK            0x0000ffff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_SHIFT           0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG2_ad_DEFAULT         0

/***************************************************************************
 *MODE_REG3 - Mode Register 3
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: reserved0 [31:17] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_MASK     0xfffe0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_reserved0_SHIFT    17

/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: valid [16:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_MASK         0x00010000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_SHIFT        16
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_valid_DEFAULT      0

/* DDR40_PHY_CONTROL_REGS_0 :: MODE_REG3 :: ad [15:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_MASK            0x0000ffff
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_SHIFT           0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_MODE_REG3_ad_DEFAULT         0

/***************************************************************************
 *STANDBY_CONTROL - Standby Control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: reserved0 [31:19] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_MASK 0xfff80000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_reserved0_SHIFT 19

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_ready [18:18] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_MASK 0x00040000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_SHIFT 18
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_ready_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_exit_pin_en [17:17] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_MASK 0x00020000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_SHIFT 17
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_exit_pin_en_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby_active [16:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_MASK 0x00010000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_SHIFT 16
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_active_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: armed [15:15] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_MASK   0x00008000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_SHIFT  15
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_armed_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: warmstart [14:14] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_MASK 0x00004000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_SHIFT 14
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_warmstart_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_ldo_volts [13:12] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_MASK 0x00003000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_SHIFT 12
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_ldo_volts_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_skip_mrs [11:11] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_MASK 0x00000800
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_SHIFT 11
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_skip_mrs_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_rst_n [10:10] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_MASK 0x00000400
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_SHIFT 10
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_rst_n_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: pwrdown_cke [09:09] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_MASK 0x00000200
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_SHIFT 9
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_pwrdown_cke_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: ldo_volts [08:07] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_MASK 0x00000180
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_SHIFT 7
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_ldo_volts_DEFAULT 2

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: skip_mrs [06:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_MASK 0x00000040
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_SHIFT 6
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_skip_mrs_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: rst_n [05:05] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_MASK   0x00000020
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_SHIFT  5
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_rst_n_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: cke [04:04] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_MASK     0x00000010
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_SHIFT    4
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_cke_DEFAULT  0

/* DDR40_PHY_CONTROL_REGS_0 :: STANDBY_CONTROL :: standby [03:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_MASK 0x0000000f
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STANDBY_CONTROL_standby_DEFAULT 0

/***************************************************************************
 *STRAP_CONTROL - Strap Control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: reserved0 [31:28] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_MASK 0xf0000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_reserved0_SHIFT 28

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: mhz [27:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_MASK       0x0fff0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_SHIFT      16
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_mhz_DEFAULT    0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: ad_width [15:14] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_MASK  0x0000c000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_SHIFT 14
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_ad_width_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: dual_rank [13:13] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_MASK 0x00002000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_SHIFT 13
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_dual_rank_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus16 [12:12] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_MASK     0x00001000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_SHIFT    12
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus16_DEFAULT  0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: bus8 [11:11] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_MASK      0x00000800
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_SHIFT     11
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_bus8_DEFAULT   0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_width [10:10] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_MASK 0x00000400
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_SHIFT 10
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_width_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: vddq [09:08] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_MASK      0x00000300
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_SHIFT     8
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_vddq_DEFAULT   0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: chip_size [07:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_MASK 0x000000c0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_SHIFT 6
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_chip_size_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: jedec_type [05:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_MASK 0x0000003e
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_jedec_type_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL :: straps_valid [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL_straps_valid_DEFAULT 0

/***************************************************************************
 *STRAP_CONTROL2 - Strap Control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: reserved0 [31:21] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_MASK 0xffe00000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_reserved0_SHIFT 21

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: ddr3 [20:20] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_MASK     0x00100000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_SHIFT    20
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_ddr3_DEFAULT  0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: al [19:17] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_MASK       0x000e0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_SHIFT      17
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_al_DEFAULT    0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: wr [16:12] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_MASK       0x0001f000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_SHIFT      12
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_wr_DEFAULT    0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cwl [11:07] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_MASK      0x00000f80
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_SHIFT     7
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cwl_DEFAULT   0

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_CONTROL2 :: cl [06:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_MASK       0x0000007f
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_SHIFT      0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_CONTROL2_cl_DEFAULT    0

/***************************************************************************
 *STRAP_STATUS - Strap Status register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: reserved0 [31:30] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_MASK  0xc0000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_reserved0_SHIFT 30

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_reg [29:29] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_MASK   0x20000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_reg_SHIFT  29

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: from_memc [28:28] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_MASK  0x10000000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_from_memc_SHIFT 28

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: mhz [27:16] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_MASK        0x0fff0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_mhz_SHIFT       16

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: ad_width [15:14] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_MASK   0x0000c000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_ad_width_SHIFT  14

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: dual_rank [13:13] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_MASK  0x00002000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_dual_rank_SHIFT 13

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus16 [12:12] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_MASK      0x00001000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus16_SHIFT     12

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: bus8 [11:11] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_MASK       0x00000800
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_bus8_SHIFT      11

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_width [10:10] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_MASK 0x00000400
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_width_SHIFT 10

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: vddq [09:08] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_MASK       0x00000300
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_vddq_SHIFT      8

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: chip_size [07:06] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_MASK  0x000000c0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_chip_size_SHIFT 6

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: jedec_type [05:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_MASK 0x0000003e
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_jedec_type_SHIFT 1

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS :: straps_valid [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS_straps_valid_SHIFT 0

/***************************************************************************
 *STRAP_STATUS2 - Strap Status register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: reserved0 [31:21] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_MASK 0xffe00000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_reserved0_SHIFT 21

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: ddr3 [20:20] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_MASK      0x00100000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_ddr3_SHIFT     20

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: al [19:17] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_MASK        0x000e0000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_al_SHIFT       17

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: wr [16:12] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_MASK        0x0001f000
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_wr_SHIFT       12

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cwl [11:07] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_MASK       0x00000f80
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cwl_SHIFT      7

/* DDR40_PHY_CONTROL_REGS_0 :: STRAP_STATUS2 :: cl [06:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_MASK        0x0000007f
#define BCHP_DDR40_PHY_CONTROL_REGS_0_STRAP_STATUS2_cl_SHIFT       0

/***************************************************************************
 *DEBUG_FREEZE_ENABLE - Freeze-on-error enable register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: reserved0 [31:04] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_MASK 0xfffffff0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_reserved0_SHIFT 4

/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl1 [03:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_MASK 0x00000008
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_SHIFT 3
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl1_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl1_bl0 [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_MASK 0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_SHIFT 2
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl1_bl0_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl1 [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_MASK 0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl1_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DEBUG_FREEZE_ENABLE :: wl0_bl0 [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DEBUG_FREEZE_ENABLE_wl0_bl0_DEFAULT 0

/***************************************************************************
 *DATAPATH_LOOPBACK - Datapth Loopback control register
 ***************************************************************************/
/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: reserved0 [31:03] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_MASK 0xfffffff8
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_reserved0_SHIFT 3

/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: xor_dm_rd_en [02:02] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_MASK 0x00000004
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_SHIFT 2
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_xor_dm_rd_en_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: use_addr_ctl [01:01] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_MASK 0x00000002
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_SHIFT 1
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_use_addr_ctl_DEFAULT 0

/* DDR40_PHY_CONTROL_REGS_0 :: DATAPATH_LOOPBACK :: enable [00:00] */
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_MASK 0x00000001
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_SHIFT 0
#define BCHP_DDR40_PHY_CONTROL_REGS_0_DATAPATH_LOOPBACK_enable_DEFAULT 0

#endif /* #ifndef BCHP_DDR40_PHY_CONTROL_REGS_0_H__ */

/* End of File */