/***************************************************************************
 *     Copyright (c) 1999-2013, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Tue Apr 16 03:27:38 2013
 *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_CLKGEN_H__
#define BCHP_CLKGEN_H__

/***************************************************************************
 *CLKGEN - clkgen registers
 ***************************************************************************/
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00420000 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00420004 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00420008 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0042000c /* Lock Status */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00420010 /* Powerdowns */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00420014 /* Resets */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0042001c /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00420020 /* Test Status */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00420024 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 0x00420028 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 0x0042002c /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 0x00420030 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 0x00420034 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL     0x00420038 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV         0x0042003c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN        0x00420040 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS 0x00420044 /* Lock Status */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC        0x00420048 /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2       0x0042004c /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN       0x00420050 /* Powerdowns */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET       0x00420054 /* Resets */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00420058 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x0042005c /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS      0x00420060 /* Test Status */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x00420064 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x00420068 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x0042006c /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x00420070 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x00420074 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x00420078 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x0042007c /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x00420080 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x00420084 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x00420088 /* Lock Status */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x0042008c /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x00420090 /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x00420094 /* Powerdowns */
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET           0x00420098 /* Resets */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x0042009c /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x004200a0 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x004200a4 /* Test Status */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x004200a8 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x004200ac /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x004200b0 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x004200b4 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x004200b8 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x004200bc /* Fractional */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x004200c0 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x004200c4 /* Lock Status */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x004200c8 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x004200cc /* Powerdowns */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x004200d0 /* Resets */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x004200d4 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x004200d8 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x004200dc /* Status */
#define BCHP_CLKGEN_ANA_SDAC40G_M7FC_CLOCK_DISABLE 0x004200e0 /* Disable ANA_SDAC40G_M7FC's clocks */
#define BCHP_CLKGEN_ANA_SDAC40G_M7FC_CLOCK_DISABLE_STATUS 0x004200e4 /* Clock Disable Status */
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE        0x004200e8 /* Avd0 top clock enable */
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS 0x004200ec /* Clock Enable Status */
#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE 0x004200f0 /* Avd0 top memory standby enable */
#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK       0x004200f4 /* Avd0 top observe clock */
#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY 0x004200f8 /* Avd0 top power switch memory */
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE    0x004200fc /* Bcm mips top clock enable */
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS 0x00420100 /* Clock Enable Status */
#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE 0x00420104 /* Bcm mips top memory standby enable */
#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK   0x00420108 /* Bcm mips top observe clock */
#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY 0x0042010c /* Bcm mips top power switch memory */
#define BCHP_CLKGEN_BVN_M2MC_TOP_CLOCK_ENABLE_M2MC 0x00420110 /* Bvn m2mc top clock enable m2mc */
#define BCHP_CLKGEN_BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_STATUS 0x00420114 /* Clock Enable Status */
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE          0x00420118 /* Bvn m2mc top enable */
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_M2MC     0x0042011c /* Bvn m2mc top enable m2mc */
#define BCHP_CLKGEN_BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE 0x00420120 /* Bvn m2mc top memory standby enable */
#define BCHP_CLKGEN_BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_M2MC 0x00420124 /* Bvn m2mc top memory standby enable m2mc */
#define BCHP_CLKGEN_BVN_M2MC_TOP_OBSERVE_CLOCK   0x00420128 /* Bvn m2mc top observe clock */
#define BCHP_CLKGEN_BVN_M2MC_TOP_POWER_SWITCH_MEMORY 0x0042012c /* Bvn m2mc top power switch memory */
#define BCHP_CLKGEN_BVN_M2MC_TOP_POWER_SWITCH_MEMORY_M2MC 0x00420130 /* Bvn m2mc top power switch memory m2mc */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x00420134 /* Disable CLKGEN's clocks */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS  0x00420138 /* Clock Disable Status */
#define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE          0x0042013c /* Clkgen clock enable */
#define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_STATUS   0x00420140 /* Clock Enable Status */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x00420144 /* Clock Monitor Control */
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x00420148 /* Clock Monitor Max Reference Count */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x0042014c /* Clock Monitor Reference Counter */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x00420150 /* Clock Monitor Reference Counter */
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x00420154 /* Clock Monitor View Counter */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE       0x00420158 /* Disable CORE_XPT's clocks */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS 0x0042015c /* Clock Disable Status */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE        0x00420160 /* Core xpt clock enable */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS 0x00420164 /* Clock Enable Status */
#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE 0x00420168 /* Core xpt memory standby enable */
#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK       0x0042016c /* Core xpt observe clock */
#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY 0x00420170 /* Core xpt power switch memory */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_DISABLE       0x00420174 /* Disable DFE_CORE's clocks */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_DISABLE_STATUS 0x00420178 /* Clock Disable Status */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE        0x0042017c /* Dfe core clock enable */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS 0x00420180 /* Clock Enable Status */
#define BCHP_CLKGEN_DFE_CORE_MEMORY_STANDBY_ENABLE 0x00420184 /* Dfe core memory standby enable */
#define BCHP_CLKGEN_DFE_CORE_OBSERVE_CLOCK       0x00420188 /* Dfe core observe clock */
#define BCHP_CLKGEN_DFE_CORE_POWER_SWITCH_MEMORY 0x0042018c /* Dfe core power switch memory */
#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE         0x00420190 /* Disable DVP_HT's clocks */
#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS  0x00420194 /* Clock Disable Status */
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE          0x00420198 /* Dvp ht clock enable */
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS   0x0042019c /* Clock Enable Status */
#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE 0x004201a0 /* Dvp ht memory standby enable */
#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK         0x004201a4 /* Dvp ht observe clock */
#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY   0x004201a8 /* Dvp ht power switch memory */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE 0x004201ac /* Disable HIF_JTAG_OTP_TOP's clocks */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_STATUS 0x004201b0 /* Clock Disable Status */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE 0x004201b4 /* Hif jtag otp top clock enable */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO 0x004201b8 /* Hif jtag otp top clock enable sdio */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_STATUS 0x004201bc /* Clock Enable Status */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_STATUS 0x004201c0 /* Clock Enable Status */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE 0x004201c4 /* Hif jtag otp top memory standby enable */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_SDIO 0x004201c8 /* Hif jtag otp top memory standby enable sdio */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY 0x004201cc /* Hif jtag otp top power switch memory */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_SDIO 0x004201d0 /* Hif jtag otp top power switch memory sdio */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x004201d4 /* Mux selects for Internal clocks */
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE          0x004201d8 /* Memsys clock enable */
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS   0x004201dc /* Clock Enable Status */
#define BCHP_CLKGEN_MEMSYS_MEMORY_STANDBY_ENABLE 0x004201e0 /* Memsys memory standby enable */
#define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK         0x004201e4 /* Memsys observe clock */
#define BCHP_CLKGEN_MEMSYS_POWER_SWITCH_MEMORY   0x004201e8 /* Memsys power switch memory */
#define BCHP_CLKGEN_MEMSYS_STATUS                0x004201ec /* Memsys status */
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA              0x004201f0 /* Mem dma m2m dma */
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_STATUS       0x004201f4 /* Clock Enable Status */
#define BCHP_CLKGEN_MEM_DMA_MEMORY_STANDBY_ENABLE 0x004201f8 /* Mem dma memory standby enable */
#define BCHP_CLKGEN_MEM_DMA_POWER_SWITCH_MEMORY  0x004201fc /* Mem dma power switch memory */
#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION   0x00420200 /* Select observation clk */
#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION   0x00420204 /* Select observation clk */
#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION   0x00420208 /* Select observation clk */
#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION   0x0042020c /* Select observation clk */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x00420210 /* Disable PAD's clocks */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS     0x00420214 /* Clock Disable Status */
#define BCHP_CLKGEN_PAD_MUX_SELECT               0x00420218 /* Mux selects for Pad clocks */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x0042021c /* PLL_AUDIO0 Reset Status */
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST 0x00420220 /* PLL_AVD_MIPS Glitchless Clock Switching */
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS 0x00420224 /* PLL_AVD_MIPS Glitchless Switching */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS 0x00420228 /* PLL_AVD_MIPS Reset Status */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x0042022c /* PLL_VCXO Reset Status */
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x00420230 /* Select clocks that can stay alive during power management standby mode. */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x00420234 /* PLL Alive in Standby Mode */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x00420238 /* Power management LDO PLL */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM        0x0042023c /* Power management LDO PLL state machine */
#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE         0x00420240 /* Rfm top clock enable */
#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_STATUS  0x00420244 /* Clock Enable Status */
#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE 0x00420248 /* Rfm top memory standby enable */
#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK        0x0042024c /* Rfm top observe clock */
#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY  0x00420250 /* Rfm top power switch memory */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00420254 /* Mux selects for Smartcard clocks */
#define BCHP_CLKGEN_SPARE                        0x00420258 /* Spares */
#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK        0x0042025c /* Sys aon observe clock */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE       0x00420260 /* Disable SYS_CTRL's clocks */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS 0x00420264 /* Clock Disable Status */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE        0x00420268 /* Sys ctrl clock enable */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS 0x0042026c /* Clock Enable Status */
#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE 0x00420270 /* Sys ctrl memory standby enable */
#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK       0x00420274 /* Sys ctrl observe clock */
#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY 0x00420278 /* Sys ctrl power switch memory */
#define BCHP_CLKGEN_TESTPORT                     0x0042027c /* Special Testport Controls */
#define BCHP_CLKGEN_USB_CLOCK_DISABLE            0x00420280 /* Disable USB's clocks */
#define BCHP_CLKGEN_USB_CLOCK_DISABLE_STATUS     0x00420284 /* Clock Disable Status */
#define BCHP_CLKGEN_USB_CLOCK_ENABLE             0x00420288 /* Usb clock enable */
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS      0x0042028c /* Clock Enable Status */
#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE    0x00420290 /* Usb memory standby enable */
#define BCHP_CLKGEN_USB_OBSERVE_CLOCK            0x00420294 /* Usb observe clock */
#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY      0x00420298 /* Usb power switch memory */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE    0x0042029c /* Disable VEC_AIO_TOP's clocks */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS 0x004202a0 /* Clock Disable Status */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO 0x004202a4 /* Vec aio top clock enable aio */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS 0x004202a8 /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC 0x004202ac /* Vec aio top clock enable vec */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS 0x004202b0 /* Clock Enable Status */
#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO 0x004202b4 /* Vec aio top memory standby enable aio */
#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC 0x004202b8 /* Vec aio top memory standby enable vec */
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK    0x004202bc /* Vec aio top observe clock */
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO 0x004202c0 /* Vec aio top observe clock aio */
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC 0x004202c4 /* Vec aio top observe clock vec */
#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO 0x004202c8 /* Vec aio top power switch memory aio */
#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC 0x004202cc /* Vec aio top power switch memory vec */
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT            0x004202d0 /* BSPI CLOCK SELECT - spi clock control */

/***************************************************************************
 *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1

/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0x00000000

/***************************************************************************
 *PLL_AUDIO0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3

/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                0x00000001

/***************************************************************************
 *PLL_AUDIO0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  0x00000001

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1

/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0

/***************************************************************************
 *PLL_AUDIO0_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1

/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0x00000000

/***************************************************************************
 *PLL_AUDIO0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2

/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0x00000000

/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0x00000000

/***************************************************************************
 *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AUDIO0_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12

/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0

/***************************************************************************
 *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000008

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x0000000f

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000000c

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000c

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000008

/* CLKGEN :: PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_reserved0_SHIFT       1

/* CLKGEN :: PLL_AVD_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_MASK          0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_SHIFT         0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_CONTROL_REF_SEL_DEFAULT       0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_MASK            0xffffe000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_reserved0_SHIFT           13

/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: PDIV [12:10] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_MASK                 0x00001c00
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_SHIFT                10
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_PDIV_DEFAULT              0x00000003

/* CLKGEN :: PLL_AVD_MIPS_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_MASK             0x000003ff
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_SHIFT            0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_DIV_NDIV_INT_DEFAULT          0x000000a7

/***************************************************************************
 *PLL_AVD_MIPS_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_MASK           0xff000000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_reserved0_SHIFT          24

/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000006

/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK   0x000000e0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT  5
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 0x00000002

/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT   2

/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK    0x00000002
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT   1

/* CLKGEN :: PLL_AVD_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_MASK         0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT        0

/***************************************************************************
 *PLL_AVD_MIPS_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_MASK           0x80000000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_reserved0_SHIFT          31

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCO_DLY [30:29] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_MASK             0x60000000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_SHIFT            29
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCO_DLY_DEFAULT          0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: VCODIV2 [28:28] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_MASK             0x10000000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_SHIFT            28
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_VCODIV2_DEFAULT          0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_MASK         0x08000000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_SHIFT        27
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT      0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_MASK         0x07000000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_SHIFT        24
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_SELECT_DEFAULT      0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__MASK         0x00800000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__SHIFT        23
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_RESET__DEFAULT      0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: STAT_MODE [22:21] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_MASK           0x00600000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_SHIFT          21
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_STAT_MODE_DEFAULT        0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_MASK           0x00100000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_SHIFT          20
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_REFCLKOUT_DEFAULT        0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: PWM_RATE [19:18] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_MASK            0x000c0000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_SHIFT           18
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_PWM_RATE_DEFAULT         0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_MASK          0x00020000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_SHIFT         17
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_POR_BYPASS_DEFAULT       0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_MASK         0x00010000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT        16
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT      0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_MASK         0x00008000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT        15
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT      0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_MASK           0x00004000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_SHIFT          14
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_FAST_LOCK_DEFAULT        0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK     0x00001ffe
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT    1
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT  0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_SHIFT           0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC_AUX_CTRL_DEFAULT         0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_reserved0_SHIFT         1

/* CLKGEN :: PLL_AVD_MIPS_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_MASK              0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_SHIFT             0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_MISC2_SPARE_DEFAULT           0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_reserved0_SHIFT         1

/* CLKGEN :: PLL_AVD_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_MASK          0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT         0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT       0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_reserved0_MASK          0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_reserved0_SHIFT         2

/* CLKGEN :: PLL_AVD_MIPS_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_RESETD_MASK             0x00000002
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_RESETD_SHIFT            1
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_RESETD_DEFAULT          0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_RESETA_MASK             0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_RESETA_SHIFT            0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_RESETA_DEFAULT          0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_MASK         0xfffff000
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_reserved0_SHIFT        12

/* CLKGEN :: PLL_AVD_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_MASK       0x00000fff
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_STATUS_TEST_STATUS_SHIFT      0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x0000000c

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x00000030

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x00000008

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 0x0000000c

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 0x00000060

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 0x00000036

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1

/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13

/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  0x00000002

/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              0x00000060

/***************************************************************************
 *PLL_SYS0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000007

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000002

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000003

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1

/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0

/***************************************************************************
 *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31

/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000

/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1

/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1

/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT             1

/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT                0
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT              0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_SYS0_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 0x00000040

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 0x000000fa

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 0x0000004b

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1

/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0x00000000

/***************************************************************************
 *PLL_VCXO_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13

/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  0x00000002

/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              0x00000040

/***************************************************************************
 *PLL_VCXO_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20

/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0x00000000

/***************************************************************************
 *PLL_VCXO_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24

/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 0x00000008

/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    0x00000001

/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 0x00000002

/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1

/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0

/***************************************************************************
 *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30

/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0x00000000

/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0x00000000

/***************************************************************************
 *PLL_VCXO_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1

/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0x00000000

/***************************************************************************
 *PLL_VCXO_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2

/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0x00000000

/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0x00000000

/***************************************************************************
 *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0x00000000

/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0x00000000

/***************************************************************************
 *PLL_VCXO_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *ANA_SDAC40G_M7FC_CLOCK_DISABLE - Disable ANA_SDAC40G_M7FC's clocks
 ***************************************************************************/
/* CLKGEN :: ANA_SDAC40G_M7FC_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_ANA_SDAC40G_M7FC_CLOCK_DISABLE_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_ANA_SDAC40G_M7FC_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: ANA_SDAC40G_M7FC_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
#define BCHP_CLKGEN_ANA_SDAC40G_M7FC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_ANA_SDAC40G_M7FC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
#define BCHP_CLKGEN_ANA_SDAC40G_M7FC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *ANA_SDAC40G_M7FC_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: ANA_SDAC40G_M7FC_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_ANA_SDAC40G_M7FC_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_ANA_SDAC40G_M7FC_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: ANA_SDAC40G_M7FC_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_ANA_SDAC40G_M7FC_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_ANA_SDAC40G_M7FC_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *AVD0_TOP_CLOCK_ENABLE - Avd0 top clock enable
 ***************************************************************************/
/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_MASK           0xfffffff0
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_reserved0_SHIFT          4

/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: AVD0_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: AVD0_CPU_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_CPU_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_CPU_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_CPU_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: AVD0_CORE_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_CORE_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_CORE_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_CORE_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE :: AVD0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_AVD0_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *AVD0_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK    0xfffffff0
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT   4

/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: AVD0_SCB_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_SCB_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: AVD0_CPU_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_CPU_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_CPU_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: AVD0_CORE_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_CORE_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_CORE_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: AVD0_TOP_CLOCK_ENABLE_STATUS :: AVD0_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_AVD0_TOP_CLOCK_ENABLE_STATUS_AVD0_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *AVD0_TOP_MEMORY_STANDBY_ENABLE - Avd0 top memory standby enable
 ***************************************************************************/
/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: AVD0_TOP_MEMORY_STANDBY_ENABLE :: AVD0_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_AVD0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_AVD0_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_AVD0_TOP_MEMORY_STANDBY_ENABLE_AVD0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *AVD0_TOP_OBSERVE_CLOCK - Avd0 top observe clock
 ***************************************************************************/
/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_reserved0_SHIFT         6

/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: AVD0_TOP_OBSERVE_CLOCK :: AVD0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_AVD0_TOP_OBSERVE_CLOCK_AVD0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *AVD0_TOP_POWER_SWITCH_MEMORY - Avd0 top power switch memory
 ***************************************************************************/
/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT   2

/* CLKGEN :: AVD0_TOP_POWER_SWITCH_MEMORY :: AVD0_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_AVD0_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_AVD0_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_AVD0_TOP_POWER_SWITCH_MEMORY_AVD0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000

/***************************************************************************
 *BCM_MIPS_TOP_CLOCK_ENABLE - Bcm mips top clock enable
 ***************************************************************************/
/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_reserved0_SHIFT      3

/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_216_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE :: MIPS_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_MIPS_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *BCM_MIPS_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 3

/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE_STATUS :: MIPS_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE_STATUS :: MIPS_216_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_216_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: BCM_MIPS_TOP_CLOCK_ENABLE_STATUS :: MIPS_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_BCM_MIPS_TOP_CLOCK_ENABLE_STATUS_MIPS_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE - Bcm mips top memory standby enable
 ***************************************************************************/
/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE :: MIPS_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BCM_MIPS_TOP_MEMORY_STANDBY_ENABLE_MIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *BCM_MIPS_TOP_OBSERVE_CLOCK - Bcm mips top observe clock
 ***************************************************************************/
/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6

/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: BCM_MIPS_TOP_OBSERVE_CLOCK :: MIPS_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_BCM_MIPS_TOP_OBSERVE_CLOCK_MIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *BCM_MIPS_TOP_POWER_SWITCH_MEMORY - Bcm mips top power switch memory
 ***************************************************************************/
/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: BCM_MIPS_TOP_POWER_SWITCH_MEMORY :: MIPS_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_BCM_MIPS_TOP_POWER_SWITCH_MEMORY_MIPS_POWER_SWITCH_MEMORY_DEFAULT 0x00000000

/***************************************************************************
 *BVN_M2MC_TOP_CLOCK_ENABLE_M2MC - Bvn m2mc top clock enable m2mc
 ***************************************************************************/
/* CLKGEN :: BVN_M2MC_TOP_CLOCK_ENABLE_M2MC :: reserved0 [31:01] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_reserved0_SHIFT 1

/* CLKGEN :: BVN_M2MC_TOP_CLOCK_ENABLE_M2MC :: M2MC_CORE_CLOCK_ENABLE_M2MC [00:00] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_M2MC_CORE_CLOCK_ENABLE_M2MC_MASK 0x00000001
#define BCHP_CLKGEN_BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_M2MC_CORE_CLOCK_ENABLE_M2MC_SHIFT 0
#define BCHP_CLKGEN_BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_M2MC_CORE_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001

/***************************************************************************
 *BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_STATUS_reserved0_SHIFT 1

/* CLKGEN :: BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_STATUS :: M2MC_CORE_CLOCK_ENABLE_M2MC_STATUS [00:00] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_STATUS_M2MC_CORE_CLOCK_ENABLE_M2MC_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_BVN_M2MC_TOP_CLOCK_ENABLE_M2MC_STATUS_M2MC_CORE_CLOCK_ENABLE_M2MC_STATUS_SHIFT 0

/***************************************************************************
 *BVN_M2MC_TOP_ENABLE - Bvn m2mc top enable
 ***************************************************************************/
/* CLKGEN :: BVN_M2MC_TOP_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_reserved0_MASK             0xfffffff8
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_reserved0_SHIFT            3

/* CLKGEN :: BVN_M2MC_TOP_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK  0x00000004
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_M2MC_TOP_ENABLE :: BVN_216_CLK_ENABLE [01:01] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_BVN_216_CLK_ENABLE_MASK    0x00000002
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_BVN_216_CLK_ENABLE_SHIFT   1
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_BVN_216_CLK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: BVN_M2MC_TOP_ENABLE :: BVN_108_CLK_ENABLE [00:00] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_BVN_108_CLK_ENABLE_MASK    0x00000001
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_BVN_108_CLK_ENABLE_SHIFT   0
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_BVN_108_CLK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *BVN_M2MC_TOP_ENABLE_M2MC - Bvn m2mc top enable m2mc
 ***************************************************************************/
/* CLKGEN :: BVN_M2MC_TOP_ENABLE_M2MC :: reserved0 [31:02] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_M2MC_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_M2MC_reserved0_SHIFT       2

/* CLKGEN :: BVN_M2MC_TOP_ENABLE_M2MC :: M2MC_SCB_CLOCK_ENABLE_M2MC [01:01] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_M2MC_M2MC_SCB_CLOCK_ENABLE_M2MC_MASK 0x00000002
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_M2MC_M2MC_SCB_CLOCK_ENABLE_M2MC_SHIFT 1
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_M2MC_M2MC_SCB_CLOCK_ENABLE_M2MC_DEFAULT 0x00000001

/* CLKGEN :: BVN_M2MC_TOP_ENABLE_M2MC :: M2MC_108_CLK_ENABLE_M2MC [00:00] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_M2MC_M2MC_108_CLK_ENABLE_M2MC_MASK 0x00000001
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_M2MC_M2MC_108_CLK_ENABLE_M2MC_SHIFT 0
#define BCHP_CLKGEN_BVN_M2MC_TOP_ENABLE_M2MC_M2MC_108_CLK_ENABLE_M2MC_DEFAULT 0x00000001

/***************************************************************************
 *BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE - Bvn m2mc top memory standby enable
 ***************************************************************************/
/* CLKGEN :: BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_M2MC - Bvn m2mc top memory standby enable m2mc
 ***************************************************************************/
/* CLKGEN :: BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_M2MC :: reserved0 [31:01] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_M2MC_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_M2MC_reserved0_SHIFT 1

/* CLKGEN :: BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_M2MC :: M2MC_MEMORY_STANDBY_ENABLE_M2MC [00:00] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_M2MC_M2MC_MEMORY_STANDBY_ENABLE_M2MC_MASK 0x00000001
#define BCHP_CLKGEN_BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_M2MC_M2MC_MEMORY_STANDBY_ENABLE_M2MC_SHIFT 0
#define BCHP_CLKGEN_BVN_M2MC_TOP_MEMORY_STANDBY_ENABLE_M2MC_M2MC_MEMORY_STANDBY_ENABLE_M2MC_DEFAULT 0x00000000

/***************************************************************************
 *BVN_M2MC_TOP_OBSERVE_CLOCK - Bvn m2mc top observe clock
 ***************************************************************************/
/* CLKGEN :: BVN_M2MC_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
#define BCHP_CLKGEN_BVN_M2MC_TOP_OBSERVE_CLOCK_reserved0_SHIFT     6

/* CLKGEN :: BVN_M2MC_TOP_OBSERVE_CLOCK :: BVN_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_OBSERVE_CLOCK_BVN_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_BVN_M2MC_TOP_OBSERVE_CLOCK_BVN_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_BVN_M2MC_TOP_OBSERVE_CLOCK_BVN_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: BVN_M2MC_TOP_OBSERVE_CLOCK :: BVN_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_OBSERVE_CLOCK_BVN_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_BVN_M2MC_TOP_OBSERVE_CLOCK_BVN_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_BVN_M2MC_TOP_OBSERVE_CLOCK_BVN_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: BVN_M2MC_TOP_OBSERVE_CLOCK :: BVN_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_OBSERVE_CLOCK_BVN_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_BVN_M2MC_TOP_OBSERVE_CLOCK_BVN_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_BVN_M2MC_TOP_OBSERVE_CLOCK_BVN_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *BVN_M2MC_TOP_POWER_SWITCH_MEMORY - Bvn m2mc top power switch memory
 ***************************************************************************/
/* CLKGEN :: BVN_M2MC_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_BVN_M2MC_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: BVN_M2MC_TOP_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_BVN_M2MC_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_BVN_M2MC_TOP_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0x00000000

/***************************************************************************
 *BVN_M2MC_TOP_POWER_SWITCH_MEMORY_M2MC - Bvn m2mc top power switch memory m2mc
 ***************************************************************************/
/* CLKGEN :: BVN_M2MC_TOP_POWER_SWITCH_MEMORY_M2MC :: reserved0 [31:02] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_POWER_SWITCH_MEMORY_M2MC_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_BVN_M2MC_TOP_POWER_SWITCH_MEMORY_M2MC_reserved0_SHIFT 2

/* CLKGEN :: BVN_M2MC_TOP_POWER_SWITCH_MEMORY_M2MC :: M2MC_POWER_SWITCH_MEMORY_M2MC [01:00] */
#define BCHP_CLKGEN_BVN_M2MC_TOP_POWER_SWITCH_MEMORY_M2MC_M2MC_POWER_SWITCH_MEMORY_M2MC_MASK 0x00000003
#define BCHP_CLKGEN_BVN_M2MC_TOP_POWER_SWITCH_MEMORY_M2MC_M2MC_POWER_SWITCH_MEMORY_M2MC_SHIFT 0
#define BCHP_CLKGEN_BVN_M2MC_TOP_POWER_SWITCH_MEMORY_M2MC_M2MC_POWER_SWITCH_MEMORY_M2MC_DEFAULT 0x00000000

/***************************************************************************
 *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
 ***************************************************************************/
/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           1

/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *CLKGEN_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_MASK     0xfffffffe
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_reserved0_SHIFT    1

/* CLKGEN :: CLKGEN_CLOCK_DISABLE_STATUS :: DISABLE_AVS_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_STATUS_DISABLE_AVS_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *CLKGEN_CLOCK_ENABLE - Clkgen clock enable
 ***************************************************************************/
/* CLKGEN :: CLKGEN_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_reserved0_SHIFT            1

/* CLKGEN :: CLKGEN_CLOCK_ENABLE :: CG_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_MASK   0x00000001
#define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_SHIFT  0
#define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *CLKGEN_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: CLKGEN_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_STATUS_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_STATUS_reserved0_SHIFT     1

/* CLKGEN :: CLKGEN_CLOCK_ENABLE_STATUS :: CG_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_STATUS_CG_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CLKGEN_CLOCK_ENABLE_STATUS_CG_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *CLOCK_MONITOR_CONTROL - Clock Monitor Control
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 0x00000001

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 0x00000001

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   0x00000001

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 0x00000001

/***************************************************************************
 *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 0xffffffff

/***************************************************************************
 *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0

/***************************************************************************
 *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1

/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0

/***************************************************************************
 *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0

/***************************************************************************
 *CORE_XPT_CLOCK_DISABLE - Disable CORE_XPT's clocks
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_reserved0_SHIFT         5

/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *CORE_XPT_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_reserved0_MASK   0xffffffe0
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_reserved0_SHIFT  5

/* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_81_CLOCK_STATUS [04:04] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_81_CLOCK_STATUS_SHIFT 4

/* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_54_CLOCK_STATUS [03:03] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_54_CLOCK_STATUS_SHIFT 3

/* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_40P5_CLOCK_STATUS [02:02] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_40P5_CLOCK_STATUS_SHIFT 2

/* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_27_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_27_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: CORE_XPT_CLOCK_DISABLE_STATUS :: DISABLE_XPT_20P25_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_CLOCK_DISABLE_STATUS_DISABLE_XPT_20P25_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *CORE_XPT_CLOCK_ENABLE - Core xpt clock enable
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_MASK           0xfffffff8
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_reserved0_SHIFT          3

/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: CORE_XPT_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *CORE_XPT_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_CLOCK_ENABLE_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_reserved0_MASK    0xfffffff8
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_reserved0_SHIFT   3

/* CLKGEN :: CORE_XPT_CLOCK_ENABLE_STATUS :: XPT_SCB_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_SCB_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: CORE_XPT_CLOCK_ENABLE_STATUS :: XPT_216_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_216_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: CORE_XPT_CLOCK_ENABLE_STATUS :: XPT_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_CLOCK_ENABLE_STATUS_XPT_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *CORE_XPT_MEMORY_STANDBY_ENABLE - Core xpt memory standby enable
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: CORE_XPT_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *CORE_XPT_OBSERVE_CLOCK - Core xpt observe clock
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_reserved0_SHIFT         6

/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: CORE_XPT_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *CORE_XPT_POWER_SWITCH_MEMORY - Core xpt power switch memory
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_reserved0_SHIFT   2

/* CLKGEN :: CORE_XPT_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000

/***************************************************************************
 *DFE_CORE_CLOCK_DISABLE - Disable DFE_CORE's clocks
 ***************************************************************************/
/* CLKGEN :: DFE_CORE_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_DISABLE_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_DFE_CORE_CLOCK_DISABLE_reserved0_SHIFT         1

/* CLKGEN :: DFE_CORE_CLOCK_DISABLE :: DISABLE_DFE_216_CLOCK [00:00] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_DISABLE_DISABLE_DFE_216_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DFE_CORE_CLOCK_DISABLE_DISABLE_DFE_216_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DFE_CORE_CLOCK_DISABLE_DISABLE_DFE_216_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DFE_CORE_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DFE_CORE_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_DISABLE_STATUS_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_DFE_CORE_CLOCK_DISABLE_STATUS_reserved0_SHIFT  1

/* CLKGEN :: DFE_CORE_CLOCK_DISABLE_STATUS :: DISABLE_DFE_216_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_DISABLE_STATUS_DISABLE_DFE_216_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DFE_CORE_CLOCK_DISABLE_STATUS_DISABLE_DFE_216_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DFE_CORE_CLOCK_ENABLE - Dfe core clock enable
 ***************************************************************************/
/* CLKGEN :: DFE_CORE_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_reserved0_MASK           0xffffffe0
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_reserved0_SHIFT          5

/* CLKGEN :: DFE_CORE_CLOCK_ENABLE :: DFE_SYS_108_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_SYS_108_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_SYS_108_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_SYS_108_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DFE_CORE_CLOCK_ENABLE :: DFE_ADC_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_ADC_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_ADC_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_ADC_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DFE_CORE_CLOCK_ENABLE :: DFE_54_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_54_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_54_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_54_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DFE_CORE_CLOCK_ENABLE :: DFE_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_216_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DFE_CORE_CLOCK_ENABLE :: DFE_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_DFE_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DFE_CORE_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DFE_CORE_CLOCK_ENABLE_STATUS :: reserved0 [31:05] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS_reserved0_MASK    0xffffffe0
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS_reserved0_SHIFT   5

/* CLKGEN :: DFE_CORE_CLOCK_ENABLE_STATUS :: DFE_SYS_108_CLOCK_ENABLE_STATUS [04:04] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS_DFE_SYS_108_CLOCK_ENABLE_STATUS_MASK 0x00000010
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS_DFE_SYS_108_CLOCK_ENABLE_STATUS_SHIFT 4

/* CLKGEN :: DFE_CORE_CLOCK_ENABLE_STATUS :: DFE_ADC_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS_DFE_ADC_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS_DFE_ADC_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: DFE_CORE_CLOCK_ENABLE_STATUS :: DFE_54_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS_DFE_54_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS_DFE_54_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: DFE_CORE_CLOCK_ENABLE_STATUS :: DFE_216_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS_DFE_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS_DFE_216_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: DFE_CORE_CLOCK_ENABLE_STATUS :: DFE_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS_DFE_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DFE_CORE_CLOCK_ENABLE_STATUS_DFE_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DFE_CORE_MEMORY_STANDBY_ENABLE - Dfe core memory standby enable
 ***************************************************************************/
/* CLKGEN :: DFE_CORE_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DFE_CORE_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_DFE_CORE_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: DFE_CORE_MEMORY_STANDBY_ENABLE :: DFE_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_DFE_CORE_MEMORY_STANDBY_ENABLE_DFE_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DFE_CORE_MEMORY_STANDBY_ENABLE_DFE_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DFE_CORE_MEMORY_STANDBY_ENABLE_DFE_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *DFE_CORE_OBSERVE_CLOCK - Dfe core observe clock
 ***************************************************************************/
/* CLKGEN :: DFE_CORE_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_DFE_CORE_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
#define BCHP_CLKGEN_DFE_CORE_OBSERVE_CLOCK_reserved0_SHIFT         6

/* CLKGEN :: DFE_CORE_OBSERVE_CLOCK :: DFE_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_DFE_CORE_OBSERVE_CLOCK_DFE_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_DFE_CORE_OBSERVE_CLOCK_DFE_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_DFE_CORE_OBSERVE_CLOCK_DFE_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DFE_CORE_OBSERVE_CLOCK :: DFE_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_DFE_CORE_OBSERVE_CLOCK_DFE_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DFE_CORE_OBSERVE_CLOCK_DFE_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DFE_CORE_OBSERVE_CLOCK_DFE_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DFE_CORE_OBSERVE_CLOCK :: DFE_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_DFE_CORE_OBSERVE_CLOCK_DFE_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_DFE_CORE_OBSERVE_CLOCK_DFE_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DFE_CORE_OBSERVE_CLOCK_DFE_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DFE_CORE_POWER_SWITCH_MEMORY - Dfe core power switch memory
 ***************************************************************************/
/* CLKGEN :: DFE_CORE_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_DFE_CORE_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_DFE_CORE_POWER_SWITCH_MEMORY_reserved0_SHIFT   2

/* CLKGEN :: DFE_CORE_POWER_SWITCH_MEMORY :: DFE_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_DFE_CORE_POWER_SWITCH_MEMORY_DFE_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_DFE_CORE_POWER_SWITCH_MEMORY_DFE_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_DFE_CORE_POWER_SWITCH_MEMORY_DFE_POWER_SWITCH_MEMORY_DEFAULT 0x00000000

/***************************************************************************
 *DVP_HT_CLOCK_DISABLE - Disable DVP_HT's clocks
 ***************************************************************************/
/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_reserved0_SHIFT           1

/* CLKGEN :: DVP_HT_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DVP_HT_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: DVP_HT_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS_reserved0_MASK     0xfffffffe
#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS_reserved0_SHIFT    1

/* CLKGEN :: DVP_HT_CLOCK_DISABLE_STATUS :: DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_CLOCK_DISABLE_STATUS_DISABLE_DVPHT_IIC_MASTER_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *DVP_HT_CLOCK_ENABLE - Dvp ht clock enable
 ***************************************************************************/
/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_MASK             0xfffffff0
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_reserved0_SHIFT            4

/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: VEC_IF_216_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_VEC_IF_216_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_VEC_IF_216_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_VEC_IF_216_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_MAX_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: DVP_HT_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *DVP_HT_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_reserved0_MASK      0xfffffff0
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_reserved0_SHIFT     4

/* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: VEC_IF_216_CLOCK_ENABLE_STATUS [03:03] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_VEC_IF_216_CLOCK_ENABLE_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_VEC_IF_216_CLOCK_ENABLE_STATUS_SHIFT 3

/* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: DVPHT_MAX_CLOCK_ENABLE_STATUS [02:02] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_MAX_CLOCK_ENABLE_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_MAX_CLOCK_ENABLE_STATUS_SHIFT 2

/* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: DVPHT_216_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_216_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: DVP_HT_CLOCK_ENABLE_STATUS :: DVPHT_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_CLOCK_ENABLE_STATUS_DVPHT_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *DVP_HT_MEMORY_STANDBY_ENABLE - Dvp ht memory standby enable
 ***************************************************************************/
/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_reserved0_SHIFT   1

/* CLKGEN :: DVP_HT_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *DVP_HT_OBSERVE_CLOCK - Dvp ht observe clock
 ***************************************************************************/
/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_MASK            0xffffffc0
#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_reserved0_SHIFT           6

/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: DVP_HT_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *DVP_HT_POWER_SWITCH_MEMORY - Dvp ht power switch memory
 ***************************************************************************/
/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_reserved0_SHIFT     2

/* CLKGEN :: DVP_HT_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0x00000000

/***************************************************************************
 *HIF_JTAG_OTP_TOP_CLOCK_DISABLE - Disable HIF_JTAG_OTP_TOP's clocks
 ***************************************************************************/
/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_reserved0_MASK  0xfffffffc
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [01:01] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 1
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [00:00] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 0
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *HIF_JTAG_OTP_TOP_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SPI_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_STATUS_DISABLE_HIF_SPI_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_DISABLE_STATUS :: DISABLE_HIF_SDIO_CARD_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_DISABLE_STATUS_DISABLE_HIF_SDIO_CARD_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *HIF_JTAG_OTP_TOP_CLOCK_ENABLE - Hif jtag otp top clock enable
 ***************************************************************************/
/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_reserved0_SHIFT  2

/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_ENABLE :: HIF_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_HIF_216_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_ENABLE :: HIF_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_HIF_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO - Hif jtag otp top clock enable sdio
 ***************************************************************************/
/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO :: reserved0 [31:02] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_reserved0_SHIFT 2

/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO :: SDIO_SCB_CLOCK_ENABLE_SDIO [01:01] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_SDIO_SCB_CLOCK_ENABLE_SDIO_MASK 0x00000002
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_SDIO_SCB_CLOCK_ENABLE_SDIO_SHIFT 1
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_SDIO_SCB_CLOCK_ENABLE_SDIO_DEFAULT 0x00000001

/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO :: SDIO_216_CLOCK_ENABLE_SDIO [00:00] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_SDIO_216_CLOCK_ENABLE_SDIO_MASK 0x00000001
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_SDIO_216_CLOCK_ENABLE_SDIO_SHIFT 0
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_SDIO_216_CLOCK_ENABLE_SDIO_DEFAULT 0x00000001

/***************************************************************************
 *HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_STATUS_reserved0_SHIFT 2

/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_STATUS :: SDIO_SCB_CLOCK_ENABLE_SDIO_STATUS [01:01] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_STATUS_SDIO_SCB_CLOCK_ENABLE_SDIO_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_STATUS_SDIO_SCB_CLOCK_ENABLE_SDIO_STATUS_SHIFT 1

/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_STATUS :: SDIO_216_CLOCK_ENABLE_SDIO_STATUS [00:00] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_STATUS_SDIO_216_CLOCK_ENABLE_SDIO_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_SDIO_STATUS_SDIO_216_CLOCK_ENABLE_SDIO_STATUS_SHIFT 0

/***************************************************************************
 *HIF_JTAG_OTP_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT 2

/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_ENABLE_STATUS :: HIF_216_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_STATUS_HIF_216_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_STATUS_HIF_216_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: HIF_JTAG_OTP_TOP_CLOCK_ENABLE_STATUS :: HIF_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_STATUS_HIF_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_CLOCK_ENABLE_STATUS_HIF_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE - Hif jtag otp top memory standby enable
 ***************************************************************************/
/* CLKGEN :: HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_SDIO - Hif jtag otp top memory standby enable sdio
 ***************************************************************************/
/* CLKGEN :: HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_SDIO :: reserved0 [31:01] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_SDIO_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_SDIO_reserved0_SHIFT 1

/* CLKGEN :: HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_SDIO :: SDIO_MEMORY_STANDBY_ENABLE_SDIO [00:00] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_SDIO_SDIO_MEMORY_STANDBY_ENABLE_SDIO_MASK 0x00000001
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_SDIO_SDIO_MEMORY_STANDBY_ENABLE_SDIO_SHIFT 0
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_MEMORY_STANDBY_ENABLE_SDIO_SDIO_MEMORY_STANDBY_ENABLE_SDIO_DEFAULT 0x00000000

/***************************************************************************
 *HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY - Hif jtag otp top power switch memory
 ***************************************************************************/
/* CLKGEN :: HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0x00000000

/***************************************************************************
 *HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_SDIO - Hif jtag otp top power switch memory sdio
 ***************************************************************************/
/* CLKGEN :: HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_SDIO :: reserved0 [31:02] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_SDIO_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_SDIO_reserved0_SHIFT 2

/* CLKGEN :: HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_SDIO :: SDIO_POWER_SWITCH_MEMORY_SDIO [01:00] */
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_SDIO_SDIO_POWER_SWITCH_MEMORY_SDIO_MASK 0x00000003
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_SDIO_SDIO_POWER_SWITCH_MEMORY_SDIO_SHIFT 0
#define BCHP_CLKGEN_HIF_JTAG_OTP_TOP_POWER_SWITCH_MEMORY_SDIO_SDIO_POWER_SWITCH_MEMORY_SDIO_DEFAULT 0x00000000

/***************************************************************************
 *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
 ***************************************************************************/
/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:05] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xffffffe0
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            5

/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [04:04] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: INTERNAL_MUX_SELECT :: M2MC_CORE_CLOCK [03:02] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_M2MC_CORE_CLOCK_MASK       0x0000000c
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_M2MC_CORE_CLOCK_SHIFT      2
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_M2MC_CORE_CLOCK_DEFAULT    0x00000000

/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved1 [01:00] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved1_MASK             0x00000003
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved1_SHIFT            0

/***************************************************************************
 *MEMSYS_CLOCK_ENABLE - Memsys clock enable
 ***************************************************************************/
/* CLKGEN :: MEMSYS_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_reserved0_SHIFT            2

/* CLKGEN :: MEMSYS_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: MEMSYS_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *MEMSYS_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: MEMSYS_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS_reserved0_SHIFT     2

/* CLKGEN :: MEMSYS_CLOCK_ENABLE_STATUS :: DDR1_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS_DDR1_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS_DDR1_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: MEMSYS_CLOCK_ENABLE_STATUS :: DDR1_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS_DDR1_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_CLOCK_ENABLE_STATUS_DDR1_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *MEMSYS_MEMORY_STANDBY_ENABLE - Memsys memory standby enable
 ***************************************************************************/
/* CLKGEN :: MEMSYS_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEMSYS_MEMORY_STANDBY_ENABLE_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_MEMSYS_MEMORY_STANDBY_ENABLE_reserved0_SHIFT   1

/* CLKGEN :: MEMSYS_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_MEMSYS_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *MEMSYS_OBSERVE_CLOCK - Memsys observe clock
 ***************************************************************************/
/* CLKGEN :: MEMSYS_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_reserved0_MASK            0xffffffc0
#define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_reserved0_SHIFT           6

/* CLKGEN :: MEMSYS_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MEMSYS_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: MEMSYS_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *MEMSYS_POWER_SWITCH_MEMORY - Memsys power switch memory
 ***************************************************************************/
/* CLKGEN :: MEMSYS_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_MEMSYS_POWER_SWITCH_MEMORY_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_MEMSYS_POWER_SWITCH_MEMORY_reserved0_SHIFT     2

/* CLKGEN :: MEMSYS_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_MEMSYS_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_MEMSYS_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0x00000000

/***************************************************************************
 *MEMSYS_STATUS - Memsys status
 ***************************************************************************/
/* CLKGEN :: MEMSYS_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEMSYS_STATUS_reserved0_MASK                   0xfffffffe
#define BCHP_CLKGEN_MEMSYS_STATUS_reserved0_SHIFT                  1

/* CLKGEN :: MEMSYS_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
#define BCHP_CLKGEN_MEMSYS_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK    0x00000001
#define BCHP_CLKGEN_MEMSYS_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT   0

/***************************************************************************
 *MEM_DMA_M2M_DMA - Mem dma m2m dma
 ***************************************************************************/
/* CLKGEN :: MEM_DMA_M2M_DMA :: reserved0 [31:03] */
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_reserved0_MASK                 0xfffffff8
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_reserved0_SHIFT                3

/* CLKGEN :: MEM_DMA_M2M_DMA :: M2M_DMA_SCB_CLOCK_ENABLE_M2M_DMA [02:02] */
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_M2M_DMA_SCB_CLOCK_ENABLE_M2M_DMA_MASK 0x00000004
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_M2M_DMA_SCB_CLOCK_ENABLE_M2M_DMA_SHIFT 2
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_M2M_DMA_SCB_CLOCK_ENABLE_M2M_DMA_DEFAULT 0x00000001

/* CLKGEN :: MEM_DMA_M2M_DMA :: M2M_DMA_216_CLOCK_ENABLE_M2M_DMA [01:01] */
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_M2M_DMA_216_CLOCK_ENABLE_M2M_DMA_MASK 0x00000002
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_M2M_DMA_216_CLOCK_ENABLE_M2M_DMA_SHIFT 1
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_M2M_DMA_216_CLOCK_ENABLE_M2M_DMA_DEFAULT 0x00000001

/* CLKGEN :: MEM_DMA_M2M_DMA :: M2M_DMA_108_CLOCK_ENABLE_M2M_DMA [00:00] */
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_M2M_DMA_108_CLOCK_ENABLE_M2M_DMA_MASK 0x00000001
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_M2M_DMA_108_CLOCK_ENABLE_M2M_DMA_SHIFT 0
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_M2M_DMA_108_CLOCK_ENABLE_M2M_DMA_DEFAULT 0x00000001

/***************************************************************************
 *MEM_DMA_M2M_DMA_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: MEM_DMA_M2M_DMA_STATUS :: reserved0 [31:03] */
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_STATUS_reserved0_MASK          0xfffffff8
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_STATUS_reserved0_SHIFT         3

/* CLKGEN :: MEM_DMA_M2M_DMA_STATUS :: M2M_DMA_SCB_CLOCK_ENABLE_M2M_DMA_STATUS [02:02] */
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_STATUS_M2M_DMA_SCB_CLOCK_ENABLE_M2M_DMA_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_STATUS_M2M_DMA_SCB_CLOCK_ENABLE_M2M_DMA_STATUS_SHIFT 2

/* CLKGEN :: MEM_DMA_M2M_DMA_STATUS :: M2M_DMA_216_CLOCK_ENABLE_M2M_DMA_STATUS [01:01] */
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_STATUS_M2M_DMA_216_CLOCK_ENABLE_M2M_DMA_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_STATUS_M2M_DMA_216_CLOCK_ENABLE_M2M_DMA_STATUS_SHIFT 1

/* CLKGEN :: MEM_DMA_M2M_DMA_STATUS :: M2M_DMA_108_CLOCK_ENABLE_M2M_DMA_STATUS [00:00] */
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_STATUS_M2M_DMA_108_CLOCK_ENABLE_M2M_DMA_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MEM_DMA_M2M_DMA_STATUS_M2M_DMA_108_CLOCK_ENABLE_M2M_DMA_STATUS_SHIFT 0

/***************************************************************************
 *MEM_DMA_MEMORY_STANDBY_ENABLE - Mem dma memory standby enable
 ***************************************************************************/
/* CLKGEN :: MEM_DMA_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEM_DMA_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_MEM_DMA_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1

/* CLKGEN :: MEM_DMA_MEMORY_STANDBY_ENABLE :: M2M_DMA_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_MEM_DMA_MEMORY_STANDBY_ENABLE_M2M_DMA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEM_DMA_MEMORY_STANDBY_ENABLE_M2M_DMA_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEM_DMA_MEMORY_STANDBY_ENABLE_M2M_DMA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *MEM_DMA_POWER_SWITCH_MEMORY - Mem dma power switch memory
 ***************************************************************************/
/* CLKGEN :: MEM_DMA_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_MEM_DMA_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_MEM_DMA_POWER_SWITCH_MEMORY_reserved0_SHIFT    2

/* CLKGEN :: MEM_DMA_POWER_SWITCH_MEMORY :: M2M_DMA_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_MEM_DMA_POWER_SWITCH_MEMORY_M2M_DMA_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_MEM_DMA_POWER_SWITCH_MEMORY_M2M_DMA_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_MEM_DMA_POWER_SWITCH_MEMORY_M2M_DMA_POWER_SWITCH_MEMORY_DEFAULT 0x00000000

/***************************************************************************
 *PAD_CLK_OBSRV0_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: reserved0 [31:08] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_MASK      0xffffff00
#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_reserved0_SHIFT     8

/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OBSRV0_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CLK_OBSRV0_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PAD_CLK_OBSRV1_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: reserved0 [31:08] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_MASK      0xffffff00
#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_reserved0_SHIFT     8

/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OBSRV1_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CLK_OBSRV1_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PAD_CLK_OBSRV2_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: reserved0 [31:08] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_MASK      0xffffff00
#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_reserved0_SHIFT     8

/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OBSRV2_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CLK_OBSRV2_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PAD_CLK_OBSRV3_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: reserved0 [31:08] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_MASK      0xffffff00
#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_reserved0_SHIFT     8

/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: SELECT_OBSERVE_CLK [07:07] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000080
#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 7
#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_MUX_SELECT [06:01] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x0000007e
#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0x00000000

/* CLKGEN :: PAD_CLK_OBSRV3_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CLK_OBSRV3_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *PAD_CLOCK_DISABLE - Disable PAD's clocks
 ***************************************************************************/
/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              1

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *PAD_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_reserved0_SHIFT       1

/* CLKGEN :: PAD_CLOCK_DISABLE_STATUS :: DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_STATUS_DISABLE_PAD_OUTPUT_CLK27_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *PAD_MUX_SELECT - Mux selects for Pad clocks
 ***************************************************************************/
/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:02] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffffc
#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 2

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [01:00] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x00000003
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    0
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0x00000000

/***************************************************************************
 *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2

/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST - PLL_AVD_MIPS Glitchless Clock Switching
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9

/* CLKGEN :: PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 0x0000001f

/* CLKGEN :: PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS - PLL_AVD_MIPS Glitchless Switching
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4

/* CLKGEN :: PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
#define BCHP_CLKGEN_PLL_AVD_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0

/***************************************************************************
 *PLL_AVD_MIPS_PLL_RESET_STATUS - PLL_AVD_MIPS Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS_reserved0_SHIFT  2

/* CLKGEN :: PLL_AVD_MIPS_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_AVD_MIPS_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
 ***************************************************************************/
/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1

/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0x00000000

/***************************************************************************
 *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
 ***************************************************************************/
/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:02] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffffc
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               2

/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [01:01] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000002
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              1
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0x00000000

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [00:00] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000001
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                0
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0x00000000

/***************************************************************************
 *PM_PLL_LDO_POWERUP - Power management LDO PLL
 ***************************************************************************/
/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:01] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             1

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD_MIPS [00:00] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MIPS_MASK 0x00000001
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MIPS_SHIFT 0
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MIPS_DEFAULT 0x00000001

/***************************************************************************
 *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine
 ***************************************************************************/
/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK           0xf8000000
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT          27

/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 0x00001518

/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 0x000000c8

/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK    0x00000001
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT   0
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0x00000000

/***************************************************************************
 *RFM_TOP_CLOCK_ENABLE - Rfm top clock enable
 ***************************************************************************/
/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_reserved0_SHIFT           1

/* CLKGEN :: RFM_TOP_CLOCK_ENABLE :: RFM_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_RFM_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *RFM_TOP_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: RFM_TOP_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_STATUS_reserved0_MASK     0xfffffffe
#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_STATUS_reserved0_SHIFT    1

/* CLKGEN :: RFM_TOP_CLOCK_ENABLE_STATUS :: RFM_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_RFM_TOP_CLOCK_ENABLE_STATUS_RFM_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *RFM_TOP_MEMORY_STANDBY_ENABLE - Rfm top memory standby enable
 ***************************************************************************/
/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_reserved0_SHIFT  1

/* CLKGEN :: RFM_TOP_MEMORY_STANDBY_ENABLE :: RFMA_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_RFM_TOP_MEMORY_STANDBY_ENABLE_RFMA_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *RFM_TOP_OBSERVE_CLOCK - Rfm top observe clock
 ***************************************************************************/
/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_reserved0_SHIFT          6

/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: RFM_TOP_OBSERVE_CLOCK :: RFM_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_RFM_TOP_OBSERVE_CLOCK_RFM_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *RFM_TOP_POWER_SWITCH_MEMORY - Rfm top power switch memory
 ***************************************************************************/
/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_reserved0_SHIFT    2

/* CLKGEN :: RFM_TOP_POWER_SWITCH_MEMORY :: RFM_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_RFM_TOP_POWER_SWITCH_MEMORY_RFM_POWER_SWITCH_MEMORY_DEFAULT 0x00000000

/***************************************************************************
 *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
 ***************************************************************************/
/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:05] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xffffffe0
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           5

/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [04:03] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000018
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        3
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0x00000000

/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [02:00] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x00000007
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           0
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0x00000000

/***************************************************************************
 *SPARE - Spares
 ***************************************************************************/
/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0x00000000

/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0x00000000

/***************************************************************************
 *SYS_AON_OBSERVE_CLOCK - Sys aon observe clock
 ***************************************************************************/
/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_MASK           0xffffffc0
#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_reserved0_SHIFT          6

/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SYS_AON_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SYS_AON_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SYS_CTRL_CLOCK_DISABLE - Disable SYS_CTRL's clocks
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_MASK          0xfffffffc
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_reserved0_SHIFT         2

/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [01:01] */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 1
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK  0x00000001
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SYS_CTRL_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_reserved0_SHIFT  2

/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE_STATUS :: DISABLE_SYSCTRL_UPG_CLOCK_STATUS [01:01] */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SYSCTRL_UPG_CLOCK_STATUS_SHIFT 1

/* CLKGEN :: SYS_CTRL_CLOCK_DISABLE_STATUS :: DISABLE_SC0_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_DISABLE_STATUS_DISABLE_SC0_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *SYS_CTRL_CLOCK_ENABLE - Sys ctrl clock enable
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_reserved0_SHIFT          1

/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE :: SYS_CTRL_SCB_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *SYS_CTRL_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS_reserved0_SHIFT   1

/* CLKGEN :: SYS_CTRL_CLOCK_ENABLE_STATUS :: SYS_CTRL_SCB_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS_SYS_CTRL_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_CLOCK_ENABLE_STATUS_SYS_CTRL_SCB_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *SYS_CTRL_MEMORY_STANDBY_ENABLE - Sys ctrl memory standby enable
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: SYS_CTRL_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *SYS_CTRL_OBSERVE_CLOCK - Sys ctrl observe clock
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_reserved0_SHIFT         6

/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: SYS_CTRL_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *SYS_CTRL_POWER_SWITCH_MEMORY - Sys ctrl power switch memory
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_reserved0_SHIFT   2

/* CLKGEN :: SYS_CTRL_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0x00000000

/***************************************************************************
 *TESTPORT - Special Testport Controls
 ***************************************************************************/
/* CLKGEN :: TESTPORT :: reserved0 [31:02] */
#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffffc
#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       2

/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [01:00] */
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x00000003
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0x00000000

/***************************************************************************
 *USB_CLOCK_DISABLE - Disable USB's clocks
 ***************************************************************************/
/* CLKGEN :: USB_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_USB_CLOCK_DISABLE_reserved0_SHIFT              1

/* CLKGEN :: USB_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [00:00] */
#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *USB_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: USB_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB_CLOCK_DISABLE_STATUS_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_USB_CLOCK_DISABLE_STATUS_reserved0_SHIFT       1

/* CLKGEN :: USB_CLOCK_DISABLE_STATUS :: DISABLE_USB_54_MDIO_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_USB_CLOCK_DISABLE_STATUS_DISABLE_USB_54_MDIO_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USB_CLOCK_DISABLE_STATUS_DISABLE_USB_54_MDIO_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *USB_CLOCK_ENABLE - Usb clock enable
 ***************************************************************************/
/* CLKGEN :: USB_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_MASK                0xfffffffc
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_reserved0_SHIFT               2

/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK    0x00000002
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT   1
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 0x00000001

/* CLKGEN :: USB_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK    0x00000001
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT   0
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 0x00000001

/***************************************************************************
 *USB_CLOCK_ENABLE_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: USB_CLOCK_ENABLE_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_reserved0_SHIFT        2

/* CLKGEN :: USB_CLOCK_ENABLE_STATUS :: USB0_SCB_CLOCK_ENABLE_STATUS [01:01] */
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_USB0_SCB_CLOCK_ENABLE_STATUS_SHIFT 1

/* CLKGEN :: USB_CLOCK_ENABLE_STATUS :: USB0_108_CLOCK_ENABLE_STATUS [00:00] */
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_USB0_108_CLOCK_ENABLE_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_USB_CLOCK_ENABLE_STATUS_USB0_108_CLOCK_ENABLE_STATUS_SHIFT 0

/***************************************************************************
 *USB_MEMORY_STANDBY_ENABLE - Usb memory standby enable
 ***************************************************************************/
/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_reserved0_SHIFT      1

/* CLKGEN :: USB_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USB_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0x00000000

/***************************************************************************
 *USB_OBSERVE_CLOCK - Usb observe clock
 ***************************************************************************/
/* CLKGEN :: USB_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_MASK               0xffffffc0
#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_reserved0_SHIFT              6

/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: USB_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *USB_POWER_SWITCH_MEMORY - Usb power switch memory
 ***************************************************************************/
/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_reserved0_SHIFT        2

/* CLKGEN :: USB_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_USB_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0x00000000

/***************************************************************************
 *VEC_AIO_TOP_CLOCK_DISABLE - Disable VEC_AIO_TOP's clocks
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_reserved0_SHIFT      1

/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *VEC_AIO_TOP_CLOCK_DISABLE_STATUS - Clock Disable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_CLOCK_DISABLE_STATUS :: DISABLE_VEC_DACADC_CLOCK_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_DISABLE_STATUS_DISABLE_VEC_DACADC_CLOCK_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_TOP_CLOCK_ENABLE_AIO - Vec aio top clock enable aio
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_reserved0_SHIFT   2

/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO :: AIO_SCB_CLOCK_ENABLE_AIO [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_SCB_CLOCK_ENABLE_AIO_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_SCB_CLOCK_ENABLE_AIO_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO :: AIO_108_CLOCK_ENABLE_AIO [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_AIO_108_CLOCK_ENABLE_AIO_DEFAULT 0x00000001

/***************************************************************************
 *VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS :: AIO_SCB_CLOCK_ENABLE_AIO_STATUS [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS_AIO_SCB_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS_AIO_SCB_CLOCK_ENABLE_AIO_STATUS_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS :: AIO_108_CLOCK_ENABLE_AIO_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS_AIO_108_CLOCK_ENABLE_AIO_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_AIO_STATUS_AIO_108_CLOCK_ENABLE_AIO_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_TOP_CLOCK_ENABLE_VEC - Vec aio top clock enable vec
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: reserved0 [31:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_reserved0_MASK    0xfffffff0
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_reserved0_SHIFT   4

/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [03:03] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000008
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 3
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [02:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 2
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 0x00000001

/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC :: QDAC_216_CLOCK_ENABLE_VEC [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 0x00000001

/***************************************************************************
 *VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS - Clock Enable Status
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_reserved0_SHIFT 4

/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS :: VEC_SCB_CLOCK_ENABLE_VEC_STATUS [03:03] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000008
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_VEC_SCB_CLOCK_ENABLE_VEC_STATUS_SHIFT 3

/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS :: VEC_216_CLOCK_ENABLE_VEC_STATUS [02:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_VEC_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_VEC_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS :: VEC_108_CLOCK_ENABLE_VEC_STATUS [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_VEC_108_CLOCK_ENABLE_VEC_STATUS_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS :: QDAC_216_CLOCK_ENABLE_VEC_STATUS [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_QDAC_216_CLOCK_ENABLE_VEC_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_CLOCK_ENABLE_VEC_STATUS_QDAC_216_CLOCK_ENABLE_VEC_STATUS_SHIFT 0

/***************************************************************************
 *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO - Vec aio top memory standby enable aio
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0x00000000

/***************************************************************************
 *VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC - Vec aio top memory standby enable vec
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0x00000000

/***************************************************************************
 *VEC_AIO_TOP_OBSERVE_CLOCK - Vec aio top observe clock
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_reserved0_SHIFT      2

/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: VEC_ENABLE_OBSERVE_CLOCK [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0x00000000

/***************************************************************************
 *VEC_AIO_TOP_OBSERVE_CLOCK_AIO - Vec aio top observe clock aio
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_AIO :: reserved0 [31:05] */
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_reserved0_MASK   0xffffffe0
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_reserved0_SHIFT  5

/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_AIO :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_AIO [04:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_AIO_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_AIO_SHIFT 4
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_AIO_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_AIO :: AIO_CONTROL_OBSERVE_CLOCK_AIO [03:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_AIO_CONTROL_OBSERVE_CLOCK_AIO_MASK 0x0000000f
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_AIO_CONTROL_OBSERVE_CLOCK_AIO_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_AIO_AIO_CONTROL_OBSERVE_CLOCK_AIO_DEFAULT 0x00000000

/***************************************************************************
 *VEC_AIO_TOP_OBSERVE_CLOCK_VEC - Vec aio top observe clock vec
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_VEC :: reserved0 [31:05] */
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_reserved0_MASK   0xffffffe0
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_reserved0_SHIFT  5

/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_VEC :: VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC [04:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC_SHIFT 4
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_ENABLE_DIVIDER_OBSERVE_CLOCK_VEC_DEFAULT 0x00000000

/* CLKGEN :: VEC_AIO_TOP_OBSERVE_CLOCK_VEC :: VEC_CONTROL_OBSERVE_CLOCK_VEC [03:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_CONTROL_OBSERVE_CLOCK_VEC_MASK 0x0000000f
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_CONTROL_OBSERVE_CLOCK_VEC_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_OBSERVE_CLOCK_VEC_VEC_CONTROL_OBSERVE_CLOCK_VEC_DEFAULT 0x00000000

/***************************************************************************
 *VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO - Vec aio top power switch memory aio
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003
#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0x00000000

/***************************************************************************
 *VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC - Vec aio top power switch memory vec
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003
#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0x00000000

/***************************************************************************
 *BSPI_CLOCK_SELECT - BSPI CLOCK SELECT - spi clock control
 ***************************************************************************/
/* CLKGEN :: BSPI_CLOCK_SELECT :: reserved0 [31:03] */
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_MASK               0xfffffff8
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_reserved0_SHIFT              3

/* CLKGEN :: BSPI_CLOCK_SELECT :: spi_clock_freq_sel [02:01] */
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_spi_clock_freq_sel_MASK      0x00000006
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_spi_clock_freq_sel_SHIFT     1
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_spi_clock_freq_sel_DEFAULT   0x00000000

/* CLKGEN :: BSPI_CLOCK_SELECT :: spi_clock_override_strap [00:00] */
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_spi_clock_override_strap_MASK 0x00000001
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_spi_clock_override_strap_SHIFT 0
#define BCHP_CLKGEN_BSPI_CLOCK_SELECT_spi_clock_override_strap_DEFAULT 0x00000000

#endif /* #ifndef BCHP_CLKGEN_H__ */

/* End of File */