/***************************************************************************
 *     Copyright (c) 1999-2012, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Wed Oct 17 03:11:30 2012
 *                 MD5 Checksum         d41d8cd98f00b204e9800998ecf8427e
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: $
 *
 ***************************************************************************/

#ifndef BCHP_USB1_CTRL_H__
#define BCHP_USB1_CTRL_H__

/***************************************************************************
 *USB1_CTRL - USB Control Registers
 ***************************************************************************/
#define BCHP_USB1_CTRL_SETUP                     0x00480200 /* Setup Register */
#define BCHP_USB1_CTRL_PLL_CTL                   0x00480204 /* PLL Control Register */
#define BCHP_USB1_CTRL_FLADJ_VALUE               0x00480208 /* Frame Adjust Value */
#define BCHP_USB1_CTRL_EBRIDGE                   0x0048020c /* Control Register for EHCI Bridge */
#define BCHP_USB1_CTRL_OBRIDGE                   0x00480210 /* Control Register for OHCI Bridge */
#define BCHP_USB1_CTRL_MDIO                      0x00480214 /* MDIO Interface Programming Register */
#define BCHP_USB1_CTRL_MDIO2                     0x00480218 /* MDIO Interface Read Register */
#define BCHP_USB1_CTRL_TEST_PORT_CTL             0x0048021c /* Test Port Control Register */
#define BCHP_USB1_CTRL_USB_SIMCTL                0x00480220 /* Simulation Register */
#define BCHP_USB1_CTRL_USB_TESTCTL               0x00480224 /* Throutput Test Control */
#define BCHP_USB1_CTRL_USB_TESTMON               0x00480228 /* Throughput Test Monitor */
#define BCHP_USB1_CTRL_UTMI_CTL_1                0x0048022c /* UTMI Control Register */
#define BCHP_USB1_CTRL_UTMI_CTL_2                0x00480230 /* UTMI Control 2 Register */
#define BCHP_USB1_CTRL_USB_PM                    0x00480234 /* Power Management Register */
#define BCHP_USB1_CTRL_OHCI_ADDR_EXT             0x00480238 /* OHCI ADDRESS Extension */
#define BCHP_USB1_CTRL_SPARE1                    0x0048023c /* Spare1 Register for future use */
#define BCHP_USB1_CTRL_PLL_LDO_CTL               0x00480240 /* 28NM USBPHY LDO Control */
#define BCHP_USB1_CTRL_PLL_LDO_PLLBIAS           0x00480244 /* 28NM USBPHY PLLBIAS Control */
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL           0x00480248 /* 28NM USBPHY AFE Bandgap Control */
#define BCHP_USB1_CTRL_AFE_USBIO_TST             0x0048024c /* 28NM USBPHY AFE Bandgap Control */
#define BCHP_USB1_CTRL_PLL_NDIV_FRAC             0x00480250 /* PLL Feedback Divider Control Register */
#define BCHP_USB1_CTRL_SPARE2                    0x00480254 /* Spare2 Register for future use */
#define BCHP_USB1_CTRL_SPARE3                    0x00480258 /* Spare1 Register for future use */
#define BCHP_USB1_CTRL_SPARE4                    0x0048025c /* Spare1 Register for future use */
#define BCHP_USB1_CTRL_USB30_CTL1                0x00480260 /* USB30 CONTROL Register 1 */
#define BCHP_USB1_CTRL_USB30_CTL2                0x00480264 /* USB30 CONTROL Register 2 */
#define BCHP_USB1_CTRL_USB30_CTL3                0x00480268 /* USB30 CONTROL Register 3 */
#define BCHP_USB1_CTRL_USB30_CTL4                0x0048026c /* USB30 CONTROL Register 4 */
#define BCHP_USB1_CTRL_SPARE5                    0x00480270 /* Spare1 Register for future use */
#define BCHP_USB1_CTRL_SPARE6                    0x00480274 /* Spare2 Register for future use */

/***************************************************************************
 *SETUP - Setup Register
 ***************************************************************************/
/* USB1_CTRL :: SETUP :: OC_DISABLE [31:28] */
#define BCHP_USB1_CTRL_SETUP_OC_DISABLE_MASK                       0xf0000000
#define BCHP_USB1_CTRL_SETUP_OC_DISABLE_SHIFT                      28
#define BCHP_USB1_CTRL_SETUP_OC_DISABLE_DEFAULT                    0x00000000

/* USB1_CTRL :: SETUP :: SRAM_CS_DIS [27:25] */
#define BCHP_USB1_CTRL_SETUP_SRAM_CS_DIS_MASK                      0x0e000000
#define BCHP_USB1_CTRL_SETUP_SRAM_CS_DIS_SHIFT                     25
#define BCHP_USB1_CTRL_SETUP_SRAM_CS_DIS_DEFAULT                   0x00000000

/* USB1_CTRL :: SETUP :: SETUP_SPARE [24:19] */
#define BCHP_USB1_CTRL_SETUP_SETUP_SPARE_MASK                      0x01f80000
#define BCHP_USB1_CTRL_SETUP_SETUP_SPARE_SHIFT                     19
#define BCHP_USB1_CTRL_SETUP_SETUP_SPARE_DEFAULT                   0x00000000

/* USB1_CTRL :: SETUP :: ohci_susp_lgcy [18:18] */
#define BCHP_USB1_CTRL_SETUP_ohci_susp_lgcy_MASK                   0x00040000
#define BCHP_USB1_CTRL_SETUP_ohci_susp_lgcy_SHIFT                  18
#define BCHP_USB1_CTRL_SETUP_ohci_susp_lgcy_DEFAULT                0x00000000

/* USB1_CTRL :: SETUP :: ss_ulpi_pp2vbus [17:17] */
#define BCHP_USB1_CTRL_SETUP_ss_ulpi_pp2vbus_MASK                  0x00020000
#define BCHP_USB1_CTRL_SETUP_ss_ulpi_pp2vbus_SHIFT                 17
#define BCHP_USB1_CTRL_SETUP_ss_ulpi_pp2vbus_DEFAULT               0x00000000

/* USB1_CTRL :: SETUP :: ss_ehci64bit_en [16:16] */
#define BCHP_USB1_CTRL_SETUP_ss_ehci64bit_en_MASK                  0x00010000
#define BCHP_USB1_CTRL_SETUP_ss_ehci64bit_en_SHIFT                 16
#define BCHP_USB1_CTRL_SETUP_ss_ehci64bit_en_DEFAULT               0x00000000

/* USB1_CTRL :: SETUP :: scb2_en [15:15] */
#define BCHP_USB1_CTRL_SETUP_scb2_en_MASK                          0x00008000
#define BCHP_USB1_CTRL_SETUP_scb2_en_SHIFT                         15
#define BCHP_USB1_CTRL_SETUP_scb2_en_DEFAULT                       0x00000000

/* USB1_CTRL :: SETUP :: scb1_en [14:14] */
#define BCHP_USB1_CTRL_SETUP_scb1_en_MASK                          0x00004000
#define BCHP_USB1_CTRL_SETUP_scb1_en_SHIFT                         14
#define BCHP_USB1_CTRL_SETUP_scb1_en_DEFAULT                       0x00000000

/* USB1_CTRL :: SETUP :: scb_client_swap [13:13] */
#define BCHP_USB1_CTRL_SETUP_scb_client_swap_MASK                  0x00002000
#define BCHP_USB1_CTRL_SETUP_scb_client_swap_SHIFT                 13
#define BCHP_USB1_CTRL_SETUP_scb_client_swap_DEFAULT               0x00000000

/* USB1_CTRL :: SETUP :: async_expire_dis [12:12] */
#define BCHP_USB1_CTRL_SETUP_async_expire_dis_MASK                 0x00001000
#define BCHP_USB1_CTRL_SETUP_async_expire_dis_SHIFT                12
#define BCHP_USB1_CTRL_SETUP_async_expire_dis_DEFAULT              0x00000000

/* USB1_CTRL :: SETUP :: SETUP_SPARE1 [11:10] */
#define BCHP_USB1_CTRL_SETUP_SETUP_SPARE1_MASK                     0x00000c00
#define BCHP_USB1_CTRL_SETUP_SETUP_SPARE1_SHIFT                    10
#define BCHP_USB1_CTRL_SETUP_SETUP_SPARE1_DEFAULT                  0x00000000

/* USB1_CTRL :: SETUP :: soft_shutdown [09:09] */
#define BCHP_USB1_CTRL_SETUP_soft_shutdown_MASK                    0x00000200
#define BCHP_USB1_CTRL_SETUP_soft_shutdown_SHIFT                   9
#define BCHP_USB1_CTRL_SETUP_soft_shutdown_DEFAULT                 0x00000000

/* USB1_CTRL :: SETUP :: utmi_bkward_en [08:08] */
#define BCHP_USB1_CTRL_SETUP_utmi_bkward_en_MASK                   0x00000100
#define BCHP_USB1_CTRL_SETUP_utmi_bkward_en_SHIFT                  8
#define BCHP_USB1_CTRL_SETUP_utmi_bkward_en_DEFAULT                0x00000000

/* USB1_CTRL :: SETUP :: utmi_pls_en [07:07] */
#define BCHP_USB1_CTRL_SETUP_utmi_pls_en_MASK                      0x00000080
#define BCHP_USB1_CTRL_SETUP_utmi_pls_en_SHIFT                     7
#define BCHP_USB1_CTRL_SETUP_utmi_pls_en_DEFAULT                   0x00000000

/* USB1_CTRL :: SETUP :: soft_reset [06:06] */
#define BCHP_USB1_CTRL_SETUP_soft_reset_MASK                       0x00000040
#define BCHP_USB1_CTRL_SETUP_soft_reset_SHIFT                      6
#define BCHP_USB1_CTRL_SETUP_soft_reset_DEFAULT                    0x00000000

/* USB1_CTRL :: SETUP :: IPP [05:05] */
#define BCHP_USB1_CTRL_SETUP_IPP_MASK                              0x00000020
#define BCHP_USB1_CTRL_SETUP_IPP_SHIFT                             5
#define BCHP_USB1_CTRL_SETUP_IPP_DEFAULT                           0x00000000

/* USB1_CTRL :: SETUP :: IOC [04:04] */
#define BCHP_USB1_CTRL_SETUP_IOC_MASK                              0x00000010
#define BCHP_USB1_CTRL_SETUP_IOC_SHIFT                             4
#define BCHP_USB1_CTRL_SETUP_IOC_DEFAULT                           0x00000000

/* USB1_CTRL :: SETUP :: WABO [03:03] */
#define BCHP_USB1_CTRL_SETUP_WABO_MASK                             0x00000008
#define BCHP_USB1_CTRL_SETUP_WABO_SHIFT                            3
#define BCHP_USB1_CTRL_SETUP_WABO_DEFAULT                          0x00000000

/* USB1_CTRL :: SETUP :: FNBO [02:02] */
#define BCHP_USB1_CTRL_SETUP_FNBO_MASK                             0x00000004
#define BCHP_USB1_CTRL_SETUP_FNBO_SHIFT                            2
#define BCHP_USB1_CTRL_SETUP_FNBO_DEFAULT                          0x00000000

/* USB1_CTRL :: SETUP :: FNHW [01:01] */
#define BCHP_USB1_CTRL_SETUP_FNHW_MASK                             0x00000002
#define BCHP_USB1_CTRL_SETUP_FNHW_SHIFT                            1
#define BCHP_USB1_CTRL_SETUP_FNHW_DEFAULT                          0x00000000

/* USB1_CTRL :: SETUP :: BABO [00:00] */
#define BCHP_USB1_CTRL_SETUP_BABO_MASK                             0x00000001
#define BCHP_USB1_CTRL_SETUP_BABO_SHIFT                            0
#define BCHP_USB1_CTRL_SETUP_BABO_DEFAULT                          0x00000000

/***************************************************************************
 *PLL_CTL - PLL Control Register
 ***************************************************************************/
/* USB1_CTRL :: PLL_CTL :: PLL_IDDQ_PWRDN [31:31] */
#define BCHP_USB1_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_MASK                 0x80000000
#define BCHP_USB1_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_SHIFT                31
#define BCHP_USB1_CTRL_PLL_CTL_PLL_IDDQ_PWRDN_DEFAULT              0x00000000

/* USB1_CTRL :: PLL_CTL :: PLL_RESETB [30:30] */
#define BCHP_USB1_CTRL_PLL_CTL_PLL_RESETB_MASK                     0x40000000
#define BCHP_USB1_CTRL_PLL_CTL_PLL_RESETB_SHIFT                    30
#define BCHP_USB1_CTRL_PLL_CTL_PLL_RESETB_DEFAULT                  0x00000001

/* USB1_CTRL :: PLL_CTL :: PHYPLL_BYP [29:29] */
#define BCHP_USB1_CTRL_PLL_CTL_PHYPLL_BYP_MASK                     0x20000000
#define BCHP_USB1_CTRL_PLL_CTL_PHYPLL_BYP_SHIFT                    29
#define BCHP_USB1_CTRL_PLL_CTL_PHYPLL_BYP_DEFAULT                  0x00000000

/* USB1_CTRL :: PLL_CTL :: PLL_PWRDWNB [28:28] */
#define BCHP_USB1_CTRL_PLL_CTL_PLL_PWRDWNB_MASK                    0x10000000
#define BCHP_USB1_CTRL_PLL_CTL_PLL_PWRDWNB_SHIFT                   28
#define BCHP_USB1_CTRL_PLL_CTL_PLL_PWRDWNB_DEFAULT                 0x00000001

/* USB1_CTRL :: PLL_CTL :: PLL_SUSPEND_EN [27:27] */
#define BCHP_USB1_CTRL_PLL_CTL_PLL_SUSPEND_EN_MASK                 0x08000000
#define BCHP_USB1_CTRL_PLL_CTL_PLL_SUSPEND_EN_SHIFT                27
#define BCHP_USB1_CTRL_PLL_CTL_PLL_SUSPEND_EN_DEFAULT              0x00000000

/* USB1_CTRL :: PLL_CTL :: PLL_Ka [26:24] */
#define BCHP_USB1_CTRL_PLL_CTL_PLL_Ka_MASK                         0x07000000
#define BCHP_USB1_CTRL_PLL_CTL_PLL_Ka_SHIFT                        24
#define BCHP_USB1_CTRL_PLL_CTL_PLL_Ka_DEFAULT                      0x00000003

/* USB1_CTRL :: PLL_CTL :: PLLCTL_SPARE3 [23:23] */
#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE3_MASK                  0x00800000
#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE3_SHIFT                 23
#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE3_DEFAULT               0x00000000

/* USB1_CTRL :: PLL_CTL :: PLL_Ki [22:20] */
#define BCHP_USB1_CTRL_PLL_CTL_PLL_Ki_MASK                         0x00700000
#define BCHP_USB1_CTRL_PLL_CTL_PLL_Ki_SHIFT                        20
#define BCHP_USB1_CTRL_PLL_CTL_PLL_Ki_DEFAULT                      0x00000003

/* USB1_CTRL :: PLL_CTL :: PLL_Kp [19:16] */
#define BCHP_USB1_CTRL_PLL_CTL_PLL_Kp_MASK                         0x000f0000
#define BCHP_USB1_CTRL_PLL_CTL_PLL_Kp_SHIFT                        16
#define BCHP_USB1_CTRL_PLL_CTL_PLL_Kp_DEFAULT                      0x0000000a

/* USB1_CTRL :: PLL_CTL :: PLLCTL_SPARE2 [15:15] */
#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE2_MASK                  0x00008000
#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE2_SHIFT                 15
#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE2_DEFAULT               0x00000000

/* USB1_CTRL :: PLL_CTL :: PLL_pdiv [14:12] */
#define BCHP_USB1_CTRL_PLL_CTL_PLL_pdiv_MASK                       0x00007000
#define BCHP_USB1_CTRL_PLL_CTL_PLL_pdiv_SHIFT                      12
#define BCHP_USB1_CTRL_PLL_CTL_PLL_pdiv_DEFAULT                    0x00000001

/* USB1_CTRL :: PLL_CTL :: PLLCTL_SPARE1 [11:10] */
#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE1_MASK                  0x00000c00
#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE1_SHIFT                 10
#define BCHP_USB1_CTRL_PLL_CTL_PLLCTL_SPARE1_DEFAULT               0x00000000

/* USB1_CTRL :: PLL_CTL :: PLL_ndiv [09:00] */
#define BCHP_USB1_CTRL_PLL_CTL_PLL_ndiv_MASK                       0x000003ff
#define BCHP_USB1_CTRL_PLL_CTL_PLL_ndiv_SHIFT                      0
#define BCHP_USB1_CTRL_PLL_CTL_PLL_ndiv_DEFAULT                    0x00000020

/***************************************************************************
 *FLADJ_VALUE - Frame Adjust Value
 ***************************************************************************/
/* USB1_CTRL :: FLADJ_VALUE :: FLADJ_VAL [31:00] */
#define BCHP_USB1_CTRL_FLADJ_VALUE_FLADJ_VAL_MASK                  0xffffffff
#define BCHP_USB1_CTRL_FLADJ_VALUE_FLADJ_VAL_SHIFT                 0
#define BCHP_USB1_CTRL_FLADJ_VALUE_FLADJ_VAL_DEFAULT               0x000c0020

/***************************************************************************
 *EBRIDGE - Control Register for EHCI Bridge
 ***************************************************************************/
/* USB1_CTRL :: EBRIDGE :: EBR_SOFT_RESET [31:31] */
#define BCHP_USB1_CTRL_EBRIDGE_EBR_SOFT_RESET_MASK                 0x80000000
#define BCHP_USB1_CTRL_EBRIDGE_EBR_SOFT_RESET_SHIFT                31
#define BCHP_USB1_CTRL_EBRIDGE_EBR_SOFT_RESET_DEFAULT              0x00000000

/* USB1_CTRL :: EBRIDGE :: ebrff_reset [30:30] */
#define BCHP_USB1_CTRL_EBRIDGE_ebrff_reset_MASK                    0x40000000
#define BCHP_USB1_CTRL_EBRIDGE_ebrff_reset_SHIFT                   30
#define BCHP_USB1_CTRL_EBRIDGE_ebrff_reset_DEFAULT                 0x00000000

/* USB1_CTRL :: EBRIDGE :: ebr_wrgwordcnt_sel [29:29] */
#define BCHP_USB1_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_MASK             0x20000000
#define BCHP_USB1_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_SHIFT            29
#define BCHP_USB1_CTRL_EBRIDGE_ebr_wrgwordcnt_sel_DEFAULT          0x00000000

/* USB1_CTRL :: EBRIDGE :: ebr_size_sel [28:28] */
#define BCHP_USB1_CTRL_EBRIDGE_ebr_size_sel_MASK                   0x10000000
#define BCHP_USB1_CTRL_EBRIDGE_ebr_size_sel_SHIFT                  28
#define BCHP_USB1_CTRL_EBRIDGE_ebr_size_sel_DEFAULT                0x00000000

/* USB1_CTRL :: EBRIDGE :: EBR_SPARE [27:17] */
#define BCHP_USB1_CTRL_EBRIDGE_EBR_SPARE_MASK                      0x0ffe0000
#define BCHP_USB1_CTRL_EBRIDGE_EBR_SPARE_SHIFT                     17
#define BCHP_USB1_CTRL_EBRIDGE_EBR_SPARE_DEFAULT                   0x00000000

/* USB1_CTRL :: EBRIDGE :: EBR_RD_THRESH [16:12] */
#define BCHP_USB1_CTRL_EBRIDGE_EBR_RD_THRESH_MASK                  0x0001f000
#define BCHP_USB1_CTRL_EBRIDGE_EBR_RD_THRESH_SHIFT                 12
#define BCHP_USB1_CTRL_EBRIDGE_EBR_RD_THRESH_DEFAULT               0x00000002

/* USB1_CTRL :: EBRIDGE :: EBR_SCB_SIZE [11:07] */
#define BCHP_USB1_CTRL_EBRIDGE_EBR_SCB_SIZE_MASK                   0x00000f80
#define BCHP_USB1_CTRL_EBRIDGE_EBR_SCB_SIZE_SHIFT                  7
#define BCHP_USB1_CTRL_EBRIDGE_EBR_SCB_SIZE_DEFAULT                0x00000004

/* USB1_CTRL :: EBRIDGE :: EBR_MISC [06:01] */
#define BCHP_USB1_CTRL_EBRIDGE_EBR_MISC_MASK                       0x0000007e
#define BCHP_USB1_CTRL_EBRIDGE_EBR_MISC_SHIFT                      1
#define BCHP_USB1_CTRL_EBRIDGE_EBR_MISC_DEFAULT                    0x00000000

/* USB1_CTRL :: EBRIDGE :: EBR_SEQ_EN [00:00] */
#define BCHP_USB1_CTRL_EBRIDGE_EBR_SEQ_EN_MASK                     0x00000001
#define BCHP_USB1_CTRL_EBRIDGE_EBR_SEQ_EN_SHIFT                    0
#define BCHP_USB1_CTRL_EBRIDGE_EBR_SEQ_EN_DEFAULT                  0x00000000

/***************************************************************************
 *OBRIDGE - Control Register for OHCI Bridge
 ***************************************************************************/
/* USB1_CTRL :: OBRIDGE :: OBR_SOFT_RESET [31:31] */
#define BCHP_USB1_CTRL_OBRIDGE_OBR_SOFT_RESET_MASK                 0x80000000
#define BCHP_USB1_CTRL_OBRIDGE_OBR_SOFT_RESET_SHIFT                31
#define BCHP_USB1_CTRL_OBRIDGE_OBR_SOFT_RESET_DEFAULT              0x00000000

/* USB1_CTRL :: OBRIDGE :: obrff_reset [30:30] */
#define BCHP_USB1_CTRL_OBRIDGE_obrff_reset_MASK                    0x40000000
#define BCHP_USB1_CTRL_OBRIDGE_obrff_reset_SHIFT                   30
#define BCHP_USB1_CTRL_OBRIDGE_obrff_reset_DEFAULT                 0x00000000

/* USB1_CTRL :: OBRIDGE :: obr_wrgwordcnt_sel [29:29] */
#define BCHP_USB1_CTRL_OBRIDGE_obr_wrgwordcnt_sel_MASK             0x20000000
#define BCHP_USB1_CTRL_OBRIDGE_obr_wrgwordcnt_sel_SHIFT            29
#define BCHP_USB1_CTRL_OBRIDGE_obr_wrgwordcnt_sel_DEFAULT          0x00000000

/* USB1_CTRL :: OBRIDGE :: obr_size_sel [28:28] */
#define BCHP_USB1_CTRL_OBRIDGE_obr_size_sel_MASK                   0x10000000
#define BCHP_USB1_CTRL_OBRIDGE_obr_size_sel_SHIFT                  28
#define BCHP_USB1_CTRL_OBRIDGE_obr_size_sel_DEFAULT                0x00000000

/* USB1_CTRL :: OBRIDGE :: OBR_SPARE [27:17] */
#define BCHP_USB1_CTRL_OBRIDGE_OBR_SPARE_MASK                      0x0ffe0000
#define BCHP_USB1_CTRL_OBRIDGE_OBR_SPARE_SHIFT                     17
#define BCHP_USB1_CTRL_OBRIDGE_OBR_SPARE_DEFAULT                   0x00000000

/* USB1_CTRL :: OBRIDGE :: OBR_RD_THRESH [16:12] */
#define BCHP_USB1_CTRL_OBRIDGE_OBR_RD_THRESH_MASK                  0x0001f000
#define BCHP_USB1_CTRL_OBRIDGE_OBR_RD_THRESH_SHIFT                 12
#define BCHP_USB1_CTRL_OBRIDGE_OBR_RD_THRESH_DEFAULT               0x00000002

/* USB1_CTRL :: OBRIDGE :: OBR_SCB_SIZE [11:07] */
#define BCHP_USB1_CTRL_OBRIDGE_OBR_SCB_SIZE_MASK                   0x00000f80
#define BCHP_USB1_CTRL_OBRIDGE_OBR_SCB_SIZE_SHIFT                  7
#define BCHP_USB1_CTRL_OBRIDGE_OBR_SCB_SIZE_DEFAULT                0x00000004

/* USB1_CTRL :: OBRIDGE :: OBR_MISC [06:01] */
#define BCHP_USB1_CTRL_OBRIDGE_OBR_MISC_MASK                       0x0000007e
#define BCHP_USB1_CTRL_OBRIDGE_OBR_MISC_SHIFT                      1
#define BCHP_USB1_CTRL_OBRIDGE_OBR_MISC_DEFAULT                    0x00000000

/* USB1_CTRL :: OBRIDGE :: OBR_SEQ_EN [00:00] */
#define BCHP_USB1_CTRL_OBRIDGE_OBR_SEQ_EN_MASK                     0x00000001
#define BCHP_USB1_CTRL_OBRIDGE_OBR_SEQ_EN_SHIFT                    0
#define BCHP_USB1_CTRL_OBRIDGE_OBR_SEQ_EN_DEFAULT                  0x00000000

/***************************************************************************
 *MDIO - MDIO Interface Programming Register
 ***************************************************************************/
/* USB1_CTRL :: MDIO :: MDIO_PHY_SEL [31:31] */
#define BCHP_USB1_CTRL_MDIO_MDIO_PHY_SEL_MASK                      0x80000000
#define BCHP_USB1_CTRL_MDIO_MDIO_PHY_SEL_SHIFT                     31
#define BCHP_USB1_CTRL_MDIO_MDIO_PHY_SEL_DEFAULT                   0x00000000

/* USB1_CTRL :: MDIO :: MDIO_SPARE [30:26] */
#define BCHP_USB1_CTRL_MDIO_MDIO_SPARE_MASK                        0x7c000000
#define BCHP_USB1_CTRL_MDIO_MDIO_SPARE_SHIFT                       26
#define BCHP_USB1_CTRL_MDIO_MDIO_SPARE_DEFAULT                     0x00000000

/* USB1_CTRL :: MDIO :: WR_START [25:25] */
#define BCHP_USB1_CTRL_MDIO_WR_START_MASK                          0x02000000
#define BCHP_USB1_CTRL_MDIO_WR_START_SHIFT                         25
#define BCHP_USB1_CTRL_MDIO_WR_START_DEFAULT                       0x00000000

/* USB1_CTRL :: MDIO :: RD_START [24:24] */
#define BCHP_USB1_CTRL_MDIO_RD_START_MASK                          0x01000000
#define BCHP_USB1_CTRL_MDIO_RD_START_SHIFT                         24
#define BCHP_USB1_CTRL_MDIO_RD_START_DEFAULT                       0x00000000

/* USB1_CTRL :: MDIO :: MDIO_ADDR [23:16] */
#define BCHP_USB1_CTRL_MDIO_MDIO_ADDR_MASK                         0x00ff0000
#define BCHP_USB1_CTRL_MDIO_MDIO_ADDR_SHIFT                        16
#define BCHP_USB1_CTRL_MDIO_MDIO_ADDR_DEFAULT                      0x00000000

/* USB1_CTRL :: MDIO :: MDIO_DATA [15:00] */
#define BCHP_USB1_CTRL_MDIO_MDIO_DATA_MASK                         0x0000ffff
#define BCHP_USB1_CTRL_MDIO_MDIO_DATA_SHIFT                        0
#define BCHP_USB1_CTRL_MDIO_MDIO_DATA_DEFAULT                      0x00000000

/***************************************************************************
 *MDIO2 - MDIO Interface Read Register
 ***************************************************************************/
/* USB1_CTRL :: MDIO2 :: SYNOPSIS_CORE_ID [31:16] */
#define BCHP_USB1_CTRL_MDIO2_SYNOPSIS_CORE_ID_MASK                 0xffff0000
#define BCHP_USB1_CTRL_MDIO2_SYNOPSIS_CORE_ID_SHIFT                16
#define BCHP_USB1_CTRL_MDIO2_SYNOPSIS_CORE_ID_DEFAULT              0x0000296a

/* USB1_CTRL :: MDIO2 :: MDIO_RD_DATA [15:00] */
#define BCHP_USB1_CTRL_MDIO2_MDIO_RD_DATA_MASK                     0x0000ffff
#define BCHP_USB1_CTRL_MDIO2_MDIO_RD_DATA_SHIFT                    0
#define BCHP_USB1_CTRL_MDIO2_MDIO_RD_DATA_DEFAULT                  0x00000000

/***************************************************************************
 *TEST_PORT_CTL - Test Port Control Register
 ***************************************************************************/
/* USB1_CTRL :: TEST_PORT_CTL :: TP_EN [31:31] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_TP_EN_MASK                    0x80000000
#define BCHP_USB1_CTRL_TEST_PORT_CTL_TP_EN_SHIFT                   31
#define BCHP_USB1_CTRL_TEST_PORT_CTL_TP_EN_DEFAULT                 0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: TPCTL_SPARE [30:28] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_TPCTL_SPARE_MASK              0x70000000
#define BCHP_USB1_CTRL_TEST_PORT_CTL_TPCTL_SPARE_SHIFT             28
#define BCHP_USB1_CTRL_TEST_PORT_CTL_TPCTL_SPARE_DEFAULT           0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: scb2_wr_data_sel [27:27] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_MASK         0x08000000
#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_SHIFT        27
#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb2_wr_data_sel_DEFAULT      0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: scb1_wr_data_sel [26:26] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_MASK         0x04000000
#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_SHIFT        26
#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb1_wr_data_sel_DEFAULT      0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: scb0_wr_data_sel [25:25] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_MASK         0x02000000
#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_SHIFT        25
#define BCHP_USB1_CTRL_TEST_PORT_CTL_scb0_wr_data_sel_DEFAULT      0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: testclk_sel [24:23] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_testclk_sel_MASK              0x01800000
#define BCHP_USB1_CTRL_TEST_PORT_CTL_testclk_sel_SHIFT             23
#define BCHP_USB1_CTRL_TEST_PORT_CTL_testclk_sel_DEFAULT           0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: pwrflt_testsel [22:21] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt_testsel_MASK           0x00600000
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt_testsel_SHIFT          21
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt_testsel_DEFAULT        0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: pwrflt1_oe [20:20] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt1_oe_MASK               0x00100000
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt1_oe_SHIFT              20
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt1_oe_DEFAULT            0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: pwrflt0_oe [19:19] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt0_oe_MASK               0x00080000
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt0_oe_SHIFT              19
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwrflt0_oe_DEFAULT            0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: pwron1_testsel [18:18] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwron1_testsel_MASK           0x00040000
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwron1_testsel_SHIFT          18
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwron1_testsel_DEFAULT        0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: pwron0_testsel [17:17] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwron0_testsel_MASK           0x00020000
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwron0_testsel_SHIFT          17
#define BCHP_USB1_CTRL_TEST_PORT_CTL_pwron0_testsel_DEFAULT        0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: tpin_sel [16:16] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_tpin_sel_MASK                 0x00010000
#define BCHP_USB1_CTRL_TEST_PORT_CTL_tpin_sel_SHIFT                16
#define BCHP_USB1_CTRL_TEST_PORT_CTL_tpin_sel_DEFAULT              0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: UTMI_TP_SEL [15:08] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_MASK              0x0000ff00
#define BCHP_USB1_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_SHIFT             8
#define BCHP_USB1_CTRL_TEST_PORT_CTL_UTMI_TP_SEL_DEFAULT           0x00000000

/* USB1_CTRL :: TEST_PORT_CTL :: TPOUT_SEL [07:00] */
#define BCHP_USB1_CTRL_TEST_PORT_CTL_TPOUT_SEL_MASK                0x000000ff
#define BCHP_USB1_CTRL_TEST_PORT_CTL_TPOUT_SEL_SHIFT               0
#define BCHP_USB1_CTRL_TEST_PORT_CTL_TPOUT_SEL_DEFAULT             0x00000000

/***************************************************************************
 *USB_SIMCTL - Simulation Register
 ***************************************************************************/
/* USB1_CTRL :: USB_SIMCTL :: sim_mode_en [31:31] */
#define BCHP_USB1_CTRL_USB_SIMCTL_sim_mode_en_MASK                 0x80000000
#define BCHP_USB1_CTRL_USB_SIMCTL_sim_mode_en_SHIFT                31
#define BCHP_USB1_CTRL_USB_SIMCTL_sim_mode_en_DEFAULT              0x00000000

/* USB1_CTRL :: USB_SIMCTL :: scale_down_en [30:30] */
#define BCHP_USB1_CTRL_USB_SIMCTL_scale_down_en_MASK               0x40000000
#define BCHP_USB1_CTRL_USB_SIMCTL_scale_down_en_SHIFT              30
#define BCHP_USB1_CTRL_USB_SIMCTL_scale_down_en_DEFAULT            0x00000000

/* USB1_CTRL :: USB_SIMCTL :: otg_scale_down_en [29:28] */
#define BCHP_USB1_CTRL_USB_SIMCTL_otg_scale_down_en_MASK           0x30000000
#define BCHP_USB1_CTRL_USB_SIMCTL_otg_scale_down_en_SHIFT          28
#define BCHP_USB1_CTRL_USB_SIMCTL_otg_scale_down_en_DEFAULT        0x00000000

/* USB1_CTRL :: USB_SIMCTL :: intr_test [27:27] */
#define BCHP_USB1_CTRL_USB_SIMCTL_intr_test_MASK                   0x08000000
#define BCHP_USB1_CTRL_USB_SIMCTL_intr_test_SHIFT                  27
#define BCHP_USB1_CTRL_USB_SIMCTL_intr_test_DEFAULT                0x00000000

/* USB1_CTRL :: USB_SIMCTL :: AUTOPPD_ON_OVERCUR_EN [26:26] */
#define BCHP_USB1_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_MASK       0x04000000
#define BCHP_USB1_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_SHIFT      26
#define BCHP_USB1_CTRL_USB_SIMCTL_AUTOPPD_ON_OVERCUR_EN_DEFAULT    0x00000000

/* USB1_CTRL :: USB_SIMCTL :: SIMCTL_SPARE [25:05] */
#define BCHP_USB1_CTRL_USB_SIMCTL_SIMCTL_SPARE_MASK                0x03ffffe0
#define BCHP_USB1_CTRL_USB_SIMCTL_SIMCTL_SPARE_SHIFT               5
#define BCHP_USB1_CTRL_USB_SIMCTL_SIMCTL_SPARE_DEFAULT             0x00000000

/* USB1_CTRL :: USB_SIMCTL :: rel_270a_comp [04:04] */
#define BCHP_USB1_CTRL_USB_SIMCTL_rel_270a_comp_MASK               0x00000010
#define BCHP_USB1_CTRL_USB_SIMCTL_rel_270a_comp_SHIFT              4
#define BCHP_USB1_CTRL_USB_SIMCTL_rel_270a_comp_DEFAULT            0x00000001

/* USB1_CTRL :: USB_SIMCTL :: SIMCTL_SPARE1 [03:00] */
#define BCHP_USB1_CTRL_USB_SIMCTL_SIMCTL_SPARE1_MASK               0x0000000f
#define BCHP_USB1_CTRL_USB_SIMCTL_SIMCTL_SPARE1_SHIFT              0
#define BCHP_USB1_CTRL_USB_SIMCTL_SIMCTL_SPARE1_DEFAULT            0x00000000

/***************************************************************************
 *USB_TESTCTL - Throutput Test Control
 ***************************************************************************/
/* USB1_CTRL :: USB_TESTCTL :: TESTCTL_SPARE2 [31:23] */
#define BCHP_USB1_CTRL_USB_TESTCTL_TESTCTL_SPARE2_MASK             0xff800000
#define BCHP_USB1_CTRL_USB_TESTCTL_TESTCTL_SPARE2_SHIFT            23
#define BCHP_USB1_CTRL_USB_TESTCTL_TESTCTL_SPARE2_DEFAULT          0x00000000

/* USB1_CTRL :: USB_TESTCTL :: CONTROLLER_SEL [22:21] */
#define BCHP_USB1_CTRL_USB_TESTCTL_CONTROLLER_SEL_MASK             0x00600000
#define BCHP_USB1_CTRL_USB_TESTCTL_CONTROLLER_SEL_SHIFT            21
#define BCHP_USB1_CTRL_USB_TESTCTL_CONTROLLER_SEL_DEFAULT          0x00000000

/* USB1_CTRL :: USB_TESTCTL :: DCNT_EN [20:20] */
#define BCHP_USB1_CTRL_USB_TESTCTL_DCNT_EN_MASK                    0x00100000
#define BCHP_USB1_CTRL_USB_TESTCTL_DCNT_EN_SHIFT                   20
#define BCHP_USB1_CTRL_USB_TESTCTL_DCNT_EN_DEFAULT                 0x00000000

/* USB1_CTRL :: USB_TESTCTL :: SPEED_SEL [19:19] */
#define BCHP_USB1_CTRL_USB_TESTCTL_SPEED_SEL_MASK                  0x00080000
#define BCHP_USB1_CTRL_USB_TESTCTL_SPEED_SEL_SHIFT                 19
#define BCHP_USB1_CTRL_USB_TESTCTL_SPEED_SEL_DEFAULT               0x00000000

/* USB1_CTRL :: USB_TESTCTL :: DCNT_SEL [18:16] */
#define BCHP_USB1_CTRL_USB_TESTCTL_DCNT_SEL_MASK                   0x00070000
#define BCHP_USB1_CTRL_USB_TESTCTL_DCNT_SEL_SHIFT                  16
#define BCHP_USB1_CTRL_USB_TESTCTL_DCNT_SEL_DEFAULT                0x00000000

/* USB1_CTRL :: USB_TESTCTL :: TESTCTL_SPARE1 [15:10] */
#define BCHP_USB1_CTRL_USB_TESTCTL_TESTCTL_SPARE1_MASK             0x0000fc00
#define BCHP_USB1_CTRL_USB_TESTCTL_TESTCTL_SPARE1_SHIFT            10
#define BCHP_USB1_CTRL_USB_TESTCTL_TESTCTL_SPARE1_DEFAULT          0x00000000

/* USB1_CTRL :: USB_TESTCTL :: MSEC_PRESCALER [09:00] */
#define BCHP_USB1_CTRL_USB_TESTCTL_MSEC_PRESCALER_MASK             0x000003ff
#define BCHP_USB1_CTRL_USB_TESTCTL_MSEC_PRESCALER_SHIFT            0
#define BCHP_USB1_CTRL_USB_TESTCTL_MSEC_PRESCALER_DEFAULT          0x00000000

/***************************************************************************
 *USB_TESTMON - Throughput Test Monitor
 ***************************************************************************/
/* USB1_CTRL :: USB_TESTMON :: TESTMON_STAT [31:00] */
#define BCHP_USB1_CTRL_USB_TESTMON_TESTMON_STAT_MASK               0xffffffff
#define BCHP_USB1_CTRL_USB_TESTMON_TESTMON_STAT_SHIFT              0

/***************************************************************************
 *UTMI_CTL_1 - UTMI Control Register
 ***************************************************************************/
/* USB1_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB_P1 [31:31] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_MASK             0x80000000
#define BCHP_USB1_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_SHIFT            31
#define BCHP_USB1_CTRL_UTMI_CTL_1_USB11_TX_OEB_P1_DEFAULT          0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG_P1 [30:28] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_MASK            0x70000000
#define BCHP_USB1_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_SHIFT           28
#define BCHP_USB1_CTRL_UTMI_CTL_1_SYNC_DET_LENG_P1_DEFAULT         0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: DFE_LPBACK_P1 [27:27] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_MASK               0x08000000
#define BCHP_USB1_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_SHIFT              27
#define BCHP_USB1_CTRL_UTMI_CTL_1_DFE_LPBACK_P1_DEFAULT            0x00000001

/* USB1_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE3 [26:25] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_MASK             0x06000000
#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_SHIFT            25
#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMICTL1_SPARE3_DEFAULT          0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: DISCON_PHY_P1 [24:24] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_DISCON_PHY_P1_MASK               0x01000000
#define BCHP_USB1_CTRL_UTMI_CTL_1_DISCON_PHY_P1_SHIFT              24
#define BCHP_USB1_CTRL_UTMI_CTL_1_DISCON_PHY_P1_DEFAULT            0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DM_PU_P1 [23:23] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_MASK               0x00800000
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_SHIFT              23
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PU_P1_DEFAULT            0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DP_PU_P1 [22:22] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_MASK               0x00400000
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_SHIFT              22
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PU_P1_DEFAULT            0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DM_PD_P1 [21:21] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_MASK               0x00200000
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_SHIFT              21
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PD_P1_DEFAULT            0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DP_PD_P1 [20:20] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_MASK               0x00100000
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_SHIFT              20
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PD_P1_DEFAULT            0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: PHY_MODE_P1 [19:18] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_PHY_MODE_P1_MASK                 0x000c0000
#define BCHP_USB1_CTRL_UTMI_CTL_1_PHY_MODE_P1_SHIFT                18
#define BCHP_USB1_CTRL_UTMI_CTL_1_PHY_MODE_P1_DEFAULT              0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB_P1 [17:17] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_MASK         0x00020000
#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_SHIFT        17
#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_P1_DEFAULT      0x00000001

/* USB1_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING_P1 [16:16] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_MASK          0x00010000
#define BCHP_USB1_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_SHIFT         16
#define BCHP_USB1_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_P1_DEFAULT       0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: USB11_TX_OEB [15:15] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_USB11_TX_OEB_MASK                0x00008000
#define BCHP_USB1_CTRL_UTMI_CTL_1_USB11_TX_OEB_SHIFT               15
#define BCHP_USB1_CTRL_UTMI_CTL_1_USB11_TX_OEB_DEFAULT             0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: SYNC_DET_LENG [14:12] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_SYNC_DET_LENG_MASK               0x00007000
#define BCHP_USB1_CTRL_UTMI_CTL_1_SYNC_DET_LENG_SHIFT              12
#define BCHP_USB1_CTRL_UTMI_CTL_1_SYNC_DET_LENG_DEFAULT            0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: DFE_LPBACK [11:11] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_DFE_LPBACK_MASK                  0x00000800
#define BCHP_USB1_CTRL_UTMI_CTL_1_DFE_LPBACK_SHIFT                 11
#define BCHP_USB1_CTRL_UTMI_CTL_1_DFE_LPBACK_DEFAULT               0x00000001

/* USB1_CTRL :: UTMI_CTL_1 :: UTMICTL1_SPARE1 [10:09] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_MASK             0x00000600
#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_SHIFT            9
#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMICTL1_SPARE1_DEFAULT          0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: DISCON_PHY [08:08] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_DISCON_PHY_MASK                  0x00000100
#define BCHP_USB1_CTRL_UTMI_CTL_1_DISCON_PHY_SHIFT                 8
#define BCHP_USB1_CTRL_UTMI_CTL_1_DISCON_PHY_DEFAULT               0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DM_PU [07:07] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PU_MASK                  0x00000080
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PU_SHIFT                 7
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PU_DEFAULT               0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DP_PU [06:06] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PU_MASK                  0x00000040
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PU_SHIFT                 6
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PU_DEFAULT               0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DM_PD [05:05] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PD_MASK                  0x00000020
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PD_SHIFT                 5
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DM_PD_DEFAULT               0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: BC10_DP_PD [04:04] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PD_MASK                  0x00000010
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PD_SHIFT                 4
#define BCHP_USB1_CTRL_UTMI_CTL_1_BC10_DP_PD_DEFAULT               0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: PHY_MODE [03:02] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_PHY_MODE_MASK                    0x0000000c
#define BCHP_USB1_CTRL_UTMI_CTL_1_PHY_MODE_SHIFT                   2
#define BCHP_USB1_CTRL_UTMI_CTL_1_PHY_MODE_DEFAULT                 0x00000000

/* USB1_CTRL :: UTMI_CTL_1 :: UTMI_SOFT_RESETB [01:01] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_MASK            0x00000002
#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_SHIFT           1
#define BCHP_USB1_CTRL_UTMI_CTL_1_UTMI_SOFT_RESETB_DEFAULT         0x00000001

/* USB1_CTRL :: UTMI_CTL_1 :: AFE_NON_DRIVING [00:00] */
#define BCHP_USB1_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_MASK             0x00000001
#define BCHP_USB1_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_SHIFT            0
#define BCHP_USB1_CTRL_UTMI_CTL_1_AFE_NON_DRIVING_DEFAULT          0x00000000

/***************************************************************************
 *UTMI_CTL_2 - UTMI Control 2 Register
 ***************************************************************************/
/* USB1_CTRL :: UTMI_CTL_2 :: UTMICTL2_SPARE [31:00] */
#define BCHP_USB1_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_MASK              0xffffffff
#define BCHP_USB1_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_SHIFT             0
#define BCHP_USB1_CTRL_UTMI_CTL_2_UTMICTL2_SPARE_DEFAULT           0x00000000

/***************************************************************************
 *USB_PM - Power Management Register
 ***************************************************************************/
/* USB1_CTRL :: USB_PM :: USB_PM_SPARE [31:05] */
#define BCHP_USB1_CTRL_USB_PM_USB_PM_SPARE_MASK                    0xffffffe0
#define BCHP_USB1_CTRL_USB_PM_USB_PM_SPARE_SHIFT                   5
#define BCHP_USB1_CTRL_USB_PM_USB_PM_SPARE_DEFAULT                 0x00000000

/* USB1_CTRL :: USB_PM :: xhc_pme_en [04:04] */
#define BCHP_USB1_CTRL_USB_PM_xhc_pme_en_MASK                      0x00000010
#define BCHP_USB1_CTRL_USB_PM_xhc_pme_en_SHIFT                     4
#define BCHP_USB1_CTRL_USB_PM_xhc_pme_en_DEFAULT                   0x00000000

/* USB1_CTRL :: USB_PM :: S2_discon_intr_en [03:03] */
#define BCHP_USB1_CTRL_USB_PM_S2_discon_intr_en_MASK               0x00000008
#define BCHP_USB1_CTRL_USB_PM_S2_discon_intr_en_SHIFT              3
#define BCHP_USB1_CTRL_USB_PM_S2_discon_intr_en_DEFAULT            0x00000000

/* USB1_CTRL :: USB_PM :: S0_discon_intr_en [02:02] */
#define BCHP_USB1_CTRL_USB_PM_S0_discon_intr_en_MASK               0x00000004
#define BCHP_USB1_CTRL_USB_PM_S0_discon_intr_en_SHIFT              2
#define BCHP_USB1_CTRL_USB_PM_S0_discon_intr_en_DEFAULT            0x00000000

/* USB1_CTRL :: USB_PM :: con_intr_en [01:01] */
#define BCHP_USB1_CTRL_USB_PM_con_intr_en_MASK                     0x00000002
#define BCHP_USB1_CTRL_USB_PM_con_intr_en_SHIFT                    1
#define BCHP_USB1_CTRL_USB_PM_con_intr_en_DEFAULT                  0x00000000

/* USB1_CTRL :: USB_PM :: rmtwkup_en [00:00] */
#define BCHP_USB1_CTRL_USB_PM_rmtwkup_en_MASK                      0x00000001
#define BCHP_USB1_CTRL_USB_PM_rmtwkup_en_SHIFT                     0
#define BCHP_USB1_CTRL_USB_PM_rmtwkup_en_DEFAULT                   0x00000000

/***************************************************************************
 *OHCI_ADDR_EXT - OHCI ADDRESS Extension
 ***************************************************************************/
/* USB1_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_SPARE [31:08] */
#define BCHP_USB1_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_MASK          0xffffff00
#define BCHP_USB1_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_SHIFT         8
#define BCHP_USB1_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_SPARE_DEFAULT       0x00000000

/* USB1_CTRL :: OHCI_ADDR_EXT :: OHCI_ADDR_EXT [07:00] */
#define BCHP_USB1_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_MASK            0x000000ff
#define BCHP_USB1_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_SHIFT           0
#define BCHP_USB1_CTRL_OHCI_ADDR_EXT_OHCI_ADDR_EXT_DEFAULT         0x00000000

/***************************************************************************
 *SPARE1 - Spare1 Register for future use
 ***************************************************************************/
/* USB1_CTRL :: SPARE1 :: SPARE1_BITS [31:00] */
#define BCHP_USB1_CTRL_SPARE1_SPARE1_BITS_MASK                     0xffffffff
#define BCHP_USB1_CTRL_SPARE1_SPARE1_BITS_SHIFT                    0
#define BCHP_USB1_CTRL_SPARE1_SPARE1_BITS_DEFAULT                  0x00000000

/***************************************************************************
 *PLL_LDO_CTL - 28NM USBPHY LDO Control
 ***************************************************************************/
/* USB1_CTRL :: PLL_LDO_CTL :: AFE_PLL_LDO_CNTL [31:16] */
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_MASK           0xffff0000
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_SHIFT          16
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_PLL_LDO_CNTL_DEFAULT        0x00000000

/* USB1_CTRL :: PLL_LDO_CTL :: DFE_LDO_CNTL [15:12] */
#define BCHP_USB1_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_MASK               0x0000f000
#define BCHP_USB1_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_SHIFT              12
#define BCHP_USB1_CTRL_PLL_LDO_CTL_DFE_LDO_CNTL_DEFAULT            0x00000000

/* USB1_CTRL :: PLL_LDO_CTL :: AFE_LDO_CNTL [11:08] */
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_MASK               0x00000f00
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_SHIFT              8
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_LDO_CNTL_DEFAULT            0x00000000

/* USB1_CTRL :: PLL_LDO_CTL :: AFE_LDO_SPARE [07:03] */
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_MASK              0x000000f8
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_SHIFT             3
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_LDO_SPARE_DEFAULT           0x00000000

/* USB1_CTRL :: PLL_LDO_CTL :: AFE_CORERDY_VDDC [02:02] */
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_MASK           0x00000004
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_SHIFT          2
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_CORERDY_VDDC_DEFAULT        0x00000001

/* USB1_CTRL :: PLL_LDO_CTL :: AFE_LDO_PWRDWNB [01:01] */
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_MASK            0x00000002
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_SHIFT           1
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_LDO_PWRDWNB_DEFAULT         0x00000001

/* USB1_CTRL :: PLL_LDO_CTL :: AFE_BG_PWRDWNB [00:00] */
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_MASK             0x00000001
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_SHIFT            0
#define BCHP_USB1_CTRL_PLL_LDO_CTL_AFE_BG_PWRDWNB_DEFAULT          0x00000001

/***************************************************************************
 *PLL_LDO_PLLBIAS - 28NM USBPHY PLLBIAS Control
 ***************************************************************************/
/* USB1_CTRL :: PLL_LDO_PLLBIAS :: PLLBIAS_SPARE [31:18] */
#define BCHP_USB1_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_MASK          0xfffc0000
#define BCHP_USB1_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_SHIFT         18
#define BCHP_USB1_CTRL_PLL_LDO_PLLBIAS_PLLBIAS_SPARE_DEFAULT       0x00000000

/* USB1_CTRL :: PLL_LDO_PLLBIAS :: AFE_PLLBIAS_TESTMODE [17:00] */
#define BCHP_USB1_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_MASK   0x0003ffff
#define BCHP_USB1_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_SHIFT  0
#define BCHP_USB1_CTRL_PLL_LDO_PLLBIAS_AFE_PLLBIAS_TESTMODE_DEFAULT 0x00000000

/***************************************************************************
 *PLL_AFE_BG_CNTL - 28NM USBPHY AFE Bandgap Control
 ***************************************************************************/
/* USB1_CTRL :: PLL_AFE_BG_CNTL :: PLL_AFE_BG_SPARE [31:17] */
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_MASK       0xfffe0000
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_SHIFT      17
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_PLL_AFE_BG_SPARE_DEFAULT    0x00000000

/* USB1_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_PRGM [16:12] */
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_MASK            0x0001f000
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_SHIFT           12
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_AFE_BG_PRGM_DEFAULT         0x00000000

/* USB1_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_AFE_PRGM [11:08] */
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_MASK 0x00000f00
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_SHIFT 8
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_AFE_PRGM_DEFAULT 0x00000000

/* USB1_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF0P7_DFE_PRGM [07:04] */
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_MASK 0x000000f0
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_SHIFT 4
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF0P7_DFE_PRGM_DEFAULT 0x00000000

/* USB1_CTRL :: PLL_AFE_BG_CNTL :: AFE_BG_VREF1P0_TRIM [03:00] */
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_MASK    0x0000000f
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_SHIFT   0
#define BCHP_USB1_CTRL_PLL_AFE_BG_CNTL_AFE_BG_VREF1P0_TRIM_DEFAULT 0x00000000

/***************************************************************************
 *AFE_USBIO_TST - 28NM USBPHY AFE Bandgap Control
 ***************************************************************************/
/* USB1_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_SPARE [31:16] */
#define BCHP_USB1_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_MASK      0xffff0000
#define BCHP_USB1_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_SHIFT     16
#define BCHP_USB1_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_SPARE_DEFAULT   0x00000000

/* USB1_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P2 [15:08] */
#define BCHP_USB1_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_MASK         0x0000ff00
#define BCHP_USB1_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_SHIFT        8
#define BCHP_USB1_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P2_DEFAULT      0x00000000

/* USB1_CTRL :: AFE_USBIO_TST :: AFE_USBIO_TST_P1 [07:00] */
#define BCHP_USB1_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_MASK         0x000000ff
#define BCHP_USB1_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_SHIFT        0
#define BCHP_USB1_CTRL_AFE_USBIO_TST_AFE_USBIO_TST_P1_DEFAULT      0x00000000

/***************************************************************************
 *PLL_NDIV_FRAC - PLL Feedback Divider Control Register
 ***************************************************************************/
/* USB1_CTRL :: PLL_NDIV_FRAC :: PLL_NDIV_FRAC_SPARE2 [31:20] */
#define BCHP_USB1_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_MASK     0xfff00000
#define BCHP_USB1_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_SHIFT    20
#define BCHP_USB1_CTRL_PLL_NDIV_FRAC_PLL_NDIV_FRAC_SPARE2_DEFAULT  0x00000000

/* USB1_CTRL :: PLL_NDIV_FRAC :: pll_ndiv_frac [19:00] */
#define BCHP_USB1_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_MASK            0x000fffff
#define BCHP_USB1_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_SHIFT           0
#define BCHP_USB1_CTRL_PLL_NDIV_FRAC_pll_ndiv_frac_DEFAULT         0x00000000

/***************************************************************************
 *SPARE2 - Spare2 Register for future use
 ***************************************************************************/
/* USB1_CTRL :: SPARE2 :: SPARE2_BITS [31:00] */
#define BCHP_USB1_CTRL_SPARE2_SPARE2_BITS_MASK                     0xffffffff
#define BCHP_USB1_CTRL_SPARE2_SPARE2_BITS_SHIFT                    0
#define BCHP_USB1_CTRL_SPARE2_SPARE2_BITS_DEFAULT                  0x00000000

/***************************************************************************
 *SPARE3 - Spare1 Register for future use
 ***************************************************************************/
/* USB1_CTRL :: SPARE3 :: SPARE3_BITS [31:00] */
#define BCHP_USB1_CTRL_SPARE3_SPARE3_BITS_MASK                     0xffffffff
#define BCHP_USB1_CTRL_SPARE3_SPARE3_BITS_SHIFT                    0
#define BCHP_USB1_CTRL_SPARE3_SPARE3_BITS_DEFAULT                  0x00000000

/***************************************************************************
 *SPARE4 - Spare1 Register for future use
 ***************************************************************************/
/* USB1_CTRL :: SPARE4 :: SPARE4_BITS [31:00] */
#define BCHP_USB1_CTRL_SPARE4_SPARE4_BITS_MASK                     0xffffffff
#define BCHP_USB1_CTRL_SPARE4_SPARE4_BITS_SHIFT                    0
#define BCHP_USB1_CTRL_SPARE4_SPARE4_BITS_DEFAULT                  0x00000000

/***************************************************************************
 *USB30_CTL1 - USB30 CONTROL Register 1
 ***************************************************************************/
/* USB1_CTRL :: USB30_CTL1 :: usb3_oc_dis [31:31] */
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_oc_dis_MASK                 0x80000000
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_oc_dis_SHIFT                31
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_oc_dis_DEFAULT              0x00000000

/* USB1_CTRL :: USB30_CTL1 :: usb3_ipp [30:30] */
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_ipp_MASK                    0x40000000
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_ipp_SHIFT                   30
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_ipp_DEFAULT                 0x00000000

/* USB1_CTRL :: USB30_CTL1 :: usb3_ioc [29:29] */
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_ioc_MASK                    0x20000000
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_ioc_SHIFT                   29
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_ioc_DEFAULT                 0x00000000

/* USB1_CTRL :: USB30_CTL1 :: usb3_pwron_sel [28:27] */
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_pwron_sel_MASK              0x18000000
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_pwron_sel_SHIFT             27
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_pwron_sel_DEFAULT           0x00000000

/* USB1_CTRL :: USB30_CTL1 :: usb3_pwron_force [26:26] */
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_pwron_force_MASK            0x04000000
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_pwron_force_SHIFT           26
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_pwron_force_DEFAULT         0x00000000

/* USB1_CTRL :: USB30_CTL1 :: usb3_pwron_force_val [25:25] */
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_pwron_force_val_MASK        0x02000000
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_pwron_force_val_SHIFT       25
#define BCHP_USB1_CTRL_USB30_CTL1_usb3_pwron_force_val_DEFAULT     0x00000000

/* USB1_CTRL :: USB30_CTL1 :: usb30_ctl1_spare2 [24:19] */
#define BCHP_USB1_CTRL_USB30_CTL1_usb30_ctl1_spare2_MASK           0x01f80000
#define BCHP_USB1_CTRL_USB30_CTL1_usb30_ctl1_spare2_SHIFT          19
#define BCHP_USB1_CTRL_USB30_CTL1_usb30_ctl1_spare2_DEFAULT        0x00000000

/* USB1_CTRL :: USB30_CTL1 :: aux_resetb [18:18] */
#define BCHP_USB1_CTRL_USB30_CTL1_aux_resetb_MASK                  0x00040000
#define BCHP_USB1_CTRL_USB30_CTL1_aux_resetb_SHIFT                 18
#define BCHP_USB1_CTRL_USB30_CTL1_aux_resetb_DEFAULT               0x00000000

/* USB1_CTRL :: USB30_CTL1 :: xhc_soft_resetb [17:17] */
#define BCHP_USB1_CTRL_USB30_CTL1_xhc_soft_resetb_MASK             0x00020000
#define BCHP_USB1_CTRL_USB30_CTL1_xhc_soft_resetb_SHIFT            17
#define BCHP_USB1_CTRL_USB30_CTL1_xhc_soft_resetb_DEFAULT          0x00000000

/* USB1_CTRL :: USB30_CTL1 :: phy3_resetb [16:16] */
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_resetb_MASK                 0x00010000
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_resetb_SHIFT                16
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_resetb_DEFAULT              0x00000001

/* USB1_CTRL :: USB30_CTL1 :: usb30_ctl1_spare1 [15:07] */
#define BCHP_USB1_CTRL_USB30_CTL1_usb30_ctl1_spare1_MASK           0x0000ff80
#define BCHP_USB1_CTRL_USB30_CTL1_usb30_ctl1_spare1_SHIFT          7
#define BCHP_USB1_CTRL_USB30_CTL1_usb30_ctl1_spare1_DEFAULT        0x00000000

/* USB1_CTRL :: USB30_CTL1 :: phy3_standalonemode [06:06] */
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_standalonemode_MASK         0x00000040
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_standalonemode_SHIFT        6
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_standalonemode_DEFAULT      0x00000000

/* USB1_CTRL :: USB30_CTL1 :: phy3_phy_iso [05:05] */
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_phy_iso_MASK                0x00000020
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_phy_iso_SHIFT               5
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_phy_iso_DEFAULT             0x00000000

/* USB1_CTRL :: USB30_CTL1 :: phy3_pll_seq_start [04:04] */
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_pll_seq_start_MASK          0x00000010
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_pll_seq_start_SHIFT         4
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_pll_seq_start_DEFAULT       0x00000000

/* USB1_CTRL :: USB30_CTL1 :: phy3_pll_refclk_sel [03:01] */
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_pll_refclk_sel_MASK         0x0000000e
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_pll_refclk_sel_SHIFT        1
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_pll_refclk_sel_DEFAULT      0x00000000

/* USB1_CTRL :: USB30_CTL1 :: phy3_pll_auxclk_sel [00:00] */
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_MASK         0x00000001
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_SHIFT        0
#define BCHP_USB1_CTRL_USB30_CTL1_phy3_pll_auxclk_sel_DEFAULT      0x00000000

/***************************************************************************
 *USB30_CTL2 - USB30 CONTROL Register 2
 ***************************************************************************/
/* USB1_CTRL :: USB30_CTL2 :: usb30_ctl2_spare2 [31:30] */
#define BCHP_USB1_CTRL_USB30_CTL2_usb30_ctl2_spare2_MASK           0xc0000000
#define BCHP_USB1_CTRL_USB30_CTL2_usb30_ctl2_spare2_SHIFT          30
#define BCHP_USB1_CTRL_USB30_CTL2_usb30_ctl2_spare2_DEFAULT        0x00000000

/* USB1_CTRL :: USB30_CTL2 :: xhci_max_scb_size [29:24] */
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_max_scb_size_MASK           0x3f000000
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_max_scb_size_SHIFT          24
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_max_scb_size_DEFAULT        0x00000020

/* USB1_CTRL :: USB30_CTL2 :: xhci_wrfifo_thrshld [23:16] */
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_MASK         0x00ff0000
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_SHIFT        16
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_wrfifo_thrshld_DEFAULT      0x00000000

/* USB1_CTRL :: USB30_CTL2 :: xhci_rdfifo_thrshld [15:08] */
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_MASK         0x0000ff00
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_SHIFT        8
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_rdfifo_thrshld_DEFAULT      0x00000000

/* USB1_CTRL :: USB30_CTL2 :: usb30_ctl2_spare1 [07:03] */
#define BCHP_USB1_CTRL_USB30_CTL2_usb30_ctl2_spare1_MASK           0x000000f8
#define BCHP_USB1_CTRL_USB30_CTL2_usb30_ctl2_spare1_SHIFT          3
#define BCHP_USB1_CTRL_USB30_CTL2_usb30_ctl2_spare1_DEFAULT        0x00000000

/* USB1_CTRL :: USB30_CTL2 :: xhci_cntl_client_en [02:02] */
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_cntl_client_en_MASK         0x00000004
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_cntl_client_en_SHIFT        2
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_cntl_client_en_DEFAULT      0x00000001

/* USB1_CTRL :: USB30_CTL2 :: xhci_swap_mode [01:00] */
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_swap_mode_MASK              0x00000003
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_swap_mode_SHIFT             0
#define BCHP_USB1_CTRL_USB30_CTL2_xhci_swap_mode_DEFAULT           0x00000000

/***************************************************************************
 *USB30_CTL3 - USB30 CONTROL Register 3
 ***************************************************************************/
/* USB1_CTRL :: USB30_CTL3 :: usb30_ctl3_spare2 [31:30] */
#define BCHP_USB1_CTRL_USB30_CTL3_usb30_ctl3_spare2_MASK           0xc0000000
#define BCHP_USB1_CTRL_USB30_CTL3_usb30_ctl3_spare2_SHIFT          30
#define BCHP_USB1_CTRL_USB30_CTL3_usb30_ctl3_spare2_DEFAULT        0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en_p1 [29:29] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_MASK    0x20000000
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_SHIFT   29
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_p1_DEFAULT 0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_p1 [28:24] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_MASK       0x1f000000
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_SHIFT      24
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txdeemph_p1_DEFAULT    0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_p1 [23:20] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_MASK       0x00f00000
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_SHIFT      20
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txmargin_p1_DEFAULT    0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_rxebufmode_p1 [19:19] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_rxebufmode_p1_MASK          0x00080000
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_rxebufmode_p1_SHIFT         19
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_rxebufmode_p1_DEFAULT       0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en_p1 [18:18] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_MASK    0x00040000
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_SHIFT   18
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_p1_DEFAULT 0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_pipe_txswing_p1 [17:17] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_MASK        0x00020000
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_SHIFT       17
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txswing_p1_DEFAULT     0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_mode_p1 [16:16] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_mode_p1_MASK                0x00010000
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_mode_p1_SHIFT               16
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_mode_p1_DEFAULT             0x00000001

/* USB1_CTRL :: USB30_CTL3 :: usb30_ctl3_spare1 [15:14] */
#define BCHP_USB1_CTRL_USB30_CTL3_usb30_ctl3_spare1_MASK           0x0000c000
#define BCHP_USB1_CTRL_USB30_CTL3_usb30_ctl3_spare1_SHIFT          14
#define BCHP_USB1_CTRL_USB30_CTL3_usb30_ctl3_spare1_DEFAULT        0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph_en [13:13] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_MASK       0x00002000
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_SHIFT      13
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txdeemph_en_DEFAULT    0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_pipe_txdeemph [12:08] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txdeemph_MASK          0x00001f00
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txdeemph_SHIFT         8
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txdeemph_DEFAULT       0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin [07:04] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txmargin_MASK          0x000000f0
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txmargin_SHIFT         4
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txmargin_DEFAULT       0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_rxebufmode [03:03] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_rxebufmode_MASK             0x00000008
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_rxebufmode_SHIFT            3
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_rxebufmode_DEFAULT          0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_pipe_txmargin_en [02:02] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_MASK       0x00000004
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_SHIFT      2
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txmargin_en_DEFAULT    0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_pipe_txswing [01:01] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txswing_MASK           0x00000002
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txswing_SHIFT          1
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_pipe_txswing_DEFAULT        0x00000000

/* USB1_CTRL :: USB30_CTL3 :: phy3_mode [00:00] */
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_mode_MASK                   0x00000001
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_mode_SHIFT                  0
#define BCHP_USB1_CTRL_USB30_CTL3_phy3_mode_DEFAULT                0x00000001

/***************************************************************************
 *USB30_CTL4 - USB30 CONTROL Register 4
 ***************************************************************************/
/* USB1_CTRL :: USB30_CTL4 :: usb30_ctl4_spare1 [31:24] */
#define BCHP_USB1_CTRL_USB30_CTL4_usb30_ctl4_spare1_MASK           0xff000000
#define BCHP_USB1_CTRL_USB30_CTL4_usb30_ctl4_spare1_SHIFT          24
#define BCHP_USB1_CTRL_USB30_CTL4_usb30_ctl4_spare1_DEFAULT        0x00000000

/* USB1_CTRL :: USB30_CTL4 :: phy3_tpout_sel [23:16] */
#define BCHP_USB1_CTRL_USB30_CTL4_phy3_tpout_sel_MASK              0x00ff0000
#define BCHP_USB1_CTRL_USB30_CTL4_phy3_tpout_sel_SHIFT             16
#define BCHP_USB1_CTRL_USB30_CTL4_phy3_tpout_sel_DEFAULT           0x00000000

/* USB1_CTRL :: USB30_CTL4 :: xhci_tpout_sel [15:00] */
#define BCHP_USB1_CTRL_USB30_CTL4_xhci_tpout_sel_MASK              0x0000ffff
#define BCHP_USB1_CTRL_USB30_CTL4_xhci_tpout_sel_SHIFT             0
#define BCHP_USB1_CTRL_USB30_CTL4_xhci_tpout_sel_DEFAULT           0x00000000

/***************************************************************************
 *SPARE5 - Spare1 Register for future use
 ***************************************************************************/
/* USB1_CTRL :: SPARE5 :: SPARE5_BITS [31:00] */
#define BCHP_USB1_CTRL_SPARE5_SPARE5_BITS_MASK                     0xffffffff
#define BCHP_USB1_CTRL_SPARE5_SPARE5_BITS_SHIFT                    0
#define BCHP_USB1_CTRL_SPARE5_SPARE5_BITS_DEFAULT                  0x00000000

/***************************************************************************
 *SPARE6 - Spare2 Register for future use
 ***************************************************************************/
/* USB1_CTRL :: SPARE6 :: SPARE6_BITS [31:00] */
#define BCHP_USB1_CTRL_SPARE6_SPARE6_BITS_MASK                     0xffffffff
#define BCHP_USB1_CTRL_SPARE6_SPARE6_BITS_SHIFT                    0
#define BCHP_USB1_CTRL_SPARE6_SPARE6_BITS_DEFAULT                  0x00000000

#endif /* #ifndef BCHP_USB1_CTRL_H__ */

/* End of File */