| /*************************************************************************** |
| * Copyright (c) 1999-2012, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Wed Oct 17 03:11:31 2012 |
| * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_DDR34_PHY_BYTE_LANE_0_0_H__ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_H__ |
| |
| /*************************************************************************** |
| *DDR34_PHY_BYTE_LANE_0_0 - DDR34 DDR34 Byte Lane #0 control registers 0 |
| ***************************************************************************/ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P 0x003b6400 /* Write channel DQS-P VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N 0x003b6404 /* Write channel DQS-N VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0 0x003b6408 /* Write channel DQ0 VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1 0x003b640c /* Write channel DQ1 VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2 0x003b6410 /* Write channel DQ2 VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3 0x003b6414 /* Write channel DQ3 VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4 0x003b6418 /* Write channel DQ4 VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5 0x003b641c /* Write channel DQ5 VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6 0x003b6420 /* Write channel DQ6 VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7 0x003b6424 /* Write channel DQ7 VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM 0x003b6428 /* Write channel DM VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC 0x003b642c /* Write channel EDC VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP 0x003b6430 /* Read channel DQSP VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN 0x003b6434 /* Read channel DQSP VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P 0x003b6438 /* Read channel DQ0-P VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N 0x003b643c /* Read channel DQ0-N VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P 0x003b6440 /* Read channel DQ1-P VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N 0x003b6444 /* Read channel DQ1-N VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P 0x003b6448 /* Read channel DQ2-P VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N 0x003b644c /* Read channel DQ2-N VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P 0x003b6450 /* Read channel DQ3-P VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N 0x003b6454 /* Read channel DQ3-N VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P 0x003b6458 /* Read channel DQ4-P VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N 0x003b645c /* Read channel DQ4-N VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P 0x003b6460 /* Read channel DQ5-P VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N 0x003b6464 /* Read channel DQ5-N VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P 0x003b6468 /* Read channel DQ6-P VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N 0x003b646c /* Read channel DQ6-N VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P 0x003b6470 /* Read channel DQ7-P VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N 0x003b6474 /* Read channel DQ7-N VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP 0x003b6478 /* Read channel DM-P VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN 0x003b647c /* Read channel DM-N VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP 0x003b6480 /* Read channel EDC-P VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN 0x003b6484 /* Read channel EDC-N VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0 0x003b6488 /* Read channel CS_N[0] read enable VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1 0x003b648c /* Read channel CS_N[1] read enable VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL 0x003b6490 /* Write leveling VDL control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC 0x003b64a0 /* Read enable bit-clock cycle delay control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC 0x003b64a4 /* Write leveling bit-clock cycle delay control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL 0x003b64b0 /* Read channel datapath control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR 0x003b64b4 /* Read fifo addresss pointer register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA 0x003b64b8 /* Read fifo data register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI 0x003b64bc /* Read fifo dm/dbi register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS 0x003b64c0 /* Read fifo status register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR 0x003b64c4 /* Read fifo status clear register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL 0x003b64c8 /* Idle mode SSTL pad control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL 0x003b64cc /* SSTL pad drive characteristics control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL 0x003b64d0 /* SSTL read enable pad drive characteristics control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL 0x003b64d4 /* pad rx and tx characteristics control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE 0x003b64d8 /* Write cycle preamble control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL 0x003b64e0 /* Read channel ODT control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL 0x003b64f0 /* GDDR5M EDC digital phase detector control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS 0x003b64f4 /* GDDR5M EDC digital phase detector status register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL 0x003b64f8 /* GDDR5M EDC digital phase detector output signal control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS 0x003b64fc /* GDDR5M EDC digital phase detector output signal status register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR 0x003b6500 /* GDDR5M EDC digital phase detector output signal status clear register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL 0x003b6504 /* GDDR5M EDC signal path CRC control register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS 0x003b6508 /* GDDR5M EDC signal path CRC status register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT 0x003b650c /* GDDR5M EDC signal path CRC counter register */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR 0x003b6510 /* GDDR5M EDC signal path CRC counter register */ |
| |
| /*************************************************************************** |
| *VDL_CONTROL_WR_DQS_P - Write channel DQS-P VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_P :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_P_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_WR_DQS_N - Write channel DQS-N VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQS_N :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQS_N_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_WR_DQ0 - Write channel DQ0 VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ0 :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ0_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_WR_DQ1 - Write channel DQ1 VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ1 :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ1_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_WR_DQ2 - Write channel DQ2 VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ2 :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ2_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_WR_DQ3 - Write channel DQ3 VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ3 :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ3_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_WR_DQ4 - Write channel DQ4 VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ4 :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ4_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_WR_DQ5 - Write channel DQ5 VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ5 :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ5_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_WR_DQ6 - Write channel DQ6 VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ6 :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ6_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_WR_DQ7 - Write channel DQ7 VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DQ7 :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DQ7_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_WR_DM - Write channel DM VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_DM :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_DM_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_WR_EDC - Write channel EDC VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_WR_EDC :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_WR_EDC_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQSP - Read channel DQSP VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSP :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSP_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQSN - Read channel DQSP VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQSN :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQSN_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ0P - Read channel DQ0-P VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0P :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0P_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ0N - Read channel DQ0-N VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ0N :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ0N_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ1P - Read channel DQ1-P VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1P :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1P_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ1N - Read channel DQ1-N VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ1N :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ1N_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ2P - Read channel DQ2-P VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2P :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2P_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ2N - Read channel DQ2-N VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ2N :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ2N_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ3P - Read channel DQ3-P VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3P :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3P_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ3N - Read channel DQ3-N VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ3N :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ3N_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ4P - Read channel DQ4-P VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4P :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4P_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ4N - Read channel DQ4-N VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ4N :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ4N_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ5P - Read channel DQ5-P VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5P :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5P_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ5N - Read channel DQ5-N VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ5N :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ5N_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ6P - Read channel DQ6-P VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6P :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6P_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ6N - Read channel DQ6-N VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ6N :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ6N_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ7P - Read channel DQ7-P VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7P :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7P_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DQ7N - Read channel DQ7-N VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DQ7N :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DQ7N_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DMP - Read channel DM-P VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMP :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMP_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_DMN - Read channel DM-N VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_DMN :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_DMN_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_EDCP - Read channel EDC-P VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCP :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCP_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_EDCN - Read channel EDC-N VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EDCN :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EDCN_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_EN_CS0 - Read channel CS_N[0] read enable VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS0 :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS0_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CONTROL_RD_EN_CS1 - Read channel CS_N[1] read enable VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: reserved2 [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved2_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_reserved2_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CONTROL_RD_EN_CS1 :: VDL_STEP [07:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_MASK 0x000000ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CONTROL_RD_EN_CS1_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VDL_CLK_CONTROL - Write leveling VDL control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: ADJ_EN [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: reserved2 [11:09] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved2_MASK 0x00000e00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_reserved2_SHIFT 9 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: VDL_CLK_CONTROL :: VDL_STEP [08:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_MASK 0x000001ff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_VDL_CLK_CONTROL_VDL_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RD_EN_DLY_CYC - Read enable bit-clock cycle delay control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: reserved1 [15:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved1_MASK 0x0000ff00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_reserved1_SHIFT 8 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: CS1_CYCLES [07:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_MASK 0x000000f0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_SHIFT 4 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS1_CYCLES_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DLY_CYC :: CS0_CYCLES [03:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_MASK 0x0000000f |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DLY_CYC_CS0_CYCLES_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WR_CHAN_DLY_CYC - Write leveling bit-clock cycle delay control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: reserved1 [15:03] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved1_MASK 0x0000fff8 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_reserved1_SHIFT 3 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: WR_CHAN_DLY_CYC :: CYCLES [02:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_MASK 0x00000007 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_CHAN_DLY_CYC_CYCLES_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *READ_CONTROL - Read channel datapath control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: reserved0 [31:05] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved0_MASK 0xffffffe0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved0_SHIFT 5 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: MODE [04:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_MASK 0x00000010 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_SHIFT 4 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_MODE_DEFAULT 0x00000001 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: reserved1 [03:03] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved1_MASK 0x00000008 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_reserved1_SHIFT 3 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_CONTROL :: RD_DATA_DLY [02:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_MASK 0x00000007 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_CONTROL_RD_DATA_DLY_DEFAULT 0x00000007 |
| |
| /*************************************************************************** |
| *READ_FIFO_ADDR - Read fifo addresss pointer register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_ADDR :: reserved0 [31:03] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_reserved0_MASK 0xfffffff8 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_reserved0_SHIFT 3 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_ADDR :: ADDR [02:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_MASK 0x00000007 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_ADDR_ADDR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *READ_FIFO_DATA - Read fifo data register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DATA :: DATA [31:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA_DATA_MASK 0xffffffff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DATA_DATA_SHIFT 0 |
| |
| /*************************************************************************** |
| *READ_FIFO_DM_DBI - Read fifo dm/dbi register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DM_DBI :: reserved0 [31:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_reserved0_MASK 0xfffffff0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_reserved0_SHIFT 4 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_DM_DBI :: DM_DBI [03:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_DM_DBI_MASK 0x0000000f |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_DM_DBI_DM_DBI_SHIFT 0 |
| |
| /*************************************************************************** |
| *READ_FIFO_STATUS - Read fifo status register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: reserved0 [31:02] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_reserved0_SHIFT 2 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: OVERFLOW [01:01] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_MASK 0x00000002 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_SHIFT 1 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_OVERFLOW_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_STATUS :: UNDERFLOW [00:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_MASK 0x00000001 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_STATUS_UNDERFLOW_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *READ_FIFO_CLEAR - Read fifo status clear register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_reserved0_SHIFT 1 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: READ_FIFO_CLEAR :: CLEAR [00:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_MASK 0x00000001 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_READ_FIFO_CLEAR_CLEAR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IDLE_PAD_CONTROL - Idle mode SSTL pad control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IDLE [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDLE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_RXENB_MODE [19:18] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_MASK 0x000c0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_SHIFT 18 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_RXENB_MODE_DEFAULT 0x00000001 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: AUTO_DQ_IDDQ_MODE [17:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_MASK 0x00030000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_AUTO_DQ_IDDQ_MODE_DEFAULT 0x00000001 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: reserved1 [15:15] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved1_MASK 0x00008000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_reserved1_SHIFT 15 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IO_IDLE_ENABLE [14:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_MASK 0x00007ff0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_SHIFT 4 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IO_IDLE_ENABLE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: RXENB [03:03] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_MASK 0x00000008 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_SHIFT 3 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_RXENB_DEFAULT 0x00000001 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: IDDQ [02:02] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_MASK 0x00000004 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_SHIFT 2 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_IDDQ_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: DOUT_N [01:01] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_MASK 0x00000002 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_SHIFT 1 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_N_DEFAULT 0x00000001 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: IDLE_PAD_CONTROL :: DOUT_P [00:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_MASK 0x00000001 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_IDLE_PAD_CONTROL_DOUT_P_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DRIVE_PAD_CTL - SSTL pad drive characteristics control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved0 [31:29] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved0_MASK 0xe0000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved0_SHIFT 29 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_IDLE_STRENGTH [28:25] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_MASK 0x1e000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_SHIFT 25 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_IDLE_STRENGTH_DEFAULT 0x0000000f |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved1 [24:24] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved1_MASK 0x01000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved1_SHIFT 24 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_IDLE_STRENGTH [23:20] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_MASK 0x00f00000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_SHIFT 20 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_IDLE_STRENGTH_DEFAULT 0x0000000f |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved2 [19:19] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved2_MASK 0x00080000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved2_SHIFT 19 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_TERM_STRENGTH [18:15] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_MASK 0x00078000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_SHIFT 15 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_TERM_STRENGTH_DEFAULT 0x00000004 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved3 [14:14] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved3_MASK 0x00004000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved3_SHIFT 14 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_TERM_STRENGTH [13:10] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_MASK 0x00003c00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_SHIFT 10 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_TERM_STRENGTH_DEFAULT 0x00000004 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved4 [09:09] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved4_MASK 0x00000200 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved4_SHIFT 9 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_PD_STRENGTH [08:05] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_MASK 0x000001e0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_SHIFT 5 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_PD_STRENGTH_DEFAULT 0x0000000f |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: reserved5 [04:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved5_MASK 0x00000010 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_reserved5_SHIFT 4 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: DRIVE_PAD_CTL :: BL_ND_STRENGTH [03:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_MASK 0x0000000f |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_DRIVE_PAD_CTL_BL_ND_STRENGTH_DEFAULT 0x0000000f |
| |
| /*************************************************************************** |
| *RD_EN_DRIVE_PAD_CTL - SSTL read enable pad drive characteristics control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: reserved0 [31:19] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved0_MASK 0xfff80000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved0_SHIFT 19 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_PD_STRENGTH [18:15] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_MASK 0x00078000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_SHIFT 15 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: reserved1 [14:14] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved1_MASK 0x00004000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved1_SHIFT 14 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: EDC_RD_EN_ND_STRENGTH [13:10] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_MASK 0x00003c00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_SHIFT 10 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_EDC_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: reserved2 [09:09] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved2_MASK 0x00000200 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved2_SHIFT 9 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_PD_STRENGTH [08:05] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_MASK 0x000001e0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_SHIFT 5 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_PD_STRENGTH_DEFAULT 0x0000000f |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: reserved3 [04:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved3_MASK 0x00000010 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_reserved3_SHIFT 4 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: RD_EN_DRIVE_PAD_CTL :: BL_RD_EN_ND_STRENGTH [03:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_MASK 0x0000000f |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_RD_EN_DRIVE_PAD_CTL_BL_RD_EN_ND_STRENGTH_DEFAULT 0x0000000f |
| |
| /*************************************************************************** |
| *STATIC_PAD_CTL - pad rx and tx characteristics control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved0 [31:21] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved0_MASK 0xffe00000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved0_SHIFT 21 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_MODE [20:20] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_MASK 0x00100000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_SHIFT 20 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_MODE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved1 [19:18] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved1_MASK 0x000c0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved1_SHIFT 18 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: EDC_MODE [17:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_MASK 0x00030000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_EDC_MODE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved2 [15:15] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved2_MASK 0x00008000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved2_SHIFT 15 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: WDBI_ENABLE [14:14] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_MASK 0x00004000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_SHIFT 14 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_WDBI_ENABLE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: RDBI_ENABLE [13:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_MASK 0x00002000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_SHIFT 13 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RDBI_ENABLE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DM_MODE [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DM_MODE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved3 [11:10] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved3_MASK 0x00000c00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved3_SHIFT 10 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: DQS_TX_DIS [09:09] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_MASK 0x00000200 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_SHIFT 9 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_DQS_TX_DIS_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: RX_LS [08:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_LS_MASK 0x00000100 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_LS_SHIFT 8 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_LS_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: TX_MODE [07:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_MASK 0x000000f0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_SHIFT 4 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_TX_MODE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: reserved4 [03:03] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved4_MASK 0x00000008 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_reserved4_SHIFT 3 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: STATIC_PAD_CTL :: RX_MODE [02:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_MASK 0x00000007 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_STATIC_PAD_CTL_RX_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *WR_PREAMBLE_MODE - Write cycle preamble control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved0 [31:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved0_MASK 0xffff0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved0_SHIFT 16 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQ_POSTAM_BITS [15:14] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_MASK 0x0000c000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_SHIFT 14 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_POSTAM_BITS_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQ_PREAM_BITS [13:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_MASK 0x00003000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQ_PREAM_BITS_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS [11:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_MASK 0x00000f00 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_SHIFT 8 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_DEFAULT 0x0000000e |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: reserved1 [07:05] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved1_MASK 0x000000e0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_reserved1_SHIFT 5 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS_POSTAM_BITS [04:03] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_MASK 0x00000018 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_SHIFT 3 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_POSTAM_BITS_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: WR_PREAMBLE_MODE :: DQS_PREAM_BITS [02:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_MASK 0x00000007 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_WR_PREAMBLE_MODE_DQS_PREAM_BITS_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *ODT_CONTROL - Read channel ODT control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: reserved0 [31:07] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved0_MASK 0xffffff80 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_reserved0_SHIFT 7 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_ENABLE [06:06] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_MASK 0x00000040 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_SHIFT 6 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_ENABLE_DEFAULT 0x00000001 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_POST_LENGTH [05:03] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_MASK 0x00000038 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_SHIFT 3 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_POST_LENGTH_DEFAULT 0x00000001 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: ODT_CONTROL :: ODT_PRE_LENGTH [02:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_MASK 0x00000007 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_ODT_CONTROL_ODT_PRE_LENGTH_DEFAULT 0x00000003 |
| |
| /*************************************************************************** |
| *EDC_DPD_CONTROL - GDDR5M EDC digital phase detector control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: reserved0 [31:06] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved0_MASK 0xffffffc0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_reserved0_SHIFT 6 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_VALUE [05:05] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_MASK 0x00000020 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_SHIFT 5 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_VALUE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: DQS_PHASE_OVERRIDE_ENABLE [04:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_MASK 0x00000010 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_SHIFT 4 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_DQS_PHASE_OVERRIDE_ENABLE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: SET_ADJ_EN [03:03] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_MASK 0x00000008 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_SHIFT 3 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_SET_ADJ_EN_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: UPDATE [02:02] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_MASK 0x00000004 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_SHIFT 2 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_UPDATE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: MONITOR [01:01] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_MASK 0x00000002 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_SHIFT 1 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_MONITOR_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_CONTROL :: INIT [00:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_MASK 0x00000001 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_CONTROL_INIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EDC_DPD_STATUS - GDDR5M EDC digital phase detector status register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: reserved0 [31:25] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved0_MASK 0xfe000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved0_SHIFT 25 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: CURRENT_DQS_PHASE [24:24] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_MASK 0x01000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_SHIFT 24 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_DQS_PHASE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: CURRENT_VDL_SETTING [23:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_MASK 0x00ff0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_CURRENT_VDL_SETTING_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: reserved1 [15:13] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved1_MASK 0x0000e000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_reserved1_SHIFT 13 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_DQS_PHASE [12:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_MASK 0x00001000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DQS_PHASE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_VDL_SETTING [11:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_MASK 0x00000ff0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_SHIFT 4 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_VDL_SETTING_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: EDGE_ERROR [03:03] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_EDGE_ERROR_MASK 0x00000008 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_EDGE_ERROR_SHIFT 3 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_EDGE_ERROR_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: MONITOR_BUSY [02:02] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_MASK 0x00000004 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_SHIFT 2 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_MONITOR_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_BUSY [01:01] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_MASK 0x00000002 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_SHIFT 1 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_STATUS :: INIT_DONE [00:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_MASK 0x00000001 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_STATUS_INIT_DONE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EDC_DPD_OUT_CONTROL - GDDR5M EDC digital phase detector output signal control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: reserved0 [31:20] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved0_MASK 0xfff00000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved0_SHIFT 20 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: LOWER_LIMIT [19:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_MASK 0x000ff000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_SHIFT 12 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_LOWER_LIMIT_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: UPPER_LIMIT [11:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_MASK 0x00000ff0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_SHIFT 4 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_UPPER_LIMIT_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: reserved1 [03:01] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved1_MASK 0x0000000e |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_reserved1_SHIFT 1 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_CONTROL :: ENABLE [00:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_MASK 0x00000001 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_CONTROL_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EDC_DPD_OUT_STATUS - GDDR5M EDC digital phase detector output signal status register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: reserved0 [31:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved0_SHIFT 12 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: VDL_SETTING [11:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_MASK 0x00000ff0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_SHIFT 4 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VDL_SETTING_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: reserved1 [03:01] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved1_MASK 0x0000000e |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_reserved1_SHIFT 1 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS :: VALID [00:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_MASK 0x00000001 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_VALID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EDC_DPD_OUT_STATUS_CLEAR - GDDR5M EDC digital phase detector output signal status clear register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS_CLEAR :: reserved0 [31:01] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_MASK 0xfffffffe |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_reserved0_SHIFT 1 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_DPD_OUT_STATUS_CLEAR :: CLEAR [00:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_MASK 0x00000001 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_DPD_OUT_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EDC_CRC_CONTROL - GDDR5M EDC signal path CRC control register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: BUSY [31:31] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_MASK 0x80000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_SHIFT 31 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_BUSY_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved0 [30:17] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved0_MASK 0x7ffe0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved0_SHIFT 17 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: FORCE [16:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_MASK 0x00010000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_FORCE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved1 [15:11] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved1_MASK 0x0000f800 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved1_SHIFT 11 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: CRCWL [10:08] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_MASK 0x00000700 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_SHIFT 8 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCWL_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved2 [07:06] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved2_MASK 0x000000c0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved2_SHIFT 6 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: CRCRL [05:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_MASK 0x00000030 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_SHIFT 4 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_CRCRL_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: reserved3 [03:03] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved3_MASK 0x00000008 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_reserved3_SHIFT 3 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: COUNT_MODE [02:02] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_COUNT_MODE_MASK 0x00000004 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_COUNT_MODE_SHIFT 2 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_COUNT_MODE_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: ENABLE_WR [01:01] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_MASK 0x00000002 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_SHIFT 1 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_WR_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_CONTROL :: ENABLE_RD [00:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_MASK 0x00000001 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_CONTROL_ENABLE_RD_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EDC_CRC_STATUS - GDDR5M EDC signal path CRC status register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: reserved0 [31:04] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_reserved0_SHIFT 4 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: WR_FAIL [03:03] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_MASK 0x00000008 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_SHIFT 3 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_FAIL_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: WR_PASS [02:02] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_MASK 0x00000004 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_SHIFT 2 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_WR_PASS_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: RD_FAIL [01:01] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_MASK 0x00000002 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_SHIFT 1 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_FAIL_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS :: RD_PASS [00:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_MASK 0x00000001 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_RD_PASS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EDC_CRC_COUNT - GDDR5M EDC signal path CRC counter register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: reserved0 [31:28] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved0_MASK 0xf0000000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved0_SHIFT 28 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: WR_COUNT [27:16] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_COUNT_MASK 0x0fff0000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_COUNT_SHIFT 16 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_WR_COUNT_DEFAULT 0x00000000 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: reserved1 [15:12] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved1_MASK 0x0000f000 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_reserved1_SHIFT 12 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_COUNT :: RD_COUNT [11:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_COUNT_MASK 0x00000fff |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_COUNT_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_COUNT_RD_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *EDC_CRC_STATUS_CLEAR - GDDR5M EDC signal path CRC counter register |
| ***************************************************************************/ |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS_CLEAR :: reserved0 [31:01] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_reserved0_MASK 0xfffffffe |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_reserved0_SHIFT 1 |
| |
| /* DDR34_PHY_BYTE_LANE_0_0 :: EDC_CRC_STATUS_CLEAR :: CLEAR [00:00] */ |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_MASK 0x00000001 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_SHIFT 0 |
| #define BCHP_DDR34_PHY_BYTE_LANE_0_0_EDC_CRC_STATUS_CLEAR_CLEAR_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_DDR34_PHY_BYTE_LANE_0_0_H__ */ |
| |
| /* End of File */ |
