| /*************************************************************************** |
| * Copyright (c) 1999-2011, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Tue Dec 6 19:01:27 2011 |
| * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7435/rdb/a0/bchp_memc_ddr23_shim_addr_cntl_0.h $ |
| * |
| * Hydra_Software_Devel/2 12/7/11 3:03p mward |
| * SW7435-3: Synced up with central rdb. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_H__ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_H__ |
| |
| /*************************************************************************** |
| *MEMC_DDR23_SHIM_ADDR_CNTL_0 - DDR23 SHIM Control Registers 0 |
| ***************************************************************************/ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG 0x003b8000 /* DDR23_SHIM Config register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID 0x003b8004 /* DDR23_SHIM Revision ID Register. */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET 0x003b8008 /* DDR soft reset register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG 0x003b8038 /* ODT Configuration register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL 0x003b8044 /* DDR PHY USE DYN VDL Control register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING 0x003b8048 /* DDR PHY Idle power saving Control register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT 0x003b804c /* DDR PHY standby exit register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL 0x003b806c /* Analog macro register bypass control */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL 0x003b8070 /* DDR PLL external clock select register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG 0x003b8074 /* DDR23_SHIM testport control register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL 0x003b807c /* DDR bypass pll mode disable register. */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL 0x003b8088 /* DDR VECTOR PLL bypass mode clock select */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL 0x003b808c /* DDR Pad control register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE 0x003b8098 /* CLK_667_ENABLE Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS 0x003b809c /* DDR23_SHIM Status Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO 0x003b8028 /* Command and Data FIFO Status Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH 0x003b802c /* Read Datapath Status Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_FLAG_BUS 0x003b8030 /* TP_OUT bus value Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC 0x003b8034 /* Miscellaneous Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW 0x003b80a4 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW 0x003b80a8 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO 0x003b80ac /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO 0x003b80b0 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL 0x003b80b4 /* FORCE_DDR3_RESET Deassert Register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS 0x003b80b8 /* SYS PLL P and N Divider Controls */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN 0x003b80bc /* SYS PLL Gain Controls */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL 0x003b80c0 /* SYS PLL Control Vector */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP 0x003b80c4 /* SSC Step Size for all 6-chan PLLs */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT 0x003b80c8 /* SSC Limit for all 6-chan PLLs */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0 0x003b80cc /* SYS PLL M Divider Controls for Channel0 */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX 0x003b80d0 /* SYS PLL M Divider Controls for Extra Unused Channels */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT 0x003b80d4 /* SYS PLL Status */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel 0x003b80d8 /* SYS PLL power-down and reference clock selection */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET 0x003b80dc /* SYS PLL Reset and post-resetb selcection */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR 0x003b80e0 /* SYS PLL control and SR selcection */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK 0x003b80e4 /* Shim to PHY gated bypass_clock selection */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0 0x003b80e8 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1 0x003b80ec /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2 0x003b80f0 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3 0x003b80f4 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4 0x003b80f8 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5 0x003b80fc /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6 0x003b8100 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7 0x003b8104 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8 0x003b8108 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9 0x003b810c /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10 0x003b8110 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11 0x003b8114 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12 0x003b8118 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13 0x003b811c /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14 0x003b8120 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15 0x003b8124 /* Spare register */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY 0x003b8128 /* Delay on phy_dyn_vdl to the PHY */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0 0x003b812c /* DDR PHY data storage register 0 */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1 0x003b8130 /* DDR PHY data storage register 0 */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2 0x003b8134 /* DDR PHY data storage register 0 */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3 0x003b8138 /* DDR PHY data storage register 0 */ |
| |
| /*************************************************************************** |
| *CONFIG - DDR23_SHIM Config register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: reserved0 [31:27] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_reserved0_MASK 0xf8000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_reserved0_SHIFT 27 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: LAST_RD_STRETCH [26:26] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_MASK 0x04000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_SHIFT 26 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_RD_STRETCH_DEFAULT 0x00000001 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: ODT_LATENCY [25:21] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_ODT_LATENCY_MASK 0x03e00000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_ODT_LATENCY_SHIFT 21 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_ODT_LATENCY_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: LAST_READ_LATENCY [20:15] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_MASK 0x001f8000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_SHIFT 15 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_LAST_READ_LATENCY_DEFAULT 0x0000000b |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: READ_LATENCY [14:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_READ_LATENCY_MASK 0x00007f00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_READ_LATENCY_SHIFT 8 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_READ_LATENCY_DEFAULT 0x00000007 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: WRITE_LATENCY [07:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_MASK 0x000000f8 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_SHIFT 3 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_WRITE_LATENCY_DEFAULT 0x0000000e |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: DRAM_WIDTH [02:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DRAM_WIDTH_MASK 0x00000006 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DRAM_WIDTH_SHIFT 1 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DRAM_WIDTH_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CONFIG :: DDR_MODE [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DDR_MODE_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DDR_MODE_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CONFIG_DDR_MODE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DDR23_SHIM_REV_ID - DDR23_SHIM Revision ID Register. |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_REV_ID :: reserved0 [31:16] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_reserved0_MASK 0xffff0000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_reserved0_SHIFT 16 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_REV_ID :: MAJOR_ID [15:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MAJOR_ID_MASK 0x0000ff00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MAJOR_ID_SHIFT 8 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MAJOR_ID_DEFAULT 0x00000001 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_REV_ID :: MINOR_ID [07:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MINOR_ID_MASK 0x000000ff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MINOR_ID_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_REV_ID_MINOR_ID_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *RESET - DDR soft reset register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: reserved0 [31:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_reserved0_MASK 0xfffffff8 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_reserved0_SHIFT 3 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: DATAPATH_216_RESET [02:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_SHIFT 2 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_216_RESET_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: DATAPATH_DDR_RESET [01:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_SHIFT 1 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_DATAPATH_DDR_RESET_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RESET :: PHY_PWRUP_RSB [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RESET_PHY_PWRUP_RSB_SHIFT 0 |
| |
| /*************************************************************************** |
| *ODT_CONFIG - ODT Configuration register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: reserved0 [31:16] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_reserved0_MASK 0xffff0000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_reserved0_SHIFT 16 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: ODT_TIE_HIGH [15:15] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_TIE_HIGH_MASK 0x00008000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_TIE_HIGH_SHIFT 15 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_TIE_HIGH_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: ODT_ENABLE [14:14] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_ENABLE_MASK 0x00004000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_ENABLE_SHIFT 14 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_ODT_ENABLE_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: STRETCH [13:11] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_STRETCH_MASK 0x00003800 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_STRETCH_SHIFT 11 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_STRETCH_DEFAULT 0x00000003 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: EARLY [10:06] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_EARLY_MASK 0x000007c0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_EARLY_SHIFT 6 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_EARLY_DEFAULT 0x00000001 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ODT_CONFIG :: DELAY [05:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_DELAY_MASK 0x0000003f |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_DELAY_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ODT_CONFIG_DELAY_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *PHY_USE_DYN_VDL - DDR PHY USE DYN VDL Control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_USE_DYN_VDL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_USE_DYN_VDL :: DISABLE [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_DISABLE_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_DISABLE_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_USE_DYN_VDL_DISABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *IDLE_POWER_SAVING - DDR PHY Idle power saving Control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: reserved0 [31:06] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_MASK 0xffffffc0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_reserved0_SHIFT 6 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: PhyAddrCntl [05:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_MASK 0x00000030 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_SHIFT 4 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_PhyAddrCntl_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane3 [03:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_MASK 0x00000008 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_SHIFT 3 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane3_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane2 [02:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_SHIFT 2 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane2_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane1 [01:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_SHIFT 1 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane1_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: IDLE_POWER_SAVING :: ByteLane0 [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_IDLE_POWER_SAVING_ByteLane0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PHY_STANDBY_EXIT - DDR PHY standby exit register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_STANDBY_EXIT :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_STANDBY_EXIT :: ENABLE [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_STANDBY_EXIT_ENABLE_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *ANALOG_BYPASS_CNTRL - Analog macro register bypass control |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ANALOG_BYPASS_CNTRL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: ANALOG_BYPASS_CNTRL :: BYPASS_PLL [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_ANALOG_BYPASS_CNTRL_BYPASS_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DDR_PLL_EXT_CLKSEL - DDR PLL external clock select register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PLL_EXT_CLKSEL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PLL_EXT_CLKSEL :: EXT_CLK_SEL [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PLL_EXT_CLKSEL_EXT_CLK_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *TEST_MODE_CNTRL_REG - DDR23_SHIM testport control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: TEST_MODE_CNTRL_REG :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_TEST_MODE_CNTRL_REG_reserved_for_eco0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DISABLE_CHIP_BYPASS_PLL - DDR bypass pll mode disable register. |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DISABLE_CHIP_BYPASS_PLL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DISABLE_CHIP_BYPASS_PLL :: DISABLE_BYPASS_PLL [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DISABLE_CHIP_BYPASS_PLL_DISABLE_BYPASS_PLL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *VECTOR_MODE_CLK_SEL - DDR VECTOR PLL bypass mode clock select |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: VECTOR_MODE_CLK_SEL :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: VECTOR_MODE_CLK_SEL :: SEL [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_VECTOR_MODE_CLK_SEL_SEL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DDR_PAD_CNTRL - DDR Pad control register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: reserved0 [31:07] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_MASK 0xffffff80 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_reserved0_SHIFT 7 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: IDDQ_MODE_ON_SELFREF [06:06] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK 0x00000040 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_SHIFT 6 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: PHY_IDLE_ENABLE [05:05] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_MASK 0x00000020 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_SHIFT 5 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_PHY_IDLE_ENABLE_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: HIZ_ON_SELFREF [04:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_MASK 0x00000010 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_SHIFT 4 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_HIZ_ON_SELFREF_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR_PAD_CNTRL :: CNTRL [03:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR_PAD_CNTRL_CNTRL_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CLK_GATE - CLK_667_ENABLE Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CLK_GATE :: UNUSED [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_UNUSED_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_UNUSED_SHIFT 1 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_UNUSED_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CLK_GATE :: CLK_667_ENABLE [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CLK_GATE_CLK_667_ENABLE_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DDR23_SHIM_STATUS - DDR23_SHIM Status Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: reserved0 [31:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_reserved0_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: BL0_AND_BL1_RDY_SLIP [03:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_MASK 0x00000008 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_AND_BL1_RDY_SLIP_SHIFT 3 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: BL0_RDY_SLIP [02:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_RDY_SLIP_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL0_RDY_SLIP_SHIFT 2 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: BL1_RDY_SLIP [01:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL1_RDY_SLIP_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_BL1_RDY_SLIP_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR23_SHIM_STATUS :: READY [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_READY_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_READY_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR23_SHIM_STATUS_READY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *CMD_DATA_FIFO - Command and Data FIFO Status Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved0 [31:26] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_MASK 0xfc000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved0_SHIFT 26 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_FULL [25:25] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_MASK 0x02000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_FULL_SHIFT 25 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: FIFO_EMPTY [24:24] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_MASK 0x01000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_FIFO_EMPTY_SHIFT 24 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: reserved1 [23:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_MASK 0x00ffff00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_reserved1_SHIFT 8 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: WR_PNTR [07:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_MASK 0x000000f0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_WR_PNTR_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: CMD_DATA_FIFO :: RD_PNTR [03:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_CMD_DATA_FIFO_RD_PNTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *RD_DATAPATH - Read Datapath Status Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: reserved0 [31:28] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_reserved0_MASK 0xf0000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_reserved0_SHIFT 28 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_3 [27:27] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_3_MASK 0x08000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_3_SHIFT 27 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_2 [26:26] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_2_MASK 0x04000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_2_SHIFT 26 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_1 [25:25] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_1_MASK 0x02000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_1_SHIFT 25 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: F_RDY_0 [24:24] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_0_MASK 0x01000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_F_RDY_0_SHIFT 24 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD3_CNT [23:20] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD3_CNT_MASK 0x00f00000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD3_CNT_SHIFT 20 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD2_CNT [19:16] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD2_CNT_MASK 0x000f0000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD2_CNT_SHIFT 16 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD1_CNT [15:12] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD1_CNT_MASK 0x0000f000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD1_CNT_SHIFT 12 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: DWORD0_CNT [11:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD0_CNT_MASK 0x00000f00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_DWORD0_CNT_SHIFT 8 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: WR_PNTR [07:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_MASK 0x000000f0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_WR_PNTR_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: RD_DATAPATH :: RD_PNTR [03:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_RD_DATAPATH_RD_PNTR_SHIFT 0 |
| |
| /*************************************************************************** |
| *FLAG_BUS - TP_OUT bus value Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: FLAG_BUS :: FLAG_BUS [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_FLAG_BUS_FLAG_BUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *MISC - Miscellaneous Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: reserved_for_eco0 [31:12] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_reserved_for_eco0_MASK 0xfffff000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_reserved_for_eco0_SHIFT 12 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_reserved_for_eco0_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: BL0_AND_BL1_RDY_SLIP_CLR [11:11] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_AND_BL1_RDY_SLIP_CLR_MASK 0x00000800 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_AND_BL1_RDY_SLIP_CLR_SHIFT 11 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_AND_BL1_RDY_SLIP_CLR_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: BL0_RDY_SLIP_CLR [10:10] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_RDY_SLIP_CLR_MASK 0x00000400 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_RDY_SLIP_CLR_SHIFT 10 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL0_RDY_SLIP_CLR_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: BL1_RDY_SLIP_CLR [09:09] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL1_RDY_SLIP_CLR_MASK 0x00000200 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL1_RDY_SLIP_CLR_SHIFT 9 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_BL1_RDY_SLIP_CLR_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: FUNC1 [08:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC1_MASK 0x00000100 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC1_SHIFT 8 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC1_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: FUNC0 [07:07] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC0_MASK 0x00000080 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC0_SHIFT 7 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_FUNC0_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: C2IO_INIT_RDY_OVR [06:06] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_MASK 0x00000040 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_SHIFT 6 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_C2IO_INIT_RDY_OVR_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: RD_FIFO_HOLD_CLR [05:05] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_MASK 0x00000020 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_SHIFT 5 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_RD_FIFO_HOLD_CLR_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: CMD_FIFO_HOLD_CLR [04:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_MASK 0x00000010 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_SHIFT 4 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_CMD_FIFO_HOLD_CLR_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD3_OVERRUN_CLR [03:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD3_OVERRUN_CLR_MASK 0x00000008 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD3_OVERRUN_CLR_SHIFT 3 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD3_OVERRUN_CLR_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD2_OVERRUN_CLR [02:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD2_OVERRUN_CLR_MASK 0x00000004 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD2_OVERRUN_CLR_SHIFT 2 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD2_OVERRUN_CLR_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD1_OVERRUN_CLR [01:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD1_OVERRUN_CLR_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD1_OVERRUN_CLR_SHIFT 1 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD1_OVERRUN_CLR_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: MISC :: DWORD0_OVERRUN_CLR [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD0_OVERRUN_CLR_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD0_OVERRUN_CLR_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_MISC_DWORD0_OVERRUN_CLR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPARE0_RW - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE0_RW :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RW_reserved_for_eco0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPARE1_RW - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE1_RW :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RW_reserved_for_eco0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPARE0_RO - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE0_RO :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE0_RO_reserved_for_eco0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SPARE1_RO - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SPARE1_RO :: reserved_for_eco0 [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SPARE1_RO_reserved_for_eco0_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *DDR3_RESET_CNTRL - FORCE_DDR3_RESET Deassert Register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: UNUSED [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_SHIFT 1 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_UNUSED_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: DDR3_RESET_CNTRL :: FORCE_DDR3_RESET [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_DDR3_RESET_CNTRL_FORCE_DDR3_RESET_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *PLL6CH_PNDIV_SYS - SYS PLL P and N Divider Controls |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: reserved0 [31:31] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_reserved0_MASK 0x80000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_reserved0_SHIFT 31 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: PDIV [30:28] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_PDIV_MASK 0x70000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_PDIV_SHIFT 28 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_PDIV_DEFAULT 0x00000002 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: NDIV_INT [27:20] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_INT_MASK 0x0ff00000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_INT_SHIFT 20 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_INT_DEFAULT 0x0000004e |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PLL6CH_PNDIV_SYS :: NDIV_FRAC [19:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_FRAC_MASK 0x000fffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_FRAC_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PLL6CH_PNDIV_SYS_NDIV_FRAC_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_PLL_GAIN - SYS PLL Gain Controls |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: reserved0 [31:23] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_reserved0_MASK 0xff800000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_reserved0_SHIFT 23 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: FB_PHASE_ENA [22:22] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_ENA_MASK 0x00400000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_ENA_SHIFT 22 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_ENA_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: FB_PHASE_OFFSET [21:10] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_OFFSET_MASK 0x003ffc00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_OFFSET_SHIFT 10 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_FB_PHASE_OFFSET_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: KP [09:06] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KP_MASK 0x000003c0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KP_SHIFT 6 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KP_DEFAULT 0x00000008 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: KI [05:03] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KI_MASK 0x00000038 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KI_SHIFT 3 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KI_DEFAULT 0x00000003 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_GAIN :: KA [02:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KA_MASK 0x00000007 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KA_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_GAIN_KA_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SYS_PLL_CTRL - SYS PLL Control Vector |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: reserved0 [31:23] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_reserved0_MASK 0xff800000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_reserved0_SHIFT 23 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: ENA_8PHASE [22:22] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_8PHASE_MASK 0x00400000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_8PHASE_SHIFT 22 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_8PHASE_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: ENA_SSC [21:21] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_SSC_MASK 0x00200000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_SSC_SHIFT 21 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_ENA_SSC_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: VCO_DIV2_EN [20:20] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_VCO_DIV2_EN_MASK 0x00100000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_VCO_DIV2_EN_SHIFT 20 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_VCO_DIV2_EN_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: AUX_CTRL [19:19] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_AUX_CTRL_MASK 0x00080000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_AUX_CTRL_SHIFT 19 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_AUX_CTRL_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: REFCLK_OUT [18:18] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_REFCLK_OUT_MASK 0x00040000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_REFCLK_OUT_SHIFT 18 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_REFCLK_OUT_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: STAT_UPDATE [17:17] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_UPDATE_MASK 0x00020000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_UPDATE_SHIFT 17 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_UPDATE_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: STAT_SELECT [16:14] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_SELECT_MASK 0x0001c000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_SELECT_SHIFT 14 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_SELECT_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: STAT_RESET [13:13] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_RESET_MASK 0x00002000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_RESET_SHIFT 13 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_STAT_RESET_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: DCO_CTRL_BYPASS_ENA [12:12] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_MASK 0x00001000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_SHIFT 12 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_ENA_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_DCO_CTRL_BYPASS_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SSC_STEP - SSC Step Size for all 6-chan PLLs |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_STEP :: reserved0 [31:16] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_reserved0_MASK 0xffff0000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_reserved0_SHIFT 16 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_STEP :: SSC_STEP [15:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_SSC_STEP_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_STEP_SSC_STEP_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SSC_LIMIT - SSC Limit for all 6-chan PLLs |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_LIMIT :: reserved0 [31:22] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_reserved0_MASK 0xffc00000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_reserved0_SHIFT 22 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SSC_LIMIT :: SSC_LIMIT [21:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_SSC_LIMIT_MASK 0x003fffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_SSC_LIMIT_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SSC_LIMIT_SSC_LIMIT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_PLL_MDIV0 - SYS PLL M Divider Controls for Channel0 |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: reserved0 [31:14] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_reserved0_MASK 0xffffc000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_reserved0_SHIFT 14 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_HOLD_OUTPUT [13:13] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_MASK 0x00002000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_SHIFT 13 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_HOLD_OUTPUT_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_LOAD_MDIV [12:12] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_MASK 0x00001000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_SHIFT 12 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_LOAD_MDIV_DEFAULT 0x00000001 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_ENA [11:11] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_ENA_MASK 0x00000800 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_ENA_SHIFT 11 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_ENA_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_MDEL [10:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDEL_MASK 0x00000700 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDEL_SHIFT 8 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDEL_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIV0 :: CHAN_MDIV [07:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDIV_MASK 0x000000ff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDIV_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIV0_CHAN_MDIV_DEFAULT 0x00000008 |
| |
| /*************************************************************************** |
| *SYS_PLL_MDIVX - SYS PLL M Divider Controls for Extra Unused Channels |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: reserved0 [31:14] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_reserved0_MASK 0xffffc000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_reserved0_SHIFT 14 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_HOLD_OUTPUT [13:13] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_MASK 0x00002000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_SHIFT 13 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_HOLD_OUTPUT_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_LOAD_MDIV [12:12] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_MASK 0x00001000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_SHIFT 12 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_LOAD_MDIV_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_ENA [11:11] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_ENA_MASK 0x00000800 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_ENA_SHIFT 11 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_ENA_DEFAULT 0x00000001 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_MDEL [10:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDEL_MASK 0x00000700 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDEL_SHIFT 8 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDEL_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_MDIVX :: CHAN_MDIV [07:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDIV_MASK 0x000000ff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDIV_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_MDIVX_CHAN_MDIV_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_PLL_STAT - SYS PLL Status |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: reserved0 [31:25] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_reserved0_MASK 0xfe000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_reserved0_SHIFT 25 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: DEBUG_OUTPUT [24:13] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_DEBUG_OUTPUT_MASK 0x01ffe000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_DEBUG_OUTPUT_SHIFT 13 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_DEBUG_OUTPUT_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: LOCK [12:12] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_LOCK_MASK 0x00001000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_LOCK_SHIFT 12 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_LOCK_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_STAT :: UNLOCK_COUNT [11:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_UNLOCK_COUNT_MASK 0x00000fff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_UNLOCK_COUNT_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_STAT_UNLOCK_COUNT_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_PLL_PWRDN_ref_clk_sel - SYS PLL power-down and reference clock selection |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_PWRDN_ref_clk_sel :: reserved0 [31:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_reserved0_MASK 0xfffffffc |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_reserved0_SHIFT 2 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_PWRDN_ref_clk_sel :: REFCLK_SEL [01:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_SHIFT 1 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_REFCLK_SEL_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_PWRDN_ref_clk_sel :: PWRDN [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_PWRDN_ref_clk_sel_PWRDN_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SYS_PLL_RESET_POST_RESET - SYS PLL Reset and post-resetb selcection |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_RESET_POST_RESET :: reserved0 [31:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_reserved0_SHIFT 2 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_RESET_POST_RESET :: POST_RESETB [01:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_POST_RESETB_MASK 0x00000002 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_POST_RESETB_SHIFT 1 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_POST_RESETB_DEFAULT 0x00000001 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_RESET_POST_RESET :: GLOBAL_RESETB [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_RESET_POST_RESET_GLOBAL_RESETB_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *SYS_PLL_CTRL_SR - SYS PLL control and SR selcection |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: reserved0 [31:29] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_reserved0_MASK 0xe0000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_reserved0_SHIFT 29 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: PLL_SR [28:11] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_SR_MASK 0x1ffff800 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_SR_SHIFT 11 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_SR_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: PLL_CTRL_1 [10:02] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_CTRL_1_MASK 0x000007fc |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_CTRL_1_SHIFT 2 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_PLL_CTRL_1_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SYS_PLL_CTRL_SR :: NDIV_INT_1 [01:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_NDIV_INT_1_MASK 0x00000003 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_NDIV_INT_1_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SYS_PLL_CTRL_SR_NDIV_INT_1_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SHIM_TO_PHY_GATED_BYPASS_CLK - Shim to PHY gated bypass_clock selection |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SHIM_TO_PHY_GATED_BYPASS_CLK :: reserved0 [31:01] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_reserved0_MASK 0xfffffffe |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_reserved0_SHIFT 1 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SHIM_TO_PHY_GATED_BYPASS_CLK :: BYPASS_CLK_GATED_TO_SHIM_PHY [00:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_MASK 0x00000001 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SHIM_TO_PHY_GATED_BYPASS_CLK_BYPASS_CLK_GATED_TO_SHIM_PHY_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG0 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG0 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG0_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG1 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG1 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG1_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG2 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG2 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG2_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG3 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG3 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG3_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG4 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG4 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG4_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG5 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG5 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG5_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG6 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG6 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG6_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG7 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG7 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG7_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG8 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG8 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG8_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG9 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG9 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG9_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG10 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG10 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG10_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG11 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG11 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG11_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG12 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG12 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG12_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG13 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG13 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG13_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG14 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG14 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG14_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *SCRATCH_REG15 - Spare register |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: SCRATCH_REG15 :: reserved_for_schmoo [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15_reserved_for_schmoo_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15_reserved_for_schmoo_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_SCRATCH_REG15_reserved_for_schmoo_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *PHY_DYN_VDL_DLY - Delay on phy_dyn_vdl to the PHY |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved0 [31:28] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved0_MASK 0xf0000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved0_SHIFT 28 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_DEASSERT_TO_READ_ENB_DLY [27:24] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_MASK 0x0f000000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_SHIFT 24 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_READ_ENB_DLY_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved1 [23:20] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved1_MASK 0x00f00000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved1_SHIFT 20 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_ASSERT_TO_READ_ENB_DLY [19:16] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_MASK 0x000f0000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_SHIFT 16 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_READ_ENB_DLY_DEFAULT 0x00000000 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved2 [15:12] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved2_MASK 0x0000f000 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved2_SHIFT 12 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_DEASSERT_TO_WR_VALID_DLY [11:08] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_MASK 0x00000f00 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_SHIFT 8 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_DEASSERT_TO_WR_VALID_DLY_DEFAULT 0x00000002 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: reserved3 [07:04] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved3_MASK 0x000000f0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_reserved3_SHIFT 4 |
| |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: PHY_DYN_VDL_DLY :: DYN_VDL_ASSERT_TO_WR_VALID_DLY [03:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_MASK 0x0000000f |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_PHY_DYN_VDL_DLY_DYN_VDL_ASSERT_TO_WR_VALID_DLY_DEFAULT 0x00000002 |
| |
| /*************************************************************************** |
| *AON_STORAGE_IN_PHY_0 - DDR PHY data storage register 0 |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_0 :: DTATA [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0_DTATA_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0_DTATA_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_0_DTATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *AON_STORAGE_IN_PHY_1 - DDR PHY data storage register 0 |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_1 :: DTATA [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1_DTATA_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1_DTATA_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_1_DTATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *AON_STORAGE_IN_PHY_2 - DDR PHY data storage register 0 |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_2 :: DTATA [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2_DTATA_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2_DTATA_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_2_DTATA_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *AON_STORAGE_IN_PHY_3 - DDR PHY data storage register 0 |
| ***************************************************************************/ |
| /* MEMC_DDR23_SHIM_ADDR_CNTL_0 :: AON_STORAGE_IN_PHY_3 :: DTATA [31:00] */ |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3_DTATA_MASK 0xffffffff |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3_DTATA_SHIFT 0 |
| #define BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_AON_STORAGE_IN_PHY_3_DTATA_DEFAULT 0x00000000 |
| |
| #endif /* #ifndef BCHP_MEMC_DDR23_SHIM_ADDR_CNTL_0_H__ */ |
| |
| /* End of File */ |
