| /*************************************************************************** |
| * Copyright (c) 1999-2012, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Sat May 5 03:10:02 2012 |
| * MD5 Checksum d41d8cd98f00b204e9800998ecf8427e |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008005 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: $ |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_HIF_CPU_TP1_INTR1_H__ |
| #define BCHP_HIF_CPU_TP1_INTR1_H__ |
| |
| /*************************************************************************** |
| *HIF_CPU_TP1_INTR1 - HIF CPU0 Thread Processor 1 (TP1) Level 1 Interrupt Controller Registers |
| ***************************************************************************/ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS 0x0041b600 /* Interrupt Status Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS 0x0041b604 /* Interrupt Status Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS 0x0041b608 /* Interrupt Status Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS 0x0041b60c /* Interrupt Status Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS 0x0041b610 /* Interrupt Mask Status Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS 0x0041b614 /* Interrupt Mask Status Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS 0x0041b618 /* Interrupt Mask Status Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS 0x0041b61c /* Interrupt Mask Status Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET 0x0041b620 /* Interrupt Mask Set Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET 0x0041b624 /* Interrupt Mask Set Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET 0x0041b628 /* Interrupt Mask Set Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET 0x0041b62c /* Interrupt Mask Set Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR 0x0041b630 /* Interrupt Mask Clear Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR 0x0041b634 /* Interrupt Mask Clear Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR 0x0041b638 /* Interrupt Mask Clear Register */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR 0x0041b63c /* Interrupt Mask Clear Register */ |
| |
| /*************************************************************************** |
| *INTR_W0_STATUS - Interrupt Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: MEMC1_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: MEMC0_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: IPI3_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI3_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI3_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI3_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: IPI2_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI2_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI2_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI2_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: IPI1_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: IPI0_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_TX_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_RX_0_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_B_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_1_A_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_B_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_05_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_04_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_03_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_02_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_01_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: EXT_IRQ_00_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: DVP_HR_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_DVP_HR_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: CLKGEN_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_1_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNM_0_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_5_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_1_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_0_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNB_0_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AVD1_0_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AVD1_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INTR_W1_STATUS - Interrupt Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_SC_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MC_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MC_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_AON_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_MAIN_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_AON_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_BSC_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_AON_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UPG_AUX_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: UHF_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_UHF_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_PM_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_AON_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SYS_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SYS_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SVD0_0_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SVD0_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SOFT_MODEM_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SID0_0_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SID0_0_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SID0_0_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SID0_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDIO1_0_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SDIO0_0_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_GRB_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SATA_AHCI_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA1_FW_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA1_FW_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA1_FW_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA1_FW_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA1_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA1_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA1_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_FW_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: RAAGA_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_NMI_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_NMI_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTR_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTR_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTD_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTD_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTC_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTC_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTB_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTB_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_INTA_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_INTA_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCIE_ERR_ATTN_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: NMI_PIN_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: MOCA_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_MOCA_CPU_INTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INTR_W2_STATUS - Interrupt Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_STATUS_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_RAV_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_PCR_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_OVFL_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_STAT_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_MSG_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: XPT_FE_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: WEBHIF_TIMER_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_TIMER_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_TIMER_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_TIMER_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: WEBHIF_STB_IPI1_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI1_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI1_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: WEBHIF_STB_IPI0_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI0_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI0_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_STB_IPI0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: WEBHIF_IPI1_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_IPI1_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_IPI1_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_IPI1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: WEBHIF_IPI0_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_IPI0_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_IPI0_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_IPI0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: WEBHIF_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_WEBHIF_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VICE1_0_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE1_0_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE1_0_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE1_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VICE0_0_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VICE0_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: VEC_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_VEC_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: V3D_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_V3D_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_1_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_OHCI_0_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_1_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_EHCI_0_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB1_BRIDGE_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_1_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_OHCI_0_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_1_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_EHCI_0_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: USB0_BRIDGE_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_TMR_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_TMR_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_TMR_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_SPI_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_SPI_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_SPI_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INTR_W3_STATUS - Interrupt Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_STATUS :: reserved0 [31:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_reserved0_SHIFT 4 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_STATUS :: SCPU_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_SCPU_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_SCPU_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_SCPU_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_STATUS :: M2MC1_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_M2MC1_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_M2MC1_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_M2MC1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_STATUS :: ZCPU_ACCESS_VIOL1_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_DEFAULT 0x00000000 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_STATUS :: ZCPU_ACCESS_VIOL0_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_DEFAULT 0x00000000 |
| |
| /*************************************************************************** |
| *INTR_W0_MASK_STATUS - Interrupt Mask Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: MEMC1_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: MEMC0_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: IPI3_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI3_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI3_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI3_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: IPI2_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI2_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI2_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI2_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: IPI1_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: IPI0_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_IPI0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_TX_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_TX_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_RX_0_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_B_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_B_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_1_A_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_1_A_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_B_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_B_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_05_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_04_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_03_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_02_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_01_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: EXT_IRQ_00_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: DVP_HR_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_DVP_HR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: CLKGEN_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_CLKGEN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_1_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNM_0_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNM_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_5_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_5_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_1_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_0_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_0_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AVD1_0_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AVD1_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W1_MASK_STATUS - Interrupt Mask Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_SC_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_SC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MC_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_AON_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_MAIN_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_AON_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_BSC_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_BSC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_AON_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UPG_AUX_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UPG_AUX_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: UHF_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_UHF_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_PM_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_PM_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_AON_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SYS_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SYS_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SVD0_0_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SVD0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SOFT_MODEM_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SID0_0_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SID0_0_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SID0_0_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SID0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDIO1_0_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO1_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SDIO0_0_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SDIO0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_GRB_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_GRB_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SATA_AHCI_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA1_FW_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA1_FW_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA1_FW_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA1_FW_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA1_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA1_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA1_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_FW_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: RAAGA_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_RAAGA_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_NMI_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTR_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTD_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTC_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTB_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_INTA_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCIE_ERR_ATTN_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: NMI_PIN_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_NMI_PIN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: MOCA_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_MOCA_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W2_MASK_STATUS - Interrupt Mask Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_STATUS_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_RAV_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_RAV_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_PCR_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_PCR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_OVFL_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_MSG_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_MSG_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: XPT_FE_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_XPT_FE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_TIMER_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_TIMER_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_TIMER_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_TIMER_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_STB_IPI1_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI1_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI1_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_STB_IPI0_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI0_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI0_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_STB_IPI0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_IPI1_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI1_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI1_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_IPI0_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI0_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI0_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_IPI0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: WEBHIF_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_WEBHIF_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VICE1_0_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE1_0_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE1_0_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE1_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VICE0_0_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VICE0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: VEC_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_VEC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: V3D_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_V3D_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_1_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_OHCI_0_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_1_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_EHCI_0_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB1_BRIDGE_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_1_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_OHCI_0_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_1_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_EHCI_0_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: USB0_BRIDGE_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_TMR_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_TMR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_SPI_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_SPI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W3_MASK_STATUS - Interrupt Mask Status Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_STATUS :: reserved0 [31:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_reserved0_MASK 0xfffffff0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_reserved0_SHIFT 4 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_STATUS :: SCPU_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_SCPU_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_SCPU_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_SCPU_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_STATUS :: M2MC1_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_M2MC1_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_M2MC1_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_M2MC1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_STATUS :: ZCPU_ACCESS_VIOL1_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_STATUS :: ZCPU_ACCESS_VIOL0_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_STATUS_ZCPU_ACCESS_VIOL0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W0_MASK_SET - Interrupt Mask Set Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: MEMC1_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: MEMC0_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: IPI3_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI3_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI3_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI3_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: IPI2_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI2_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI2_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI2_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: IPI1_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: IPI0_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_IPI0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_TX_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_TX_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_RX_0_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_B_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_B_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_1_A_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_1_A_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_B_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_B_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_05_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_04_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_03_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_02_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_01_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: EXT_IRQ_00_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: DVP_HR_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_DVP_HR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: CLKGEN_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_CLKGEN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_1_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNM_0_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNM_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_5_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_5_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_1_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_0_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNB_0_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AVD1_0_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AVD1_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W1_MASK_SET - Interrupt Mask Set Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_SC_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_SC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MC_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_AON_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_MAIN_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_AON_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_BSC_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_BSC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_AON_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UPG_AUX_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UPG_AUX_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: UHF_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_UHF_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_PM_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_PM_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_AON_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SYS_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SYS_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SVD0_0_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SVD0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SOFT_MODEM_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SID0_0_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SID0_0_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SID0_0_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SID0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDIO1_0_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO1_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SDIO0_0_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SDIO0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_GRB_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_GRB_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SATA_AHCI_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA1_FW_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA1_FW_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA1_FW_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA1_FW_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA1_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA1_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA1_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_FW_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: RAAGA_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_RAAGA_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_NMI_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTR_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTD_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTC_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTB_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_INTA_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCIE_ERR_ATTN_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: NMI_PIN_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_NMI_PIN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: MOCA_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_MOCA_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W2_MASK_SET - Interrupt Mask Set Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_STATUS_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_RAV_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_RAV_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_PCR_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_PCR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_OVFL_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_STAT_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_MSG_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_MSG_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: XPT_FE_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_XPT_FE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_TIMER_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_TIMER_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_TIMER_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_TIMER_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_STB_IPI1_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI1_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI1_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_STB_IPI0_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI0_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI0_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_STB_IPI0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_IPI1_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI1_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI1_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_IPI0_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI0_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI0_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_IPI0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: WEBHIF_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_WEBHIF_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VICE1_0_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE1_0_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE1_0_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE1_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VICE0_0_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VICE0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: VEC_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_VEC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: V3D_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_V3D_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_1_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_OHCI_0_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_1_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_EHCI_0_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB1_BRIDGE_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_1_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_OHCI_0_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_1_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_EHCI_0_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: USB0_BRIDGE_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_TMR_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_TMR_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_TMR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_SPI_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_SPI_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_SPI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W3_MASK_SET - Interrupt Mask Set Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_SET :: reserved0 [31:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_reserved0_MASK 0xfffffff0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_reserved0_SHIFT 4 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_SET :: SCPU_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_SCPU_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_SCPU_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_SCPU_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_SET :: M2MC1_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_M2MC1_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_M2MC1_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_M2MC1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_SET :: ZCPU_ACCESS_VIOL1_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL1_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL1_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_SET :: ZCPU_ACCESS_VIOL0_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL0_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL0_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_SET_ZCPU_ACCESS_VIOL0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC1_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC0_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: IPI3_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI3_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI3_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI3_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: IPI2_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI2_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI2_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI2_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: IPI1_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: IPI0_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_IPI0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_TX_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_TX_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_RX_0_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_RX_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_B_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_B_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_1_A_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_1_A_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_B_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_B_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_05_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_05_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_04_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_04_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_03_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_03_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_02_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_02_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_01_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_01_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: EXT_IRQ_00_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_EXT_IRQ_00_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: DVP_HR_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_DVP_HR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: CLKGEN_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_CLKGEN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_1_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNM_0_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNM_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_5_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_5_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_1_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_0_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_0_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AVD1_0_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AVD1_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_SC_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_SC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MC_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_AON_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_MAIN_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_MAIN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_AON_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_BSC_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_BSC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_AON_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UPG_AUX_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UPG_AUX_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: UHF_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_UHF_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_PM_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_PM_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_AON_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_AON_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SYS_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SYS_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SVD0_0_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SVD0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SOFT_MODEM_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SOFT_MODEM_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SID0_0_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SID0_0_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SID0_0_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SID0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO1_0_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO1_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SDIO0_0_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SDIO0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_GRB_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_GRB_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SATA_AHCI_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SATA_AHCI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA1_FW_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_FW_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_FW_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_FW_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA1_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_FW_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_FW_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: RAAGA_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_RAAGA_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_NMI_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_NMI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTR_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTD_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTD_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTC_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTB_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTB_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_INTA_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_INTA_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCIE_ERR_ATTN_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCIE_ERR_ATTN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: NMI_PIN_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_NMI_PIN_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: MOCA_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_MOCA_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_STATUS_CPU_INTR [31:31] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x80000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 31 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_STATUS_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_RAV_CPU_INTR [30:30] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x40000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 30 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_RAV_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_PCR_CPU_INTR [29:29] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x20000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 29 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_PCR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_OVFL_CPU_INTR [28:28] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x10000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 28 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_OVFL_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [27:27] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x08000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 27 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_MSG_CPU_INTR [26:26] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x04000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 26 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_MSG_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: XPT_FE_CPU_INTR [25:25] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x02000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 25 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_XPT_FE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_TIMER_CPU_INTR [24:24] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_TIMER_CPU_INTR_MASK 0x01000000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_TIMER_CPU_INTR_SHIFT 24 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_TIMER_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_STB_IPI1_CPU_INTR [23:23] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI1_CPU_INTR_MASK 0x00800000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI1_CPU_INTR_SHIFT 23 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_STB_IPI0_CPU_INTR [22:22] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI0_CPU_INTR_MASK 0x00400000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI0_CPU_INTR_SHIFT 22 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_STB_IPI0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_IPI1_CPU_INTR [21:21] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI1_CPU_INTR_MASK 0x00200000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI1_CPU_INTR_SHIFT 21 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_IPI0_CPU_INTR [20:20] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI0_CPU_INTR_MASK 0x00100000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI0_CPU_INTR_SHIFT 20 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_IPI0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: WEBHIF_CPU_INTR [19:19] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_CPU_INTR_MASK 0x00080000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_CPU_INTR_SHIFT 19 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_WEBHIF_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VICE1_0_CPU_INTR [18:18] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE1_0_CPU_INTR_MASK 0x00040000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE1_0_CPU_INTR_SHIFT 18 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE1_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VICE0_0_CPU_INTR [17:17] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_MASK 0x00020000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_SHIFT 17 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VICE0_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: VEC_CPU_INTR [16:16] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_MASK 0x00010000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_SHIFT 16 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_VEC_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: V3D_CPU_INTR [15:15] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_MASK 0x00008000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_SHIFT 15 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_V3D_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_1_CPU_INTR [14:14] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_MASK 0x00004000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_SHIFT 14 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_OHCI_0_CPU_INTR [13:13] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_MASK 0x00002000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_SHIFT 13 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_OHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_1_CPU_INTR [12:12] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_MASK 0x00001000 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_SHIFT 12 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_EHCI_0_CPU_INTR [11:11] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_MASK 0x00000800 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_SHIFT 11 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_EHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB1_BRIDGE_CPU_INTR [10:10] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_MASK 0x00000400 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_SHIFT 10 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB1_BRIDGE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_1_CPU_INTR [09:09] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_MASK 0x00000200 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_SHIFT 9 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_OHCI_0_CPU_INTR [08:08] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_MASK 0x00000100 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_SHIFT 8 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_OHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_1_CPU_INTR [07:07] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_MASK 0x00000080 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_SHIFT 7 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_EHCI_0_CPU_INTR [06:06] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_MASK 0x00000040 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_SHIFT 6 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_EHCI_0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: USB0_BRIDGE_CPU_INTR [05:05] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_MASK 0x00000020 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_SHIFT 5 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_USB0_BRIDGE_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [04:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000010 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 4 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART0_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART0_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_TMR_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_TMR_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_SPI_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_SPI_CPU_INTR_DEFAULT 0x00000001 |
| |
| /*************************************************************************** |
| *INTR_W3_MASK_CLEAR - Interrupt Mask Clear Register |
| ***************************************************************************/ |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_CLEAR :: reserved0 [31:04] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_reserved0_MASK 0xfffffff0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_reserved0_SHIFT 4 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_CLEAR :: SCPU_CPU_INTR [03:03] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_SCPU_CPU_INTR_MASK 0x00000008 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_SCPU_CPU_INTR_SHIFT 3 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_SCPU_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_CLEAR :: M2MC1_CPU_INTR [02:02] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_M2MC1_CPU_INTR_MASK 0x00000004 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_M2MC1_CPU_INTR_SHIFT 2 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_M2MC1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_CLEAR :: ZCPU_ACCESS_VIOL1_CPU_INTR [01:01] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL1_CPU_INTR_MASK 0x00000002 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL1_CPU_INTR_SHIFT 1 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL1_CPU_INTR_DEFAULT 0x00000001 |
| |
| /* HIF_CPU_TP1_INTR1 :: INTR_W3_MASK_CLEAR :: ZCPU_ACCESS_VIOL0_CPU_INTR [00:00] */ |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL0_CPU_INTR_MASK 0x00000001 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL0_CPU_INTR_SHIFT 0 |
| #define BCHP_HIF_CPU_TP1_INTR1_INTR_W3_MASK_CLEAR_ZCPU_ACCESS_VIOL0_CPU_INTR_DEFAULT 0x00000001 |
| |
| #endif /* #ifndef BCHP_HIF_CPU_TP1_INTR1_H__ */ |
| |
| /* End of File */ |
