/***************************************************************************
 *     Copyright (c) 1999-2011, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Mon Apr 11 13:43:31 2011
 *                 MD5 Checksum         8cf142ad25caa9f873c54e8bb2bb1755
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_memc_ddr_1.h $
 * 
 * Hydra_Software_Devel/2   4/12/11 9:00a vanessah
 * SW7425-112: Update rdb files for 7425 B0.
 *
 ***************************************************************************/

#ifndef BCHP_MEMC_DDR_1_H__
#define BCHP_MEMC_DDR_1_H__

/***************************************************************************
 *MEMC_DDR_1 - Memory Controller Sequencer (DDR Param/Control) Registers 1
 ***************************************************************************/
#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG            0x003c2000 /* Memory Controller Mode-Configuration Register. */
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL          0x003c2004 /* Dram iniitialization control */
#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS         0x003c2008 /* Dram iniitialization status */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0              0x003c200c /* Dram Mode0 register */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1              0x003c2010 /* Dram Mode1 register */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2              0x003c2014 /* Dram Mode2 register */
#define BCHP_MEMC_DDR_1_DRAM_MODE_3              0x003c2018 /* Dram Mode3 register */
#define BCHP_MEMC_DDR_1_PPD_CONFIG               0x003c201c /* Precharge power down mode configuration register */
#define BCHP_MEMC_DDR_1_SRPD_CONFIG              0x003c2020 /* Self-refresh power down mode configuration register */
#define BCHP_MEMC_DDR_1_SSPD_CMD                 0x003c2024 /* Software standby power down mode */
#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS        0x003c2028 /* Power down status */
#define BCHP_MEMC_DDR_1_WARM_BOOT                0x003c202c /* Warm boot control registers */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0            0x003c2030 /* DDR-SDRAM Timing Register. */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_1            0x003c2034 /* DDR-SDRAM Timing Register. */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_2            0x003c2038 /* Read to Write & write to read timing register */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_3            0x003c203c /* DDR-SDRAM Timing Register. */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4            0x003c2040 /* DDR-SDRAM Timing Register. */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5            0x003c2044 /* DDR-SDRAM Timing Register. */
#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ         0x003c2048 /* Memory Controller Sequencer Enable */
#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT        0x003c204c /* Memory Controller , state machine timeout register. */
#define BCHP_MEMC_DDR_1_BANK_STATUS              0x003c2050 /* Memory Controller, Bank Status Register. */
#define BCHP_MEMC_DDR_1_TESTER_LATENCY           0x003c2054 /* Memory Controller, Tester Latency Register. */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0               0x003c2058 /* Memory Controller, DATA_PINMAP_BYTE0_SEL Register. */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1               0x003c205c /* Memory Controller, DATA_PINMAP_BYTE1_SEL Register. */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2               0x003c2060 /* Memory Controller, DATA_PINMAP_BYTE2_SEL Register. */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3               0x003c2064 /* Memory Controller, DATA_PINMAP_BYTE3_SEL Register. */
#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD   0x003c2068 /* Memory Controller, DDR3 DRAM reset Register. */
#define BCHP_MEMC_DDR_1_STAT_CONTROL             0x003c206c /* Statistics Control register */
#define BCHP_MEMC_DDR_1_STAT_TIMER               0x003c2070 /* Statistics Timer */
#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP            0x003c2074 /* DRAM Idle_NOP Cycle Count Register. */
#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP        0x003c2078 /* Maximum DRAM idle_NOP cycle count register. */
#define BCHP_MEMC_DDR_1_STAT_CAS_ALL             0x003c207c /* CAS Count Register. */
#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL         0x003c2080 /* Maximum DRAM CAS cycle count register. */
#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL         0x003c2084 /* DRAM Penalty Cycle Count register. */
#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL 0x003c2088 /* Maximum number of transactions cycles (CAS+Penalty_ALL). */
#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL      0x003c208c /* Number of overall system memory read transactions. */
#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL     0x003c2090 /* Number of overall system memory write transactions. */
#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL       0x003c2094 /* Maximum Number of Overall System memory transactions. */
#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL       0x003c2098 /* Minimum Number of Overall System memory transactions. */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS  0x003c209c /* Service CAS Cycle Count register. */
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS 0x003c20a0 /* Maximum service CAS cycle count register. */
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS 0x003c20a4 /* Minimum service CAS cycle count register. */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY 0x003c20a8 /* Service Intra DRAM Penalty Cycle Count register. */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY 0x003c20ac /* Service Post DRAM Penalty Cycle Count register. */
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES 0x003c20b0 /* Maximum service cycle count register. */
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES 0x003c20b4 /* Minimum service cycle count register. */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ 0x003c20b8 /* Service Read Transaction Count register. */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE 0x003c20bc /* Service Write Transaction Count register. */
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS 0x003c20c0 /* Maximum service Transaction count register. */
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS 0x003c20c4 /* Minimum service cycle Transaction register. */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY 0x003c20c8 /* Service Latency Count register. */
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY 0x003c20cc /* Maximum Service Latency count register. */
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY 0x003c20d0 /* Minimum Service Latency count register. */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY 0x003c20d4 /* Absolute Minimum Service Latency count register. */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY 0x003c20d8 /* Absolute Maximum Service Latency count register. */
#define BCHP_MEMC_DDR_1_STAT_REFRESH             0x003c20dc /* Total number of refreshes issuedr. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0        0x003c20e0 /* CAS cycle count register for client 0. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1        0x003c20e4 /* CAS cycle count register for client 1. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2        0x003c20e8 /* CAS cycle count register for client 2. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3        0x003c20ec /* CAS cycle count register for client 3. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4        0x003c20f0 /* CAS cycle count register for client 4. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5        0x003c20f4 /* CAS cycle count register for client 5. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6        0x003c20f8 /* CAS cycle count register for client 6. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7        0x003c20fc /* CAS cycle count register for client 7. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8        0x003c2100 /* CAS cycle count register for client 8. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9        0x003c2104 /* CAS cycle count register for client 9. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10       0x003c2108 /* CAS cycle count register for client 10. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11       0x003c210c /* CAS cycle count register for client 11. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12       0x003c2110 /* CAS cycle count register for client 12. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13       0x003c2114 /* CAS cycle count register for client 13. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14       0x003c2118 /* CAS cycle count register for client 14. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15       0x003c211c /* CAS cycle count register for client 15. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16       0x003c2120 /* CAS cycle count register for client 16. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17       0x003c2124 /* CAS cycle count register for client 17. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18       0x003c2128 /* CAS cycle count register for client 18. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19       0x003c212c /* CAS cycle count register for client 19. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20       0x003c2130 /* CAS cycle count register for client 20. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21       0x003c2134 /* CAS cycle count register for client 21. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22       0x003c2138 /* CAS cycle count register for client 22. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23       0x003c213c /* CAS cycle count register for client 23. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24       0x003c2140 /* CAS cycle count register for client 24. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25       0x003c2144 /* CAS cycle count register for client 25. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26       0x003c2148 /* CAS cycle count register for client 26. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27       0x003c214c /* CAS cycle count register for client 27. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28       0x003c2150 /* CAS cycle count register for client 28. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29       0x003c2154 /* CAS cycle count register for client 29. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30       0x003c2158 /* CAS cycle count register for client 30. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31       0x003c215c /* CAS cycle count register for client 31. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32       0x003c2160 /* CAS cycle count register for client 32. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33       0x003c2164 /* CAS cycle count register for client 33. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34       0x003c2168 /* CAS cycle count register for client 34. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35       0x003c216c /* CAS cycle count register for client 35. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36       0x003c2170 /* CAS cycle count register for client 36. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37       0x003c2174 /* CAS cycle count register for client 37. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38       0x003c2178 /* CAS cycle count register for client 38. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39       0x003c217c /* CAS cycle count register for client 39. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40       0x003c2180 /* CAS cycle count register for client 40. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41       0x003c2184 /* CAS cycle count register for client 41. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42       0x003c2188 /* CAS cycle count register for client 42. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43       0x003c218c /* CAS cycle count register for client 43. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44       0x003c2190 /* CAS cycle count register for client 44. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45       0x003c2194 /* CAS cycle count register for client 45. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46       0x003c2198 /* CAS cycle count register for client 46. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47       0x003c219c /* CAS cycle count register for client 47. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48       0x003c21a0 /* CAS cycle count register for client 48. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49       0x003c21a4 /* CAS cycle count register for client 49. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50       0x003c21a8 /* CAS cycle count register for client 50. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51       0x003c21ac /* CAS cycle count register for client 51. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52       0x003c21b0 /* CAS cycle count register for client 52. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53       0x003c21b4 /* CAS cycle count register for client 53. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54       0x003c21b8 /* CAS cycle count register for client 54. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55       0x003c21bc /* CAS cycle count register for client 55. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56       0x003c21c0 /* CAS cycle count register for client 56. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57       0x003c21c4 /* CAS cycle count register for client 57. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58       0x003c21c8 /* CAS cycle count register for client 58. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59       0x003c21cc /* CAS cycle count register for client 59. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60       0x003c21d0 /* CAS cycle count register for client 60. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61       0x003c21d4 /* CAS cycle count register for client 61. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62       0x003c21d8 /* CAS cycle count register for client 62. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63       0x003c21dc /* CAS cycle count register for client 63. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64       0x003c21e0 /* CAS cycle count register for client 64. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65       0x003c21e4 /* CAS cycle count register for client 65. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66       0x003c21e8 /* CAS cycle count register for client 66. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67       0x003c21ec /* CAS cycle count register for client 67. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68       0x003c21f0 /* CAS cycle count register for client 68. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69       0x003c21f4 /* CAS cycle count register for client 69. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70       0x003c21f8 /* CAS cycle count register for client 70. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71       0x003c21fc /* CAS cycle count register for client 71. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72       0x003c2200 /* CAS cycle count register for client 72. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73       0x003c2204 /* CAS cycle count register for client 73. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74       0x003c2208 /* CAS cycle count register for client 74. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75       0x003c220c /* CAS cycle count register for client 75. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76       0x003c2210 /* CAS cycle count register for client 76. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77       0x003c2214 /* CAS cycle count register for client 77. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78       0x003c2218 /* CAS cycle count register for client 78. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79       0x003c221c /* CAS cycle count register for client 79. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80       0x003c2220 /* CAS cycle count register for client 80. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81       0x003c2224 /* CAS cycle count register for client 81. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82       0x003c2228 /* CAS cycle count register for client 82. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83       0x003c222c /* CAS cycle count register for client 83. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84       0x003c2230 /* CAS cycle count register for client 84. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85       0x003c2234 /* CAS cycle count register for client 85. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86       0x003c2238 /* CAS cycle count register for client 86. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87       0x003c223c /* CAS cycle count register for client 87. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88       0x003c2240 /* CAS cycle count register for client 88. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89       0x003c2244 /* CAS cycle count register for client 89. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90       0x003c2248 /* CAS cycle count register for client 90. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91       0x003c224c /* CAS cycle count register for client 91. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92       0x003c2250 /* CAS cycle count register for client 92. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93       0x003c2254 /* CAS cycle count register for client 93. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94       0x003c2258 /* CAS cycle count register for client 94. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95       0x003c225c /* CAS cycle count register for client 95. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96       0x003c2260 /* CAS cycle count register for client 96. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97       0x003c2264 /* CAS cycle count register for client 97. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98       0x003c2268 /* CAS cycle count register for client 98. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99       0x003c226c /* CAS cycle count register for client 99. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100      0x003c2270 /* CAS cycle count register for client 100. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101      0x003c2274 /* CAS cycle count register for client 101. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102      0x003c2278 /* CAS cycle count register for client 102. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103      0x003c227c /* CAS cycle count register for client 103. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104      0x003c2280 /* CAS cycle count register for client 104. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105      0x003c2284 /* CAS cycle count register for client 105. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106      0x003c2288 /* CAS cycle count register for client 106. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107      0x003c228c /* CAS cycle count register for client 107. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108      0x003c2290 /* CAS cycle count register for client 108. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109      0x003c2294 /* CAS cycle count register for client 109. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110      0x003c2298 /* CAS cycle count register for client 110. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111      0x003c229c /* CAS cycle count register for client 111. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112      0x003c22a0 /* CAS cycle count register for client 112. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113      0x003c22a4 /* CAS cycle count register for client 113. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114      0x003c22a8 /* CAS cycle count register for client 114. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115      0x003c22ac /* CAS cycle count register for client 115. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116      0x003c22b0 /* CAS cycle count register for client 116. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117      0x003c22b4 /* CAS cycle count register for client 117. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118      0x003c22b8 /* CAS cycle count register for client 118. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119      0x003c22bc /* CAS cycle count register for client 119. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120      0x003c22c0 /* CAS cycle count register for client 120. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121      0x003c22c4 /* CAS cycle count register for client 121. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122      0x003c22c8 /* CAS cycle count register for client 122. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123      0x003c22cc /* CAS cycle count register for client 123. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124      0x003c22d0 /* CAS cycle count register for client 124. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125      0x003c22d4 /* CAS cycle count register for client 125. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126      0x003c22d8 /* CAS cycle count register for client 126. */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127      0x003c22dc /* CAS cycle count register for client 127. */
#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL         0x003c22e0 /* Minimum DRAM CAS cycle count register. */
#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL 0x003c22e4 /* Minimum number of transactions cycles (CAS+Penalty_ALL). */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL 0x003c22e8 /* MEMSYS Auto Init Control. */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS  0x003c22ec /* MEMSYS Auto Init Status. */
#define BCHP_MEMC_DDR_1_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE 0x003c22f0 /* PHY VDL calibrate override from memc auto init. */
#define BCHP_MEMC_DDR_1_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE 0x003c22f4 /* SHIM PLL pndiv override from memc auto init. */
#define BCHP_MEMC_DDR_1_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE 0x003c22f8 /* SHIM PLL mdiv override from memc auto init. */
#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY          0x003c22fc /* Dynamic VDL shmoo command delay. */

/***************************************************************************
 *CNTRLR_CONFIG - Memory Controller Mode-Configuration Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: CNTRLR_CONFIG :: reserved0 [31:03] */
#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_reserved0_MASK               0xfffffff8
#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_reserved0_SHIFT              3

/* MEMC_DDR_1 :: CNTRLR_CONFIG :: DEVICE_TECH [02:00] */
#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DEVICE_TECH_MASK             0x00000007
#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DEVICE_TECH_SHIFT            0
#define BCHP_MEMC_DDR_1_CNTRLR_CONFIG_DEVICE_TECH_DEFAULT          3

/***************************************************************************
 *DRAM_INIT_CNTRL - Dram iniitialization control
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: reserved0 [31:03] */
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_reserved0_MASK             0xfffffff8
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_reserved0_SHIFT            3

/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: BYPASS_PHY_INIT_RDY [02:02] */
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_MASK   0x00000004
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_SHIFT  2
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_BYPASS_PHY_INIT_RDY_DEFAULT 0

/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: DDR_TECH [01:01] */
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_MASK              0x00000002
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_SHIFT             1
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_DEFAULT           1
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_DDR2              0
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR_TECH_DDR3              1

/* MEMC_DDR_1 :: DRAM_INIT_CNTRL :: DDR3_INIT_MODE [00:00] */
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR3_INIT_MODE_MASK        0x00000001
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR3_INIT_MODE_SHIFT       0
#define BCHP_MEMC_DDR_1_DRAM_INIT_CNTRL_DDR3_INIT_MODE_DEFAULT     0

/***************************************************************************
 *DRAM_INIT_STATUS - Dram iniitialization status
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_INIT_STATUS :: reserved0 [31:01] */
#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_reserved0_MASK            0xfffffffe
#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_reserved0_SHIFT           1

/* MEMC_DDR_1 :: DRAM_INIT_STATUS :: INIT_DONE [00:00] */
#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_INIT_DONE_MASK            0x00000001
#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_INIT_DONE_SHIFT           0
#define BCHP_MEMC_DDR_1_DRAM_INIT_STATUS_INIT_DONE_DEFAULT         0

/***************************************************************************
 *DRAM_MODE_0 - Dram Mode0 register
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_MODE_0 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_reserved0_MASK                 0xffff0000
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_reserved0_SHIFT                16

/* MEMC_DDR_1 :: DRAM_MODE_0 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_unused_0_MASK                  0x0000e000
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_unused_0_SHIFT                 13
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_unused_0_DEFAULT               0

/* union - case DDR2 [12:00] */
/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: PD_EXIT [12:12] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_PD_EXIT_MASK              0x00001000
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_PD_EXIT_SHIFT             12
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_PD_EXIT_DEFAULT           0

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: WR [11:09] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_WR_MASK                   0x00000e00
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_WR_SHIFT                  9
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_WR_DEFAULT                7

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: DLL_RST [08:08] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_DLL_RST_MASK              0x00000100
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_DLL_RST_SHIFT             8
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_DLL_RST_DEFAULT           0

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: TEST_MODE [07:07] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_TEST_MODE_MASK            0x00000080
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_TEST_MODE_SHIFT           7
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_TEST_MODE_DEFAULT         0

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: CL [06:04] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_CL_MASK                   0x00000070
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_CL_SHIFT                  4
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_CL_DEFAULT                7

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: BT [03:03] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BT_MASK                   0x00000008
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BT_SHIFT                  3
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BT_DEFAULT                0

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR2 :: BL [02:00] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BL_MASK                   0x00000007
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BL_SHIFT                  0
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR2_BL_DEFAULT                2

/* union - case DDR3 [12:00] */
/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: DLL_CNTRL_PPD [12:12] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_MASK        0x00001000
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_SHIFT       12
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_CNTRL_PPD_DEFAULT     0

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: WR [11:09] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_WR_MASK                   0x00000e00
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_WR_SHIFT                  9
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_WR_DEFAULT                4

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: DLL_RST [08:08] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_RST_MASK              0x00000100
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_RST_SHIFT             8
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_DLL_RST_DEFAULT           0

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: TEST_MODE [07:07] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_TEST_MODE_MASK            0x00000080
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_TEST_MODE_SHIFT           7
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_TEST_MODE_DEFAULT         0

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: CL_3_1 [06:04] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_3_1_MASK               0x00000070
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_3_1_SHIFT              4
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_3_1_DEFAULT            4

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: RBT [03:03] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_RBT_MASK                  0x00000008
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_RBT_SHIFT                 3
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_RBT_DEFAULT               0

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: CL_0 [02:02] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_0_MASK                 0x00000004
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_0_SHIFT                2
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_CL_0_DEFAULT              0

/* MEMC_DDR_1 :: DRAM_MODE_0 :: DDR3 :: BL [01:00] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_BL_MASK                   0x00000003
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_BL_SHIFT                  0
#define BCHP_MEMC_DDR_1_DRAM_MODE_0_DDR3_BL_DEFAULT                0

/***************************************************************************
 *DRAM_MODE_1 - Dram Mode1 register
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_MODE_1 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_reserved0_MASK                 0xffff0000
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_reserved0_SHIFT                16

/* MEMC_DDR_1 :: DRAM_MODE_1 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_unused_0_MASK                  0x0000e000
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_unused_0_SHIFT                 13
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_unused_0_DEFAULT               0

/* union - case DDR2 [12:00] */
/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: Q_OFF [12:12] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_MASK                0x00001000
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_SHIFT               12
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_DEFAULT             0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_ENABLE              0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_Q_OFF_DISABLE             1

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: RDQS [11:11] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_MASK                 0x00000800
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_SHIFT                11
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_DEFAULT              0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_ENABLE               1
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_RDQS_DISABLE              0

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: DQSB [10:10] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_MASK                 0x00000400
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_SHIFT                10
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_DEFAULT              0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_ENABLE               0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DQSB_DISABLE              1

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: OCD_CAL [09:07] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_OCD_CAL_MASK              0x00000380
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_OCD_CAL_SHIFT             7
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_OCD_CAL_DEFAULT           0

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_1 [06:06] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_1_MASK          0x00000040
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_1_SHIFT         6
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_1_DEFAULT       1

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: AL [05:03] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_AL_MASK                   0x00000038
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_AL_SHIFT                  3
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_AL_DEFAULT                6

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: ODT_CNTRL_0 [02:02] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_0_MASK          0x00000004
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_0_SHIFT         2
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_ODT_CNTRL_0_DEFAULT       0

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: DRV_IMP [01:01] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DRV_IMP_MASK              0x00000002
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DRV_IMP_SHIFT             1
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DRV_IMP_DEFAULT           0

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR2 :: DLL_EN [00:00] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_MASK               0x00000001
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_SHIFT              0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_DEFAULT            0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_ENABLE             0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR2_DLL_EN_DISABLE            1

/* union - case DDR3 [12:00] */
/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: Q_OFF [12:12] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_MASK                0x00001000
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_SHIFT               12
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_DEFAULT             0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_ENABLE              0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_Q_OFF_DISABLE             1

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: TDQS [11:11] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_MASK                 0x00000800
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_SHIFT                11
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_DEFAULT              0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_ENABLE               1
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_TDQS_DISABLE              0

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: unused_1 [10:10] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_1_MASK             0x00000400
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_1_SHIFT            10
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_1_DEFAULT          0

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_2 [09:09] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_2_MASK          0x00000200
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_2_SHIFT         9
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_2_DEFAULT       0

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: unused_2 [08:08] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_2_MASK             0x00000100
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_2_SHIFT            8
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_unused_2_DEFAULT          0

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: WR_LEVEL [07:07] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_MASK             0x00000080
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_SHIFT            7
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_DEFAULT          0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_ENABLE           1
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_WR_LEVEL_DISABLE          0

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_1 [06:06] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_1_MASK          0x00000040
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_1_SHIFT         6
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_1_DEFAULT       0

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_1 [05:05] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_MASK   0x00000020
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_SHIFT  5
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_1_DEFAULT 0

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: AL [04:03] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_AL_MASK                   0x00000018
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_AL_SHIFT                  3
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_AL_DEFAULT                1

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: ODT_CNTRL_0 [02:02] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_0_MASK          0x00000004
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_0_SHIFT         2
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_ODT_CNTRL_0_DEFAULT       1

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: DRIVER_IMP_CNTRL_0 [01:01] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_MASK   0x00000002
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_SHIFT  1
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DRIVER_IMP_CNTRL_0_DEFAULT 0

/* MEMC_DDR_1 :: DRAM_MODE_1 :: DDR3 :: DLL_EN [00:00] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_MASK               0x00000001
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_SHIFT              0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_DEFAULT            0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_ENABLE             0
#define BCHP_MEMC_DDR_1_DRAM_MODE_1_DDR3_DLL_EN_DISABLE            1

/***************************************************************************
 *DRAM_MODE_2 - Dram Mode2 register
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_MODE_2 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_reserved0_MASK                 0xffff0000
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_reserved0_SHIFT                16

/* MEMC_DDR_1 :: DRAM_MODE_2 :: unused_0 [15:13] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_unused_0_MASK                  0x0000e000
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_unused_0_SHIFT                 13
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_unused_0_DEFAULT               0

/* union - case DDR2 [12:00] */
/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: unused_1 [12:08] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_1_MASK             0x00001f00
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_1_SHIFT            8
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_1_DEFAULT          0

/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: HT_SRF [07:07] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_MASK               0x00000080
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_SHIFT              7
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_DEFAULT            0
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_ENABLE             1
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_HT_SRF_DISABLE            0

/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: unused_2 [06:04] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_2_MASK             0x00000070
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_2_SHIFT            4
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_unused_2_DEFAULT          0

/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: DCC_ENABLE [03:03] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_MASK           0x00000008
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_SHIFT          3
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_DEFAULT        0
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_ENABLE         1
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_DCC_ENABLE_DISABLE        0

/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR2 :: PASR [02:00] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_PASR_MASK                 0x00000007
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_PASR_SHIFT                0
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR2_PASR_DEFAULT              0

/* union - case DDR3 [12:00] */
/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: unused_1 [12:11] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_1_MASK             0x00001800
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_1_SHIFT            11
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_1_DEFAULT          0

/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: WR_ODT [10:09] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WR_ODT_MASK               0x00000600
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WR_ODT_SHIFT              9
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WR_ODT_DEFAULT            1

/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: unused_2 [08:08] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_2_MASK             0x00000100
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_2_SHIFT            8
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_unused_2_DEFAULT          0

/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: SRF_TR [07:07] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_SRF_TR_MASK               0x00000080
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_SRF_TR_SHIFT              7
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_SRF_TR_DEFAULT            0

/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: AUTO_SR [06:06] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_AUTO_SR_MASK              0x00000040
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_AUTO_SR_SHIFT             6
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_AUTO_SR_DEFAULT           1

/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: WCL [05:03] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WCL_MASK                  0x00000038
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WCL_SHIFT                 3
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_WCL_DEFAULT               1

/* MEMC_DDR_1 :: DRAM_MODE_2 :: DDR3 :: PASR [02:00] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_PASR_MASK                 0x00000007
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_PASR_SHIFT                0
#define BCHP_MEMC_DDR_1_DRAM_MODE_2_DDR3_PASR_DEFAULT              0

/***************************************************************************
 *DRAM_MODE_3 - Dram Mode3 register
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_MODE_3 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_reserved0_MASK                 0xffff0000
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_reserved0_SHIFT                16

/* MEMC_DDR_1 :: DRAM_MODE_3 :: unused_0 [15:03] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_unused_0_MASK                  0x0000fff8
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_unused_0_SHIFT                 3
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_unused_0_DEFAULT               0

/* union - case DDR2 [02:00] */
/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR2 :: unused_1 [02:00] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR2_unused_1_MASK             0x00000007
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR2_unused_1_SHIFT            0
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR2_unused_1_DEFAULT          0

/* union - case DDR3 [02:00] */
/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR3 :: MPR [02:02] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_MASK                  0x00000004
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_SHIFT                 2
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_DEFAULT               0

/* MEMC_DDR_1 :: DRAM_MODE_3 :: DDR3 :: MPR_LOC [01:00] */
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_LOC_MASK              0x00000003
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_LOC_SHIFT             0
#define BCHP_MEMC_DDR_1_DRAM_MODE_3_DDR3_MPR_LOC_DEFAULT           0

/***************************************************************************
 *PPD_CONFIG - Precharge power down mode configuration register
 ***************************************************************************/
/* MEMC_DDR_1 :: PPD_CONFIG :: reserved0 [31:13] */
#define BCHP_MEMC_DDR_1_PPD_CONFIG_reserved0_MASK                  0xffffe000
#define BCHP_MEMC_DDR_1_PPD_CONFIG_reserved0_SHIFT                 13

/* MEMC_DDR_1 :: PPD_CONFIG :: PPD_EN [12:12] */
#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_EN_MASK                     0x00001000
#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_EN_SHIFT                    12
#define BCHP_MEMC_DDR_1_PPD_CONFIG_PPD_EN_DEFAULT                  0

/* MEMC_DDR_1 :: PPD_CONFIG :: INACT_COUNT [11:00] */
#define BCHP_MEMC_DDR_1_PPD_CONFIG_INACT_COUNT_MASK                0x00000fff
#define BCHP_MEMC_DDR_1_PPD_CONFIG_INACT_COUNT_SHIFT               0
#define BCHP_MEMC_DDR_1_PPD_CONFIG_INACT_COUNT_DEFAULT             0

/***************************************************************************
 *SRPD_CONFIG - Self-refresh power down mode configuration register
 ***************************************************************************/
/* MEMC_DDR_1 :: SRPD_CONFIG :: reserved0 [31:17] */
#define BCHP_MEMC_DDR_1_SRPD_CONFIG_reserved0_MASK                 0xfffe0000
#define BCHP_MEMC_DDR_1_SRPD_CONFIG_reserved0_SHIFT                17

/* MEMC_DDR_1 :: SRPD_CONFIG :: SRPD_EN [16:16] */
#define BCHP_MEMC_DDR_1_SRPD_CONFIG_SRPD_EN_MASK                   0x00010000
#define BCHP_MEMC_DDR_1_SRPD_CONFIG_SRPD_EN_SHIFT                  16
#define BCHP_MEMC_DDR_1_SRPD_CONFIG_SRPD_EN_DEFAULT                0

/* MEMC_DDR_1 :: SRPD_CONFIG :: INACT_COUNT [15:00] */
#define BCHP_MEMC_DDR_1_SRPD_CONFIG_INACT_COUNT_MASK               0x0000ffff
#define BCHP_MEMC_DDR_1_SRPD_CONFIG_INACT_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_SRPD_CONFIG_INACT_COUNT_DEFAULT            0

/***************************************************************************
 *SSPD_CMD - Software standby power down mode
 ***************************************************************************/
/* MEMC_DDR_1 :: SSPD_CMD :: reserved0 [31:01] */
#define BCHP_MEMC_DDR_1_SSPD_CMD_reserved0_MASK                    0xfffffffe
#define BCHP_MEMC_DDR_1_SSPD_CMD_reserved0_SHIFT                   1

/* MEMC_DDR_1 :: SSPD_CMD :: SSPD [00:00] */
#define BCHP_MEMC_DDR_1_SSPD_CMD_SSPD_MASK                         0x00000001
#define BCHP_MEMC_DDR_1_SSPD_CMD_SSPD_SHIFT                        0
#define BCHP_MEMC_DDR_1_SSPD_CMD_SSPD_DEFAULT                      0

/***************************************************************************
 *POWER_DOWN_STATUS - Power down status
 ***************************************************************************/
/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: reserved0 [31:03] */
#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_reserved0_MASK           0xfffffff8
#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_reserved0_SHIFT          3

/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: SSPD [02:02] */
#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SSPD_MASK                0x00000004
#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SSPD_SHIFT               2
#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SSPD_DEFAULT             0

/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: SRPD [01:01] */
#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SRPD_MASK                0x00000002
#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SRPD_SHIFT               1
#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_SRPD_DEFAULT             0

/* MEMC_DDR_1 :: POWER_DOWN_STATUS :: PPD [00:00] */
#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_PPD_MASK                 0x00000001
#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_PPD_SHIFT                0
#define BCHP_MEMC_DDR_1_POWER_DOWN_STATUS_PPD_DEFAULT              0

/***************************************************************************
 *WARM_BOOT - Warm boot control registers
 ***************************************************************************/
/* MEMC_DDR_1 :: WARM_BOOT :: reserved0 [31:01] */
#define BCHP_MEMC_DDR_1_WARM_BOOT_reserved0_MASK                   0xfffffffe
#define BCHP_MEMC_DDR_1_WARM_BOOT_reserved0_SHIFT                  1

/* MEMC_DDR_1 :: WARM_BOOT :: WARM_BOOT [00:00] */
#define BCHP_MEMC_DDR_1_WARM_BOOT_WARM_BOOT_MASK                   0x00000001
#define BCHP_MEMC_DDR_1_WARM_BOOT_WARM_BOOT_SHIFT                  0
#define BCHP_MEMC_DDR_1_WARM_BOOT_WARM_BOOT_DEFAULT                0

/***************************************************************************
 *DRAM_TIMING_0 - DDR-SDRAM Timing Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRRD_NOP [31:24] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRRD_NOP_MASK                0xff000000
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRRD_NOP_SHIFT               24
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRRD_NOP_DEFAULT             6

/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRCD_NOP [23:16] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRCD_NOP_MASK                0x00ff0000
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRCD_NOP_SHIFT               16
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRCD_NOP_DEFAULT             8

/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRP_NOP [15:08] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRP_NOP_MASK                 0x0000ff00
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRP_NOP_SHIFT                8
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRP_NOP_DEFAULT              8

/* MEMC_DDR_1 :: DRAM_TIMING_0 :: TRAS_NOP [07:00] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRAS_NOP_MASK                0x000000ff
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRAS_NOP_SHIFT               0
#define BCHP_MEMC_DDR_1_DRAM_TIMING_0_TRAS_NOP_DEFAULT             20

/***************************************************************************
 *DRAM_TIMING_1 - DDR-SDRAM Timing Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_TIMING_1 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_reserved0_MASK               0xffff0000
#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_reserved0_SHIFT              16

/* MEMC_DDR_1 :: DRAM_TIMING_1 :: TFAW_NOP [15:08] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TFAW_NOP_MASK                0x0000ff00
#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TFAW_NOP_SHIFT               8
#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TFAW_NOP_DEFAULT             27

/* MEMC_DDR_1 :: DRAM_TIMING_1 :: TRTP_NOP [07:00] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TRTP_NOP_MASK                0x000000ff
#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TRTP_NOP_SHIFT               0
#define BCHP_MEMC_DDR_1_DRAM_TIMING_1_TRTP_NOP_DEFAULT             4

/***************************************************************************
 *DRAM_TIMING_2 - Read to Write & write to read timing register
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_TIMING_2 :: reserved0 [31:16] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_reserved0_MASK               0xffff0000
#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_reserved0_SHIFT              16

/* MEMC_DDR_1 :: DRAM_TIMING_2 :: WR2RD_NOP [15:08] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RD_NOP_MASK               0x0000ff00
#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RD_NOP_SHIFT              8
#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_WR2RD_NOP_DEFAULT            14

/* MEMC_DDR_1 :: DRAM_TIMING_2 :: RD2WR_NOP [07:00] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_RD2WR_NOP_MASK               0x000000ff
#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_RD2WR_NOP_SHIFT              0
#define BCHP_MEMC_DDR_1_DRAM_TIMING_2_RD2WR_NOP_DEFAULT            9

/***************************************************************************
 *DRAM_TIMING_3 - DDR-SDRAM Timing Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_TIMING_3 :: reserved0 [31:24] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_reserved0_MASK               0xff000000
#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_reserved0_SHIFT              24

/* MEMC_DDR_1 :: DRAM_TIMING_3 :: CKENB_CKE_DELAY [23:19] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_CKENB_CKE_DELAY_MASK         0x00f80000
#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_CKENB_CKE_DELAY_SHIFT        19
#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_CKENB_CKE_DELAY_DEFAULT      12

/* MEMC_DDR_1 :: DRAM_TIMING_3 :: POWERUP_CKE_DELAY [18:10] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_POWERUP_CKE_DELAY_MASK       0x0007fc00
#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_POWERUP_CKE_DELAY_SHIFT      10
#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_POWERUP_CKE_DELAY_DEFAULT    94

/* MEMC_DDR_1 :: DRAM_TIMING_3 :: DLL_LOCK_DELAY [09:00] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_DLL_LOCK_DELAY_MASK          0x000003ff
#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_DLL_LOCK_DELAY_SHIFT         0
#define BCHP_MEMC_DDR_1_DRAM_TIMING_3_DLL_LOCK_DELAY_DEFAULT       512

/***************************************************************************
 *DRAM_TIMING_4 - DDR-SDRAM Timing Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_TIMING_4 :: reserved0 [31:29] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_reserved0_MASK               0xe0000000
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_reserved0_SHIFT              29

/* MEMC_DDR_1 :: DRAM_TIMING_4 :: PRECHARGE_ALL_DELAY [28:24] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_MASK     0x1f000000
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_SHIFT    24
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_PRECHARGE_ALL_DELAY_DEFAULT  8

/* MEMC_DDR_1 :: DRAM_TIMING_4 :: LOAD_MODE_DELAY [23:19] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_LOAD_MODE_DELAY_MASK         0x00f80000
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_LOAD_MODE_DELAY_SHIFT        19
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_LOAD_MODE_DELAY_DEFAULT      12

/* MEMC_DDR_1 :: DRAM_TIMING_4 :: REFRESH_DELAY [18:10] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_REFRESH_DELAY_MASK           0x0007fc00
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_REFRESH_DELAY_SHIFT          10
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_REFRESH_DELAY_DEFAULT        88

/* MEMC_DDR_1 :: DRAM_TIMING_4 :: ZQCALIB_DELAY [09:00] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_ZQCALIB_DELAY_MASK           0x000003ff
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_ZQCALIB_DELAY_SHIFT          0
#define BCHP_MEMC_DDR_1_DRAM_TIMING_4_ZQCALIB_DELAY_DEFAULT        512

/***************************************************************************
 *DRAM_TIMING_5 - DDR-SDRAM Timing Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_TIMING_5 :: reserved0 [31:29] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_reserved0_MASK               0xe0000000
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_reserved0_SHIFT              29

/* MEMC_DDR_1 :: DRAM_TIMING_5 :: CKE_ASSETION_DELAY [28:19] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_ASSETION_DELAY_MASK      0x1ff80000
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_ASSETION_DELAY_SHIFT     19
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_ASSETION_DELAY_DEFAULT   261

/* MEMC_DDR_1 :: DRAM_TIMING_5 :: CKE_MIN_WIDTH [18:15] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_MIN_WIDTH_MASK           0x00078000
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_MIN_WIDTH_SHIFT          15
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_CKE_MIN_WIDTH_DEFAULT        3

/* MEMC_DDR_1 :: DRAM_TIMING_5 :: PWDN_EXIT_DELAY [14:10] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_PWDN_EXIT_DELAY_MASK         0x00007c00
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_PWDN_EXIT_DELAY_SHIFT        10
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_PWDN_EXIT_DELAY_DEFAULT      13

/* MEMC_DDR_1 :: DRAM_TIMING_5 :: SELFREF_EXIT_DELAY [09:00] */
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_SELFREF_EXIT_DELAY_MASK      0x000003ff
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_SELFREF_EXIT_DELAY_SHIFT     0
#define BCHP_MEMC_DDR_1_DRAM_TIMING_5_SELFREF_EXIT_DELAY_DEFAULT   512

/***************************************************************************
 *CNTRLR_START_SEQ - Memory Controller Sequencer Enable
 ***************************************************************************/
/* MEMC_DDR_1 :: CNTRLR_START_SEQ :: reserved0 [31:01] */
#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_reserved0_MASK            0xfffffffe
#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_reserved0_SHIFT           1

/* MEMC_DDR_1 :: CNTRLR_START_SEQ :: START_SEQ [00:00] */
#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_START_SEQ_MASK            0x00000001
#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_START_SEQ_SHIFT           0
#define BCHP_MEMC_DDR_1_CNTRLR_START_SEQ_START_SEQ_DEFAULT         0

/***************************************************************************
 *CNTRLR_SM_TIMEOUT - Memory Controller , state machine timeout register.
 ***************************************************************************/
/* MEMC_DDR_1 :: CNTRLR_SM_TIMEOUT :: reserved0 [31:17] */
#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_reserved0_MASK           0xfffe0000
#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_reserved0_SHIFT          17

/* MEMC_DDR_1 :: CNTRLR_SM_TIMEOUT :: ENABLE [16:16] */
#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_ENABLE_MASK              0x00010000
#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_ENABLE_SHIFT             16
#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_ENABLE_DEFAULT           0

/* MEMC_DDR_1 :: CNTRLR_SM_TIMEOUT :: COUNT [15:00] */
#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_COUNT_MASK               0x0000ffff
#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_CNTRLR_SM_TIMEOUT_COUNT_DEFAULT            65535

/***************************************************************************
 *BANK_STATUS - Memory Controller, Bank Status Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: BANK_STATUS :: reserved0 [31:08] */
#define BCHP_MEMC_DDR_1_BANK_STATUS_reserved0_MASK                 0xffffff00
#define BCHP_MEMC_DDR_1_BANK_STATUS_reserved0_SHIFT                8

/* MEMC_DDR_1 :: BANK_STATUS :: BANK7_STATUS [07:07] */
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK7_STATUS_MASK              0x00000080
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK7_STATUS_SHIFT             7
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK7_STATUS_DEFAULT           1

/* MEMC_DDR_1 :: BANK_STATUS :: BANK6_STATUS [06:06] */
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK6_STATUS_MASK              0x00000040
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK6_STATUS_SHIFT             6
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK6_STATUS_DEFAULT           1

/* MEMC_DDR_1 :: BANK_STATUS :: BANK5_STATUS [05:05] */
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK5_STATUS_MASK              0x00000020
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK5_STATUS_SHIFT             5
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK5_STATUS_DEFAULT           1

/* MEMC_DDR_1 :: BANK_STATUS :: BANK4_STATUS [04:04] */
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK4_STATUS_MASK              0x00000010
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK4_STATUS_SHIFT             4
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK4_STATUS_DEFAULT           1

/* MEMC_DDR_1 :: BANK_STATUS :: BANK3_STATUS [03:03] */
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK3_STATUS_MASK              0x00000008
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK3_STATUS_SHIFT             3
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK3_STATUS_DEFAULT           1

/* MEMC_DDR_1 :: BANK_STATUS :: BANK2_STATUS [02:02] */
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK2_STATUS_MASK              0x00000004
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK2_STATUS_SHIFT             2
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK2_STATUS_DEFAULT           1

/* MEMC_DDR_1 :: BANK_STATUS :: BANK1_STATUS [01:01] */
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK1_STATUS_MASK              0x00000002
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK1_STATUS_SHIFT             1
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK1_STATUS_DEFAULT           1

/* MEMC_DDR_1 :: BANK_STATUS :: BANK0_STATUS [00:00] */
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK0_STATUS_MASK              0x00000001
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK0_STATUS_SHIFT             0
#define BCHP_MEMC_DDR_1_BANK_STATUS_BANK0_STATUS_DEFAULT           1

/***************************************************************************
 *TESTER_LATENCY - Memory Controller, Tester Latency Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: TESTER_LATENCY :: reserved0 [31:07] */
#define BCHP_MEMC_DDR_1_TESTER_LATENCY_reserved0_MASK              0xffffff80
#define BCHP_MEMC_DDR_1_TESTER_LATENCY_reserved0_SHIFT             7

/* MEMC_DDR_1 :: TESTER_LATENCY :: TLATENCY_SEL [06:00] */
#define BCHP_MEMC_DDR_1_TESTER_LATENCY_TLATENCY_SEL_MASK           0x0000007f
#define BCHP_MEMC_DDR_1_TESTER_LATENCY_TLATENCY_SEL_SHIFT          0
#define BCHP_MEMC_DDR_1_TESTER_LATENCY_TLATENCY_SEL_DEFAULT        0

/***************************************************************************
 *DTPM_BYTE0 - Memory Controller, DATA_PINMAP_BYTE0_SEL Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved0 [31:31] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved0_MASK                  0x80000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved0_SHIFT                 31

/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_7_SEL [30:28] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_7_SEL_MASK                   0x70000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_7_SEL_SHIFT                  28
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_7_SEL_DEFAULT                7

/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved1 [27:27] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved1_MASK                  0x08000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved1_SHIFT                 27

/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_6_SEL [26:24] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_6_SEL_MASK                   0x07000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_6_SEL_SHIFT                  24
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_6_SEL_DEFAULT                6

/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved2 [23:23] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved2_MASK                  0x00800000
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved2_SHIFT                 23

/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_5_SEL [22:20] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_5_SEL_MASK                   0x00700000
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_5_SEL_SHIFT                  20
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_5_SEL_DEFAULT                5

/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved3 [19:19] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved3_MASK                  0x00080000
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved3_SHIFT                 19

/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_4_SEL [18:16] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_4_SEL_MASK                   0x00070000
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_4_SEL_SHIFT                  16
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_4_SEL_DEFAULT                4

/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved4 [15:15] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved4_MASK                  0x00008000
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved4_SHIFT                 15

/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_3_SEL [14:12] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_3_SEL_MASK                   0x00007000
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_3_SEL_SHIFT                  12
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_3_SEL_DEFAULT                3

/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved5 [11:11] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved5_MASK                  0x00000800
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved5_SHIFT                 11

/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_2_SEL [10:08] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_2_SEL_MASK                   0x00000700
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_2_SEL_SHIFT                  8
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_2_SEL_DEFAULT                2

/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved6 [07:07] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved6_MASK                  0x00000080
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved6_SHIFT                 7

/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_1_SEL [06:04] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_1_SEL_MASK                   0x00000070
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_1_SEL_SHIFT                  4
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_1_SEL_DEFAULT                1

/* MEMC_DDR_1 :: DTPM_BYTE0 :: reserved7 [03:03] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved7_MASK                  0x00000008
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_reserved7_SHIFT                 3

/* MEMC_DDR_1 :: DTPM_BYTE0 :: DT_0_SEL [02:00] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_0_SEL_MASK                   0x00000007
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_0_SEL_SHIFT                  0
#define BCHP_MEMC_DDR_1_DTPM_BYTE0_DT_0_SEL_DEFAULT                0

/***************************************************************************
 *DTPM_BYTE1 - Memory Controller, DATA_PINMAP_BYTE1_SEL Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved0 [31:31] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved0_MASK                  0x80000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved0_SHIFT                 31

/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_7_SEL [30:28] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_7_SEL_MASK                   0x70000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_7_SEL_SHIFT                  28
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_7_SEL_DEFAULT                7

/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved1 [27:27] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved1_MASK                  0x08000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved1_SHIFT                 27

/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_6_SEL [26:24] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_6_SEL_MASK                   0x07000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_6_SEL_SHIFT                  24
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_6_SEL_DEFAULT                6

/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved2 [23:23] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved2_MASK                  0x00800000
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved2_SHIFT                 23

/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_5_SEL [22:20] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_5_SEL_MASK                   0x00700000
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_5_SEL_SHIFT                  20
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_5_SEL_DEFAULT                5

/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved3 [19:19] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved3_MASK                  0x00080000
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved3_SHIFT                 19

/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_4_SEL [18:16] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_4_SEL_MASK                   0x00070000
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_4_SEL_SHIFT                  16
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_4_SEL_DEFAULT                4

/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved4 [15:15] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved4_MASK                  0x00008000
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved4_SHIFT                 15

/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_3_SEL [14:12] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_3_SEL_MASK                   0x00007000
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_3_SEL_SHIFT                  12
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_3_SEL_DEFAULT                3

/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved5 [11:11] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved5_MASK                  0x00000800
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved5_SHIFT                 11

/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_2_SEL [10:08] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_2_SEL_MASK                   0x00000700
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_2_SEL_SHIFT                  8
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_2_SEL_DEFAULT                2

/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved6 [07:07] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved6_MASK                  0x00000080
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved6_SHIFT                 7

/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_1_SEL [06:04] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_1_SEL_MASK                   0x00000070
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_1_SEL_SHIFT                  4
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_1_SEL_DEFAULT                1

/* MEMC_DDR_1 :: DTPM_BYTE1 :: reserved7 [03:03] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved7_MASK                  0x00000008
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_reserved7_SHIFT                 3

/* MEMC_DDR_1 :: DTPM_BYTE1 :: DT_0_SEL [02:00] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_0_SEL_MASK                   0x00000007
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_0_SEL_SHIFT                  0
#define BCHP_MEMC_DDR_1_DTPM_BYTE1_DT_0_SEL_DEFAULT                0

/***************************************************************************
 *DTPM_BYTE2 - Memory Controller, DATA_PINMAP_BYTE2_SEL Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved0 [31:31] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved0_MASK                  0x80000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved0_SHIFT                 31

/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_7_SEL [30:28] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_7_SEL_MASK                   0x70000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_7_SEL_SHIFT                  28
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_7_SEL_DEFAULT                7

/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved1 [27:27] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved1_MASK                  0x08000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved1_SHIFT                 27

/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_6_SEL [26:24] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_6_SEL_MASK                   0x07000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_6_SEL_SHIFT                  24
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_6_SEL_DEFAULT                6

/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved2 [23:23] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved2_MASK                  0x00800000
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved2_SHIFT                 23

/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_5_SEL [22:20] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_5_SEL_MASK                   0x00700000
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_5_SEL_SHIFT                  20
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_5_SEL_DEFAULT                5

/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved3 [19:19] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved3_MASK                  0x00080000
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved3_SHIFT                 19

/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_4_SEL [18:16] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_4_SEL_MASK                   0x00070000
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_4_SEL_SHIFT                  16
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_4_SEL_DEFAULT                4

/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved4 [15:15] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved4_MASK                  0x00008000
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved4_SHIFT                 15

/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_3_SEL [14:12] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_3_SEL_MASK                   0x00007000
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_3_SEL_SHIFT                  12
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_3_SEL_DEFAULT                3

/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved5 [11:11] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved5_MASK                  0x00000800
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved5_SHIFT                 11

/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_2_SEL [10:08] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_2_SEL_MASK                   0x00000700
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_2_SEL_SHIFT                  8
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_2_SEL_DEFAULT                2

/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved6 [07:07] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved6_MASK                  0x00000080
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved6_SHIFT                 7

/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_1_SEL [06:04] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_1_SEL_MASK                   0x00000070
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_1_SEL_SHIFT                  4
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_1_SEL_DEFAULT                1

/* MEMC_DDR_1 :: DTPM_BYTE2 :: reserved7 [03:03] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved7_MASK                  0x00000008
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_reserved7_SHIFT                 3

/* MEMC_DDR_1 :: DTPM_BYTE2 :: DT_0_SEL [02:00] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_0_SEL_MASK                   0x00000007
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_0_SEL_SHIFT                  0
#define BCHP_MEMC_DDR_1_DTPM_BYTE2_DT_0_SEL_DEFAULT                0

/***************************************************************************
 *DTPM_BYTE3 - Memory Controller, DATA_PINMAP_BYTE3_SEL Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved0 [31:31] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved0_MASK                  0x80000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved0_SHIFT                 31

/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_7_SEL [30:28] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_7_SEL_MASK                   0x70000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_7_SEL_SHIFT                  28
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_7_SEL_DEFAULT                7

/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved1 [27:27] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved1_MASK                  0x08000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved1_SHIFT                 27

/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_6_SEL [26:24] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_6_SEL_MASK                   0x07000000
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_6_SEL_SHIFT                  24
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_6_SEL_DEFAULT                6

/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved2 [23:23] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved2_MASK                  0x00800000
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved2_SHIFT                 23

/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_5_SEL [22:20] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_5_SEL_MASK                   0x00700000
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_5_SEL_SHIFT                  20
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_5_SEL_DEFAULT                5

/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved3 [19:19] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved3_MASK                  0x00080000
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved3_SHIFT                 19

/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_4_SEL [18:16] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_4_SEL_MASK                   0x00070000
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_4_SEL_SHIFT                  16
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_4_SEL_DEFAULT                4

/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved4 [15:15] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved4_MASK                  0x00008000
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved4_SHIFT                 15

/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_3_SEL [14:12] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_3_SEL_MASK                   0x00007000
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_3_SEL_SHIFT                  12
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_3_SEL_DEFAULT                3

/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved5 [11:11] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved5_MASK                  0x00000800
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved5_SHIFT                 11

/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_2_SEL [10:08] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_2_SEL_MASK                   0x00000700
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_2_SEL_SHIFT                  8
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_2_SEL_DEFAULT                2

/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved6 [07:07] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved6_MASK                  0x00000080
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved6_SHIFT                 7

/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_1_SEL [06:04] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_1_SEL_MASK                   0x00000070
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_1_SEL_SHIFT                  4
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_1_SEL_DEFAULT                1

/* MEMC_DDR_1 :: DTPM_BYTE3 :: reserved7 [03:03] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved7_MASK                  0x00000008
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_reserved7_SHIFT                 3

/* MEMC_DDR_1 :: DTPM_BYTE3 :: DT_0_SEL [02:00] */
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_0_SEL_MASK                   0x00000007
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_0_SEL_SHIFT                  0
#define BCHP_MEMC_DDR_1_DTPM_BYTE3_DT_0_SEL_DEFAULT                0

/***************************************************************************
 *DRAM_DDR3_RESET_PERIOD - Memory Controller, DDR3 DRAM reset Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: DRAM_DDR3_RESET_PERIOD :: reserved0 [31:20] */
#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_reserved0_MASK      0xfff00000
#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_reserved0_SHIFT     20

/* MEMC_DDR_1 :: DRAM_DDR3_RESET_PERIOD :: DRAM_RESET_PERIOD [19:00] */
#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_MASK 0x000fffff
#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_SHIFT 0
#define BCHP_MEMC_DDR_1_DRAM_DDR3_RESET_PERIOD_DRAM_RESET_PERIOD_DEFAULT 43200

/***************************************************************************
 *STAT_CONTROL - Statistics Control register
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CONTROL :: reserved0 [31:09] */
#define BCHP_MEMC_DDR_1_STAT_CONTROL_reserved0_MASK                0xfffffe00
#define BCHP_MEMC_DDR_1_STAT_CONTROL_reserved0_SHIFT               9

/* MEMC_DDR_1 :: STAT_CONTROL :: COUNTER_MODE [08:08] */
#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_MASK             0x00000100
#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_SHIFT            8
#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_DEFAULT          0
#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_MAX_MIN_FUNCT    1
#define BCHP_MEMC_DDR_1_STAT_CONTROL_COUNTER_MODE_NORMAL           0

/* MEMC_DDR_1 :: STAT_CONTROL :: STAT_ENABLE [07:07] */
#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_MASK              0x00000080
#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_SHIFT             7
#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_DEFAULT           0
#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_ENABLE            1
#define BCHP_MEMC_DDR_1_STAT_CONTROL_STAT_ENABLE_DISABLE           0

/* MEMC_DDR_1 :: STAT_CONTROL :: CLIENT_ID [06:00] */
#define BCHP_MEMC_DDR_1_STAT_CONTROL_CLIENT_ID_MASK                0x0000007f
#define BCHP_MEMC_DDR_1_STAT_CONTROL_CLIENT_ID_SHIFT               0
#define BCHP_MEMC_DDR_1_STAT_CONTROL_CLIENT_ID_DEFAULT             0

/***************************************************************************
 *STAT_TIMER - Statistics Timer
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_TIMER :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_TIMER_COUNT_MASK                      0xffffffff
#define BCHP_MEMC_DDR_1_STAT_TIMER_COUNT_SHIFT                     0
#define BCHP_MEMC_DDR_1_STAT_TIMER_COUNT_DEFAULT                   0

/***************************************************************************
 *STAT_IDLE_NOP - DRAM Idle_NOP Cycle Count Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_IDLE_NOP :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP_COUNT_MASK                   0xffffffff
#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP_COUNT_SHIFT                  0
#define BCHP_MEMC_DDR_1_STAT_IDLE_NOP_COUNT_DEFAULT                0

/***************************************************************************
 *STAT_MAX_IDLE_NOP - Maximum DRAM idle_NOP cycle count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MAX_IDLE_NOP :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP_COUNT_MASK               0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_STAT_MAX_IDLE_NOP_COUNT_DEFAULT            0

/***************************************************************************
 *STAT_CAS_ALL - CAS Count Register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_ALL_COUNT_MASK                    0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_ALL_COUNT_SHIFT                   0
#define BCHP_MEMC_DDR_1_STAT_CAS_ALL_COUNT_DEFAULT                 0

/***************************************************************************
 *STAT_MAX_CAS_ALL - Maximum DRAM CAS cycle count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MAX_CAS_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL_COUNT_MASK                0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL_COUNT_SHIFT               0
#define BCHP_MEMC_DDR_1_STAT_MAX_CAS_ALL_COUNT_DEFAULT             0

/***************************************************************************
 *STAT_PENALTY_ALL - DRAM Penalty Cycle Count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_PENALTY_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL_COUNT_MASK                0xffffffff
#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL_COUNT_SHIFT               0
#define BCHP_MEMC_DDR_1_STAT_PENALTY_ALL_COUNT_DEFAULT             0

/***************************************************************************
 *STAT_MAX_TRANS_CYCLES_ALL - Maximum number of transactions cycles (CAS+Penalty_ALL).
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MAX_TRANS_CYCLES_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL_COUNT_SHIFT      0
#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_CYCLES_ALL_COUNT_DEFAULT    0

/***************************************************************************
 *STAT_TRANS_READ_ALL - Number of overall system memory read transactions.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_TRANS_READ_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_TRANS_READ_ALL_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_TRANS_WRITE_ALL - Number of overall system memory write transactions.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_TRANS_WRITE_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL_COUNT_MASK            0xffffffff
#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL_COUNT_SHIFT           0
#define BCHP_MEMC_DDR_1_STAT_TRANS_WRITE_ALL_COUNT_DEFAULT         0

/***************************************************************************
 *STAT_MAX_TRANS_ALL - Maximum Number of Overall System memory transactions.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MAX_TRANS_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_MAX_TRANS_ALL_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_MIN_TRANS_ALL - Minimum Number of Overall System memory transactions.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MIN_TRANS_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_ALL_COUNT_DEFAULT           4294967295

/***************************************************************************
 *STAT_CLIENT_SERVICE_CAS - Service CAS Cycle Count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_CAS :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS_COUNT_MASK         0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS_COUNT_SHIFT        0
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_CAS_COUNT_DEFAULT      0

/***************************************************************************
 *STAT_MAX_CLIENT_SERVICE_CAS - Maximum service CAS cycle count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_CAS :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CAS_COUNT_DEFAULT  0

/***************************************************************************
 *STAT_MIN_CLIENT_SERVICE_CAS - Minimum service CAS cycle count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_CAS :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_MASK     0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_SHIFT    0
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CAS_COUNT_DEFAULT  4294967295

/***************************************************************************
 *STAT_CLIENT_SERVICE_INTR_PENALTY - Service Intra DRAM Penalty Cycle Count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_INTR_PENALTY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_INTR_PENALTY_COUNT_DEFAULT 0

/***************************************************************************
 *STAT_CLIENT_SERVICE_POST_PENALTY - Service Post DRAM Penalty Cycle Count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_POST_PENALTY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_POST_PENALTY_COUNT_DEFAULT 0

/***************************************************************************
 *STAT_MAX_CLIENT_SERVICE_CYCLES - Maximum service cycle count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 0

/***************************************************************************
 *STAT_MIN_CLIENT_SERVICE_CYCLES - Minimum service cycle count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_CYCLES :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_MASK  0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_CYCLES_COUNT_DEFAULT 4294967295

/***************************************************************************
 *STAT_CLIENT_SERVICE_TRANS_READ - Service Read Transaction Count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_TRANS_READ :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_MASK  0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_READ_COUNT_DEFAULT 0

/***************************************************************************
 *STAT_CLIENT_SERVICE_TRANS_WRITE - Service Write Transaction Count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_TRANS_WRITE :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_TRANS_WRITE_COUNT_DEFAULT 0

/***************************************************************************
 *STAT_MAX_CLIENT_SERVICE_TRANS - Maximum service Transaction count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 0

/***************************************************************************
 *STAT_MIN_CLIENT_SERVICE_TRANS - Minimum service cycle Transaction register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_TRANS :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_MASK   0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_SHIFT  0
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_TRANS_COUNT_DEFAULT 4294967295

/***************************************************************************
 *STAT_CLIENT_SERVICE_LATENCY - Service Latency Count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY_COUNT_MASK     0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY_COUNT_SHIFT    0
#define BCHP_MEMC_DDR_1_STAT_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT  0

/***************************************************************************
 *STAT_MAX_CLIENT_SERVICE_LATENCY - Maximum Service Latency count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MAX_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_1_STAT_MAX_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 0

/***************************************************************************
 *STAT_MIN_CLIENT_SERVICE_LATENCY - Minimum Service Latency count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MIN_CLIENT_SERVICE_LATENCY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_1_STAT_MIN_CLIENT_SERVICE_LATENCY_COUNT_DEFAULT 4294967295

/***************************************************************************
 *STAT_CLIENT_ABS_MAX_SERVICE_LATENCY - Absolute Minimum Service Latency count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CLIENT_ABS_MAX_SERVICE_LATENCY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MAX_SERVICE_LATENCY_COUNT_DEFAULT 0

/***************************************************************************
 *STAT_CLIENT_ABS_MIN_SERVICE_LATENCY - Absolute Maximum Service Latency count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CLIENT_ABS_MIN_SERVICE_LATENCY :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_MASK 0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_SHIFT 0
#define BCHP_MEMC_DDR_1_STAT_CLIENT_ABS_MIN_SERVICE_LATENCY_COUNT_DEFAULT 4294967295

/***************************************************************************
 *STAT_REFRESH - Total number of refreshes issuedr.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_REFRESH :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_REFRESH_COUNT_MASK                    0xffffffff
#define BCHP_MEMC_DDR_1_STAT_REFRESH_COUNT_SHIFT                   0
#define BCHP_MEMC_DDR_1_STAT_REFRESH_COUNT_DEFAULT                 0

/***************************************************************************
 *STAT_CAS_CLIENT_0 - CAS cycle count register for client 0.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_0 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0_COUNT_MASK               0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_0_COUNT_DEFAULT            0

/***************************************************************************
 *STAT_CAS_CLIENT_1 - CAS cycle count register for client 1.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_1 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1_COUNT_MASK               0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_1_COUNT_DEFAULT            0

/***************************************************************************
 *STAT_CAS_CLIENT_2 - CAS cycle count register for client 2.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_2 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2_COUNT_MASK               0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_2_COUNT_DEFAULT            0

/***************************************************************************
 *STAT_CAS_CLIENT_3 - CAS cycle count register for client 3.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_3 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3_COUNT_MASK               0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_3_COUNT_DEFAULT            0

/***************************************************************************
 *STAT_CAS_CLIENT_4 - CAS cycle count register for client 4.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_4 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4_COUNT_MASK               0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_4_COUNT_DEFAULT            0

/***************************************************************************
 *STAT_CAS_CLIENT_5 - CAS cycle count register for client 5.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_5 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5_COUNT_MASK               0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_5_COUNT_DEFAULT            0

/***************************************************************************
 *STAT_CAS_CLIENT_6 - CAS cycle count register for client 6.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_6 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6_COUNT_MASK               0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_6_COUNT_DEFAULT            0

/***************************************************************************
 *STAT_CAS_CLIENT_7 - CAS cycle count register for client 7.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_7 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7_COUNT_MASK               0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_7_COUNT_DEFAULT            0

/***************************************************************************
 *STAT_CAS_CLIENT_8 - CAS cycle count register for client 8.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_8 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8_COUNT_MASK               0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_8_COUNT_DEFAULT            0

/***************************************************************************
 *STAT_CAS_CLIENT_9 - CAS cycle count register for client 9.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_9 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9_COUNT_MASK               0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9_COUNT_SHIFT              0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_9_COUNT_DEFAULT            0

/***************************************************************************
 *STAT_CAS_CLIENT_10 - CAS cycle count register for client 10.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_10 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_10_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_11 - CAS cycle count register for client 11.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_11 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_11_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_12 - CAS cycle count register for client 12.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_12 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_12_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_13 - CAS cycle count register for client 13.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_13 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_13_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_14 - CAS cycle count register for client 14.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_14 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_14_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_15 - CAS cycle count register for client 15.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_15 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_15_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_16 - CAS cycle count register for client 16.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_16 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_16_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_17 - CAS cycle count register for client 17.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_17 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_17_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_18 - CAS cycle count register for client 18.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_18 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_18_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_19 - CAS cycle count register for client 19.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_19 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_19_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_20 - CAS cycle count register for client 20.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_20 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_20_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_21 - CAS cycle count register for client 21.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_21 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_21_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_22 - CAS cycle count register for client 22.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_22 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_22_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_23 - CAS cycle count register for client 23.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_23 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_23_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_24 - CAS cycle count register for client 24.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_24 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_24_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_25 - CAS cycle count register for client 25.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_25 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_25_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_26 - CAS cycle count register for client 26.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_26 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_26_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_27 - CAS cycle count register for client 27.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_27 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_27_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_28 - CAS cycle count register for client 28.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_28 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_28_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_29 - CAS cycle count register for client 29.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_29 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_29_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_30 - CAS cycle count register for client 30.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_30 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_30_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_31 - CAS cycle count register for client 31.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_31 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_31_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_32 - CAS cycle count register for client 32.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_32 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_32_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_33 - CAS cycle count register for client 33.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_33 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_33_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_34 - CAS cycle count register for client 34.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_34 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_34_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_35 - CAS cycle count register for client 35.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_35 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_35_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_36 - CAS cycle count register for client 36.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_36 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_36_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_37 - CAS cycle count register for client 37.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_37 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_37_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_38 - CAS cycle count register for client 38.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_38 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_38_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_39 - CAS cycle count register for client 39.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_39 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_39_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_40 - CAS cycle count register for client 40.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_40 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_40_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_41 - CAS cycle count register for client 41.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_41 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_41_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_42 - CAS cycle count register for client 42.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_42 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_42_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_43 - CAS cycle count register for client 43.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_43 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_43_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_44 - CAS cycle count register for client 44.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_44 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_44_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_45 - CAS cycle count register for client 45.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_45 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_45_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_46 - CAS cycle count register for client 46.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_46 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_46_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_47 - CAS cycle count register for client 47.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_47 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_47_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_48 - CAS cycle count register for client 48.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_48 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_48_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_49 - CAS cycle count register for client 49.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_49 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_49_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_50 - CAS cycle count register for client 50.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_50 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_50_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_51 - CAS cycle count register for client 51.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_51 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_51_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_52 - CAS cycle count register for client 52.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_52 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_52_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_53 - CAS cycle count register for client 53.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_53 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_53_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_54 - CAS cycle count register for client 54.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_54 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_54_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_55 - CAS cycle count register for client 55.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_55 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_55_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_56 - CAS cycle count register for client 56.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_56 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_56_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_57 - CAS cycle count register for client 57.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_57 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_57_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_58 - CAS cycle count register for client 58.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_58 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_58_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_59 - CAS cycle count register for client 59.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_59 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_59_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_60 - CAS cycle count register for client 60.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_60 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_60_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_61 - CAS cycle count register for client 61.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_61 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_61_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_62 - CAS cycle count register for client 62.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_62 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_62_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_63 - CAS cycle count register for client 63.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_63 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_63_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_64 - CAS cycle count register for client 64.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_64 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_64_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_65 - CAS cycle count register for client 65.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_65 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_65_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_66 - CAS cycle count register for client 66.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_66 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_66_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_67 - CAS cycle count register for client 67.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_67 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_67_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_68 - CAS cycle count register for client 68.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_68 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_68_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_69 - CAS cycle count register for client 69.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_69 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_69_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_70 - CAS cycle count register for client 70.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_70 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_70_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_71 - CAS cycle count register for client 71.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_71 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_71_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_72 - CAS cycle count register for client 72.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_72 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_72_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_73 - CAS cycle count register for client 73.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_73 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_73_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_74 - CAS cycle count register for client 74.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_74 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_74_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_75 - CAS cycle count register for client 75.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_75 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_75_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_76 - CAS cycle count register for client 76.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_76 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_76_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_77 - CAS cycle count register for client 77.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_77 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_77_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_78 - CAS cycle count register for client 78.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_78 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_78_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_79 - CAS cycle count register for client 79.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_79 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_79_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_80 - CAS cycle count register for client 80.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_80 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_80_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_81 - CAS cycle count register for client 81.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_81 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_81_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_82 - CAS cycle count register for client 82.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_82 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_82_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_83 - CAS cycle count register for client 83.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_83 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_83_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_84 - CAS cycle count register for client 84.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_84 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_84_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_85 - CAS cycle count register for client 85.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_85 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_85_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_86 - CAS cycle count register for client 86.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_86 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_86_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_87 - CAS cycle count register for client 87.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_87 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_87_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_88 - CAS cycle count register for client 88.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_88 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_88_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_89 - CAS cycle count register for client 89.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_89 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_89_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_90 - CAS cycle count register for client 90.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_90 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_90_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_91 - CAS cycle count register for client 91.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_91 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_91_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_92 - CAS cycle count register for client 92.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_92 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_92_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_93 - CAS cycle count register for client 93.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_93 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_93_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_94 - CAS cycle count register for client 94.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_94 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_94_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_95 - CAS cycle count register for client 95.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_95 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_95_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_96 - CAS cycle count register for client 96.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_96 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_96_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_97 - CAS cycle count register for client 97.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_97 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_97_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_98 - CAS cycle count register for client 98.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_98 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_98_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_99 - CAS cycle count register for client 99.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_99 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99_COUNT_MASK              0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99_COUNT_SHIFT             0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_99_COUNT_DEFAULT           0

/***************************************************************************
 *STAT_CAS_CLIENT_100 - CAS cycle count register for client 100.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_100 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_100_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_101 - CAS cycle count register for client 101.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_101 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_101_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_102 - CAS cycle count register for client 102.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_102 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_102_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_103 - CAS cycle count register for client 103.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_103 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_103_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_104 - CAS cycle count register for client 104.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_104 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_104_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_105 - CAS cycle count register for client 105.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_105 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_105_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_106 - CAS cycle count register for client 106.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_106 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_106_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_107 - CAS cycle count register for client 107.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_107 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_107_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_108 - CAS cycle count register for client 108.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_108 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_108_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_109 - CAS cycle count register for client 109.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_109 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_109_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_110 - CAS cycle count register for client 110.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_110 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_110_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_111 - CAS cycle count register for client 111.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_111 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_111_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_112 - CAS cycle count register for client 112.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_112 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_112_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_113 - CAS cycle count register for client 113.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_113 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_113_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_114 - CAS cycle count register for client 114.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_114 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_114_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_115 - CAS cycle count register for client 115.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_115 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_115_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_116 - CAS cycle count register for client 116.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_116 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_116_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_117 - CAS cycle count register for client 117.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_117 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_117_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_118 - CAS cycle count register for client 118.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_118 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_118_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_119 - CAS cycle count register for client 119.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_119 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_119_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_120 - CAS cycle count register for client 120.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_120 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_120_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_121 - CAS cycle count register for client 121.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_121 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_121_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_122 - CAS cycle count register for client 122.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_122 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_122_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_123 - CAS cycle count register for client 123.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_123 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_123_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_124 - CAS cycle count register for client 124.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_124 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_124_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_125 - CAS cycle count register for client 125.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_125 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_125_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_126 - CAS cycle count register for client 126.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_126 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_126_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_CAS_CLIENT_127 - CAS cycle count register for client 127.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_CAS_CLIENT_127 :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127_COUNT_MASK             0xffffffff
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127_COUNT_SHIFT            0
#define BCHP_MEMC_DDR_1_STAT_CAS_CLIENT_127_COUNT_DEFAULT          0

/***************************************************************************
 *STAT_MIN_CAS_ALL - Minimum DRAM CAS cycle count register.
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MIN_CAS_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL_COUNT_MASK                0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL_COUNT_SHIFT               0
#define BCHP_MEMC_DDR_1_STAT_MIN_CAS_ALL_COUNT_DEFAULT             4294967295

/***************************************************************************
 *STAT_MIN_TRANS_CYCLES_ALL - Minimum number of transactions cycles (CAS+Penalty_ALL).
 ***************************************************************************/
/* MEMC_DDR_1 :: STAT_MIN_TRANS_CYCLES_ALL :: COUNT [31:00] */
#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL_COUNT_MASK       0xffffffff
#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL_COUNT_SHIFT      0
#define BCHP_MEMC_DDR_1_STAT_MIN_TRANS_CYCLES_ALL_COUNT_DEFAULT    4294967295

/***************************************************************************
 *MEMSYS_AUTO_INIT_CONTROL - MEMSYS Auto Init Control.
 ***************************************************************************/
/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: reserved0 [31:10] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_reserved0_MASK    0xfffffc00
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_reserved0_SHIFT   10

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_DIVIDER [09:09] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_MASK 0x00000200
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_SHIFT 9
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_DIVIDER_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_VDL_CALIB_AUTO_INIT [08:08] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_MASK 0x00000100
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_SHIFT 8
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_VDL_CALIB_AUTO_INIT_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_DRAM_INIT_DONE_SET [07:07] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_MASK 0x00000080
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_SHIFT 7
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_DRAM_INIT_DONE_SET_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_RESET [06:06] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_MASK 0x00000040
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_SHIFT 6
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_RESET_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_STRAP_VALID_SET [05:05] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_MASK 0x00000020
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_SHIFT 5
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_STRAP_VALID_SET_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_PHY_READY_SET [04:04] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_MASK 0x00000010
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_SHIFT 4
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_PHY_READY_SET_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_AUTO_INIT_ACTIVE_RESET [03:03] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_MASK 0x00000008
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_SHIFT 3
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_AUTO_INIT_ACTIVE_RESET_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET [02:02] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_MASK 0x00000004
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_SHIFT 2
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_OVERRIDE_SHIM_PLL_LOCK_TO_PHY_SET_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: SKIP_PHY_AUTO_INIT [01:01] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_MASK 0x00000002
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_SHIFT 1
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_SKIP_PHY_AUTO_INIT_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_CONTROL :: MEMSYS_AUTO_INIT_START [00:00] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_MASK 0x00000001
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_SHIFT 0
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_CONTROL_MEMSYS_AUTO_INIT_START_DEFAULT 0

/***************************************************************************
 *MEMSYS_AUTO_INIT_STATUS - MEMSYS Auto Init Status.
 ***************************************************************************/
/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: reserved0 [31:12] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_reserved0_MASK     0xfffff000
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_reserved0_SHIFT    12

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: MEMC_AUTO_INIT_STATES [11:06] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_MASK 0x00000fc0
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_SHIFT 6
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMC_AUTO_INIT_STATES_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: AUTO_INIT_ACTIVE [05:05] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_MASK 0x00000020
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_SHIFT 5
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_AUTO_INIT_ACTIVE_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: PHY_STRAP_VALID [04:04] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_MASK 0x00000010
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_SHIFT 4
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_STRAP_VALID_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: PHY_READY [03:03] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_READY_MASK     0x00000008
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_READY_SHIFT    3
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_PHY_READY_DEFAULT  0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: DRAM_INIT_DONE [02:02] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_MASK 0x00000004
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_SHIFT 2
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_DRAM_INIT_DONE_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_FAIL [01:01] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_MASK 0x00000002
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_SHIFT 1
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_FAIL_DEFAULT 0

/* MEMC_DDR_1 :: MEMSYS_AUTO_INIT_STATUS :: MEMSYS_AUTO_INIT_DONE [00:00] */
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_MASK 0x00000001
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_SHIFT 0
#define BCHP_MEMC_DDR_1_MEMSYS_AUTO_INIT_STATUS_MEMSYS_AUTO_INIT_DONE_DEFAULT 0

/***************************************************************************
 *PHY_VDL_CALIB_AUTO_INIT_OVERRIDE - PHY VDL calibrate override from memc auto init.
 ***************************************************************************/
/* MEMC_DDR_1 :: PHY_VDL_CALIB_AUTO_INIT_OVERRIDE :: PHY_VDL_CALIB_OVERRIDE_VAL [31:00] */
#define BCHP_MEMC_DDR_1_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_MASK 0xffffffff
#define BCHP_MEMC_DDR_1_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_SHIFT 0
#define BCHP_MEMC_DDR_1_PHY_VDL_CALIB_AUTO_INIT_OVERRIDE_PHY_VDL_CALIB_OVERRIDE_VAL_DEFAULT 268435456

/***************************************************************************
 *SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE - SHIM PLL pndiv override from memc auto init.
 ***************************************************************************/
/* MEMC_DDR_1 :: SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_PNDIV_OVERRIDE_VAL [31:00] */
#define BCHP_MEMC_DDR_1_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_MASK 0xffffffff
#define BCHP_MEMC_DDR_1_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_SHIFT 0
#define BCHP_MEMC_DDR_1_SHIM_PLL_PNDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_PNDIV_OVERRIDE_VAL_DEFAULT 598736896

/***************************************************************************
 *SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE - SHIM PLL mdiv override from memc auto init.
 ***************************************************************************/
/* MEMC_DDR_1 :: SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE :: SHIM_PLL_MDIV_OVERRIDE_VAL [31:00] */
#define BCHP_MEMC_DDR_1_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_MASK 0xffffffff
#define BCHP_MEMC_DDR_1_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_SHIFT 0
#define BCHP_MEMC_DDR_1_SHIM_PLL_MDIV_AUTO_INIT_OVERRIDE_SHIM_PLL_MDIV_OVERRIDE_VAL_DEFAULT 4099

/***************************************************************************
 *DYN_VDL_CMD_DLY - Dynamic VDL shmoo command delay.
 ***************************************************************************/
/* MEMC_DDR_1 :: DYN_VDL_CMD_DLY :: reserved0 [31:12] */
#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_reserved0_MASK             0xfffff000
#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_reserved0_SHIFT            12

/* MEMC_DDR_1 :: DYN_VDL_CMD_DLY :: END_CAS_DLY [11:06] */
#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_END_CAS_DLY_MASK           0x00000fc0
#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_END_CAS_DLY_SHIFT          6
#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_END_CAS_DLY_DEFAULT        0

/* MEMC_DDR_1 :: DYN_VDL_CMD_DLY :: START_CAS_DLY [05:00] */
#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_START_CAS_DLY_MASK         0x0000003f
#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_START_CAS_DLY_SHIFT        0
#define BCHP_MEMC_DDR_1_DYN_VDL_CMD_DLY_START_CAS_DLY_DEFAULT      0

#endif /* #ifndef BCHP_MEMC_DDR_1_H__ */

/* End of File */