include/linux/brcmstb/7425b0/bchp_ddr40_phy_word_lane_1_1.h

/***************************************************************************
 *     Copyright (c) 1999-2011, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Mon Apr 11 12:04:18 2011
 *                 MD5 Checksum         8cf142ad25caa9f873c54e8bb2bb1755
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_ddr40_phy_word_lane_1_1.h $
 * 
 * Hydra_Software_Devel/2   4/11/11 11:58p vanessah
 * SW7425-112: Update rdb files for 7425 B0.
 *
 ***************************************************************************/

#ifndef BCHP_DDR40_PHY_WORD_LANE_1_1_H__
#define BCHP_DDR40_PHY_WORD_LANE_1_1_H__

/***************************************************************************
 *DDR40_PHY_WORD_LANE_1_1 - DDR40 DDR40 word lane #1 control registers 1
 ***************************************************************************/
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE_RD_EN 0x003c6400 /* Read Enable Byte VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_W 0x003c6404 /* Write Byte VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_P 0x003c6408 /* Read Byte DQSP VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_R_N 0x003c640c /* Read Byte DQSN VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_W 0x003c6410 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_W 0x003c6414 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_W 0x003c6418 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_W 0x003c641c /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_W 0x003c6420 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_W 0x003c6424 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_W 0x003c6428 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_W 0x003c642c /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_DM_W 0x003c6430 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003c6434 /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003c6438 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003c643c /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003c6440 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003c6444 /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003c6448 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003c644c /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003c6450 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003c6454 /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003c6458 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003c645c /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003c6460 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003c6464 /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003c6468 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003c646c /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003c6470 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003c6474 /* Read Enable Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_W 0x003c64a4 /* Write Byte VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_P 0x003c64a8 /* Read Byte DQSP VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_R_N 0x003c64ac /* Read Byte DQSN VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_W 0x003c64b0 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_W 0x003c64b4 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_W 0x003c64b8 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_W 0x003c64bc /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_W 0x003c64c0 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_W 0x003c64c4 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_W 0x003c64c8 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_W 0x003c64cc /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_DM_W 0x003c64d0 /* Write Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003c64d4 /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003c64d8 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003c64dc /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003c64e0 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003c64e4 /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003c64e8 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003c64ec /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003c64f0 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003c64f4 /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003c64f8 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003c64fc /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003c6500 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003c6504 /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003c6508 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003c650c /* Read DQSP Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003c6510 /* Read DQSN Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003c6514 /* Read Enable Bit VDL static override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_P 0x003c6528 /* Read DQSP VDL dynamic override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_R_N 0x003c652c /* Read DQSN VDL dynamic override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003c6530 /* Read DQ-P VDL dynamic override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003c6534 /* Read DQ-N VDL dynamic override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_W 0x003c6538 /* Write DQ Byte VDL dynamic override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003c653c /* Write DQ Bit VDL dynamic override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_P 0x003c6548 /* Read DQSP VDL dynamic override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_R_N 0x003c654c /* Read DQSN VDL dynamic override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003c6550 /* Read DQ-P VDL dynamic override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003c6554 /* Read DQ-N VDL dynamic override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_W 0x003c6558 /* Write DQ Byte VDL dynamic override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003c655c /* Write DQ Bit VDL dynamic override control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_DATA_DLY 0x003c6560 /* Word Lane read channel control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_CONTROL 0x003c6564 /* Word Lane read channel control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_0 0x003c6570 /* Read fifo data register, first data */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_1 0x003c6574 /* Read fifo data register, second data */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_2 0x003c6578 /* Read fifo data register, third data */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL0_3 0x003c657c /* Read fifo data register, fourth data */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_0 0x003c6580 /* Read fifo data register, first data */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_1 0x003c6584 /* Read fifo data register, second data */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_2 0x003c6588 /* Read fifo data register, third data */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_DATA_BL1_3 0x003c658c /* Read fifo data register, fourth data */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_STATUS 0x003c6590 /* Read fifo status register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_READ_FIFO_CLEAR 0x003c6594 /* Read fifo status clear register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_IDLE_PAD_CONTROL 0x003c65a0 /* Idle mode SSTL pad control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_DRIVE_PAD_CTL 0x003c65a4 /* SSTL pad drive characteristics control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_CLOCK_PAD_DISABLE 0x003c65a8 /* Clock pad disable register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_WR_PREAMBLE_MODE 0x003c65ac /* Write cycle preamble control register */
#define BCHP_DDR40_PHY_WORD_LANE_1_1_PHYBIST_VDL_ADJ 0x003c65b0 /* PHYBIST mode VDL step select adjustment register */

#endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_1_H__ */

/* End of File */