| /*************************************************************************** |
| * Copyright (c) 1999-2011, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Mon Apr 11 12:01:44 2011 |
| * MD5 Checksum 8cf142ad25caa9f873c54e8bb2bb1755 |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_ddr40_phy_word_lane_1_0.h $ |
| * |
| * Hydra_Software_Devel/2 4/11/11 11:57p vanessah |
| * SW7425-112: Update rdb files for 7425 B0. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_H__ |
| |
| /*************************************************************************** |
| *DDR40_PHY_WORD_LANE_1_0 - DDR40 DDR40 word lane #1 control registers 0 |
| ***************************************************************************/ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE_RD_EN 0x003b6400 /* Read Enable Byte VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_W 0x003b6404 /* Write Byte VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_P 0x003b6408 /* Read Byte DQSP VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_R_N 0x003b640c /* Read Byte DQSN VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_W 0x003b6410 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_W 0x003b6414 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_W 0x003b6418 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_W 0x003b641c /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_W 0x003b6420 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_W 0x003b6424 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_W 0x003b6428 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_W 0x003b642c /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_DM_W 0x003b6430 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_P 0x003b6434 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT0_R_N 0x003b6438 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_P 0x003b643c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT1_R_N 0x003b6440 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_P 0x003b6444 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT2_R_N 0x003b6448 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_P 0x003b644c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT3_R_N 0x003b6450 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_P 0x003b6454 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT4_R_N 0x003b6458 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_P 0x003b645c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT5_R_N 0x003b6460 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_P 0x003b6464 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT6_R_N 0x003b6468 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_P 0x003b646c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT7_R_N 0x003b6470 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE0_BIT_RD_EN 0x003b6474 /* Read Enable Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_W 0x003b64a4 /* Write Byte VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_P 0x003b64a8 /* Read Byte DQSP VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_R_N 0x003b64ac /* Read Byte DQSN VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_W 0x003b64b0 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_W 0x003b64b4 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_W 0x003b64b8 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_W 0x003b64bc /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_W 0x003b64c0 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_W 0x003b64c4 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_W 0x003b64c8 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_W 0x003b64cc /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_DM_W 0x003b64d0 /* Write Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_P 0x003b64d4 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT0_R_N 0x003b64d8 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_P 0x003b64dc /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT1_R_N 0x003b64e0 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_P 0x003b64e4 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT2_R_N 0x003b64e8 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_P 0x003b64ec /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT3_R_N 0x003b64f0 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_P 0x003b64f4 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT4_R_N 0x003b64f8 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_P 0x003b64fc /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT5_R_N 0x003b6500 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_P 0x003b6504 /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT6_R_N 0x003b6508 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_P 0x003b650c /* Read DQSP Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT7_R_N 0x003b6510 /* Read DQSN Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_VDL_OVRIDE_BYTE1_BIT_RD_EN 0x003b6514 /* Read Enable Bit VDL static override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_P 0x003b6528 /* Read DQSP VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_R_N 0x003b652c /* Read DQSN VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_P 0x003b6530 /* Read DQ-P VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_R_N 0x003b6534 /* Read DQ-N VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_W 0x003b6538 /* Write DQ Byte VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE0_BIT_W 0x003b653c /* Write DQ Bit VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_P 0x003b6548 /* Read DQSP VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_R_N 0x003b654c /* Read DQSN VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_P 0x003b6550 /* Read DQ-P VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_R_N 0x003b6554 /* Read DQ-N VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_W 0x003b6558 /* Write DQ Byte VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DYN_VDL_OVRIDE_BYTE1_BIT_W 0x003b655c /* Write DQ Bit VDL dynamic override control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_DATA_DLY 0x003b6560 /* Word Lane read channel control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_CONTROL 0x003b6564 /* Word Lane read channel control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_0 0x003b6570 /* Read fifo data register, first data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_1 0x003b6574 /* Read fifo data register, second data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_2 0x003b6578 /* Read fifo data register, third data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL0_3 0x003b657c /* Read fifo data register, fourth data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_0 0x003b6580 /* Read fifo data register, first data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_1 0x003b6584 /* Read fifo data register, second data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_2 0x003b6588 /* Read fifo data register, third data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_DATA_BL1_3 0x003b658c /* Read fifo data register, fourth data */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_STATUS 0x003b6590 /* Read fifo status register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_READ_FIFO_CLEAR 0x003b6594 /* Read fifo status clear register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_IDLE_PAD_CONTROL 0x003b65a0 /* Idle mode SSTL pad control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_DRIVE_PAD_CTL 0x003b65a4 /* SSTL pad drive characteristics control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_CLOCK_PAD_DISABLE 0x003b65a8 /* Clock pad disable register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_WR_PREAMBLE_MODE 0x003b65ac /* Write cycle preamble control register */ |
| #define BCHP_DDR40_PHY_WORD_LANE_1_0_PHYBIST_VDL_ADJ 0x003b65b0 /* PHYBIST mode VDL step select adjustment register */ |
| |
| #endif /* #ifndef BCHP_DDR40_PHY_WORD_LANE_1_0_H__ */ |
| |
| /* End of File */ |
