| /*************************************************************************** |
| * Copyright (c) 1999-2011, Broadcom Corporation |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| * |
| * You should have received a copy of the GNU General Public License |
| * along with this program; if not, write to the Free Software |
| * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. |
| * |
| * Module Description: |
| * DO NOT EDIT THIS FILE DIRECTLY |
| * |
| * This module was generated magically with RDB from a source description |
| * file. You must edit the source file for changes to be made to this file. |
| * |
| * |
| * Date: Generated on Tue May 31 16:33:38 2011 |
| * MD5 Checksum 0b9cc5de2a03cabbf9a0a767bc10763a |
| * |
| * Compiled with: RDB Utility combo_header.pl |
| * RDB Parser 3.0 |
| * unknown unknown |
| * Perl Interpreter 5.008008 |
| * Operating System linux |
| * |
| * Revision History: |
| * |
| * $brcm_Log: /magnum/basemodules/chp/7346/rdb/b0/bchp_clkgen.h $ |
| * |
| * Hydra_Software_Devel/3 5/31/11 5:25p albertl |
| * SW7346-143: Updated to match RDB. |
| * |
| ***************************************************************************/ |
| |
| #ifndef BCHP_CLKGEN_H__ |
| #define BCHP_CLKGEN_H__ |
| |
| /*************************************************************************** |
| *CLKGEN - clkgen registers |
| ***************************************************************************/ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN 0x00420000 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL 0x00420004 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV 0x00420008 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x0042000c /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN 0x00420010 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00420014 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00420018 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC 0x0042001c /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2 0x00420020 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS 0x00420024 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS 0x00420028 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET 0x0042002c /* Resets */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN 0x00420030 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL 0x00420034 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV 0x00420038 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x0042003c /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x00420040 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x00420044 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN 0x00420048 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x0042004c /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x00420050 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC 0x00420054 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS 0x00420058 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_STATUS 0x0042005c /* Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET 0x00420060 /* Resets */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN 0x00420064 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL 0x00420068 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV 0x0042006c /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN 0x00420070 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00420074 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x00420078 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS 0x0042007c /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS 0x00420080 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET 0x00420084 /* Resets */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN 0x00420088 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL 0x0042008c /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV 0x00420090 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x00420094 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x00420098 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x0042009c /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x004200a0 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN 0x004200a4 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x004200a8 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x004200ac /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC 0x004200b0 /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2 0x004200b4 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS 0x004200b8 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS 0x004200bc /* Test Status */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET 0x004200c0 /* Resets */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN 0x004200c4 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL 0x004200c8 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV 0x004200cc /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x004200d0 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x004200d4 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x004200d8 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x004200dc /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x004200e0 /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x004200e4 /* PLL CHANNEL control CH 5 */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN 0x004200e8 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x004200ec /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x004200f0 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC 0x004200f4 /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2 0x004200f8 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS 0x004200fc /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS 0x00420100 /* Test Status */ |
| #define BCHP_CLKGEN_SCRATCH5 0x00420104 /* clkgen Scratch register */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL 0x00420108 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_SCRATCH3 0x0042010c /* clkgen Scratch register */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x00420110 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x00420114 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x00420118 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x0042011c /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x00420120 /* PLL CHANNEL control CH 4 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x00420124 /* PLL CHANNEL control CH 5 */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN 0x00420128 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x0042012c /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x00420130 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC 0x00420134 /* Miscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2 0x00420138 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS 0x0042013c /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS 0x00420140 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET 0x00420144 /* Resets */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN 0x00420148 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL 0x0042014c /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV 0x00420150 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x00420154 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN 0x0042015c /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x00420160 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x00420164 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC 0x00420168 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS 0x0042016c /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS 0x00420170 /* Status */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET 0x00420174 /* Resets */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN 0x00420178 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL 0x0042017c /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV 0x00420180 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x00420184 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00420188 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2 0x0042018c /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN 0x00420190 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x00420194 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x00420198 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC 0x0042019c /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS 0x004201a0 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS 0x004201a4 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET 0x004201a8 /* Resets */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN 0x004201ac /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL 0x004201b0 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV 0x004201b4 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC 0x004201b8 /* Fractional */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x004201bc /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x004201c0 /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x004201c4 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 0x004201c8 /* PLL CHANNEL control CH 3 */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN 0x004201cc /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x004201d0 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x004201d4 /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC 0x004201d8 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS 0x004201dc /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS 0x004201e0 /* Test Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET 0x004201e4 /* Resets */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN 0x004201e8 /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL 0x004201ec /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV 0x004201f0 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN 0x004201f4 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x004201f8 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x004201fc /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS 0x00420200 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS 0x00420204 /* Test Status */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE 0x00420208 /* Disable HIF_INST's clocks */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE 0x0042020c /* Memsys 32 inst memory standby enable */ |
| #define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE 0x00420210 /* Disable SDS0_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK 0x00420214 /* Usb1 inst observe clock */ |
| #define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE 0x00420218 /* Ftm top inst clock enable */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x0042021c /* Disable VEC_AIO_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE 0x00420220 /* Usb0 inst memory standby enable */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE 0x00420224 /* Graphics inst clock enable */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL 0x00420228 /* Select clocks that can stay alive during power management standby mode. */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE 0x0042022c /* Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE 0x00420230 /* Disable SYS_CTRL_INST's clocks */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420234 /* Sds0 afec top inst memory standby enable */ |
| #define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION 0x00420238 /* Select observation clk */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE 0x0042023c /* Memsys 32 inst clock enable */ |
| #define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE 0x00420240 /* Usb1 inst memory standby enable */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA 0x00420244 /* Sectop inst clock enable */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE 0x00420248 /* Disable PAD's clocks */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE 0x0042024c /* Disable UHFR_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT 0x00420250 /* Mux selects for Internal clocks */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE 0x00420254 /* Disable DVP_HT_INST's clocks */ |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK 0x00420258 /* Usb0 inst observe clock */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE 0x0042025c /* Disable USB0_INST's clocks */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE 0x00420260 /* Disable CORE_XPT_INST's clocks */ |
| #define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE 0x00420264 /* Dvp ht inst memory standby enable */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT 0x00420268 /* Mux selects for Pad clocks */ |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK 0x0042026c /* Sys aon inst observe clock */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY 0x00420270 /* Uhfr top inst power switch memory */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A 0x00420274 /* Dual genet top dual rgmii inst power switch memory a */ |
| #define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY 0x00420278 /* Usb0 inst power switch memory */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT 0x0042027c /* Mux selects for Smartcard clocks */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE 0x00420280 /* Disable USB1_INST's clocks */ |
| #define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE 0x00420284 /* Disable SDS1_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE 0x00420288 /* Disable GRAPHICS_INST's clocks */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE 0x0042028c /* Sds1 afec top inst clock enable */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x00420290 /* Vec aio top inst clock enable aio */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK 0x00420294 /* Sds0 afec top inst observe clock */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO 0x00420298 /* Vec aio top inst memory standby enable aio */ |
| #define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY 0x0042029c /* Dvp ht inst power switch memory */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x004202a0 /* Dual genet top dual rgmii inst memory standby enable a */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE 0x004202a4 /* Dvp ht inst clock enable */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK 0x004202a8 /* Memsys 32 inst observe clock */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT 0x004202ac /* Memsys 32 inst power management */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE 0x004202b0 /* Core xpt inst clock enable */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE 0x004202b4 /* Core xpt inst memory standby enable */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x004202b8 /* Vec aio top inst observe clock */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE 0x004202bc /* Graphics inst memory standby enable */ |
| #define BCHP_CLKGEN_SCRATCH7 0x004202c0 /* clkgen Scratch register */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK 0x004202c4 /* Uhfr top inst observe clock */ |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK 0x004202c8 /* Dvp ht inst observe clock */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT 0x004202cc /* Dual genet top dual rgmii inst clock select */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2 0x004202d0 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE 0x004202d4 /* Ftm top inst memory standby enable */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE 0x004202d8 /* Uhfr top inst memory standby enable */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE 0x004202dc /* Sds1 afec top inst memory standby enable */ |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE 0x004202e0 /* Disable ZCPU_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_SCRATCH6 0x004202e4 /* clkgen Scratch register */ |
| #define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK 0x004202e8 /* Sds1 receiver inst observe clock */ |
| #define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK 0x004202ec /* Sds1 tfec top inst observe clock */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x004202f0 /* Vec aio top inst clock enable */ |
| #define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY 0x004202f4 /* Ftm top inst power switch memory */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC 0x004202f8 /* Vec aio top inst memory standby enable vec */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE 0x004202fc /* Sds0 afec top inst clock enable */ |
| #define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK 0x00420300 /* Sds0 receiver inst observe clock */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO 0x00420304 /* Vec aio top inst power switch memory aio */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY 0x00420308 /* Raaga dsp top inst power switch memory */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE 0x0042030c /* Moca top inst memory standby enable */ |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION 0x00420310 /* Select observation clk */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420314 /* Svd top inst memory standby enable */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK 0x00420318 /* Raaga Dsp top inst observe clock */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE 0x0042031c /* Raaga dsp top inst clock enable */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420320 /* Bvn top inst memory standby enable */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY 0x00420324 /* Bvn top inst power switch memory */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT 0x00420328 /* Sata3 top inst clock select */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC 0x0042032c /* Vec aio top inst power switch memory vec */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK 0x00420330 /* Sds1 afec top inst observe clock */ |
| #define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE 0x00420334 /* Sds0 top inst clock enable */ |
| #define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY 0x00420338 /* Usb1 inst power switch memory */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE 0x0042033c /* Usb0 inst clock enable */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE 0x00420340 /* Sata3 top inst memory standby enable */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x00420344 /* Vec aio top inst clock enable vec */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK 0x00420348 /* Moca top inst observe clock */ |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION 0x0042034c /* Select observation clk */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK 0x00420350 /* Sectop inst observe clock */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY 0x00420354 /* Memsys 32 inst power switch memory */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY 0x00420358 /* Graphics inst power switch memory */ |
| #define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK 0x0042035c /* Sds0 tfec top inst observe clock */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY 0x00420360 /* Sata3 top inst power switch memory */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE 0x00420364 /* Svd top inst clock enable */ |
| #define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY 0x00420368 /* Hif inst power switch memory */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE 0x0042036c /* Sata3 top inst clock enable */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK 0x00420370 /* Core xpt inst observe clock */ |
| #define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE 0x00420374 /* Hif inst memory standby enable */ |
| #define BCHP_CLKGEN_SCRATCH8 0x00420378 /* clkgen Scratch register */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY 0x0042037c /* Svd top inst power switch memory */ |
| #define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE 0x00420380 /* Sds1 top inst clock enable */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE 0x00420384 /* Uhfr top inst clock enable */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY 0x00420388 /* Sds1 afec top inst power switch memory */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE 0x0042038c /* Usb1 inst clock enable */ |
| #define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE 0x00420390 /* Disable SATA3_TOP_INST's clocks */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK 0x00420394 /* Sata3 top inst observe clock */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE 0x00420398 /* Sys ctrl inst memory standby enable */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK 0x0042039c /* Dual genet top dual rgmii inst observe clock */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE 0x004203a0 /* Dual genet top dual rgmii inst clock enable */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE 0x004203a4 /* Raaga dsp top inst memory standby enable */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY 0x004203a8 /* Core xpt inst power switch memory */ |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION 0x004203ac /* Select observation clk */ |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK 0x004203b0 /* Zcpu top inst observe clock */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK 0x004203b4 /* Graphics inst observe clock */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE 0x004203b8 /* Disable GRAPHICS_INST's m2mc clock */ |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL 0x004203bc /* Select clocks that can stay alive during power management standby mode. */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY 0x004203c0 /* Sds0 afec top inst power switch memory */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK 0x004203c4 /* Sys ctrl inst observe clock */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE 0x004203c8 /* Bvn top inst clock enable */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY 0x004203cc /* Sys ctrl inst power switch memory */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY 0x004203d0 /* Moca top inst power switch memory */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE 0x004203d4 /* Moca top inst clock enable */ |
| #define BCHP_CLKGEN_SCRATCH4 0x004203d8 /* clkgen Scratch register */ |
| #define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS 0x004203dc /* Lock Status */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL 0x004203e0 /* pll alive in standby mode */ |
| #define BCHP_CLKGEN_SPI_CLOCK_SELECT 0x004203e4 /* spi clock control */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS 0x004203e8 /* Bypass DUAL_GENET_TOP_DUAL_RGMII_INST clocks */ |
| #define BCHP_CLKGEN_SCRATCH2 0x004203ec /* clkgen Scratch register */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE 0x004203f0 /* Graphics inst V3D clock enable */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL 0x004203f4 /* Mips PLL Control Register */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS 0x004203f8 /* Resets status */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS 0x004203fc /* Resets status */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS 0x00420400 /* Resets status */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS 0x00420404 /* Resets status */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS 0x00420408 /* Resets status */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS 0x0042040c /* Resets status */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS 0x00420410 /* Resets status */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS 0x00420414 /* Resets status */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS 0x00420418 /* Resets status */ |
| #define BCHP_CLKGEN_TESTPORT 0x0042041c /* Special Testport Controls */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET 0x00420428 /* Resets */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN 0x0042042c /* Powerdowns */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL 0x00420430 /* Miscellaneous Controls */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_DIV 0x00420434 /* Pre multiplier */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 0x00420438 /* PLL CHANNEL control CH 0 */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 0x0042043c /* PLL CHANNEL control CH 1 */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 0x00420440 /* PLL CHANNEL control CH 2 */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN 0x00420444 /* PLL GAIN */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW 0x00420448 /* Lower bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH 0x0042044c /* Higher bits of Spread Spectrum mode control */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC 0x00420450 /* Mscellaneous control bus. */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS 0x00420454 /* Lock Status */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS 0x00420458 /* Status */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS 0x0042045c /* Resets status */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC2 0x00420460 /* Miscellaneous control bus continued. */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL 0x00420464 /* Clock Monitor Control */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT 0x00420468 /* Clock Monitor Max Reference Count */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER 0x0042046c /* Clock Monitor Reference Counter */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE 0x00420470 /* Clock Monitor Reference Counter */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER 0x00420474 /* Clock Monitor View Counter */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP 0x00420478 /* Power management LDO PLL */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM 0x0042047c /* Power management LDO PLL state machine */ |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT 3 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 2 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [30:30] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK 0x40000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [29:29] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [28:28] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [27:27] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [25:24] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK 0x03000000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [23:22] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [21:20] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK 0x00300000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [19:19] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK 0x00080000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [17:17] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [16:14] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK 0x0001c000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [13:13] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [12:03] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK 0x00001ff8 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT 142 |
| |
| /* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT 3 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 6 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 8 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 100 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6 |
| |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2 |
| |
| /* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 2 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: LDO_REF_SEL [30:30] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_MASK 0x40000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: POR_BYPASS [29:29] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [28:28] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [27:27] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_DLY [25:24] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_MASK 0x03000000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [23:22] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [21:20] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK 0x00300000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: AUX_CTRL [19:19] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_MASK 0x00080000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [17:17] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [16:14] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK 0x0001c000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET_ [13:13] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [12:03] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK 0x00001ff8 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT 125 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT 3 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 18 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 9 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 90 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 2 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: LDO_REF_SEL [30:30] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_LDO_REF_SEL_MASK 0x40000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_LDO_REF_SEL_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_LDO_REF_SEL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: POR_BYPASS [29:29] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_POR_BYPASS_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_POR_BYPASS_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_POR_BYPASS_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: NDIV_RELOCK [28:28] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_NDIV_RELOCK_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_NDIV_RELOCK_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_NDIV_RELOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [27:27] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [25:24] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK 0x03000000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [23:22] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [21:20] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK 0x00300000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [19:19] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK 0x00080000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [17:17] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [16:14] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK 0x0001c000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_MISC2_SPARE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_STATUS :: LOCK_LOST [11:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_LOCK_LOST_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_LOCK_LOST_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [12:03] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK 0x00001ff8 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT 200 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT 3 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 16 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 36 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 72 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [13:06] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 9 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [05:05] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [04:04] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [03:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [13:06] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 36 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [05:05] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [04:04] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [03:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 2 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: LDO_REF_SEL [30:30] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_MASK 0x40000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: POR_BYPASS [29:29] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [28:28] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [27:27] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_DLY [25:24] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_MASK 0x03000000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [23:22] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT 2 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [21:20] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK 0x00300000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: AUX_CTRL [19:19] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_MASK 0x00080000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [17:17] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [16:14] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK 0x0001c000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET_ [13:13] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__SHIFT 13 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *SCRATCH5 - clkgen Scratch register |
| ***************************************************************************/ |
| /* CLKGEN :: SCRATCH5 :: VALUE [31:00] */ |
| #define BCHP_CLKGEN_SCRATCH5_VALUE_MASK 0xffffffff |
| #define BCHP_CLKGEN_SCRATCH5_VALUE_SHIFT 0 |
| #define BCHP_CLKGEN_SCRATCH5_VALUE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SCRATCH3 - clkgen Scratch register |
| ***************************************************************************/ |
| /* CLKGEN :: SCRATCH3 :: VALUE [31:00] */ |
| #define BCHP_CLKGEN_SCRATCH3_VALUE_MASK 0xffffffff |
| #define BCHP_CLKGEN_SCRATCH3_VALUE_SHIFT 0 |
| #define BCHP_CLKGEN_SCRATCH3_VALUE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [03:03] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000008 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [02:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 48 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [13:06] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 10 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [05:05] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [03:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [13:06] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 144 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [05:05] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [03:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 9 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 2 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_MISC - Miscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [30:30] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK 0x40000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [29:29] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [28:28] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [27:27] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [25:24] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK 0x03000000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [23:22] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT 2 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [21:20] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK 0x00300000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [19:19] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK 0x00080000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [17:17] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [16:14] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK 0x0001c000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [13:13] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SYS0_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [12:03] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK 0x00001ff8 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT 143 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT 2 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 7 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 9 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 2 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: LDO_REF_SEL [30:30] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_MASK 0x40000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: POR_BYPASS [29:29] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [28:28] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [27:27] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCODIV2 [26:26] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_MASK 0x04000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_SHIFT 26 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_DLY [25:24] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_MASK 0x03000000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [23:22] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK 0x00c00000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT 22 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT 2 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [21:20] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK 0x00300000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: AUX_CTRL [19:19] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_MASK 0x00080000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [17:17] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [16:14] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK 0x0001c000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET_ [13:13] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__SHIFT 13 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [01:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [12:03] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK 0x00001ff8 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT 64 |
| |
| /* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 40 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 40 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 40 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2 |
| |
| /* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [29:29] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [28:28] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [27:27] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [26:25] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK 0x06000000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [24:23] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK 0x01800000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [20:20] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [19:19] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK 0x00080000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [17:17] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [16:14] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK 0x0001c000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [13:13] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT 13 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [12:03] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK 0x00001ff8 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT 64 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT 2 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_FRAC - Fractional |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK 0xfff00000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT 20 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK 0x000fffff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 64 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 250 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 75 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 4 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [29:29] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [28:28] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [27:27] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [26:25] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK 0x06000000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [24:23] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK 0x01800000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [20:20] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [19:19] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK 0x00080000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [17:17] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [16:14] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK 0x0001c000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [13:13] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT 13 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_STATUS - Test Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *MEMSYS_32_INST_MEMORY_STANDBY_ENABLE - Memsys 32 inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: DDR_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_DDR_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS0_TOP_INST_CLOCK_DISABLE - Disable SDS0_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SDS0_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SDS0_TOP_INST_CLOCK_DISABLE :: DISABLE_SDS_108_PRESPMBALANCE_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *USB1_INST_OBSERVE_CLOCK - Usb1 inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *FTM_TOP_INST_CLOCK_ENABLE - Ftm top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: FTM_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: FTM_TOP_INST_CLOCK_ENABLE :: FTM_CH1_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH1_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH1_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH1_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: FTM_TOP_INST_CLOCK_ENABLE :: FTM_CH0_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: FTM_TOP_INST_CLOCK_ENABLE :: FTM_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_FTM_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *USB0_INST_MEMORY_STANDBY_ENABLE - Usb0 inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode. |
| ***************************************************************************/ |
| /* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */ |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT 0 |
| #define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE - Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:08] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xffffff00 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 8 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [07:07] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000080 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 7 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [06:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000040 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 6 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_FAST_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_FAST_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_EPHY_PLL_INPUT_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_EPHY_PLL_INPUT_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_EPHY_PLL_INPUT_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_EPHY_PLL_INPUT_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE - Sds0 afec top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PAD_OBSERVE_PLL_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */ |
| #define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100 |
| #define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8 |
| #define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */ |
| #define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe |
| #define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *MEMSYS_32_INST_CLOCK_ENABLE - Memsys 32 inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: DDR_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_SCB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: DDR_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_DDR_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *USB1_INST_MEMORY_STANDBY_ENABLE - Usb1 inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SECTOP_INST_CLOCK_ENABLE_M2MDMA - Sectop inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA [00:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001 |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0 |
| #define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PAD_CLOCK_DISABLE - Disable PAD's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_SC_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLKUSB_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKUSB_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKUSB_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKUSB_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *UHFR_TOP_INST_CLOCK_DISABLE - Disable UHFR_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: DISABLE_UHFR_ALWAYSON_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *INTERNAL_MUX_SELECT - Mux selects for Internal clocks |
| ***************************************************************************/ |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *USB0_INST_OBSERVE_CLOCK - Usb0 inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *USB0_INST_CLOCK_DISABLE - Disable USB0_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_INST_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_54_FREERUN_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_54_MDIO_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_MEMORY_STANDBY_ENABLE - Dvp ht inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PAD_MUX_SELECT - Mux selects for Pad clocks |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_VCXO27_CLOCK [02:02] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000004 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLKUSB_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKUSB_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKUSB_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKUSB_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SYS_AON_INST_OBSERVE_CLOCK - Sys aon inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *UHFR_TOP_INST_POWER_SWITCH_MEMORY - Uhfr top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: UHFR_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A - Dual genet top dual rgmii inst power switch memory a |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0 |
| |
| /*************************************************************************** |
| *USB0_INST_POWER_SWITCH_MEMORY - Usb0 inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK 0xfffff800 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT 11 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK 0x00000700 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT 8 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK 0x000000e0 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK 0x0000001c |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT 2 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */ |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *USB1_INST_CLOCK_DISABLE - Disable USB1_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: USB1_INST_CLOCK_DISABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_54_FREERUN_CLOCK [01:01] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_SHIFT 1 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_54_MDIO_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS1_TOP_INST_CLOCK_DISABLE - Disable SDS1_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SDS1_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SDS1_TOP_INST_CLOCK_DISABLE :: DISABLE_SDS_108_PRESPMBALANCE_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_DISABLE_DISABLE_SDS_108_PRESPMBALANCE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_CLOCK_DISABLE - Disable GRAPHICS_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS1_AFEC_TOP_INST_CLOCK_ENABLE - Sds1 afec top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SDS1_AFEC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SDS1_AFEC_TOP_INST_CLOCK_ENABLE :: SDSAFEC1_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC1_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC1_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC1_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 1 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_DEFAULT 1 |
| |
| /*************************************************************************** |
| *SDS0_AFEC_TOP_INST_OBSERVE_CLOCK - Sds0 afec top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO - Vec aio top inst memory standby enable aio |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_POWER_SWITCH_MEMORY - Dvp ht inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Dual genet top dual rgmii inst memory standby enable a |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_CLK_VEC_ENABLE [05:05] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_MASK 0x00000020 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_SHIFT 5 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_CLK_MAX_ENABLE [04:04] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK 0x00000010 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT 4 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *MEMSYS_32_INST_OBSERVE_CLOCK - Memsys 32 inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: DDR_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: DDR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: DDR_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_DDR_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *MEMSYS_32_INST_POWER_MANAGEMENT - Memsys 32 inst power management |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_INST_POWER_MANAGEMENT :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MEMSYS_32_INST_POWER_MANAGEMENT :: MEMSYS_PLL_PWRDN_POWER_MANAGEMENT [00:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK 0x00000001 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_DEFAULT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *CORE_XPT_INST_MEMORY_STANDBY_ENABLE - Core xpt inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_MEMORY_STANDBY_ENABLE - Graphics inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SCRATCH7 - clkgen Scratch register |
| ***************************************************************************/ |
| /* CLKGEN :: SCRATCH7 :: VALUE [31:00] */ |
| #define BCHP_CLKGEN_SCRATCH7_VALUE_MASK 0xffffffff |
| #define BCHP_CLKGEN_SCRATCH7_VALUE_SHIFT 0 |
| #define BCHP_CLKGEN_SCRATCH7_VALUE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *UHFR_TOP_INST_OBSERVE_CLOCK - Uhfr top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT - Dual genet top dual rgmii inst clock select |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET1_GMII_CLOCK_SELECT [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_SHIFT 3 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET1_CLOCK_SELECT [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_SHIFT 2 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *FTM_TOP_INST_MEMORY_STANDBY_ENABLE - Ftm top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: FTM_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: FTM_TOP_INST_MEMORY_STANDBY_ENABLE :: FTM_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_FTM_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *UHFR_TOP_INST_MEMORY_STANDBY_ENABLE - Uhfr top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: UHFR_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE - Sds1 afec top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: SDSAFEC1_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC1_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC1_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC1_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ZCPU_TOP_INST_CLOCK_DISABLE - Disable ZCPU_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_FUNC_BYP_CLOCK [00:00] */ |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SCRATCH6 - clkgen Scratch register |
| ***************************************************************************/ |
| /* CLKGEN :: SCRATCH6 :: VALUE [31:00] */ |
| #define BCHP_CLKGEN_SCRATCH6_VALUE_MASK 0xffffffff |
| #define BCHP_CLKGEN_SCRATCH6_VALUE_SHIFT 0 |
| #define BCHP_CLKGEN_SCRATCH6_VALUE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS1_RECEIVER_INST_OBSERVE_CLOCK - Sds1 receiver inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SDS1_RECEIVER_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SDS1_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR1_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SDS1_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SDS1_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR1_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SDS1_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR1_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS1_TFEC_TOP_INST_OBSERVE_CLOCK - Sds1 tfec top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SDS1_TFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SDS1_TFEC_TOP_INST_OBSERVE_CLOCK :: SDTFECR1_ENABLE_DIVIDER_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SDS1_TFEC_TOP_INST_OBSERVE_CLOCK :: SDSTFEC1_ENABLE_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_ENABLE_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_ENABLE_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SDS1_TFEC_TOP_INST_OBSERVE_CLOCK :: SDSTFEC1_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SDS1_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC1_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_ALTERNATE_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *FTM_TOP_INST_POWER_SWITCH_MEMORY - Ftm top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: FTM_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: FTM_TOP_INST_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_FTM_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC - Vec aio top inst memory standby enable vec |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS0_AFEC_TOP_INST_CLOCK_ENABLE - Sds0 afec top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SDS0_AFEC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SDS0_AFEC_TOP_INST_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *SDS0_RECEIVER_INST_OBSERVE_CLOCK - Sds0 receiver inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SDS0_RECEIVER_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SDS0_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SDS0_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SDS0_RECEIVER_INST_OBSERVE_CLOCK :: SDSRCVR0_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SDS0_RECEIVER_INST_OBSERVE_CLOCK_SDSRCVR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO - Vec aio top inst power switch memory aio |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY - Raaga dsp top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *MOCA_TOP_INST_MEMORY_STANDBY_ENABLE - Moca top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: MOCA_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PAD_CODEC_MCLK_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */ |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100 |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8 |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */ |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SVD_TOP_INST_MEMORY_STANDBY_ENABLE - Svd top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SVD_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SVD_TOP_INST_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SVD_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_INST_OBSERVE_CLOCK - Raaga Dsp top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_INST_CLOCK_ENABLE - Raaga dsp top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *BVN_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *BVN_TOP_INST_POWER_SWITCH_MEMORY - Bvn top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_CLOCK_SELECT - Sata3 top inst clock select |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 1 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC - Vec aio top inst power switch memory vec |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS1_AFEC_TOP_INST_OBSERVE_CLOCK - Sds1 afec top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SDS1_AFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SDS1_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC1_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SDS1_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SDS1_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC1_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC1_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS0_TOP_INST_CLOCK_ENABLE - Sds0 top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SDS0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SDS0_TOP_INST_CLOCK_ENABLE :: SDS0_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS0_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS0_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS0_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *USB1_INST_POWER_SWITCH_MEMORY - Usb1 inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *USB0_INST_CLOCK_ENABLE - Usb0 inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB0_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_MEMORY_STANDBY_ENABLE - Sata3 top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: SATA3_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec |
| ***************************************************************************/ |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [04:04] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000010 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 4 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_QDAC_216_CLOCK_ENABLE_VEC [03:03] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000008 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 3 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC [02:02] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_MASK 0x00000004 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_SHIFT 2 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_DEFAULT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 1 |
| |
| /* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [00:00] */ |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000001 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 0 |
| #define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 1 |
| |
| /*************************************************************************** |
| *MOCA_TOP_INST_OBSERVE_CLOCK - Moca top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PAD_CLK27_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_CLK27_OBSERVATION :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PAD_CLK27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */ |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100 |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8 |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */ |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *MEMSYS_32_INST_POWER_SWITCH_MEMORY - Memsys 32 inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: DDR_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_DDR_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_DDR_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_DDR_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_POWER_SWITCH_MEMORY - Graphics inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS0_TFEC_TOP_INST_OBSERVE_CLOCK - Sds0 tfec top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SDS0_TFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SDS0_TFEC_TOP_INST_OBSERVE_CLOCK :: SDTFECR0_ENABLE_DIVIDER_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDTFECR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SDS0_TFEC_TOP_INST_OBSERVE_CLOCK :: SDSTFEC0_ENABLE_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SDS0_TFEC_TOP_INST_OBSERVE_CLOCK :: SDSTFEC0_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SDS0_TFEC_TOP_INST_OBSERVE_CLOCK_SDSTFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_POWER_SWITCH_MEMORY - Sata3 top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: SATA3_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SVD_TOP_INST_CLOCK_ENABLE - Svd top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010 |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4 |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_AVD_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_AVD_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: SVD_TOP_INST_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SVD_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *HIF_INST_POWER_SWITCH_MEMORY - Hif inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_CLOCK_ENABLE - Sata3 top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *HIF_INST_MEMORY_STANDBY_ENABLE - Hif inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SCRATCH8 - clkgen Scratch register |
| ***************************************************************************/ |
| /* CLKGEN :: SCRATCH8 :: VALUE [31:00] */ |
| #define BCHP_CLKGEN_SCRATCH8_VALUE_MASK 0xffffffff |
| #define BCHP_CLKGEN_SCRATCH8_VALUE_SHIFT 0 |
| #define BCHP_CLKGEN_SCRATCH8_VALUE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SVD_TOP_INST_POWER_SWITCH_MEMORY - Svd top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: SVD_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SVD_TOP_INST_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_SVD_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS1_TOP_INST_CLOCK_ENABLE - Sds1 top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: SDS1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SDS1_TOP_INST_CLOCK_ENABLE :: SDS1_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_SDS1_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_SDS1_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SDS1_TOP_INST_CLOCK_ENABLE_SDS1_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *UHFR_TOP_INST_CLOCK_ENABLE - Uhfr top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: UHFR_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY - Sds1 afec top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: SDSAFEC1_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC1_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC1_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_SDS1_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC1_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *USB1_INST_CLOCK_ENABLE - Usb1 inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: USB1_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *SATA3_INST_CLOCK_DISABLE - Disable SATA3_TOP_INST's clocks |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_INST_CLOCK_DISABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SATA3_INST_CLOCK_DISABLE :: DISABLE_27_FUNC_CLK_30 [00:00] */ |
| #define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_MASK 0x00000001 |
| #define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SATA3_TOP_INST_OBSERVE_CLOCK - Sata3 top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SYS_CTRL_INST_MEMORY_STANDBY_ENABLE - Sys ctrl inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK - Dual genet top dual rgmii inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE - Dual genet top dual rgmii inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [15:15] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00008000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 15 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [14:14] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00004000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 14 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE [13:13] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00002000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 13 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_L2INTR_CLOCK_ENABLE [11:11] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_MASK 0x00000800 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_SHIFT 11 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_HFB_CLOCK_ENABLE [10:10] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_MASK 0x00000400 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_SHIFT 10 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_GMII_CLOCK_ENABLE [09:09] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_MASK 0x00000200 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_SHIFT 9 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_EEE_CLOCK_ENABLE [08:08] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_MASK 0x00000100 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_SHIFT 8 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_CLK_250_CLOCK_ENABLE [07:07] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_MASK 0x00000080 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_SHIFT 7 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE - Raaga dsp top inst memory standby enable |
| ***************************************************************************/ |
| /* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *CORE_XPT_INST_POWER_SWITCH_MEMORY - Core xpt inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PAD_VCXO27_OBSERVATION - Select observation clk |
| ***************************************************************************/ |
| /* CLKGEN :: PAD_VCXO27_OBSERVATION :: reserved0 [31:09] */ |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_MASK 0xfffffe00 |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_SHIFT 9 |
| |
| /* CLKGEN :: PAD_VCXO27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */ |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100 |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8 |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */ |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1 |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *ZCPU_TOP_INST_OBSERVE_CLOCK - Zcpu top inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_M2MC_CLOCK_ENABLE - Disable GRAPHICS_INST's m2mc clock |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_M2MC_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_INST_M2MC_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode. |
| ***************************************************************************/ |
| /* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:05] */ |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK 0xffffffe0 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT 5 |
| |
| /* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDS1 [04:04] */ |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS1_MASK 0x00000010 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS1_SHIFT 4 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS1_DEFAULT 0 |
| |
| /* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDS0 [03:03] */ |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS0_MASK 0x00000008 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS0_SHIFT 3 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDS0_DEFAULT 0 |
| |
| /* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC1 [02:02] */ |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC1_MASK 0x00000004 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC1_SHIFT 2 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC1_DEFAULT 0 |
| |
| /* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC0 [01:01] */ |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_MASK 0x00000002 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_SHIFT 1 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_DEFAULT 0 |
| |
| /* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_FTM [00:00] */ |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FTM_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FTM_SHIFT 0 |
| #define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FTM_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY - Sds0 afec top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT 6 |
| |
| /* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0 |
| |
| /*************************************************************************** |
| *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *SYS_CTRL_INST_POWER_SWITCH_MEMORY - Sys ctrl inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *MOCA_TOP_INST_POWER_SWITCH_MEMORY - Moca top inst power switch memory |
| ***************************************************************************/ |
| /* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: MOCA_POWER_SWITCH_MEMORY [01:00] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_MASK 0x00000003 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_SHIFT 0 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_DEFAULT 0 |
| |
| /*************************************************************************** |
| *MOCA_TOP_INST_CLOCK_ENABLE - Moca top inst clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_SCB_CLOCK_ENABLE [01:01] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK 0x00000002 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT 1 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_DEFAULT 1 |
| |
| /* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_108_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *SCRATCH4 - clkgen Scratch register |
| ***************************************************************************/ |
| /* CLKGEN :: SCRATCH4 :: VALUE [31:00] */ |
| #define BCHP_CLKGEN_SCRATCH4_VALUE_MASK 0xffffffff |
| #define BCHP_CLKGEN_SCRATCH4_VALUE_SHIFT 0 |
| #define BCHP_CLKGEN_SCRATCH4_VALUE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_DDR_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_DDR_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_DDR_PLL_LOCK_STATUS :: DDR_LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_PLL_ALIVE_SEL - pll alive in standby mode |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK 0xfffffff8 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT 3 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_DDR [02:02] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR_MASK 0x00000004 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR_SHIFT 2 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR_DEFAULT 0 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [01:01] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK 0x00000002 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT 1 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT 0 |
| |
| /* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SPI_CLOCK_SELECT - spi clock control |
| ***************************************************************************/ |
| /* CLKGEN :: SPI_CLOCK_SELECT :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_SPI_CLOCK_SELECT_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_SPI_CLOCK_SELECT_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: SPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */ |
| #define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001 |
| #define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0 |
| #define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0 |
| |
| /*************************************************************************** |
| *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS - Bypass DUAL_GENET_TOP_DUAL_RGMII_INST clocks |
| ***************************************************************************/ |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: EEE_25_CLOCK_BYPASS [00:00] */ |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_MASK 0x00000001 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *SCRATCH2 - clkgen Scratch register |
| ***************************************************************************/ |
| /* CLKGEN :: SCRATCH2 :: VALUE [31:00] */ |
| #define BCHP_CLKGEN_SCRATCH2_VALUE_MASK 0xffffffff |
| #define BCHP_CLKGEN_SCRATCH2_VALUE_SHIFT 0 |
| #define BCHP_CLKGEN_SCRATCH2_VALUE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *GRAPHICS_INST_V3D_CLOCK_ENABLE - Graphics inst V3D clock enable |
| ***************************************************************************/ |
| /* CLKGEN :: GRAPHICS_INST_V3D_CLOCK_ENABLE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: GRAPHICS_INST_V3D_CLOCK_ENABLE :: GFX_V3D_CLOCK_ENABLE [00:00] */ |
| #define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_MASK 0x00000001 |
| #define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_SHIFT 0 |
| #define BCHP_CLKGEN_GRAPHICS_INST_V3D_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_MIPS_CTRL - Mips PLL Control Register |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_CTRL :: reserved0 [31:31] */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved0_MASK 0x80000000 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved0_SHIFT 31 |
| |
| /* CLKGEN :: PLL_MIPS_CTRL :: BYPASS_PLL_RQ [30:30] */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_MASK 0x40000000 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_SHIFT 30 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_CTRL :: BYPASS_PLL_STATE [29:29] */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_DEFAULT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_normal_PLL_mode 0 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_bypassed_PLL_mode 1 |
| |
| /* union - case normal_PLL_mode [28:23] */ |
| /* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: A_RST_PLL [28:28] */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: D_RST_PLL [27:27] */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: CPU_FREQ [26:24] */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [23:23] */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_DEFAULT 0 |
| |
| /* union - case bypassed_PLL_mode [28:23] */ |
| /* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: A_RST_PLL [28:28] */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: D_RST_PLL [27:27] */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: CPU_FREQ [26:24] */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_MASK 0x07000000 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_SHIFT 24 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [23:23] */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_MIPS_CTRL :: reserved1 [22:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved1_MASK 0x007fffff |
| #define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved1_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_MIPS_PLL_RESET_STATUS - Resets status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_AUDIO0_PLL_RESET_STATUS - Resets status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_AUDIO1_PLL_RESET_STATUS - Resets status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_RESET_STATUS - Resets status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETD_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_RESETA_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_MOCA_PLL_RESET_STATUS - Resets status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_VCXO_PLL_RESET_STATUS - Resets status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETD_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_RESETA_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_RAAGA_PLL_RESET_STATUS - Resets status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_SYS1_PLL_RESET_STATUS - Resets status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETD_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_RESETA_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_SC_PLL_RESET_STATUS - Resets status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_DEFAULT 1 |
| |
| /*************************************************************************** |
| *TESTPORT - Special Testport Controls |
| ***************************************************************************/ |
| /* CLKGEN :: TESTPORT :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_TESTPORT_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */ |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK 0x0000000f |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT 0 |
| #define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_RESET - Resets |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_RESET :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_RESET :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETD_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_RESET :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_RESETA_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_PWRDN - Powerdowns |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_PWRDN :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_PWRDN :: PWRDN_PLL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_PWRDN_PLL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_PWRDN_PLL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_PWRDN_PWRDN_PLL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_CONTROL - Miscellaneous Controls |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_CONTROL :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CONTROL :: REF_SEL [00:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_REF_SEL_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_REF_SEL_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CONTROL_REF_SEL_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_DIV - Pre multiplier |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_DIV :: reserved0 [31:13] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_reserved0_MASK 0xffffe000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_reserved0_SHIFT 13 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_DIV :: NDIV_INT [12:03] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_NDIV_INT_MASK 0x00001ff8 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_NDIV_INT_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_NDIV_INT_DEFAULT 64 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_DIV :: PDIV [02:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_PDIV_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_PDIV_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_DIV_PDIV_DEFAULT 2 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 4 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 36 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2 |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x00003fc0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 36 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_GAIN - PLL GAIN |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_GAIN :: reserved0 [31:24] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_reserved0_MASK 0xff000000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_reserved0_SHIFT 24 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK 0x00000007 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_MISC - Mscellaneous control bus. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: reserved0 [31:30] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_reserved0_MASK 0xc0000000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_reserved0_SHIFT 30 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: MDIV_RELOCK [29:29] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_MDIV_RELOCK_MASK 0x20000000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_MDIV_RELOCK_SHIFT 29 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_MDIV_RELOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: FAST_LOCK [28:28] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_FAST_LOCK_MASK 0x10000000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_FAST_LOCK_SHIFT 28 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_FAST_LOCK_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: VCODIV2 [27:27] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_MASK 0x08000000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_SHIFT 27 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: VCO_DLY [26:25] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCO_DLY_MASK 0x06000000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCO_DLY_SHIFT 25 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCO_DLY_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: PWM_RATE [24:23] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_PWM_RATE_MASK 0x01800000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_PWM_RATE_SHIFT 23 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_PWM_RATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: STAT_MODE [22:21] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_MODE_MASK 0x00600000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_MODE_SHIFT 21 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_MODE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: VCODIV2_POST [20:20] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_POST_MASK 0x00100000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_POST_SHIFT 20 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_VCODIV2_POST_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: AUX_CTRL [19:19] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_AUX_CTRL_MASK 0x00080000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_AUX_CTRL_SHIFT 19 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_AUX_CTRL_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: REFCLKOUT [18:18] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_REFCLKOUT_MASK 0x00040000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_REFCLKOUT_SHIFT 18 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_REFCLKOUT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: STAT_UPDATE [17:17] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_UPDATE_MASK 0x00020000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_UPDATE_SHIFT 17 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_UPDATE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: STAT_SELECT [16:14] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_SELECT_MASK 0x0001c000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_SELECT_SHIFT 14 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_SELECT_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: STAT_RESET_ [13:13] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_RESET__MASK 0x00002000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_RESET__SHIFT 13 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_STAT_RESET__DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT 0 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_LOCK_STATUS - Lock Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_LOCK_STATUS :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_LOCK_STATUS :: LOCK [00:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS_LOCK_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_LOCK_STATUS_LOCK_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_STATUS - Status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_STATUS :: reserved0 [31:12] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS_reserved0_MASK 0xfffff000 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS_reserved0_SHIFT 12 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_STATUS :: TEST_STATUS [11:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS_TEST_STATUS_MASK 0x00000fff |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_STATUS_TEST_STATUS_SHIFT 0 |
| |
| /*************************************************************************** |
| *PLL_AFEC_PLL_RESET_STATUS - Resets status |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AFEC_PLL_RESET_STATUS :: reserved0 [31:02] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_reserved0_MASK 0xfffffffc |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_reserved0_SHIFT 2 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_RESET_STATUS :: RESETD [01:01] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETD_MASK 0x00000002 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETD_SHIFT 1 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETD_DEFAULT 1 |
| |
| /* CLKGEN :: PLL_AFEC_PLL_RESET_STATUS :: RESETA [00:00] */ |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETA_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETA_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AFEC_PLL_RESET_STATUS_RESETA_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PLL_AVD_PLL_MISC2 - Miscellaneous control bus continued. |
| ***************************************************************************/ |
| /* CLKGEN :: PLL_AVD_PLL_MISC2 :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: PLL_AVD_PLL_MISC2 :: SPARE [00:00] */ |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_MASK 0x00000001 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_SHIFT 0 |
| #define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_DEFAULT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_CONTROL - Clock Monitor Control |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK 0x00000008 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT 3 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 1 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK 0x00000004 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT 2 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 1 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK 0x00000002 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT 1 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT 1 |
| |
| /* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 1 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 4294967295 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK 0xfffffffe |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT 1 |
| |
| /* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK 0x00000001 |
| #define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT 0 |
| |
| /*************************************************************************** |
| *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter |
| ***************************************************************************/ |
| /* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */ |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff |
| #define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0 |
| |
| /*************************************************************************** |
| *PM_PLL_LDO_POWERUP - Power management LDO PLL |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:04] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK 0xfffffff0 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT 4 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_SYS1 [03:03] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SYS1_MASK 0x00000008 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SYS1_SHIFT 3 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_SYS1_DEFAULT 1 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [02:02] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK 0x00000004 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT 2 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 1 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [01:01] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK 0x00000002 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT 1 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT 1 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT 1 |
| |
| /*************************************************************************** |
| *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine |
| ***************************************************************************/ |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK 0xf8000000 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT 27 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 5400 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 200 |
| |
| /* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */ |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK 0x00000001 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT 0 |
| #define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0 |
| |
| #endif /* #ifndef BCHP_CLKGEN_H__ */ |
| |
| /* End of File */ |
