/***************************************************************************
 *     Copyright (c) 1999-2011, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Tue May 31 13:56:02 2011
 *                 MD5 Checksum         b0a0062767e487fe78d25d07b5b21b78
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7344/rdb/b0/bchp_clkgen.h $
 * 
 * Hydra_Software_Devel/2   5/31/11 3:28p albertl
 * SW7344-40: Updated to match RDB.
 *
 ***************************************************************************/

#ifndef BCHP_CLKGEN_H__
#define BCHP_CLKGEN_H__

/***************************************************************************
 *CLKGEN - clkgen registers
 ***************************************************************************/
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x00040000 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x00040004 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x00040008 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x0004000c /* Lock Status */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x00040010 /* Powerdowns */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x00040014 /* Resets */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x00040018 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x0004001c /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x00040020 /* Test Status */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x00040024 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x00040028 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x0004002c /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x00040030 /* Lock Status */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x00040034 /* Powerdowns */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x00040038 /* Resets */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x0004003c /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x00040040 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x00040044 /* Test Status */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0 0x00040048 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1 0x0004004c /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2 0x00040050 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL          0x00040054 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV              0x00040058 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN             0x0004005c /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS      0x00040060 /* Lock Status */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC             0x00040064 /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2            0x00040068 /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN            0x0004006c /* Powerdowns */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET            0x00040070 /* Resets */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH 0x00040074 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW 0x00040078 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS           0x0004007c /* Test Status */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x00040080 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 0x00040084 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL         0x00040088 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV             0x0004008c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN            0x00040090 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS     0x00040094 /* Lock Status */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC            0x00040098 /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2           0x0004009c /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN           0x000400a0 /* Powerdowns */
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET           0x000400a4 /* Resets */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x000400a8 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x000400ac /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS          0x000400b0 /* Test Status */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x000400b4 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x000400b8 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x000400bc /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x000400c0 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x000400c4 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x000400c8 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL         0x000400cc /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV             0x000400d0 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN            0x000400d4 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS     0x000400d8 /* Lock Status */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC            0x000400dc /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2           0x000400e0 /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN           0x000400e4 /* Powerdowns */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET           0x000400e8 /* Resets */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x000400ec /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x000400f0 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS          0x000400f4 /* Test Status */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x000400f8 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 0x000400fc /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL        0x00040100 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV            0x00040104 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN           0x00040108 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS    0x0004010c /* Lock Status */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC           0x00040110 /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2          0x00040114 /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN          0x00040118 /* Powerdowns */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET          0x0004011c /* Resets */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x00040120 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x00040124 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS         0x00040128 /* Test Status */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x0004012c /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x00040130 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2 0x00040134 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x00040138 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x0004013c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x00040140 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x00040144 /* Lock Status */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x00040148 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x0004014c /* Powerdowns */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x00040150 /* Resets */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x00040154 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x00040158 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x0004015c /* Test Status */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x00040160 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x00040164 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x00040168 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x0004016c /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x00040170 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x00040174 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x00040178 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV             0x0004017c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x00040180 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x00040184 /* Lock Status */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x00040188 /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x0004018c /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN           0x00040190 /* Powerdowns */
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET           0x00040194 /* Resets */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x00040198 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x0004019c /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x000401a0 /* Test Status */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 0x000401a4 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 0x000401a8 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 0x000401ac /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 0x000401b0 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 0x000401b4 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 0x000401b8 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL         0x000401bc /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV             0x000401c0 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN            0x000401c4 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS     0x000401c8 /* Lock Status */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC            0x000401cc /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN           0x000401d0 /* Powerdowns */
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET           0x000401d4 /* Resets */
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH 0x000401d8 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW 0x000401dc /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS          0x000401e0 /* Status */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 0x000401e4 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 0x000401e8 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 0x000401ec /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL         0x000401f0 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV             0x000401f4 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC            0x000401f8 /* Fractional */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN            0x000401fc /* PLL GAIN */
#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS     0x00040200 /* Lock Status */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC            0x00040204 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN           0x00040208 /* Powerdowns */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET           0x0004020c /* Resets */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH 0x00040210 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW 0x00040214 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS          0x00040218 /* Test Status */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE    0x0004021c /* Bvn top inst clock enable */
#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040220 /* Bvn top inst memory standby enable */
#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY 0x00040224 /* Bvn top inst power switch memory */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE         0x00040228 /* Disable CLKGEN's clocks */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE     0x0004022c /* Clkgen inst clock enable */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x00040230 /* Clock Monitor Control */
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x00040234 /* Clock Monitor Max Reference Count */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x00040238 /* Clock Monitor Reference Counter */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x0004023c /* Clock Monitor Reference Counter */
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x00040240 /* Clock Monitor View Counter */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE  0x00040244 /* Disable CORE_XPT_INST's clocks */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE   0x00040248 /* Core xpt inst clock enable */
#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE 0x0004024c /* Core xpt inst memory standby enable */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK  0x00040250 /* Core xpt inst observe clock */
#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY 0x00040254 /* Core xpt inst power switch memory */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE 0x00040258 /* Disable DUAL_GENET_TOP_RGMII_INST's clocks */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE 0x0004025c /* Dual genet top rgmii inst clock enable */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT 0x00040260 /* Dual genet top rgmii inst clock select */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x00040264 /* Dual genet top rgmii inst memory standby enable a */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK 0x00040268 /* Dual genet top rgmii inst observe clock */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A 0x0004026c /* Dual genet top rgmii inst power switch memory a */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE    0x00040270 /* Disable DVP_HT_INST's clocks */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE     0x00040274 /* Dvp ht inst clock enable */
#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE 0x00040278 /* Dvp ht inst memory standby enable */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK    0x0004027c /* Dvp ht inst observe clock */
#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY 0x00040280 /* Dvp ht inst power switch memory */
#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE    0x00040284 /* Fsk top inst clock enable */
#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040288 /* Fsk top inst memory standby enable */
#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY 0x0004028c /* Fsk top inst power switch memory */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE  0x00040290 /* Disable GRAPHICS_INST's clocks */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE   0x00040294 /* Graphics inst clock enable */
#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE 0x00040298 /* Graphics inst memory standby enable */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK  0x0004029c /* Graphics inst observe clock */
#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY 0x000402a0 /* Graphics inst power switch memory */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE       0x000402a4 /* Disable HIF_INST's clocks */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x000402a8 /* Mux selects for Internal clocks */
#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE  0x000402ac /* Memsys 32 inst clock enable */
#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE 0x000402b0 /* Memsys 32 inst memory standby enable */
#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK 0x000402b4 /* Memsys 32 inst observe clock */
#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY 0x000402b8 /* Memsys 32 inst power switch memory */
#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS        0x000402bc /* Memsys 32 inst status */
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE   0x000402c0 /* Moca top inst clock enable */
#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE 0x000402c4 /* Moca top inst memory standby enable */
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK  0x000402c8 /* Moca top inst observe clock */
#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY 0x000402cc /* Moca top inst power switch memory */
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION        0x000402d0 /* Select observation clk */
#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION      0x000402d4 /* Select observation clk */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x000402d8 /* Disable PAD's clocks */
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION   0x000402dc /* Select observation clk */
#define BCHP_CLKGEN_PAD_MUX_SELECT               0x000402e0 /* Mux selects for Pad clocks */
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION       0x000402e4 /* Select observation clk */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x000402e8 /* PLL_AUDIO0 Reset Status */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x000402ec /* PLL_AUDIO1 Reset Status */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS     0x000402f0 /* PLL_AVD Reset Status */
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL       0x000402f4 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST 0x000402f8 /* PLL_MIPS Glitchless Clock Switching */
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS 0x000402fc /* PLL_MIPS Glitchless Switching */
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS    0x00040300 /* PLL_MIPS Reset Status */
#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL      0x00040304 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS    0x00040308 /* PLL_MOCA Reset Status */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL      0x0004030c /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS   0x00040310 /* PLL_RAAGA Reset Status */
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL     0x00040314 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x00040318 /* PLL_SC Reset Status */
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE           0x0004031c /* Disable */
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL      0x00040320 /* PLL RDB Macro Disable */
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS    0x00040324 /* PLL_SYS1 Reset Status */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS    0x00040328 /* PLL_VCXO Reset Status */
#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL       0x0004032c /* Select clocks that can stay alive during power management standby mode. */
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x00040330 /* Select clocks that can stay alive during power management standby mode. */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x00040334 /* PLL Alive in Standby Mode */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x00040338 /* Power management LDO PLL */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM        0x0004033c /* Power management LDO PLL state machine */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE 0x00040340 /* Raaga dsp top inst clock enable */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040344 /* Raaga dsp top inst memory standby enable */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK 0x00040348 /* Raaga dsp top inst observe clock */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY 0x0004034c /* Raaga dsp top inst power switch memory */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE 0x00040350 /* Sds0 afec top inst clock enable */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040354 /* Sds0 afec top inst memory standby enable */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK 0x00040358 /* Sds0 afec top inst observe clock */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY 0x0004035c /* Sds0 afec top inst power switch memory */
#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE  0x00040360 /* Disable SDS0_TOP_INST's clocks */
#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE   0x00040364 /* Sds0 top inst clock enable */
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK  0x00040368 /* Sds0 top inst observe clock */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA 0x0004036c /* Sectop inst clock enable m2mdma */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x00040370 /* Sectop inst observe clock */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00040374 /* Mux selects for Smartcard clocks */
#define BCHP_CLKGEN_SPARE                        0x00040378 /* Spares */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE   0x0004037c /* Svd0 top inst clock enable */
#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE 0x00040380 /* Svd0 top inst memory standby enable */
#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY 0x00040384 /* Svd0 top inst power switch memory */
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK   0x00040388 /* Sys aon inst observe clock */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE  0x0004038c /* Disable SYS_CTRL_INST's clocks */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE   0x00040390 /* Sys ctrl inst clock enable */
#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE 0x00040394 /* Sys ctrl inst memory standby enable */
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK  0x00040398 /* Sys ctrl inst observe clock */
#define BCHP_CLKGEN_TESTPORT                     0x0004039c /* Special Testport Controls */
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE  0x000403a0 /* Disable UHFR_TOP_INST's clocks */
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE   0x000403a4 /* Uhfr top inst clock enable */
#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE 0x000403a8 /* Uhfr top inst memory standby enable */
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK  0x000403ac /* Uhfr top inst observe clock */
#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY 0x000403b0 /* Uhfr top inst power switch memory */
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE      0x000403b4 /* Disable USB0_INST's clocks */
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE       0x000403b8 /* Usb0 inst clock enable */
#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE 0x000403bc /* Usb0 inst memory standby enable */
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK      0x000403c0 /* Usb0 inst observe clock */
#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY 0x000403c4 /* Usb0 inst power switch memory */
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE      0x000403c8 /* Disable USB1_INST's clocks */
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE       0x000403cc /* Usb1 inst clock enable */
#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE 0x000403d0 /* Usb1 inst memory standby enable */
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK      0x000403d4 /* Usb1 inst observe clock */
#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY 0x000403d8 /* Usb1 inst power switch memory */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x000403dc /* Disable VEC_AIO_TOP_INST's clocks */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x000403e0 /* Vec aio top inst clock enable */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x000403e4 /* Vec aio top inst clock enable aio */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x000403e8 /* Vec aio top inst clock enable vec */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO 0x000403ec /* Vec aio top inst memory standby enable aio */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC 0x000403f0 /* Vec aio top inst memory standby enable vec */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x000403f4 /* Vec aio top inst observe clock */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO 0x000403f8 /* Vec aio top inst power switch memory aio */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC 0x000403fc /* Vec aio top inst power switch memory vec */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE  0x00040400 /* Disable ZCPU_TOP_INST's clocks */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE   0x00040404 /* Zcpu top inst clock enable */
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK  0x00040408 /* Zcpu top inst observe clock */

/***************************************************************************
 *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1

/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0

/***************************************************************************
 *PLL_AUDIO0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3

/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                1

/***************************************************************************
 *PLL_AUDIO0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1

/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0

/***************************************************************************
 *PLL_AUDIO0_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1

/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0

/***************************************************************************
 *PLL_AUDIO0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2

/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0

/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0

/***************************************************************************
 *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO0_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12

/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0

/***************************************************************************
 *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1

/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0

/***************************************************************************
 *PLL_AUDIO1_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3

/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                1

/***************************************************************************
 *PLL_AUDIO1_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x000000e0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    5
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1

/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0

/***************************************************************************
 *PLL_AUDIO1_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1

/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0

/***************************************************************************
 *PLL_AUDIO1_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2

/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0

/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0

/***************************************************************************
 *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO1_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12

/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffffc000
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  14

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 6

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xffffc000
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  14

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 8

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_AVD_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK   0xffffc000
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT  14

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK    0x000001fe
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT   1
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 100

/* CLKGEN :: PLL_AVD_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_AVD_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_reserved0_SHIFT            1

/* CLKGEN :: PLL_AVD_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_SHIFT              0
#define BCHP_CLKGEN_PLL_AVD_PLL_CONTROL_REF_SEL_DEFAULT            0

/***************************************************************************
 *PLL_AVD_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_MASK                 0xffffe000
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_reserved0_SHIFT                13

/* CLKGEN :: PLL_AVD_PLL_DIV :: PDIV [12:10] */
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_MASK                      0x00001c00
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_SHIFT                     10
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_PDIV_DEFAULT                   3

/* CLKGEN :: PLL_AVD_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_MASK                  0x000003ff
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_SHIFT                 0
#define BCHP_CLKGEN_PLL_AVD_PLL_DIV_NDIV_INT_DEFAULT               142

/***************************************************************************
 *PLL_AVD_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_MASK                0xff000000
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_reserved0_SHIFT               24

/* CLKGEN :: PLL_AVD_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6

/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x000000e0
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       5
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     2

/* CLKGEN :: PLL_AVD_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_AVD_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/***************************************************************************
 *PLL_AVD_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_MASK         0x00000002
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_LOST_SHIFT        1

/* CLKGEN :: PLL_AVD_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_LOCK_STATUS_LOCK_SHIFT             0

/***************************************************************************
 *PLL_AVD_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_MASK                0x80000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_reserved0_SHIFT               31

/* CLKGEN :: PLL_AVD_PLL_MISC :: VCO_DLY [30:29] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_MASK                  0x60000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_SHIFT                 29
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCO_DLY_DEFAULT               0

/* CLKGEN :: PLL_AVD_PLL_MISC :: VCODIV2 [28:28] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_MASK                  0x10000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_SHIFT                 28
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_VCODIV2_DEFAULT               0

/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_UPDATE [27:27] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_MASK              0x08000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_SHIFT             27
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_UPDATE_DEFAULT           0

/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_SELECT [26:24] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_MASK              0x07000000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_SHIFT             24
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_SELECT_DEFAULT           0

/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_RESET_ [23:23] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__MASK              0x00800000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__SHIFT             23
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_RESET__DEFAULT           0

/* CLKGEN :: PLL_AVD_PLL_MISC :: STAT_MODE [22:21] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_MASK                0x00600000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_SHIFT               21
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_STAT_MODE_DEFAULT             0

/* CLKGEN :: PLL_AVD_PLL_MISC :: REFCLKOUT [20:20] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_MASK                0x00100000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_SHIFT               20
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_REFCLKOUT_DEFAULT             0

/* CLKGEN :: PLL_AVD_PLL_MISC :: PWM_RATE [19:18] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_MASK                 0x000c0000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_SHIFT                18
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_PWM_RATE_DEFAULT              0

/* CLKGEN :: PLL_AVD_PLL_MISC :: POR_BYPASS [17:17] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_MASK               0x00020000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_SHIFT              17
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_POR_BYPASS_DEFAULT            0

/* CLKGEN :: PLL_AVD_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_MASK              0x00010000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_SHIFT             16
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_NDIV_RELOCK_DEFAULT           0

/* CLKGEN :: PLL_AVD_PLL_MISC :: LDO_REF_SEL [15:15] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_MASK              0x00008000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_SHIFT             15
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_LDO_REF_SEL_DEFAULT           0

/* CLKGEN :: PLL_AVD_PLL_MISC :: FAST_LOCK [14:14] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_MASK                0x00004000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_SHIFT               14
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_FAST_LOCK_DEFAULT             0

/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00002000
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  13
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00001ffe
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         1
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0

/* CLKGEN :: PLL_AVD_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_SHIFT                0
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC_AUX_CTRL_DEFAULT              0

/***************************************************************************
 *PLL_AVD_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_reserved0_SHIFT              1

/* CLKGEN :: PLL_AVD_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_MASK                   0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_SHIFT                  0
#define BCHP_CLKGEN_PLL_AVD_PLL_MISC2_SPARE_DEFAULT                0

/***************************************************************************
 *PLL_AVD_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_reserved0_SHIFT              1

/* CLKGEN :: PLL_AVD_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_SHIFT              0
#define BCHP_CLKGEN_PLL_AVD_PLL_PWRDN_PWRDN_PLL_DEFAULT            0

/***************************************************************************
 *PLL_AVD_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_reserved0_SHIFT              2

/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_MASK                  0x00000002
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_SHIFT                 1
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETD_DEFAULT               0

/* CLKGEN :: PLL_AVD_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_SHIFT                 0
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_RESETA_DEFAULT               0

/***************************************************************************
 *PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_AVD_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/* CLKGEN :: PLL_AVD_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/***************************************************************************
 *PLL_AVD_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_MASK              0xfffff000
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_reserved0_SHIFT             12

/* CLKGEN :: PLL_AVD_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
#define BCHP_CLKGEN_PLL_AVD_PLL_STATUS_TEST_STATUS_SHIFT           0

/***************************************************************************
 *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 3

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 100

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT           1

/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT             0
#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT           0

/***************************************************************************
 *PLL_MIPS_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK                0xffffe000
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT               13

/* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [12:10] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK                     0x00001c00
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT                    10
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT                  3

/* CLKGEN :: PLL_MIPS_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_MASK                 0x000003ff
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_SHIFT                0
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_NDIV_INT_DEFAULT              150

/***************************************************************************
 *PLL_MIPS_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK               0xff000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT              24

/* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6

/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2

/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/***************************************************************************
 *PLL_MIPS_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1

/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT            0

/***************************************************************************
 *PLL_MIPS_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK               0x80000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT              31

/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [30:29] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK                 0x60000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT                29
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT              0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [28:28] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK                 0x10000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT                28
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT              0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [27:27] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK             0x08000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT            27
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT          0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [26:24] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK             0x07000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT            24
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT          0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [23:23] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK             0x00800000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT            23
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT          0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [22:21] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK               0x00600000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT              21
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT            0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [20:20] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK               0x00100000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT              20
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT            0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [19:18] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK                0x000c0000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT               18
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT             0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [17:17] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK              0x00020000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT             17
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT           0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT            16
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT          0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [15:15] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT            15
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT          0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [14:14] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK               0x00004000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT              14
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT            0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT               0
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT             0

/***************************************************************************
 *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT             1

/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT                 0
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT               0

/***************************************************************************
 *PLL_MIPS_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_reserved0_SHIFT             1

/* CLKGEN :: PLL_MIPS_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_MIPS_PLL_PWRDN_PWRDN_PLL_DEFAULT           0

/***************************************************************************
 *PLL_MIPS_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_reserved0_SHIFT             2

/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_MASK                 0x00000002
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_SHIFT                1
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETD_DEFAULT              0

/* CLKGEN :: PLL_MIPS_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_SHIFT                0
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_RESETA_DEFAULT              0

/***************************************************************************
 *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/***************************************************************************
 *PLL_MIPS_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 16

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 36

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 72

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 9

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 75

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_SHIFT           1

/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_SHIFT             0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_DEFAULT           0

/***************************************************************************
 *PLL_MOCA_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK                0xffffe000
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT               13

/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [12:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK                     0x00001c00
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT                    10
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT                  3

/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK                 0x000003ff
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT                0
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT              200

/***************************************************************************
 *PLL_MOCA_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK               0xff000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT              24

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1

/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT            0

/***************************************************************************
 *PLL_MOCA_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_MASK               0x80000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_SHIFT              31

/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_DLY [30:29] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_MASK                 0x60000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_SHIFT                29
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_DEFAULT              0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCODIV2 [28:28] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_MASK                 0x10000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_SHIFT                28
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_DEFAULT              1

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [27:27] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK             0x08000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT            27
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT          0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [26:24] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK             0x07000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT            24
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT          0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET_ [23:23] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__MASK             0x00800000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__SHIFT            23
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__DEFAULT          0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [22:21] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK               0x00600000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT              21
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT            0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: REFCLKOUT [20:20] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_MASK               0x00100000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_SHIFT              20
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_DEFAULT            0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [19:18] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK                0x000c0000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT               18
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT             2

/* CLKGEN :: PLL_MOCA_PLL_MISC :: POR_BYPASS [17:17] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_MASK              0x00020000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_SHIFT             17
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_DEFAULT           0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT            16
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT          0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: LDO_REF_SEL [15:15] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_SHIFT            15
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_DEFAULT          0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [14:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK               0x00004000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT              14
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT            0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_SHIFT               0
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_DEFAULT             0

/***************************************************************************
 *PLL_MOCA_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_SHIFT             1

/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_SHIFT                 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_DEFAULT               0

/***************************************************************************
 *PLL_MOCA_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_SHIFT             1

/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_DEFAULT           0

/***************************************************************************
 *PLL_MOCA_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT             2

/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK                 0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT                1
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT              0

/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT                0
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT              0

/***************************************************************************
 *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 7

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x000001fe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 9

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_RAAGA_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_SHIFT          1

/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_SHIFT            0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_DEFAULT          0

/***************************************************************************
 *PLL_RAAGA_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK               0xffffe000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT              13

/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [12:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK                    0x00001c00
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT                   10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT                 2

/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK                0x000003ff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT               0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT             143

/***************************************************************************
 *PLL_RAAGA_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK              0xff000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT             24

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 9

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x000000e0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     5
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   2

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/***************************************************************************
 *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      1

/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT           0

/***************************************************************************
 *PLL_RAAGA_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_MASK              0x80000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_SHIFT             31

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_DLY [30:29] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_MASK                0x60000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_SHIFT               29
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_DEFAULT             0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCODIV2 [28:28] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_MASK                0x10000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_SHIFT               28
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_DEFAULT             1

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [27:27] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK            0x08000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT           27
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT         0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [26:24] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK            0x07000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT           24
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT         0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET_ [23:23] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__MASK            0x00800000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__SHIFT           23
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__DEFAULT         0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [22:21] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK              0x00600000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT             21
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT           0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: REFCLKOUT [20:20] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_MASK              0x00100000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_SHIFT             20
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_DEFAULT           0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [19:18] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK               0x000c0000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT              18
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT            2

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POR_BYPASS [17:17] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_MASK             0x00020000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_SHIFT            17
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_DEFAULT          0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK            0x00010000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT           16
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT         0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: LDO_REF_SEL [15:15] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_MASK            0x00008000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_SHIFT           15
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_DEFAULT         0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [14:14] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK              0x00004000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT             14
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT           0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00001ffe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_SHIFT              0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_DEFAULT            0

/***************************************************************************
 *PLL_RAAGA_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_SHIFT            1

/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_SHIFT                0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_DEFAULT              0

/***************************************************************************
 *PLL_RAAGA_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_SHIFT            1

/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_DEFAULT          0

/***************************************************************************
 *PLL_RAAGA_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT             0

/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT             0

/***************************************************************************
 *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/***************************************************************************
 *PLL_RAAGA_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x000001fe
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    1
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  40

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x000001fe
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    1
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  40

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_SC_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK    0xffffc000
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT   14

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK     0x000001fe
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT    1
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT  96

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_SC_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1

/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0

/***************************************************************************
 *PLL_SC_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13

/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [12:10] */
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00001c00
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      10
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    1

/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x000003ff
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  0
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                64

/***************************************************************************
 *PLL_SC_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24

/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7

/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x000000e0
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        5
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      1

/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/***************************************************************************
 *PLL_SC_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1

/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0

/***************************************************************************
 *PLL_SC_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30

/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [29:28] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x30000000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  28
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0

/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [27:27] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x08000000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             27
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0

/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [26:26] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x04000000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  26
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0

/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [25:25] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x02000000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              25
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0

/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [24:22] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x01c00000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              22
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0

/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [21:21] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00200000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              21
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0

/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [20:19] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00180000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                19
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0

/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0

/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [17:16] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x00030000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 16
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0

/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [15:15] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x00008000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              15
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0

/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [14:14] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x00004000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                14
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0

/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00002000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   13
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00001ffe
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          1
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0

/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 0
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0

/***************************************************************************
 *PLL_SC_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1

/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0

/***************************************************************************
 *PLL_SC_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2

/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0

/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0

/***************************************************************************
 *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00400000
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/***************************************************************************
 *PLL_SC_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12

/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 18

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 36

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 81

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 48

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 10

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1

/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0

/***************************************************************************
 *PLL_SYS0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_MASK                0xffffe000
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_reserved0_SHIFT               13

/* CLKGEN :: PLL_SYS0_PLL_DIV :: PDIV [12:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_MASK                     0x00001c00
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_SHIFT                    10
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_PDIV_DEFAULT                  1

/* CLKGEN :: PLL_SYS0_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_MASK                 0x000003ff
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_SHIFT                0
#define BCHP_CLKGEN_PLL_SYS0_PLL_DIV_NDIV_INT_DEFAULT              72

/***************************************************************************
 *PLL_SYS0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 10

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    3

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [01:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000002
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       1

/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            0

/***************************************************************************
 *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31

/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [30:29] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x60000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                29
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [28:28] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x10000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                28
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              1

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [27:27] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x08000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            27
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [26:24] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x07000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            24
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [23:23] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00800000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            23
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [22:21] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00600000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              21
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [20:20] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00100000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              20
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [19:18] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x000c0000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               18
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             2

/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [17:17] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x00020000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             17
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [16:16] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x00010000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            16
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [15:15] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x00008000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            15
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [14:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x00004000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              14
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               0
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0

/***************************************************************************
 *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1

/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0

/***************************************************************************
 *PLL_SYS0_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_reserved0_SHIFT             1

/* CLKGEN :: PLL_SYS0_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_SYS0_PLL_PWRDN_PWRDN_PLL_DEFAULT           0

/***************************************************************************
 *PLL_SYS0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_RESET :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_reserved0_SHIFT             1

/* CLKGEN :: PLL_SYS0_PLL_RESET :: RESETD [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_SHIFT                0
#define BCHP_CLKGEN_PLL_SYS0_PLL_RESET_RESETD_DEFAULT              0

/***************************************************************************
 *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 18

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 9

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [13:13] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [12:12] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [11:09] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [08:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 90

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0

/***************************************************************************
 *PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [13:13] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [12:12] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [11:09] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [08:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 90

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0

/***************************************************************************
 *PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [13:13] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00002000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [12:12] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00001000
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [11:09] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 9
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [08:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  1
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 45

/* CLKGEN :: PLL_SYS1_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS1_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0

/***************************************************************************
 *PLL_SYS1_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_reserved0_SHIFT           1

/* CLKGEN :: PLL_SYS1_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_SHIFT             0
#define BCHP_CLKGEN_PLL_SYS1_PLL_CONTROL_REF_SEL_DEFAULT           0

/***************************************************************************
 *PLL_SYS1_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_MASK                0xffffe000
#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_reserved0_SHIFT               13

/* CLKGEN :: PLL_SYS1_PLL_DIV :: PDIV [12:10] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_MASK                     0x00001c00
#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_SHIFT                    10
#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_PDIV_DEFAULT                  3

/* CLKGEN :: PLL_SYS1_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_MASK                 0x000003ff
#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_SHIFT                0
#define BCHP_CLKGEN_PLL_SYS1_PLL_DIV_NDIV_INT_DEFAULT              125

/***************************************************************************
 *PLL_SYS1_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_MASK               0xff000000
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_reserved0_SHIFT              24

/* CLKGEN :: PLL_SYS1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8

/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1

/* CLKGEN :: PLL_SYS1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_SYS1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/***************************************************************************
 *PLL_SYS1_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_reserved0_SHIFT       1

/* CLKGEN :: PLL_SYS1_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_LOCK_STATUS_LOCK_SHIFT            0

/***************************************************************************
 *PLL_SYS1_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_MISC :: reserved0 [31:30] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_MASK               0xc0000000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_reserved0_SHIFT              30

/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCO_DLY [29:28] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_MASK                 0x30000000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_SHIFT                28
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCO_DLY_DEFAULT              0

/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2_POST [27:27] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_MASK            0x08000000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_SHIFT           27
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_POST_DEFAULT         0

/* CLKGEN :: PLL_SYS1_PLL_MISC :: VCODIV2 [26:26] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_MASK                 0x04000000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_SHIFT                26
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_VCODIV2_DEFAULT              1

/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_UPDATE [25:25] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_MASK             0x02000000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_SHIFT            25
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_UPDATE_DEFAULT          0

/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_SELECT [24:22] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_MASK             0x01c00000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_SHIFT            22
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_SELECT_DEFAULT          0

/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_RESET_ [21:21] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__MASK             0x00200000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__SHIFT            21
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_RESET__DEFAULT          0

/* CLKGEN :: PLL_SYS1_PLL_MISC :: STAT_MODE [20:19] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_MASK               0x00180000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_SHIFT              19
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_STAT_MODE_DEFAULT            0

/* CLKGEN :: PLL_SYS1_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_MASK               0x00040000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_SHIFT              18
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_REFCLKOUT_DEFAULT            0

/* CLKGEN :: PLL_SYS1_PLL_MISC :: PWM_RATE [17:16] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_MASK                0x00030000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_SHIFT               16
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_PWM_RATE_DEFAULT             2

/* CLKGEN :: PLL_SYS1_PLL_MISC :: MDIV_RELOCK [15:15] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_SHIFT            15
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_MDIV_RELOCK_DEFAULT          0

/* CLKGEN :: PLL_SYS1_PLL_MISC :: FAST_LOCK [14:14] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_MASK               0x00004000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_SHIFT              14
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_FAST_LOCK_DEFAULT            0

/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0

/* CLKGEN :: PLL_SYS1_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_SHIFT               0
#define BCHP_CLKGEN_PLL_SYS1_PLL_MISC_AUX_CTRL_DEFAULT             0

/***************************************************************************
 *PLL_SYS1_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_reserved0_SHIFT             1

/* CLKGEN :: PLL_SYS1_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_SYS1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0

/***************************************************************************
 *PLL_SYS1_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_reserved0_SHIFT             2

/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_MASK                 0x00000002
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_SHIFT                1
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETD_DEFAULT              0

/* CLKGEN :: PLL_SYS1_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_SHIFT                0
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_RESETA_DEFAULT              0

/***************************************************************************
 *PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/* CLKGEN :: PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/***************************************************************************
 *PLL_SYS1_PLL_STATUS - Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_SYS1_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_SYS1_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [13:13] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00002000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [12:12] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00001000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 12
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [11:09] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  1
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 64

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [13:13] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00002000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [12:12] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00001000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 12
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [11:09] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  1
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 250

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [13:13] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00002000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [12:12] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00001000
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 12
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [11:09] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x00000e00
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 9
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [08:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x000001fe
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  1
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 75

/* CLKGEN :: PLL_VCXO_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_VCXO_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_reserved0_SHIFT           1

/* CLKGEN :: PLL_VCXO_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_SHIFT             0
#define BCHP_CLKGEN_PLL_VCXO_PLL_CONTROL_REF_SEL_DEFAULT           0

/***************************************************************************
 *PLL_VCXO_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_MASK                0xffffe000
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_reserved0_SHIFT               13

/* CLKGEN :: PLL_VCXO_PLL_DIV :: PDIV [12:10] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_MASK                     0x00001c00
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_SHIFT                    10
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_PDIV_DEFAULT                  2

/* CLKGEN :: PLL_VCXO_PLL_DIV :: NDIV_INT [09:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_MASK                 0x000003ff
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_SHIFT                0
#define BCHP_CLKGEN_PLL_VCXO_PLL_DIV_NDIV_INT_DEFAULT              64

/***************************************************************************
 *PLL_VCXO_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_MASK               0xfff00000
#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_reserved0_SHIFT              20

/* CLKGEN :: PLL_VCXO_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_MASK            0x000fffff
#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_SHIFT           0
#define BCHP_CLKGEN_PLL_VCXO_PLL_FRAC_FRAC_CONTROL_DEFAULT         0

/***************************************************************************
 *PLL_VCXO_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_MASK               0xff000000
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_reserved0_SHIFT              24

/* CLKGEN :: PLL_VCXO_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [23:12] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x00fff000
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 12
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [11:08] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x00000f00
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 8
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8

/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_IN_FREQ [07:05] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x000000e0
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      5
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    1

/* CLKGEN :: PLL_VCXO_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [04:02] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x0000001c
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 2
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_VCXO_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [01:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/***************************************************************************
 *PLL_VCXO_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_reserved0_SHIFT       1

/* CLKGEN :: PLL_VCXO_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_LOCK_STATUS_LOCK_SHIFT            0

/***************************************************************************
 *PLL_VCXO_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_MISC :: reserved0 [31:30] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_MASK               0xc0000000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_reserved0_SHIFT              30

/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCO_DLY [29:28] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_MASK                 0x30000000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_SHIFT                28
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCO_DLY_DEFAULT              0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2_POST [27:27] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_MASK            0x08000000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_SHIFT           27
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_POST_DEFAULT         0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: VCODIV2 [26:26] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_MASK                 0x04000000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_SHIFT                26
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_VCODIV2_DEFAULT              0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_UPDATE [25:25] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_MASK             0x02000000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_SHIFT            25
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_UPDATE_DEFAULT          0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_SELECT [24:22] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_MASK             0x01c00000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_SHIFT            22
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_SELECT_DEFAULT          0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_RESET_ [21:21] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__MASK             0x00200000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__SHIFT            21
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_RESET__DEFAULT          0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: STAT_MODE [20:19] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_MASK               0x00180000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_SHIFT              19
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_STAT_MODE_DEFAULT            0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_MASK               0x00040000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_SHIFT              18
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_REFCLKOUT_DEFAULT            0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: PWM_RATE [17:16] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_MASK                0x00030000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_SHIFT               16
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_PWM_RATE_DEFAULT             0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: MDIV_RELOCK [15:15] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_MASK             0x00008000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_SHIFT            15
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_MDIV_RELOCK_DEFAULT          0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: FAST_LOCK [14:14] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_MASK               0x00004000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_SHIFT              14
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_FAST_LOCK_DEFAULT            0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [13:13] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00002000
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 13
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: DCO_CTRL_BYPASS [12:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00001ffe
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        1
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0

/* CLKGEN :: PLL_VCXO_PLL_MISC :: AUX_CTRL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO_PLL_MISC_AUX_CTRL_DEFAULT             0

/***************************************************************************
 *PLL_VCXO_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_reserved0_SHIFT             1

/* CLKGEN :: PLL_VCXO_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_VCXO_PLL_PWRDN_PWRDN_PLL_DEFAULT           0

/***************************************************************************
 *PLL_VCXO_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_reserved0_SHIFT             2

/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_MASK                 0x00000002
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_SHIFT                1
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETD_DEFAULT              0

/* CLKGEN :: PLL_VCXO_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_SHIFT                0
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_RESETA_DEFAULT              0

/***************************************************************************
 *PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [22:22] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00400000
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 22
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/* CLKGEN :: PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [21:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x003fffff
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/***************************************************************************
 *PLL_VCXO_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_VCXO_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_VCXO_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
 ***************************************************************************/
/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *BVN_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *BVN_TOP_INST_POWER_SWITCH_MEMORY - Bvn top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *CLKGEN_CLOCK_DISABLE - Disable CLKGEN's clocks
 ***************************************************************************/
/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_reserved0_SHIFT           2

/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_OSC_DIGITAL_CLOCK [01:01] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_SHIFT 1
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_OSC_DIGITAL_CLOCK_DEFAULT 0

/* CLKGEN :: CLKGEN_CLOCK_DISABLE :: DISABLE_AVS_CLOCK [00:00] */
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_MASK    0x00000001
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_SHIFT   0
#define BCHP_CLKGEN_CLKGEN_CLOCK_DISABLE_DISABLE_AVS_CLOCK_DEFAULT 0

/***************************************************************************
 *CLKGEN_INST_CLOCK_ENABLE - Clkgen inst clock enable
 ***************************************************************************/
/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_reserved0_SHIFT       1

/* CLKGEN :: CLKGEN_INST_CLOCK_ENABLE :: CG_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CLKGEN_INST_CLOCK_ENABLE_CG_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *CLOCK_MONITOR_CONTROL - Clock Monitor Control
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 1

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 1

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   1

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 1

/***************************************************************************
 *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 4294967295

/***************************************************************************
 *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0

/***************************************************************************
 *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1

/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0

/***************************************************************************
 *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0

/***************************************************************************
 *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK     0xffffffe0
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT    5

/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0

/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0

/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0

/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0

/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0

/***************************************************************************
 *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT     3

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *CORE_XPT_INST_MEMORY_STANDBY_ENABLE - Core xpt inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *CORE_XPT_INST_POWER_SWITCH_MEMORY - Core xpt inst power switch memory
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE - Disable DUAL_GENET_TOP_RGMII_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:06] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 6

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [05:05] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 5
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [04:04] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [03:03] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 3
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_FAST_CLOCK [02:02] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_SHIFT 2
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_FAST_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [01:01] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 1
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [00:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE - Dual genet top rgmii inst clock enable
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:15] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xffff8000
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 15

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [14:14] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00004000
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 14
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [13:13] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 13
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE [12:12] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 12
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE [11:11] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000800
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 11
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_L2INTR_CLOCK_ENABLE [10:10] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_MASK 0x00000400
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_SHIFT 10
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_HFB_CLOCK_ENABLE [09:09] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_MASK 0x00000200
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_SHIFT 9
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_GMII_CLOCK_ENABLE [08:08] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_MASK 0x00000100
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_SHIFT 8
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET1_EEE_CLOCK_ENABLE [07:07] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_MASK 0x00000080
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_SHIFT 7
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT - Dual genet top rgmii inst clock select
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: reserved0 [31:04] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 4

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET1_GMII_CLOCK_SELECT [03:03] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_MASK 0x00000008
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_SHIFT 3
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET1_CLOCK_SELECT [02:02] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_MASK 0x00000004
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_SHIFT 2
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Dual genet top rgmii inst memory standby enable a
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:01] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 1

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK - Dual genet top rgmii inst observe clock
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A - Dual genet top rgmii inst power switch memory a
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2

/* CLKGEN :: DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0

/***************************************************************************
 *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT      1

/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0

/***************************************************************************
 *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:06] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK        0xffffffc0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT       6

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_VEC_CLOCK_ENABLE [05:05] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_VEC_CLOCK_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_VEC_CLOCK_ENABLE_SHIFT 5
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_VEC_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_MAX_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_MAX_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *DVP_HT_INST_MEMORY_STANDBY_ENABLE - Dvp ht inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT      6

/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *DVP_HT_INST_POWER_SWITCH_MEMORY - Dvp ht inst power switch memory
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *FSK_TOP_INST_CLOCK_ENABLE - Fsk top inst clock enable
 ***************************************************************************/
/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      2

/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: FTM_CH0_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_CH0_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: FSK_TOP_INST_CLOCK_ENABLE :: FTM_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_FSK_TOP_INST_CLOCK_ENABLE_FTM_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *FSK_TOP_INST_MEMORY_STANDBY_ENABLE - Fsk top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: FSK_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: FSK_TOP_INST_MEMORY_STANDBY_ENABLE :: FTM_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_FSK_TOP_INST_MEMORY_STANDBY_ENABLE_FTM_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *FSK_TOP_INST_POWER_SWITCH_MEMORY - Fsk top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: FSK_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: FSK_TOP_INST_POWER_SWITCH_MEMORY :: FTM_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_FSK_TOP_INST_POWER_SWITCH_MEMORY_FTM_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *GRAPHICS_INST_CLOCK_DISABLE - Disable GRAPHICS_INST's clocks
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_reserved0_SHIFT    2

/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: DISABLE_GFX_V3D_CORE_CLOCK [01:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_V3D_CORE_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_V3D_CORE_CLOCK_SHIFT 1
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_V3D_CORE_CLOCK_DEFAULT 0

/* CLKGEN :: GRAPHICS_INST_CLOCK_DISABLE :: DISABLE_GFX_M2MC_CORE_CLOCK [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_DISABLE_DISABLE_GFX_M2MC_CORE_CLOCK_DEFAULT 0

/***************************************************************************
 *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:07] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK      0xffffff80
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT     7

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_V3D_CLOCK_ENABLE [06:06] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_MASK 0x00000040
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_SHIFT 6
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_V3D_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [05:05] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 5
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_ALTERNATE_216_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *GRAPHICS_INST_MEMORY_STANDBY_ENABLE - Graphics inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *GRAPHICS_INST_POWER_SWITCH_MEMORY - Graphics inst power switch memory
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *HIF_INST_CLOCK_DISABLE - Disable HIF_INST's clocks
 ***************************************************************************/
/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK          0xfffffff0
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT         4

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [03:03] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 3
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CLOCK [02:02] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_SHIFT 2
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_DEFAULT 0

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_EBI_CLOCK [01:01] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_SHIFT 1
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_EBI_CLOCK_DEFAULT 0

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_54_SCANCLOCK [00:00] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_MASK 0x00000001
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_SHIFT 0
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_54_SCANCLOCK_DEFAULT 1

/***************************************************************************
 *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
 ***************************************************************************/
/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:05] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xffffffe0
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            5

/* CLKGEN :: INTERNAL_MUX_SELECT :: STRAP_OVERRIDE_HIF_SPI_CLOCK [04:04] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_STRAP_OVERRIDE_HIF_SPI_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_STRAP_OVERRIDE_HIF_SPI_CLOCK_SHIFT 4
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_STRAP_OVERRIDE_HIF_SPI_CLOCK_DEFAULT 0

/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [03:03] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 3
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0

/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [02:02] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 2
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0

/* CLKGEN :: INTERNAL_MUX_SELECT :: HIF_SPI_CLOCK [01:00] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_HIF_SPI_CLOCK_MASK         0x00000003
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_HIF_SPI_CLOCK_SHIFT        0
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_HIF_SPI_CLOCK_DEFAULT      0

/***************************************************************************
 *MEMSYS_32_INST_CLOCK_ENABLE - Memsys 32 inst clock enable
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_reserved0_SHIFT    2

/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: MEMSYS_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: MEMSYS_32_INST_CLOCK_ENABLE :: MEMSYS_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_INST_CLOCK_ENABLE_MEMSYS_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *MEMSYS_32_INST_MEMORY_STANDBY_ENABLE - Memsys 32 inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: MEMSYS_32_INST_MEMORY_STANDBY_ENABLE :: MEMSYS_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_MEMSYS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_MEMSYS_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_INST_MEMORY_STANDBY_ENABLE_MEMSYS_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *MEMSYS_32_INST_OBSERVE_CLOCK - Memsys 32 inst observe clock
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_reserved0_SHIFT   6

/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: MEMSYS_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: MEMSYS_32_INST_OBSERVE_CLOCK :: MEMSYS_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_INST_OBSERVE_CLOCK_MEMSYS_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *MEMSYS_32_INST_POWER_SWITCH_MEMORY - Memsys 32 inst power switch memory
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: MEMSYS_32_INST_POWER_SWITCH_MEMORY :: MEMSYS_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_INST_POWER_SWITCH_MEMORY_MEMSYS_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *MEMSYS_32_INST_STATUS - Memsys 32 inst status
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_INST_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_reserved0_SHIFT          1

/* CLKGEN :: MEMSYS_32_INST_STATUS :: MEMSYS_PLL_LOCKED_STATUS [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_MEMSYS_PLL_LOCKED_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_INST_STATUS_MEMSYS_PLL_LOCKED_STATUS_SHIFT 0

/***************************************************************************
 *MOCA_TOP_INST_CLOCK_ENABLE - Moca top inst clock enable
 ***************************************************************************/
/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     2

/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *MOCA_TOP_INST_MEMORY_STANDBY_ENABLE - Moca top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: MOCA_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *MOCA_TOP_INST_OBSERVE_CLOCK - Moca top inst observe clock
 ***************************************************************************/
/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *MOCA_TOP_INST_POWER_SWITCH_MEMORY - Moca top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: MOCA_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *PAD_CLK27_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CLK27_OBSERVATION :: reserved0 [31:09] */
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_MASK           0xfffffe00
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_SHIFT          9

/* CLKGEN :: PAD_CLK27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_MASK  0x00000100
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0

/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_MASK  0x000000fe
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0

/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK  0x00000001
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0

/***************************************************************************
 *PAD_CLK_ACC_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CLK_ACC_OBSERVATION :: reserved0 [31:09] */
#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_reserved0_MASK         0xfffffe00
#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_reserved0_SHIFT        9

/* CLKGEN :: PAD_CLK_ACC_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0

/* CLKGEN :: PAD_CLK_ACC_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0

/* CLKGEN :: PAD_CLK_ACC_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CLK_ACC_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0

/***************************************************************************
 *PAD_CLOCK_DISABLE - Disable PAD's clocks
 ***************************************************************************/
/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xfffffff0
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              4

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK [03:03] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 3
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [02:02] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 2
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLKACC_CLOCK [01:01] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKACC_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKACC_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLKACC_CLOCK_DEFAULT 0

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0

/***************************************************************************
 *PAD_CODEC_MCLK_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK      0xfffffe00
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT     9

/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0

/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0

/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0

/***************************************************************************
 *PAD_MUX_SELECT - Mux selects for Pad clocks
 ***************************************************************************/
/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:10] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffc00
#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 10

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_VCXO27_CLOCK [09:07] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_MASK    0x00000380
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT   7
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLKACC_CLOCK [06:04] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKACC_CLOCK_MASK    0x00000070
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKACC_CLOCK_SHIFT   4
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLKACC_CLOCK_DEFAULT 0

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [03:01] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x0000000e
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    1
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0

/* CLKGEN :: PAD_MUX_SELECT :: ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK [00:00] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PAD_MUX_SELECT_ENABLE_INVERT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0

/***************************************************************************
 *PAD_VCXO27_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_VCXO27_OBSERVATION :: reserved0 [31:09] */
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_MASK          0xfffffe00
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_SHIFT         9

/* CLKGEN :: PAD_VCXO27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0

/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0

/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO0_PLL_RESET_STATUS - PLL_AUDIO0 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2

/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_AUDIO1_PLL_RESET_STATUS - PLL_AUDIO1 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2

/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_AVD_PLL_RESET_STATUS - PLL_AVD Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_AVD_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_AVD_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_MASK          0xfffffff0
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_reserved0_SHIFT         4

/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: PLL_AVD_OPTIONS_DISABLE_RDB_MACRO [03:03] */
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_PLL_AVD_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0

/* CLKGEN :: PLL_AVD_RDB_MACRO_CTRL :: OPTIONS [02:00] */
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_MASK            0x00000007
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_SHIFT           0
#define BCHP_CLKGEN_PLL_AVD_RDB_MACRO_CTRL_OPTIONS_DEFAULT         0

/***************************************************************************
 *PLL_MIPS_GLITCHLESS_SWITCH_REQUEST - PLL_MIPS Glitchless Clock Switching
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: reserved0 [31:09] */
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_MASK 0xfffffe00
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_reserved0_SHIFT 9

/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: TRANSACTION_WAIT [08:01] */
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_MASK 0x000001fe
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_SHIFT 1
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_TRANSACTION_WAIT_DEFAULT 31

/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_REQUEST :: PLL_BYPASS_REQUEST [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_SHIFT 0
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_REQUEST_PLL_BYPASS_REQUEST_DEFAULT 0

/***************************************************************************
 *PLL_MIPS_GLITCHLESS_SWITCH_STATUS - PLL_MIPS Glitchless Switching
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_reserved0_SHIFT 4

/* CLKGEN :: PLL_MIPS_GLITCHLESS_SWITCH_STATUS :: PLL_BYPASS_STATUS [03:00] */
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_MASK 0x0000000f
#define BCHP_CLKGEN_PLL_MIPS_GLITCHLESS_SWITCH_STATUS_PLL_BYPASS_STATUS_SHIFT 0

/***************************************************************************
 *PLL_MIPS_PLL_RESET_STATUS - PLL_MIPS Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_MIPS_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: reserved0 [31:05] */
#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_reserved0_MASK         0xffffffe0
#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_reserved0_SHIFT        5

/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO [04:04] */
#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000010
#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_SHIFT 4
#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_PLL_MIPS_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0

/* CLKGEN :: PLL_MIPS_RDB_MACRO_CTRL :: OPTIONS [03:00] */
#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_MASK           0x0000000f
#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
#define BCHP_CLKGEN_PLL_MIPS_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0

/***************************************************************************
 *PLL_MOCA_PLL_RESET_STATUS - PLL_MOCA Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_MOCA_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_reserved0_SHIFT        2

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000002
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 1
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_PLL_MOCA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0

/* CLKGEN :: PLL_MOCA_RDB_MACRO_CTRL :: OPTIONS [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_MASK           0x00000001
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
#define BCHP_CLKGEN_PLL_MOCA_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0

/***************************************************************************
 *PLL_RAAGA_PLL_RESET_STATUS - PLL_RAAGA Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_RAAGA_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: reserved0 [31:04] */
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_MASK        0xfffffff0
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_reserved0_SHIFT       4

/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO [03:03] */
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000008
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_SHIFT 3
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_PLL_RAAGA_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_RDB_MACRO_CTRL :: OPTIONS [02:00] */
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_MASK          0x00000007
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_SHIFT         0
#define BCHP_CLKGEN_PLL_RAAGA_RDB_MACRO_CTRL_OPTIONS_DEFAULT       0

/***************************************************************************
 *PLL_SC_PLL_RESET_STATUS - PLL_SC Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_STRAP_OVERRIDE - Disable
 ***************************************************************************/
/* CLKGEN :: PLL_STRAP_OVERRIDE :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_reserved0_SHIFT             2

/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLSYS0_DISABLE [01:01] */
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLSYS0_DISABLE_MASK 0x00000002
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLSYS0_DISABLE_SHIFT 1
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLSYS0_DISABLE_DEFAULT 0

/* CLKGEN :: PLL_STRAP_OVERRIDE :: STRAP_FREQ_PLLMIPS_DISABLE [00:00] */
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_SHIFT 0
#define BCHP_CLKGEN_PLL_STRAP_OVERRIDE_STRAP_FREQ_PLLMIPS_DISABLE_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_RDB_MACRO_CTRL - PLL RDB Macro Disable
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_reserved0_MASK         0xfffffff8
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_reserved0_SHIFT        3

/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: PLL_SYS0_OPTIONS_DISABLE_RDB_MACRO [02:02] */
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_OPTIONS_DISABLE_RDB_MACRO_MASK 0x00000004
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_OPTIONS_DISABLE_RDB_MACRO_SHIFT 2
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_PLL_SYS0_OPTIONS_DISABLE_RDB_MACRO_DEFAULT 0

/* CLKGEN :: PLL_SYS0_RDB_MACRO_CTRL :: OPTIONS [01:00] */
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_OPTIONS_MASK           0x00000003
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_OPTIONS_SHIFT          0
#define BCHP_CLKGEN_PLL_SYS0_RDB_MACRO_CTRL_OPTIONS_DEFAULT        0

/***************************************************************************
 *PLL_SYS1_PLL_RESET_STATUS - PLL_SYS1 Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_SYS1_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS1_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PLL_VCXO_PLL_RESET_STATUS - PLL_VCXO Reset Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_DRESET_STATUS [01:01] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_MASK 0x00000002
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_DRESET_STATUS_SHIFT 1

/* CLKGEN :: PLL_VCXO_PLL_RESET_STATUS :: PLL_ARESET_STATUS [00:00] */
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO_PLL_RESET_STATUS_PLL_ARESET_STATUS_SHIFT 0

/***************************************************************************
 *PM_CLOCK_108_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
 ***************************************************************************/
/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: reserved0 [31:03] */
#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_MASK          0xfffffff8
#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_reserved0_SHIFT         3

/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSTOP0 [02:02] */
#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTOP0_MASK 0x00000004
#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTOP0_SHIFT 2
#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSTOP0_DEFAULT 0

/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_SDSAFEC0 [01:01] */
#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_MASK 0x00000002
#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_SHIFT 1
#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_SDSAFEC0_DEFAULT 0

/* CLKGEN :: PM_CLOCK_108_ALIVE_SEL :: CLOCK_108_CG_FSK [00:00] */
#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FSK_MASK   0x00000001
#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FSK_SHIFT  0
#define BCHP_CLKGEN_PM_CLOCK_108_ALIVE_SEL_CLOCK_108_CG_FSK_DEFAULT 0

/***************************************************************************
 *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
 ***************************************************************************/
/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1

/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0

/***************************************************************************
 *PM_PLL_ALIVE_SEL - PLL Alive in Standby Mode
 ***************************************************************************/
/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3

/* CLKGEN :: PM_PLL_ALIVE_SEL :: memsys_PLL [02:02] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_MASK               0x00000004
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_SHIFT              2
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_memsys_PLL_DEFAULT            0

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [01:01] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000002
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                1
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [00:00] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK                 0x00000001
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT                0
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT              0

/***************************************************************************
 *PM_PLL_LDO_POWERUP - Power management LDO PLL
 ***************************************************************************/
/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:03] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffffff8
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             3

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [02:02] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK    0x00000004
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT   2
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 1

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [01:01] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK     0x00000002
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT    1
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT  1

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [00:00] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK      0x00000001
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT     0
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT   1

/***************************************************************************
 *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine
 ***************************************************************************/
/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK           0xf8000000
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT          27

/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 5400

/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 200

/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK    0x00000001
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT   0
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0

/***************************************************************************
 *RAAGA_DSP_TOP_INST_CLOCK_ENABLE - Raaga dsp top inst clock enable
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3

/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE - Raaga dsp top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: RAAGAA_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGAA_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *RAAGA_DSP_TOP_INST_OBSERVE_CLOCK - Raaga dsp top inst observe clock
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 2

/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 1
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY - Raaga dsp top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *SDS0_AFEC_TOP_INST_CLOCK_ENABLE - Sds0 afec top inst clock enable
 ***************************************************************************/
/* CLKGEN :: SDS0_AFEC_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: SDS0_AFEC_TOP_INST_CLOCK_ENABLE :: SDSAFEC0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_CLOCK_ENABLE_SDSAFEC0_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE - Sds0 afec top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE :: SDSAFEC0_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_MEMORY_STANDBY_ENABLE_SDSAFEC0_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *SDS0_AFEC_TOP_INST_OBSERVE_CLOCK - Sds0 afec top inst observe clock
 ***************************************************************************/
/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SDS0_AFEC_TOP_INST_OBSERVE_CLOCK :: SDSAFEC0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_OBSERVE_CLOCK_SDSAFEC0_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY - Sds0 afec top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY :: SDSAFEC0_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_SDS0_AFEC_TOP_INST_POWER_SWITCH_MEMORY_SDSAFEC0_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *SDS0_TOP_INST_CLOCK_DISABLE - Disable SDS0_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: SDS0_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1

/* CLKGEN :: SDS0_TOP_INST_CLOCK_DISABLE :: DISABLE_SDSTOP0_108_PRESPMBALANCE_CLOCK [00:00] */
#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDSTOP0_108_PRESPMBALANCE_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDSTOP0_108_PRESPMBALANCE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_DISABLE_DISABLE_SDSTOP0_108_PRESPMBALANCE_CLOCK_DEFAULT 0

/***************************************************************************
 *SDS0_TOP_INST_CLOCK_ENABLE - Sds0 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: SDS0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1

/* CLKGEN :: SDS0_TOP_INST_CLOCK_ENABLE :: SDS_TOP0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS_TOP0_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS_TOP0_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SDS0_TOP_INST_CLOCK_ENABLE_SDS_TOP0_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *SDS0_TOP_INST_OBSERVE_CLOCK - Sds0 top inst observe clock
 ***************************************************************************/
/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:12] */
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xfffff000
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    12

/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_TFEC_ENABLE_OBSERVE_CLOCK [11:11] */
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000800
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_OBSERVE_CLOCK_SHIFT 11
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_TFEC_ENABLE_DIVIDER_OBSERVE_CLOCK [10:10] */
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 10
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_TFEC_CONTROL_OBSERVE_CLOCK [09:06] */
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_CONTROL_OBSERVE_CLOCK_MASK 0x000003c0
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_CONTROL_OBSERVE_CLOCK_SHIFT 6
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_TFEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_RCVR_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_RCVR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SDS0_TOP_INST_OBSERVE_CLOCK :: SDS_TOP0_RCVR_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SDS0_TOP_INST_OBSERVE_CLOCK_SDS_TOP0_RCVR_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *SECTOP_INST_CLOCK_ENABLE_M2MDMA - Sectop inst clock enable m2mdma
 ***************************************************************************/
/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT 1

/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA [00:00] */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 1

/***************************************************************************
 *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
 ***************************************************************************/
/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6

/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SEC_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SEC_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SEC_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SEC_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
 ***************************************************************************/
/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:08] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xffffff00
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           8

/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0

/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0

/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0

/***************************************************************************
 *SPARE - Spares
 ***************************************************************************/
/* CLKGEN :: SPARE :: SPARE_RESET_LOW [31:12] */
#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_MASK                     0xfffff000
#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_SHIFT                    12
#define BCHP_CLKGEN_SPARE_SPARE_RESET_LOW_DEFAULT                  0

/* CLKGEN :: SPARE :: SPARE_RESET_HIGH [11:00] */
#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_MASK                    0x00000fff
#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_SHIFT                   0
#define BCHP_CLKGEN_SPARE_SPARE_RESET_HIGH_DEFAULT                 0

/***************************************************************************
 *SVD0_TOP_INST_CLOCK_ENABLE - Svd0 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xffffffe0
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     5

/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_SCB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_CPU_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CPU_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_CORE_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_CORE_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_ALTERNATE_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_ALTERNATE_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *SVD0_TOP_INST_MEMORY_STANDBY_ENABLE - Svd0 top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: SVD_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *SVD0_TOP_INST_POWER_SWITCH_MEMORY - Svd0 top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: SVD_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *SYS_AON_INST_OBSERVE_CLOCK - Sys aon inst observe clock
 ***************************************************************************/
/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_SHIFT     6

/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff0
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT    4

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UHFR_CLOCK [03:03] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UHFR_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UHFR_CLOCK_SHIFT 3
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UHFR_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0

/***************************************************************************
 *SYS_CTRL_INST_CLOCK_ENABLE - Sys ctrl inst clock enable
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_reserved0_SHIFT     1

/* CLKGEN :: SYS_CTRL_INST_CLOCK_ENABLE :: SYS_CTRL_SCB_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_ENABLE_SYS_CTRL_SCB_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *SYS_CTRL_INST_MEMORY_STANDBY_ENABLE - Sys ctrl inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *TESTPORT - Special Testport Controls
 ***************************************************************************/
/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff0
#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       4

/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x0000000f
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0

/***************************************************************************
 *UHFR_TOP_INST_CLOCK_DISABLE - Disable UHFR_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1

/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: DISABLE_UHFR_ALWAYSON_CLOCK [00:00] */
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_DEFAULT 0

/***************************************************************************
 *UHFR_TOP_INST_CLOCK_ENABLE - Uhfr top inst clock enable
 ***************************************************************************/
/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1

/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: UHFR_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *UHFR_TOP_INST_MEMORY_STANDBY_ENABLE - Uhfr top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: UHFR_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *UHFR_TOP_INST_OBSERVE_CLOCK - Uhfr top inst observe clock
 ***************************************************************************/
/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *UHFR_TOP_INST_POWER_SWITCH_MEMORY - Uhfr top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: UHFR_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *USB0_INST_CLOCK_DISABLE - Disable USB0_INST's clocks
 ***************************************************************************/
/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_SHIFT        2

/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0

/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_27_FREERUN_CLOCK [00:00] */
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_27_FREERUN_CLOCK_DEFAULT 0

/***************************************************************************
 *USB0_INST_CLOCK_ENABLE - Usb0 inst clock enable
 ***************************************************************************/
/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_SHIFT         2

/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB0_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *USB0_INST_MEMORY_STANDBY_ENABLE - Usb0 inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *USB0_INST_OBSERVE_CLOCK - Usb0 inst observe clock
 ***************************************************************************/
/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_SHIFT        6

/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *USB0_INST_POWER_SWITCH_MEMORY - Usb0 inst power switch memory
 ***************************************************************************/
/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2

/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *USB1_INST_CLOCK_DISABLE - Disable USB1_INST's clocks
 ***************************************************************************/
/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_SHIFT        2

/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB_54_MDIO_CLOCK [01:01] */
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_SHIFT 1
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB_54_MDIO_CLOCK_DEFAULT 0

/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_27_FREERUN_CLOCK [00:00] */
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_27_FREERUN_CLOCK_DEFAULT 0

/***************************************************************************
 *USB1_INST_CLOCK_ENABLE - Usb1 inst clock enable
 ***************************************************************************/
/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_SHIFT         2

/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *USB1_INST_MEMORY_STANDBY_ENABLE - Usb1 inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *USB1_INST_OBSERVE_CLOCK - Usb1 inst observe clock
 ***************************************************************************/
/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_SHIFT        6

/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *USB1_INST_POWER_SWITCH_MEMORY - Usb1 inst power switch memory
 ***************************************************************************/
/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2

/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_CLOCK [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_CLOCK_DEFAULT 0

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_ALTERNATE_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_DEFAULT 1

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:05] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 5

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [04:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 4
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_QDAC_216_CLOCK_ENABLE_VEC [03:03] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000008
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 3
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC [02:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_SHIFT 2
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_DEFAULT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 1

/***************************************************************************
 *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO - Vec aio top inst memory standby enable aio
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC - Vec aio top inst memory standby enable vec
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: VEC_AIO_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_VEC_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO - Vec aio top inst power switch memory aio
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC - Vec aio top inst power switch memory vec
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0

/***************************************************************************
 *ZCPU_TOP_INST_CLOCK_DISABLE - Disable ZCPU_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1

/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_SLOWMIPS_CLOCK [00:00] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_SHIFT 0
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_SLOWMIPS_CLOCK_DEFAULT 0

/***************************************************************************
 *ZCPU_TOP_INST_CLOCK_ENABLE - Zcpu top inst clock enable
 ***************************************************************************/
/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff8
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     3

/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *ZCPU_TOP_INST_OBSERVE_CLOCK - Zcpu top inst observe clock
 ***************************************************************************/
/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0

#endif /* #ifndef BCHP_CLKGEN_H__ */

/* End of File */