/***************************************************************************
 *     Copyright (c) 1999-2011, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Wed Apr 13 13:24:34 2011
 *                 MD5 Checksum         5014fc6b805cdf8eed48fe0da9f96997
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7231/rdb/b0/bchp_hif_mspi.h $
 * 
 * Hydra_Software_Devel/1   4/13/11 5:35p albertl
 * SW7231-123: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_HIF_MSPI_H__
#define BCHP_HIF_MSPI_H__

/***************************************************************************
 *HIF_MSPI - Public MSPI Registers
 ***************************************************************************/
#define BCHP_HIF_MSPI_SPCR0_LSB                  0x00413200 /* SPCR0_LSB REGISTER */
#define BCHP_HIF_MSPI_SPCR0_MSB                  0x00413204 /* SPCR0_MSB Register */
#define BCHP_HIF_MSPI_SPCR1_LSB                  0x00413208 /* SPCR1_LSB REGISTER */
#define BCHP_HIF_MSPI_SPCR1_MSB                  0x0041320c /* SPCR1_MSB REGISTER */
#define BCHP_HIF_MSPI_NEWQP                      0x00413210 /* NEWQP REGISTER */
#define BCHP_HIF_MSPI_ENDQP                      0x00413214 /* ENDQP REGISTER */
#define BCHP_HIF_MSPI_SPCR2                      0x00413218 /* SPCR2 REGISTER */
#define BCHP_HIF_MSPI_MSPI_STATUS                0x00413220 /* MSPI STATUS REGISTER */
#define BCHP_HIF_MSPI_CPTQP                      0x00413224 /* CPTQP REGISTER */
#define BCHP_HIF_MSPI_TXRAM00                    0x00413240 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
#define BCHP_HIF_MSPI_TXRAM01                    0x00413244 /* LSbyte for bit 16 operation only (queue pointer = 0) */
#define BCHP_HIF_MSPI_TXRAM02                    0x00413248 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
#define BCHP_HIF_MSPI_TXRAM03                    0x0041324c /* LSbyte for bit 16 operation only (queue pointer = 1) */
#define BCHP_HIF_MSPI_TXRAM04                    0x00413250 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
#define BCHP_HIF_MSPI_TXRAM05                    0x00413254 /* LSbyte for bit 16 operation only (queue pointer = 2) */
#define BCHP_HIF_MSPI_TXRAM06                    0x00413258 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
#define BCHP_HIF_MSPI_TXRAM07                    0x0041325c /* LSbyte for bit 16 operation only (queue pointer = 3) */
#define BCHP_HIF_MSPI_TXRAM08                    0x00413260 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
#define BCHP_HIF_MSPI_TXRAM09                    0x00413264 /* LSbyte for bit 16 operation only (queue pointer = 4) */
#define BCHP_HIF_MSPI_TXRAM10                    0x00413268 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
#define BCHP_HIF_MSPI_TXRAM11                    0x0041326c /* LSbyte for bit 16 operation only (queue pointer = 5) */
#define BCHP_HIF_MSPI_TXRAM12                    0x00413270 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
#define BCHP_HIF_MSPI_TXRAM13                    0x00413274 /* LSbyte for bit 16 operation only (queue pointer = 6) */
#define BCHP_HIF_MSPI_TXRAM14                    0x00413278 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
#define BCHP_HIF_MSPI_TXRAM15                    0x0041327c /* LSbyte for bit 16 operation only (queue pointer = 7) */
#define BCHP_HIF_MSPI_TXRAM16                    0x00413280 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
#define BCHP_HIF_MSPI_TXRAM17                    0x00413284 /* LSbyte for bit 16 operation only (queue pointer = 8) */
#define BCHP_HIF_MSPI_TXRAM18                    0x00413288 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
#define BCHP_HIF_MSPI_TXRAM19                    0x0041328c /* LSbyte for bit 16 operation only (queue pointer = 9) */
#define BCHP_HIF_MSPI_TXRAM20                    0x00413290 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
#define BCHP_HIF_MSPI_TXRAM21                    0x00413294 /* LSbyte for bit 16 operation only (queue pointer = a) */
#define BCHP_HIF_MSPI_TXRAM22                    0x00413298 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
#define BCHP_HIF_MSPI_TXRAM23                    0x0041329c /* LSbyte for bit 16 operation only (queue pointer = b) */
#define BCHP_HIF_MSPI_TXRAM24                    0x004132a0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
#define BCHP_HIF_MSPI_TXRAM25                    0x004132a4 /* LSbyte for bit 16 operation only (queue pointer = c) */
#define BCHP_HIF_MSPI_TXRAM26                    0x004132a8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
#define BCHP_HIF_MSPI_TXRAM27                    0x004132ac /* LSbyte for bit 16 operation only (queue pointer = d) */
#define BCHP_HIF_MSPI_TXRAM28                    0x004132b0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
#define BCHP_HIF_MSPI_TXRAM29                    0x004132b4 /* LSbyte for bit 16 operation only (queue pointer = e) */
#define BCHP_HIF_MSPI_TXRAM30                    0x004132b8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
#define BCHP_HIF_MSPI_TXRAM31                    0x004132bc /* LSbyte for bit 16 operation only (queue pointer = f) */
#define BCHP_HIF_MSPI_RXRAM00                    0x004132c0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 0) */
#define BCHP_HIF_MSPI_RXRAM01                    0x004132c4 /* LSbyte for bit 16 operation only (queue pointer = 0) */
#define BCHP_HIF_MSPI_RXRAM02                    0x004132c8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 1) */
#define BCHP_HIF_MSPI_RXRAM03                    0x004132cc /* LSbyte for bit 16 operation only (queue pointer = 1) */
#define BCHP_HIF_MSPI_RXRAM04                    0x004132d0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 2) */
#define BCHP_HIF_MSPI_RXRAM05                    0x004132d4 /* LSbyte for bit 16 operation only (queue pointer = 2) */
#define BCHP_HIF_MSPI_RXRAM06                    0x004132d8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 3) */
#define BCHP_HIF_MSPI_RXRAM07                    0x004132dc /* LSbyte for bit 16 operation only (queue pointer = 3) */
#define BCHP_HIF_MSPI_RXRAM08                    0x004132e0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 4) */
#define BCHP_HIF_MSPI_RXRAM09                    0x004132e4 /* LSbyte for bit 16 operation only (queue pointer = 4) */
#define BCHP_HIF_MSPI_RXRAM10                    0x004132e8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 5) */
#define BCHP_HIF_MSPI_RXRAM11                    0x004132ec /* LSbyte for bit 16 operation only (queue pointer = 5) */
#define BCHP_HIF_MSPI_RXRAM12                    0x004132f0 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 6) */
#define BCHP_HIF_MSPI_RXRAM13                    0x004132f4 /* LSbyte for bit 16 operation only (queue pointer = 6) */
#define BCHP_HIF_MSPI_RXRAM14                    0x004132f8 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 7) */
#define BCHP_HIF_MSPI_RXRAM15                    0x004132fc /* LSbyte for bit 16 operation only (queue pointer = 7) */
#define BCHP_HIF_MSPI_RXRAM16                    0x00413300 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 8) */
#define BCHP_HIF_MSPI_RXRAM17                    0x00413304 /* LSbyte for bit 16 operation only (queue pointer = 8) */
#define BCHP_HIF_MSPI_RXRAM18                    0x00413308 /* MSbyte for bit 16 or bit 8 operation (queue pointer = 9) */
#define BCHP_HIF_MSPI_RXRAM19                    0x0041330c /* LSbyte for bit 16 operation only (queue pointer = 9) */
#define BCHP_HIF_MSPI_RXRAM20                    0x00413310 /* MSbyte for bit 16 or bit 8 operation (queue pointer = a) */
#define BCHP_HIF_MSPI_RXRAM21                    0x00413314 /* LSbyte for bit 16 operation only (queue pointer = a) */
#define BCHP_HIF_MSPI_RXRAM22                    0x00413318 /* MSbyte for bit 16 or bit 8 operation (queue pointer = b) */
#define BCHP_HIF_MSPI_RXRAM23                    0x0041331c /* LSbyte for bit 16 operation only (queue pointer = b) */
#define BCHP_HIF_MSPI_RXRAM24                    0x00413320 /* MSbyte for bit 16 or bit 8 operation (queue pointer = c) */
#define BCHP_HIF_MSPI_RXRAM25                    0x00413324 /* LSbyte for bit 16 operation only (queue pointer = c) */
#define BCHP_HIF_MSPI_RXRAM26                    0x00413328 /* MSbyte for bit 16 or bit 8 operation (queue pointer = d) */
#define BCHP_HIF_MSPI_RXRAM27                    0x0041332c /* LSbyte for bit 16 operation only (queue pointer = d) */
#define BCHP_HIF_MSPI_RXRAM28                    0x00413330 /* MSbyte for bit 16 or bit 8 operation (queue pointer = e) */
#define BCHP_HIF_MSPI_RXRAM29                    0x00413334 /* LSbyte for bit 16 operation only (queue pointer = e) */
#define BCHP_HIF_MSPI_RXRAM30                    0x00413338 /* MSbyte for bit 16 or bit 8 operation (queue pointer = f) */
#define BCHP_HIF_MSPI_RXRAM31                    0x0041333c /* LSbyte for bit 16 operation only (queue pointer = f) */
#define BCHP_HIF_MSPI_CDRAM00                    0x00413340 /* 8-bit command (queue pointer = 0) */
#define BCHP_HIF_MSPI_CDRAM01                    0x00413344 /* 8-bit command (queue pointer = 1) */
#define BCHP_HIF_MSPI_CDRAM02                    0x00413348 /* 8-bit command (queue pointer = 2) */
#define BCHP_HIF_MSPI_CDRAM03                    0x0041334c /* 8-bit command (queue pointer = 3) */
#define BCHP_HIF_MSPI_CDRAM04                    0x00413350 /* 8-bit command (queue pointer = 4) */
#define BCHP_HIF_MSPI_CDRAM05                    0x00413354 /* 8-bit command (queue pointer = 5) */
#define BCHP_HIF_MSPI_CDRAM06                    0x00413358 /* 8-bit command (queue pointer = 6) */
#define BCHP_HIF_MSPI_CDRAM07                    0x0041335c /* 8-bit command (queue pointer = 7) */
#define BCHP_HIF_MSPI_CDRAM08                    0x00413360 /* 8-bit command (queue pointer = 8) */
#define BCHP_HIF_MSPI_CDRAM09                    0x00413364 /* 8-bit command (queue pointer = 9) */
#define BCHP_HIF_MSPI_CDRAM10                    0x00413368 /* 8-bit command (queue pointer = a) */
#define BCHP_HIF_MSPI_CDRAM11                    0x0041336c /* 8-bit command (queue pointer = b) */
#define BCHP_HIF_MSPI_CDRAM12                    0x00413370 /* 8-bit command (queue pointer = c) */
#define BCHP_HIF_MSPI_CDRAM13                    0x00413374 /* 8-bit command (queue pointer = d) */
#define BCHP_HIF_MSPI_CDRAM14                    0x00413378 /* 8-bit command (queue pointer = e) */
#define BCHP_HIF_MSPI_CDRAM15                    0x0041337c /* 8-bit command (queue pointer = f) */
#define BCHP_HIF_MSPI_WRITE_LOCK                 0x00413380 /* Control bit to lock group of write commands */
#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN          0x00413384 /* Debug bit to mask the generation of flush signals from Mspi */

/***************************************************************************
 *SPCR0_LSB - SPCR0_LSB REGISTER
 ***************************************************************************/
/* HIF_MSPI :: SPCR0_LSB :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_MASK                     0xffffff00
#define BCHP_HIF_MSPI_SPCR0_LSB_reserved0_SHIFT                    8

/* HIF_MSPI :: SPCR0_LSB :: SPBR [07:00] */
#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_MASK                          0x000000ff
#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_SHIFT                         0
#define BCHP_HIF_MSPI_SPCR0_LSB_SPBR_DEFAULT                       0

/***************************************************************************
 *SPCR0_MSB - SPCR0_MSB Register
 ***************************************************************************/
/* HIF_MSPI :: SPCR0_MSB :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_MASK                     0xffffff00
#define BCHP_HIF_MSPI_SPCR0_MSB_reserved0_SHIFT                    8

/* HIF_MSPI :: SPCR0_MSB :: MSTR [07:07] */
#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_MASK                          0x00000080
#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_SHIFT                         7
#define BCHP_HIF_MSPI_SPCR0_MSB_MSTR_DEFAULT                       1

/* HIF_MSPI :: SPCR0_MSB :: StartTransDelay [06:06] */
#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_MASK               0x00000040
#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_SHIFT              6
#define BCHP_HIF_MSPI_SPCR0_MSB_StartTransDelay_DEFAULT            0

/* HIF_MSPI :: SPCR0_MSB :: BitS [05:02] */
#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_MASK                          0x0000003c
#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_SHIFT                         2
#define BCHP_HIF_MSPI_SPCR0_MSB_BitS_DEFAULT                       0

/* HIF_MSPI :: SPCR0_MSB :: CPOL [01:01] */
#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_MASK                          0x00000002
#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_SHIFT                         1
#define BCHP_HIF_MSPI_SPCR0_MSB_CPOL_DEFAULT                       0

/* HIF_MSPI :: SPCR0_MSB :: CPHA [00:00] */
#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_MASK                          0x00000001
#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_SHIFT                         0
#define BCHP_HIF_MSPI_SPCR0_MSB_CPHA_DEFAULT                       0

/***************************************************************************
 *SPCR1_LSB - SPCR1_LSB REGISTER
 ***************************************************************************/
/* HIF_MSPI :: SPCR1_LSB :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_MASK                     0xffffff00
#define BCHP_HIF_MSPI_SPCR1_LSB_reserved0_SHIFT                    8

/* HIF_MSPI :: SPCR1_LSB :: DTL [07:00] */
#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_MASK                           0x000000ff
#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_SHIFT                          0
#define BCHP_HIF_MSPI_SPCR1_LSB_DTL_DEFAULT                        0

/***************************************************************************
 *SPCR1_MSB - SPCR1_MSB REGISTER
 ***************************************************************************/
/* HIF_MSPI :: SPCR1_MSB :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_MASK                     0xffffff00
#define BCHP_HIF_MSPI_SPCR1_MSB_reserved0_SHIFT                    8

/* HIF_MSPI :: SPCR1_MSB :: RDSCLK [07:00] */
#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_MASK                        0x000000ff
#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_SHIFT                       0
#define BCHP_HIF_MSPI_SPCR1_MSB_RDSCLK_DEFAULT                     0

/***************************************************************************
 *NEWQP - NEWQP REGISTER
 ***************************************************************************/
/* HIF_MSPI :: NEWQP :: reserved0 [31:04] */
#define BCHP_HIF_MSPI_NEWQP_reserved0_MASK                         0xfffffff0
#define BCHP_HIF_MSPI_NEWQP_reserved0_SHIFT                        4

/* HIF_MSPI :: NEWQP :: newqp [03:00] */
#define BCHP_HIF_MSPI_NEWQP_newqp_MASK                             0x0000000f
#define BCHP_HIF_MSPI_NEWQP_newqp_SHIFT                            0
#define BCHP_HIF_MSPI_NEWQP_newqp_DEFAULT                          0

/***************************************************************************
 *ENDQP - ENDQP REGISTER
 ***************************************************************************/
/* HIF_MSPI :: ENDQP :: reserved0 [31:04] */
#define BCHP_HIF_MSPI_ENDQP_reserved0_MASK                         0xfffffff0
#define BCHP_HIF_MSPI_ENDQP_reserved0_SHIFT                        4

/* HIF_MSPI :: ENDQP :: endqp [03:00] */
#define BCHP_HIF_MSPI_ENDQP_endqp_MASK                             0x0000000f
#define BCHP_HIF_MSPI_ENDQP_endqp_SHIFT                            0
#define BCHP_HIF_MSPI_ENDQP_endqp_DEFAULT                          0

/***************************************************************************
 *SPCR2 - SPCR2 REGISTER
 ***************************************************************************/
/* HIF_MSPI :: SPCR2 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_SPCR2_reserved0_MASK                         0xffffff00
#define BCHP_HIF_MSPI_SPCR2_reserved0_SHIFT                        8

/* HIF_MSPI :: SPCR2 :: cont_after_cmd [07:07] */
#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_MASK                    0x00000080
#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_SHIFT                   7
#define BCHP_HIF_MSPI_SPCR2_cont_after_cmd_DEFAULT                 0

/* HIF_MSPI :: SPCR2 :: spe [06:06] */
#define BCHP_HIF_MSPI_SPCR2_spe_MASK                               0x00000040
#define BCHP_HIF_MSPI_SPCR2_spe_SHIFT                              6
#define BCHP_HIF_MSPI_SPCR2_spe_DEFAULT                            0

/* HIF_MSPI :: SPCR2 :: spifie [05:05] */
#define BCHP_HIF_MSPI_SPCR2_spifie_MASK                            0x00000020
#define BCHP_HIF_MSPI_SPCR2_spifie_SHIFT                           5
#define BCHP_HIF_MSPI_SPCR2_spifie_DEFAULT                         0

/* HIF_MSPI :: SPCR2 :: wren [04:04] */
#define BCHP_HIF_MSPI_SPCR2_wren_MASK                              0x00000010
#define BCHP_HIF_MSPI_SPCR2_wren_SHIFT                             4
#define BCHP_HIF_MSPI_SPCR2_wren_DEFAULT                           0

/* HIF_MSPI :: SPCR2 :: wrt0 [03:03] */
#define BCHP_HIF_MSPI_SPCR2_wrt0_MASK                              0x00000008
#define BCHP_HIF_MSPI_SPCR2_wrt0_SHIFT                             3
#define BCHP_HIF_MSPI_SPCR2_wrt0_DEFAULT                           0

/* HIF_MSPI :: SPCR2 :: loopq [02:02] */
#define BCHP_HIF_MSPI_SPCR2_loopq_MASK                             0x00000004
#define BCHP_HIF_MSPI_SPCR2_loopq_SHIFT                            2
#define BCHP_HIF_MSPI_SPCR2_loopq_DEFAULT                          0

/* HIF_MSPI :: SPCR2 :: hie [01:01] */
#define BCHP_HIF_MSPI_SPCR2_hie_MASK                               0x00000002
#define BCHP_HIF_MSPI_SPCR2_hie_SHIFT                              1
#define BCHP_HIF_MSPI_SPCR2_hie_DEFAULT                            0

/* HIF_MSPI :: SPCR2 :: halt [00:00] */
#define BCHP_HIF_MSPI_SPCR2_halt_MASK                              0x00000001
#define BCHP_HIF_MSPI_SPCR2_halt_SHIFT                             0
#define BCHP_HIF_MSPI_SPCR2_halt_DEFAULT                           0

/***************************************************************************
 *MSPI_STATUS - MSPI STATUS REGISTER
 ***************************************************************************/
/* HIF_MSPI :: MSPI_STATUS :: reserved0 [31:02] */
#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_MASK                   0xfffffffc
#define BCHP_HIF_MSPI_MSPI_STATUS_reserved0_SHIFT                  2

/* HIF_MSPI :: MSPI_STATUS :: HALTA [01:01] */
#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_MASK                       0x00000002
#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_SHIFT                      1
#define BCHP_HIF_MSPI_MSPI_STATUS_HALTA_DEFAULT                    0

/* HIF_MSPI :: MSPI_STATUS :: SPIF [00:00] */
#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_MASK                        0x00000001
#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_SHIFT                       0
#define BCHP_HIF_MSPI_MSPI_STATUS_SPIF_DEFAULT                     0

/***************************************************************************
 *CPTQP - CPTQP REGISTER
 ***************************************************************************/
/* HIF_MSPI :: CPTQP :: reserved0 [31:04] */
#define BCHP_HIF_MSPI_CPTQP_reserved0_MASK                         0xfffffff0
#define BCHP_HIF_MSPI_CPTQP_reserved0_SHIFT                        4

/* HIF_MSPI :: CPTQP :: cptqp [03:00] */
#define BCHP_HIF_MSPI_CPTQP_cptqp_MASK                             0x0000000f
#define BCHP_HIF_MSPI_CPTQP_cptqp_SHIFT                            0
#define BCHP_HIF_MSPI_CPTQP_cptqp_DEFAULT                          0

/***************************************************************************
 *TXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM00 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM00_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM00_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM00 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM00_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM00_txram_SHIFT                          0

/***************************************************************************
 *TXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM01 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM01_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM01_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM01 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM01_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM01_txram_SHIFT                          0

/***************************************************************************
 *TXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM02 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM02_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM02_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM02 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM02_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM02_txram_SHIFT                          0

/***************************************************************************
 *TXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM03 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM03_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM03_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM03 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM03_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM03_txram_SHIFT                          0

/***************************************************************************
 *TXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM04 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM04_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM04_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM04 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM04_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM04_txram_SHIFT                          0

/***************************************************************************
 *TXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM05 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM05_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM05_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM05 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM05_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM05_txram_SHIFT                          0

/***************************************************************************
 *TXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM06 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM06_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM06_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM06 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM06_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM06_txram_SHIFT                          0

/***************************************************************************
 *TXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM07 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM07_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM07_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM07 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM07_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM07_txram_SHIFT                          0

/***************************************************************************
 *TXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM08 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM08_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM08_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM08 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM08_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM08_txram_SHIFT                          0

/***************************************************************************
 *TXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM09 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM09_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM09_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM09 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM09_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM09_txram_SHIFT                          0

/***************************************************************************
 *TXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM10 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM10_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM10_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM10 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM10_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM10_txram_SHIFT                          0

/***************************************************************************
 *TXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM11 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM11_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM11_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM11 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM11_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM11_txram_SHIFT                          0

/***************************************************************************
 *TXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM12 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM12_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM12_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM12 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM12_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM12_txram_SHIFT                          0

/***************************************************************************
 *TXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM13 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM13_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM13_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM13 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM13_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM13_txram_SHIFT                          0

/***************************************************************************
 *TXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM14 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM14_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM14_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM14 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM14_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM14_txram_SHIFT                          0

/***************************************************************************
 *TXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM15 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM15_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM15_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM15 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM15_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM15_txram_SHIFT                          0

/***************************************************************************
 *TXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM16 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM16_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM16_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM16 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM16_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM16_txram_SHIFT                          0

/***************************************************************************
 *TXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM17 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM17_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM17_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM17 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM17_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM17_txram_SHIFT                          0

/***************************************************************************
 *TXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM18 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM18_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM18_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM18 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM18_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM18_txram_SHIFT                          0

/***************************************************************************
 *TXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM19 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM19_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM19_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM19 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM19_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM19_txram_SHIFT                          0

/***************************************************************************
 *TXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM20 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM20_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM20_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM20 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM20_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM20_txram_SHIFT                          0

/***************************************************************************
 *TXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM21 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM21_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM21_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM21 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM21_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM21_txram_SHIFT                          0

/***************************************************************************
 *TXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM22 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM22_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM22_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM22 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM22_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM22_txram_SHIFT                          0

/***************************************************************************
 *TXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM23 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM23_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM23_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM23 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM23_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM23_txram_SHIFT                          0

/***************************************************************************
 *TXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM24 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM24_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM24_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM24 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM24_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM24_txram_SHIFT                          0

/***************************************************************************
 *TXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM25 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM25_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM25_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM25 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM25_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM25_txram_SHIFT                          0

/***************************************************************************
 *TXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM26 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM26_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM26_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM26 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM26_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM26_txram_SHIFT                          0

/***************************************************************************
 *TXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM27 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM27_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM27_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM27 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM27_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM27_txram_SHIFT                          0

/***************************************************************************
 *TXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM28 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM28_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM28_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM28 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM28_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM28_txram_SHIFT                          0

/***************************************************************************
 *TXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM29 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM29_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM29_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM29 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM29_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM29_txram_SHIFT                          0

/***************************************************************************
 *TXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM30 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM30_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM30_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM30 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM30_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM30_txram_SHIFT                          0

/***************************************************************************
 *TXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
 ***************************************************************************/
/* HIF_MSPI :: TXRAM31 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_TXRAM31_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_TXRAM31_reserved0_SHIFT                      8

/* HIF_MSPI :: TXRAM31 :: txram [07:00] */
#define BCHP_HIF_MSPI_TXRAM31_txram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_TXRAM31_txram_SHIFT                          0

/***************************************************************************
 *RXRAM00 - MSbyte for bit 16 or bit 8 operation (queue pointer = 0)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM00 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM00_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM00_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM00 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM00_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM00_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM01 - LSbyte for bit 16 operation only (queue pointer = 0)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM01 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM01_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM01_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM01 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM01_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM01_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM02 - MSbyte for bit 16 or bit 8 operation (queue pointer = 1)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM02 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM02_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM02_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM02 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM02_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM02_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM03 - LSbyte for bit 16 operation only (queue pointer = 1)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM03 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM03_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM03_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM03 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM03_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM03_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM04 - MSbyte for bit 16 or bit 8 operation (queue pointer = 2)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM04 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM04_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM04_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM04 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM04_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM04_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM05 - LSbyte for bit 16 operation only (queue pointer = 2)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM05 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM05_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM05_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM05 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM05_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM05_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM06 - MSbyte for bit 16 or bit 8 operation (queue pointer = 3)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM06 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM06_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM06_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM06 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM06_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM06_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM07 - LSbyte for bit 16 operation only (queue pointer = 3)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM07 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM07_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM07_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM07 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM07_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM07_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM08 - MSbyte for bit 16 or bit 8 operation (queue pointer = 4)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM08 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM08_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM08_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM08 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM08_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM08_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM09 - LSbyte for bit 16 operation only (queue pointer = 4)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM09 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM09_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM09_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM09 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM09_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM09_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM10 - MSbyte for bit 16 or bit 8 operation (queue pointer = 5)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM10 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM10_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM10_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM10 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM10_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM10_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM11 - LSbyte for bit 16 operation only (queue pointer = 5)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM11 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM11_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM11_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM11 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM11_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM11_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM12 - MSbyte for bit 16 or bit 8 operation (queue pointer = 6)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM12 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM12_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM12_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM12 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM12_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM12_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM13 - LSbyte for bit 16 operation only (queue pointer = 6)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM13 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM13_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM13_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM13 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM13_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM13_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM14 - MSbyte for bit 16 or bit 8 operation (queue pointer = 7)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM14 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM14_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM14_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM14 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM14_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM14_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM15 - LSbyte for bit 16 operation only (queue pointer = 7)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM15 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM15_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM15_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM15 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM15_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM15_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM16 - MSbyte for bit 16 or bit 8 operation (queue pointer = 8)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM16 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM16_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM16_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM16 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM16_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM16_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM17 - LSbyte for bit 16 operation only (queue pointer = 8)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM17 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM17_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM17_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM17 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM17_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM17_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM18 - MSbyte for bit 16 or bit 8 operation (queue pointer = 9)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM18 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM18_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM18_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM18 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM18_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM18_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM19 - LSbyte for bit 16 operation only (queue pointer = 9)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM19 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM19_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM19_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM19 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM19_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM19_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM20 - MSbyte for bit 16 or bit 8 operation (queue pointer = a)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM20 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM20_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM20_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM20 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM20_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM20_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM21 - LSbyte for bit 16 operation only (queue pointer = a)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM21 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM21_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM21_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM21 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM21_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM21_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM22 - MSbyte for bit 16 or bit 8 operation (queue pointer = b)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM22 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM22_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM22_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM22 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM22_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM22_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM23 - LSbyte for bit 16 operation only (queue pointer = b)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM23 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM23_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM23_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM23 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM23_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM23_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM24 - MSbyte for bit 16 or bit 8 operation (queue pointer = c)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM24 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM24_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM24_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM24 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM24_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM24_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM25 - LSbyte for bit 16 operation only (queue pointer = c)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM25 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM25_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM25_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM25 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM25_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM25_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM26 - MSbyte for bit 16 or bit 8 operation (queue pointer = d)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM26 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM26_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM26_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM26 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM26_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM26_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM27 - LSbyte for bit 16 operation only (queue pointer = d)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM27 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM27_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM27_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM27 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM27_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM27_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM28 - MSbyte for bit 16 or bit 8 operation (queue pointer = e)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM28 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM28_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM28_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM28 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM28_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM28_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM29 - LSbyte for bit 16 operation only (queue pointer = e)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM29 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM29_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM29_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM29 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM29_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM29_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM30 - MSbyte for bit 16 or bit 8 operation (queue pointer = f)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM30 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM30_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM30_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM30 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM30_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM30_rxram_SHIFT                          0

/***************************************************************************
 *RXRAM31 - LSbyte for bit 16 operation only (queue pointer = f)
 ***************************************************************************/
/* HIF_MSPI :: RXRAM31 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_RXRAM31_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_RXRAM31_reserved0_SHIFT                      8

/* HIF_MSPI :: RXRAM31 :: rxram [07:00] */
#define BCHP_HIF_MSPI_RXRAM31_rxram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_RXRAM31_rxram_SHIFT                          0

/***************************************************************************
 *CDRAM00 - 8-bit command (queue pointer = 0)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM00 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM00_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM00_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM00 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM00_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM00_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM01 - 8-bit command (queue pointer = 1)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM01 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM01_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM01_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM01 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM01_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM01_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM02 - 8-bit command (queue pointer = 2)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM02 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM02_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM02_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM02 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM02_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM02_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM03 - 8-bit command (queue pointer = 3)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM03 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM03_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM03_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM03 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM03_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM03_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM04 - 8-bit command (queue pointer = 4)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM04 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM04_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM04_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM04 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM04_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM04_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM05 - 8-bit command (queue pointer = 5)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM05 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM05_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM05_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM05 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM05_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM05_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM06 - 8-bit command (queue pointer = 6)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM06 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM06_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM06_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM06 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM06_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM06_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM07 - 8-bit command (queue pointer = 7)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM07 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM07_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM07_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM07 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM07_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM07_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM08 - 8-bit command (queue pointer = 8)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM08 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM08_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM08_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM08 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM08_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM08_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM09 - 8-bit command (queue pointer = 9)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM09 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM09_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM09_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM09 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM09_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM09_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM10 - 8-bit command (queue pointer = a)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM10 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM10_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM10_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM10 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM10_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM10_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM11 - 8-bit command (queue pointer = b)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM11 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM11_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM11_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM11 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM11_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM11_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM12 - 8-bit command (queue pointer = c)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM12 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM12_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM12_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM12 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM12_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM12_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM13 - 8-bit command (queue pointer = d)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM13 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM13_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM13_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM13 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM13_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM13_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM14 - 8-bit command (queue pointer = e)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM14 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM14_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM14_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM14 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM14_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM14_cdram_SHIFT                          0

/***************************************************************************
 *CDRAM15 - 8-bit command (queue pointer = f)
 ***************************************************************************/
/* HIF_MSPI :: CDRAM15 :: reserved0 [31:08] */
#define BCHP_HIF_MSPI_CDRAM15_reserved0_MASK                       0xffffff00
#define BCHP_HIF_MSPI_CDRAM15_reserved0_SHIFT                      8

/* HIF_MSPI :: CDRAM15 :: cdram [07:00] */
#define BCHP_HIF_MSPI_CDRAM15_cdram_MASK                           0x000000ff
#define BCHP_HIF_MSPI_CDRAM15_cdram_SHIFT                          0

/***************************************************************************
 *WRITE_LOCK - Control bit to lock group of write commands
 ***************************************************************************/
/* HIF_MSPI :: WRITE_LOCK :: reserved0 [31:01] */
#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_MASK                    0xfffffffe
#define BCHP_HIF_MSPI_WRITE_LOCK_reserved0_SHIFT                   1

/* HIF_MSPI :: WRITE_LOCK :: WriteLock [00:00] */
#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_MASK                    0x00000001
#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_SHIFT                   0
#define BCHP_HIF_MSPI_WRITE_LOCK_WriteLock_DEFAULT                 0

/***************************************************************************
 *DISABLE_FLUSH_GEN - Debug bit to mask the generation of flush signals from Mspi
 ***************************************************************************/
/* HIF_MSPI :: DISABLE_FLUSH_GEN :: reserved0 [31:01] */
#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_MASK             0xfffffffe
#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_reserved0_SHIFT            1

/* HIF_MSPI :: DISABLE_FLUSH_GEN :: DisableFlushGen [00:00] */
#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_MASK       0x00000001
#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_SHIFT      0
#define BCHP_HIF_MSPI_DISABLE_FLUSH_GEN_DisableFlushGen_DEFAULT    0

#endif /* #ifndef BCHP_HIF_MSPI_H__ */

/* End of File */