/***************************************************************************
 *     Copyright (c) 1999-2010, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Tue Mar 30 14:45:11 2010
 *                 MD5 Checksum         fcc80e937f0852e5e867bbe2ad915642
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7550/rdb/a0/bchp_sun_top_ctrl.h $
 * 
 * Hydra_Software_Devel/8   3/30/10 7:49p albertl
 * SW7550-351: Updated to match RDB.
 *
 ***************************************************************************/

#ifndef BCHP_SUN_TOP_CTRL_H__
#define BCHP_SUN_TOP_CTRL_H__

/***************************************************************************
 *SUN_TOP_CTRL - Top Control registers
 ***************************************************************************/
#define BCHP_SUN_TOP_CTRL_PROD_REVISION          0x00404000 /* Product Revision ID */
#define BCHP_SUN_TOP_CTRL_SUN_REVISION           0x00404004 /* Sundry Revision ID */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404008 /* Reset control */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL               0x00404010 /* Control register for NMI */
#define BCHP_SUN_TOP_CTRL_SW_RESET               0x00404014 /* Software reset register */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404018 /* Reset history */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6         0x00404098 /* General control register 6 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x0040409c /* General status register 0 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x004040a0 /* General status register 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a4 /* General status register 2 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3       0x004040a8 /* General status register 3 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4       0x004040ac /* General status register 4 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_5       0x004040b0 /* General status register 5 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_6       0x004040b4 /* General status register 6 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040b8 /* General control register without scan 0 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040bc /* General control register without scan 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040c0 /* General control register without scan 2 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040c4 /* General control register without scan 3 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040c8 /* General control register without scan 4 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040cc /* General control register without scan 5 */
#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x004040d0 /* Scratch register */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x004040d4 /* Spare control bits reserved for future use */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00404140 /* Pad pull-up/pull-down control register 0 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404144 /* Pad pull-up/pull-down control register 1 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404148 /* Pad pull-up/pull-down control register 2 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x0040414c /* Pad pull-up/pull-down control register 3 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00404150 /* Pad pull-up/pull-down control register 4 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404154 /* Pad pull-up/pull-down control register 5 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404158 /* Pad pull-up/pull-down control register 6 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x0040415c /* Pad pull-up/pull-down control register 7 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x00404160 /* Pad pull-up/pull-down control register 8 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x00404164 /* Pad pull-up/pull-down control register 9 */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404180 /* Bypass clock unselect register 0 */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404200 /* Test port control */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404204 /* Testport peek register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404208 /* Testport poke register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040420c /* Testport peek register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404210 /* Testport poke register */
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404214 /* EJTAG input bus enables */
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404218 /* EJTAG output select */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040421c /* UART Router select */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404300 /* Serial Slave Port configuration register */
#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404320 /* SERS Revision Register */
#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404324 /* SERS Configuration Register */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404400 /* Block select for RO testmode */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL         0x00404500 /* Test_mode control register */
#define BCHP_SUN_TOP_CTRL_TEST_MODE              0x00404504 /* Register source for test_mode */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE          0x00404508 /* Register source for sub_test_mode */
#define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE      0x0040450c /* Final latched testmode value */
#define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE  0x00404510 /* Final latched sub-testmode value */
#define BCHP_SUN_TOP_CTRL_PM_CTRL                0x00404600 /* Control register for Power Controller */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS    0x00404604 /* Power Management IRQ input status */
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT     0x00404608 /* Power Management Wait counter in place of Wait for MIPS IRQ */

/***************************************************************************
 *PROD_REVISION - Product Revision ID
 ***************************************************************************/
/* SUN_TOP_CTRL :: PROD_REVISION :: product_revision [31:00] */
#define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_MASK      0xffffffff
#define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_SHIFT     0

/***************************************************************************
 *SUN_REVISION - Sundry Revision ID
 ***************************************************************************/
/* SUN_TOP_CTRL :: SUN_REVISION :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_MASK              0xffff0000
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_SHIFT             16

/* SUN_TOP_CTRL :: SUN_REVISION :: sundry_revision [15:00] */
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_MASK        0x0000ffff
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_SHIFT       0

/***************************************************************************
 *RESET_CTRL - Reset control
 ***************************************************************************/
/* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_monitor [31:31] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_MASK       0x80000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_SHIFT      31

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_monitor [30:30] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_MASK 0x40000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_SHIFT 30

/* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_def_val_monitor [29:29] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_def_val_monitor_MASK 0x20000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_def_val_monitor_SHIFT 29

/* SUN_TOP_CTRL :: RESET_CTRL :: reset_ext_mode_monitor [28:28] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_ext_mode_monitor_MASK   0x10000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_ext_mode_monitor_SHIFT  28

/* SUN_TOP_CTRL :: RESET_CTRL :: reset_timer_205_monitor [27:27] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_205_monitor_MASK  0x08000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_205_monitor_SHIFT 27

/* SUN_TOP_CTRL :: RESET_CTRL :: reset_timer_200_monitor [26:26] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_200_monitor_MASK  0x04000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_200_monitor_SHIFT 26

/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [25:12] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0x03fff000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               12

/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [11:11] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000800
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     11

/* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable_lock [10:10] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_SHIFT 10

/* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable [09:09] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_SHIFT 9

/* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable_lock [08:08] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_SHIFT 8

/* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable [07:07] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_MASK    0x00000080
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_SHIFT   7

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [06:06] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 6

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable [05:05] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT 5

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_polarity [04:04] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT 4

/* SUN_TOP_CTRL :: RESET_CTRL :: master_reset_en [03:03] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_MASK          0x00000008
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_SHIFT         3

/* SUN_TOP_CTRL :: RESET_CTRL :: reserved1 [02:02] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_MASK                0x00000004
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_SHIFT               2

/* SUN_TOP_CTRL :: RESET_CTRL :: sc_insert_reset_en [01:00] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_MASK       0x00000003
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_SHIFT      0

/***************************************************************************
 *NMI_CTRL - Control register for NMI
 ***************************************************************************/
/* SUN_TOP_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_config_lock_MASK            0x80000000
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_config_lock_SHIFT           31

/* SUN_TOP_CTRL :: NMI_CTRL :: reserved0 [30:03] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_reserved0_MASK                  0x7ffffff8
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_reserved0_SHIFT                 3

/* SUN_TOP_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_pad_monitor_MASK            0x00000004
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT           2

/* SUN_TOP_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_config_nmi_polarity_MASK        0x00000002
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT       1

/* SUN_TOP_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_disable_pad_nmi_MASK            0x00000001
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT           0

/***************************************************************************
 *SW_RESET - Software reset register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SW_RESET :: chip_master_reset [31:31] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_MASK          0x80000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_SHIFT         31

/* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_1shot [30:30] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_MASK         0x40000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_SHIFT        30

/* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_1shot [29:29] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_MASK        0x20000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_SHIFT       29

/* SUN_TOP_CTRL :: SW_RESET :: pci_rstb_out_sw_reset [28:28] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_pci_rstb_out_sw_reset_MASK      0x10000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_pci_rstb_out_sw_reset_SHIFT     28

/* SUN_TOP_CTRL :: SW_RESET :: reserved0 [27:22] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_MASK                  0x0fc00000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_SHIFT                 22

/* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_level [21:21] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_MASK        0x00200000
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_SHIFT       21

/* SUN_TOP_CTRL :: SW_RESET :: reserved1 [20:17] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved1_MASK                  0x001e0000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved1_SHIFT                 17

/* SUN_TOP_CTRL :: SW_RESET :: rptd_sw_reset [16:16] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_rptd_sw_reset_MASK              0x00010000
#define BCHP_SUN_TOP_CTRL_SW_RESET_rptd_sw_reset_SHIFT             16

/* SUN_TOP_CTRL :: SW_RESET :: ddr0_sw_reset [15:15] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ddr0_sw_reset_MASK              0x00008000
#define BCHP_SUN_TOP_CTRL_SW_RESET_ddr0_sw_reset_SHIFT             15

/* SUN_TOP_CTRL :: SW_RESET :: memc_sw_reset [14:14] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_memc_sw_reset_MASK              0x00004000
#define BCHP_SUN_TOP_CTRL_SW_RESET_memc_sw_reset_SHIFT             14

/* SUN_TOP_CTRL :: SW_RESET :: usb_sw_reset [13:13] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_usb_sw_reset_MASK               0x00002000
#define BCHP_SUN_TOP_CTRL_SW_RESET_usb_sw_reset_SHIFT              13

/* SUN_TOP_CTRL :: SW_RESET :: enet_sw_reset [12:12] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_enet_sw_reset_MASK              0x00001000
#define BCHP_SUN_TOP_CTRL_SW_RESET_enet_sw_reset_SHIFT             12

/* SUN_TOP_CTRL :: SW_RESET :: hdmi_sw_reset [11:11] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_hdmi_sw_reset_MASK              0x00000800
#define BCHP_SUN_TOP_CTRL_SW_RESET_hdmi_sw_reset_SHIFT             11

/* SUN_TOP_CTRL :: SW_RESET :: thd_sw_reset [10:10] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_thd_sw_reset_MASK               0x00000400
#define BCHP_SUN_TOP_CTRL_SW_RESET_thd_sw_reset_SHIFT              10

/* SUN_TOP_CTRL :: SW_RESET :: xpt_sw_reset [09:09] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_MASK               0x00000200
#define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_SHIFT              9

/* SUN_TOP_CTRL :: SW_RESET :: aio_sw_reset [08:08] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_aio_sw_reset_MASK               0x00000100
#define BCHP_SUN_TOP_CTRL_SW_RESET_aio_sw_reset_SHIFT              8

/* SUN_TOP_CTRL :: SW_RESET :: vec_sw_reset [07:07] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_vec_sw_reset_MASK               0x00000080
#define BCHP_SUN_TOP_CTRL_SW_RESET_vec_sw_reset_SHIFT              7

/* SUN_TOP_CTRL :: SW_RESET :: bvn_sw_reset [06:06] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_sw_reset_MASK               0x00000040
#define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_sw_reset_SHIFT              6

/* SUN_TOP_CTRL :: SW_RESET :: avd0_sw_reset [05:05] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_MASK              0x00000020
#define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_SHIFT             5

/* SUN_TOP_CTRL :: SW_RESET :: jtag_otp_sw_reset [04:04] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_MASK          0x00000010
#define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_SHIFT         4

/* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_level [03:03] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_MASK         0x00000008
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_SHIFT        3

/* SUN_TOP_CTRL :: SW_RESET :: ebi_sw_reset [02:02] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ebi_sw_reset_MASK               0x00000004
#define BCHP_SUN_TOP_CTRL_SW_RESET_ebi_sw_reset_SHIFT              2

/* SUN_TOP_CTRL :: SW_RESET :: pci_sw_reset [01:01] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_pci_sw_reset_MASK               0x00000002
#define BCHP_SUN_TOP_CTRL_SW_RESET_pci_sw_reset_SHIFT              1

/* SUN_TOP_CTRL :: SW_RESET :: sundry_sw_reset [00:00] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_MASK            0x00000001
#define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_SHIFT           0

/***************************************************************************
 *RESET_HISTORY - Reset history
 ***************************************************************************/
/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:12] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffff000
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            12

/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset [11:11] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_MASK   0x00000800
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_SHIFT  11

/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_sft_sft_rst_b [10:10] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_SHIFT 10

/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_hrd_sft_rst_b [09:09] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_SHIFT 9

/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [08:08] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 8

/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset [07:07] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_MASK  0x00000080
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_SHIFT 7

/* SUN_TOP_CTRL :: RESET_HISTORY :: special_sw_reset [06:06] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_MASK      0x00000040
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_SHIFT     6

/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved1 [05:05] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_MASK             0x00000020
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_SHIFT            5

/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [04:04] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000010
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 4

/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [03:03] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 3

/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [02:02] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 2

/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1

/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0

/***************************************************************************
 *STRAP_VALUE_0 - Strapping values
 ***************************************************************************/
/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:14] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffc000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            14

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [13:13] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 13

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_sys_clk_mux_select [12:12] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_sys_clk_mux_select_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_sys_clk_mux_select_SHIFT 12

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_nand_ecc [11:09] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_nand_ecc_MASK        0x00000e00
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_nand_ecc_SHIFT       9

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ixtal_adj [08:07] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ixtal_adj_MASK       0x00000180
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ixtal_adj_SHIFT      7

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_diffosc_highpass_up [06:06] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_diffosc_highpass_up_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_diffosc_highpass_up_SHIFT 6

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_xtal_bypass [05:05] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_bypass_MASK     0x00000020
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_bypass_SHIFT    5

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_hp_wake [04:04] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_hp_wake_MASK         0x00000010
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_hp_wake_SHIFT        4

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_cpu_speed [03:03] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_cpu_speed_MASK       0x00000008
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_cpu_speed_SHIFT      3

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [02:02] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 2

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_config [01:00] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_config_MASK     0x00000003
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_config_SHIFT    0

/***************************************************************************
 *STRAP_VALUE_1 - Strapping values
 ***************************************************************************/
/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:03] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff8
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            3

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_2 [02:02] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_SHIFT 2

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_1_SHIFT 1

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_0_SHIFT 0

/***************************************************************************
 *BOND_STATUS - Bond option value register
 ***************************************************************************/
/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1

/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0

/***************************************************************************
 *OTP_OPTION_TEST_0 - OTP option test register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [31:25] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK         0xfe000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT        25

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_system_big_endian [24:24] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_system_big_endian_MASK 0x01000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_system_big_endian_SHIFT 24

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_nand_ecc [23:21] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_nand_ecc_MASK 0x00e00000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_nand_ecc_SHIFT 21

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_boot_config [20:19] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_boot_config_MASK 0x00180000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_boot_config_SHIFT 19

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_boot_strap_override [18:18] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_boot_strap_override_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_boot_strap_override_SHIFT 18

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_boot_rom_enable [17:17] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_boot_rom_enable_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_boot_rom_enable_SHIFT 17

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_mcard_in_disable [16:16] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_mcard_in_disable_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_mcard_in_disable_SHIFT 16

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_isdbt_disable [15:15] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_isdbt_disable_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_isdbt_disable_SHIFT 15

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tuner_disable [14:14] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner_disable_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner_disable_SHIFT 14

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_enet_disable [13:13] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_enet_disable_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_enet_disable_SHIFT 13

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_disable [12:12] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_SHIFT 12

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [11:11] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 11

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [10:09] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000600
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 9

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [08:08] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 8

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_hd_display [07:07] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_hd_display_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_hd_display_SHIFT 7

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [06:06] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 6

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [05:05] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 5

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_enable [04:04] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_enable_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_enable_SHIFT 4

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_product_id [03:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_product_id_MASK 0x0000000f
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_product_id_SHIFT 0

/***************************************************************************
 *OTP_OPTION_TEST_1 - OTP option test register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_jtag_otp_3 [31:31] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_jtag_otp_3_MASK 0x80000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_jtag_otp_3_SHIFT 31

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_jtag_otp_2 [30:30] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_jtag_otp_2_MASK 0x40000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_jtag_otp_2_SHIFT 30

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_jtag_otp_1 [29:29] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_jtag_otp_1_MASK 0x20000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_jtag_otp_1_SHIFT 29

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_spare_jtag_otp_0 [28:28] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_jtag_otp_0_MASK 0x10000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_spare_jtag_otp_0_SHIFT 28

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_3 [27:27] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_3_MASK 0x08000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_3_SHIFT 27

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_2 [26:26] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_2_MASK 0x04000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_2_SHIFT 26

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_1 [25:25] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_1_MASK 0x02000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_1_SHIFT 25

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_0 [24:24] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_0_MASK 0x01000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_0_SHIFT 24

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: reserved0 [23:20] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved0_MASK         0x00f00000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved0_SHIFT        20

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_linreg_1p5 [19:15] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_linreg_1p5_MASK 0x000f8000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_linreg_1p5_SHIFT 15

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_linreg_2p5 [14:10] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_linreg_2p5_MASK 0x00007c00
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_linreg_2p5_SHIFT 10

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_linreg_1p2 [09:05] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_linreg_1p2_MASK 0x000003e0
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_linreg_1p2_SHIFT 5

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_swreg_1p2 [04:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_swreg_1p2_MASK 0x0000001f
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_swreg_1p2_SHIFT 0

/***************************************************************************
 *OTP_OPTION_STATUS_0 - OTP option status register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [31:25] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK       0xfe000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT      25

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_system_big_endian [24:24] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_system_big_endian_MASK 0x01000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_system_big_endian_SHIFT 24

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_nand_ecc [23:21] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_nand_ecc_MASK 0x00e00000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_nand_ecc_SHIFT 21

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_boot_config [20:19] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_boot_config_MASK 0x00180000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_boot_config_SHIFT 19

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_boot_strap_override [18:18] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_boot_strap_override_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_boot_strap_override_SHIFT 18

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_boot_rom_enable [17:17] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_boot_rom_enable_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_boot_rom_enable_SHIFT 17

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_mcard_in_disable [16:16] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_mcard_in_disable_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_mcard_in_disable_SHIFT 16

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_isdbt_disable [15:15] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_isdbt_disable_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_isdbt_disable_SHIFT 15

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tuner_disable [14:14] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner_disable_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner_disable_SHIFT 14

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_enet_disable [13:13] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_enet_disable_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_enet_disable_SHIFT 13

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_disable [12:12] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_SHIFT 12

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [11:11] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 11

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [10:09] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000600
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 9

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [08:08] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 8

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_hd_display [07:07] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_hd_display_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_hd_display_SHIFT 7

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [06:06] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 6

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [05:05] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 5

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_enable [04:04] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_enable_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_enable_SHIFT 4

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_product_id [03:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_product_id_MASK 0x0000000f
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_product_id_SHIFT 0

/***************************************************************************
 *OTP_OPTION_STATUS_1 - OTP option status register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_jtag_otp_3 [31:31] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_jtag_otp_3_MASK 0x80000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_jtag_otp_3_SHIFT 31

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_jtag_otp_2 [30:30] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_jtag_otp_2_MASK 0x40000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_jtag_otp_2_SHIFT 30

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_jtag_otp_1 [29:29] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_jtag_otp_1_MASK 0x20000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_jtag_otp_1_SHIFT 29

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_spare_jtag_otp_0 [28:28] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_jtag_otp_0_MASK 0x10000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_spare_jtag_otp_0_SHIFT 28

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_3 [27:27] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_3_MASK 0x08000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_3_SHIFT 27

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_2 [26:26] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_2_MASK 0x04000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_2_SHIFT 26

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_1 [25:25] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_1_MASK 0x02000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_1_SHIFT 25

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_0 [24:24] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_0_MASK 0x01000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_0_SHIFT 24

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: reserved0 [23:20] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved0_MASK       0x00f00000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved0_SHIFT      20

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_linreg_1p5 [19:15] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_linreg_1p5_MASK 0x000f8000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_linreg_1p5_SHIFT 15

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_linreg_2p5 [14:10] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_linreg_2p5_MASK 0x00007c00
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_linreg_2p5_SHIFT 10

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_linreg_1p2 [09:05] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_linreg_1p2_MASK 0x000003e0
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_linreg_1p2_SHIFT 5

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_swreg_1p2 [04:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_swreg_1p2_MASK 0x0000001f
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_swreg_1p2_SHIFT 0

/***************************************************************************
 *SEMAPHORE_0 - Semaphore channel 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_1 - Semaphore channel 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_2 - Semaphore channel 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_3 - Semaphore channel 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_4 - Semaphore channel 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_5 - Semaphore channel 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_6 - Semaphore channel 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_7 - Semaphore channel 7
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_8 - Semaphore channel 8
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_9 - Semaphore channel 9
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_10 - Semaphore channel 10
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_11 - Semaphore channel 11
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_12 - Semaphore channel 12
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_13 - Semaphore channel 13
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_14 - Semaphore channel 14
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_15 - Semaphore channel 15
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *GEN_WATCHDOG_0 - General watchdog timer 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0

/***************************************************************************
 *GEN_WATCHDOG_1 - General watchdog timer 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_0 - General control register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_reserved [31:25] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_reserved_MASK    0xfe000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_reserved_SHIFT   25

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_burst_stat_sel [24:24] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_burst_stat_sel_MASK 0x01000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_burst_stat_sel_SHIFT 24

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_access_mode [23:22] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_access_mode_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_access_mode_SHIFT 22

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_otp_prog_en [21:21] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_prog_en_MASK 0x00200000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_prog_en_SHIFT 21

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_otp_debug_mode [20:20] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_debug_mode_MASK 0x00100000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_debug_mode_SHIFT 20

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_continue_on_fail [19:19] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_continue_on_fail_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_continue_on_fail_SHIFT 19

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_time_margin [18:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_time_margin_MASK 0x00070000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_time_margin_SHIFT 16

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_sadbyp [15:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_sadbyp_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_sadbyp_SHIFT 15

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_unused [14:14] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_unused_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_unused_SHIFT 14

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_pbyp [13:13] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pbyp_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pbyp_SHIFT 13

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_pcount [12:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pcount_MASK 0x00001c00
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pcount_SHIFT 10

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_vsel [09:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_vsel_MASK 0x000003c0
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_vsel_SHIFT 6

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_prog_sel [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_prog_sel_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_prog_sel_SHIFT 5

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_command [04:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_command_MASK 0x0000001e
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_command_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_start [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_start_MASK  0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_start_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_1 - General control register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: jtag_otp_cpu_addr [31:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_addr_MASK    0xffff0000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_addr_SHIFT   16

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [15:12] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0x0000f000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           12

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: irw_top_sw_sram_write_not_read [11:11] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_sram_write_not_read_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_sram_write_not_read_SHIFT 11

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: irw_top_sw_sram_enable [10:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_sram_enable_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_sram_enable_SHIFT 10

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: irw_top_sw_clear_plugin_status [09:09] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_clear_plugin_status_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_clear_plugin_status_SHIFT 9

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: irw_sw_ring_osc_disable [08:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_sw_ring_osc_disable_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_sw_ring_osc_disable_SHIFT 8

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: irw_top_sw_timer_shift_reg_enable [07:07] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_timer_shift_reg_enable_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_timer_shift_reg_enable_SHIFT 7

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: irw_top_sw_timer_shift_reg_data [06:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_timer_shift_reg_data_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_timer_shift_reg_data_SHIFT 6

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: irw_top_sw_timer_shift_reg_clk [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_timer_shift_reg_clk_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_timer_shift_reg_clk_SHIFT 5

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: irw_top_ir_bypass [04:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_ir_bypass_MASK    0x00000010
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_ir_bypass_SHIFT   4

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: irw_top_sw_req_ir_code [03:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_req_ir_code_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_req_ir_code_SHIFT 3

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: irw_top_sw_led_cntrl [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_led_cntrl_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_led_cntrl_SHIFT 2

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: irw_top_sw_pwroff [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_pwroff_MASK    0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_irw_top_sw_pwroff_SHIFT   1

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: jtag_otp_cpu_mode [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_mode_MASK    0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_mode_SHIFT   0

/***************************************************************************
 *GENERAL_CTRL_2 - General control register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: jtag_otp_cpu_data [31:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_jtag_otp_cpu_data_MASK    0xffffffff
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_jtag_otp_cpu_data_SHIFT   0

/***************************************************************************
 *GENERAL_CTRL_3 - General control register 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: vrc_ldo_ctrl [31:30] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_ldo_ctrl_MASK         0xc0000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_ldo_ctrl_SHIFT        30

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: vrc_osc1p2 [29:28] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_osc1p2_MASK           0x30000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_osc1p2_SHIFT          28

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: vrc_ovcur_prot [27:26] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_ovcur_prot_MASK       0x0c000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_ovcur_prot_SHIFT      26

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: vrc_pwrdn1p2linreg [25:25] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_pwrdn1p2linreg_MASK   0x02000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_pwrdn1p2linreg_SHIFT  25

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: vrc_pwrdn1p5 [24:24] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_pwrdn1p5_MASK         0x01000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_pwrdn1p5_SHIFT        24

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: vrc_pwrdn2p5 [23:23] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_pwrdn2p5_MASK         0x00800000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_pwrdn2p5_SHIFT        23

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: vrc_ramp1p2 [22:20] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_ramp1p2_MASK          0x00700000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_ramp1p2_SHIFT         20

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: vrc_sel1p2 [19:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_sel1p2_MASK           0x000f8000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_sel1p2_SHIFT          15

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: vrc_sel1p5 [14:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_sel1p5_MASK           0x00007c00
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_sel1p5_SHIFT          10

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: vrc_sel2p5 [09:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_sel2p5_MASK           0x000003e0
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_sel2p5_SHIFT          5

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: vrc_swreg_sel1p2 [04:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_swreg_sel1p2_MASK     0x0000001f
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_vrc_swreg_sel1p2_SHIFT    0

/***************************************************************************
 *GENERAL_CTRL_4 - General control register 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xffff0000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           16

/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: vreg_linreg_1p2_sel_reg [15:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vreg_linreg_1p2_sel_reg_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vreg_linreg_1p2_sel_reg_SHIFT 15

/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: vreg_linreg_1p5_sel_reg [14:14] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vreg_linreg_1p5_sel_reg_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vreg_linreg_1p5_sel_reg_SHIFT 14

/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: vreg_linreg_2p5_sel_reg [13:13] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vreg_linreg_2p5_sel_reg_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vreg_linreg_2p5_sel_reg_SHIFT 13

/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: vreg_swreg_1p2_sel_reg [12:12] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vreg_swreg_1p2_sel_reg_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vreg_swreg_1p2_sel_reg_SHIFT 12

/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: vrc_adj [11:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vrc_adj_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vrc_adj_SHIFT             8

/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: vrc_adj1p2 [07:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vrc_adj1p2_MASK           0x000000f0
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vrc_adj1p2_SHIFT          4

/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: vrc_novl_delay1p2 [03:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vrc_novl_delay1p2_MASK    0x0000000f
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_vrc_novl_delay1p2_SHIFT   0

/***************************************************************************
 *GENERAL_CTRL_5 - General control register 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffff0
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           4

/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: chip_test_config [03:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_chip_test_config_MASK     0x0000000f
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_chip_test_config_SHIFT    0

/***************************************************************************
 *GENERAL_CTRL_6 - General control register 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_MASK            0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_reserved0_SHIFT           2

/* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: general_ctrl6_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_general_ctrl6_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_general_ctrl6_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_6 :: general_ctrl6_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_general_ctrl6_0_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_6_general_ctrl6_0_SHIFT     0

/***************************************************************************
 *GENERAL_STATUS_0 - General status register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: jtag_otp_cpu_data_out [31:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_jtag_otp_cpu_data_out_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_jtag_otp_cpu_data_out_SHIFT 0

/***************************************************************************
 *GENERAL_STATUS_1 - General status register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xffff0000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         16

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: jtag_otp_cpu_status [15:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_jtag_otp_cpu_status_MASK 0x0000ffff
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_jtag_otp_cpu_status_SHIFT 0

/***************************************************************************
 *GENERAL_STATUS_2 - General status register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xfffffff8
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         3

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: irw_plugin_status [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_irw_plugin_status_MASK  0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_irw_plugin_status_SHIFT 2

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: irw_top_sw_sram_ack [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_irw_top_sw_sram_ack_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_irw_top_sw_sram_ack_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: irw_top_sw_sram_dataout [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_irw_top_sw_sram_dataout_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_irw_top_sw_sram_dataout_SHIFT 0

/***************************************************************************
 *GENERAL_STATUS_3 - General status register 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_reserved0_MASK          0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_reserved0_SHIFT         2

/* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: general_status3_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_general_status3_1_MASK  0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_general_status3_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_STATUS_3 :: general_status3_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_general_status3_0_MASK  0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_3_general_status3_0_SHIFT 0

/***************************************************************************
 *GENERAL_STATUS_4 - General status register 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_reserved0_MASK          0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_reserved0_SHIFT         2

/* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: general_status4_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_general_status4_1_MASK  0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_general_status4_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_STATUS_4 :: general_status4_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_general_status4_0_MASK  0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_4_general_status4_0_SHIFT 0

/***************************************************************************
 *GENERAL_STATUS_5 - General status register 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_5 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_5_reserved0_MASK          0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_5_reserved0_SHIFT         2

/* SUN_TOP_CTRL :: GENERAL_STATUS_5 :: general_status5_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_5_general_status5_1_MASK  0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_5_general_status5_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_STATUS_5 :: general_status5_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_5_general_status5_0_MASK  0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_5_general_status5_0_SHIFT 0

/***************************************************************************
 *GENERAL_STATUS_6 - General status register 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_6 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_6_reserved0_MASK          0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_6_reserved0_SHIFT         2

/* SUN_TOP_CTRL :: GENERAL_STATUS_6 :: general_status6_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_6_general_status6_1_MASK  0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_6_general_status6_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_STATUS_6 :: general_status6_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_6_general_status6_0_MASK  0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_6_general_status6_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:23] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xff800000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   23

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_059 [22:22] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_059_MASK 0x00400000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_059_SHIFT 22

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_058 [21:21] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_058_MASK 0x00200000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_058_SHIFT 21

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_057 [20:20] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_057_MASK 0x00100000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_057_SHIFT 20

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_056 [19:19] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_056_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_056_SHIFT 19

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_055 [18:18] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_055_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_055_SHIFT 18

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_054 [17:17] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_054_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_054_SHIFT 17

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_053 [16:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_053_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_053_SHIFT 16

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_052 [15:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_052_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_052_SHIFT 15

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_051 [14:14] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_051_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_051_SHIFT 14

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_050 [13:13] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_050_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_050_SHIFT 13

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_049 [12:12] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_049_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_049_SHIFT 12

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_048 [11:11] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_048_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_048_SHIFT 11

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_047 [10:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_047_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_047_SHIFT 10

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_046 [09:09] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_046_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_046_SHIFT 9

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_045 [08:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_045_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_045_SHIFT 8

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_044 [07:07] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_044_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_044_SHIFT 7

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_043 [06:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_043_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_043_SHIFT 6

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_042 [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_042_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_042_SHIFT 5

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_041 [04:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_041_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_041_SHIFT 4

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_040 [03:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_040_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_040_SHIFT 3

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_039 [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_039_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_039_SHIFT 2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_038 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_038_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_038_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: pad_mode_gpio_037 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_037_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_pad_mode_gpio_037_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0

/***************************************************************************
 *UNCLEARED_SCRATCH - Scratch register
 ***************************************************************************/
/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0

/***************************************************************************
 *SPARE_CTRL - Spare control bits reserved for future use
 ***************************************************************************/
/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0

/***************************************************************************
 *PIN_MUX_CTRL_0 - Pinmux control register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_EBI_ADDR2         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_LED_LD2           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MII_RXD_02        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_PM_GPIO_02        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_EBI_ADDR1         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_LED_LD1           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MII_RXD_03        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_PM_GPIO_01        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_EBI_ADDR0         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_LED_LD0           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MII_TX_CLK        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_PM_GPIO_00        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: spi_s_ssb [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_spi_s_ssb_MASK            0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_spi_s_ssb_SHIFT           16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_spi_s_ssb_SPI_S_SSB       0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_spi_s_ssb_PM_SPI_S_SSB    1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: spi_s_miso [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_spi_s_miso_MASK           0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_spi_s_miso_SHIFT          12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_spi_s_miso_SPI_S_MISO     0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_spi_s_miso_PM_SPI_S_MISO  1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_sck [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_MASK               0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SHIFT              8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_SF_SCK             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_sck_PM_SF_SCK          1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_mosi [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_SF_MOSI           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_mosi_PM_SF_MOSI        1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: sf_miso [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_SF_MISO           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_sf_miso_PM_SF_MISO        1

/***************************************************************************
 *PIN_MUX_CTRL_1 - Pinmux control register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_EBI_ADDR10        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_LED_LS2           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MII_TX_EN         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_PM_GPIO_10        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_TP_IN_06          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_RC_TP_IN_06       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_EBI_ADDR9         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_LED_LS1           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MII_TXD_00        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_PM_GPIO_09        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_TP_IN_05          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_RC_TP_IN_05       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_EBI_ADDR8         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_LED_LS0           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MII_TXD_01        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_PM_GPIO_08        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_TP_IN_04          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_RC_TP_IN_04       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_07 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_GPIO_07           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_EBI_ADDR7         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_LED_LD7           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_MII_TXD_02        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_PM_GPIO_07        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_TP_IN_03          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_07_RC_TP_IN_03       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_06 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_GPIO_06           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_EBI_ADDR6         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_LED_LD6           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_MII_TXD_03        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_PM_GPIO_06        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_TP_IN_02          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_06_RC_TP_IN_02       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_05 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_GPIO_05           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_EBI_ADDR5         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_LED_LD5           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_MII_TX_ER         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_PM_GPIO_05        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_TP_IN_01          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_05_RC_TP_IN_01       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_04 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_GPIO_04           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_EBI_ADDR4         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_LED_LD4           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_IR1_OUT           3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_PM_GPIO_04        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_TP_IN_00          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_04_RC_TP_IN_00       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_03 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_GPIO_03           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_EBI_ADDR3         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_LED_LD3           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_IR1_INT           3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_03_PM_GPIO_03        4

/***************************************************************************
 *PIN_MUX_CTRL_2 - Pinmux control register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_18 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_GPIO_18           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_EBI_CLK_OUT       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_PM_GPIO_18        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_TP_IN_14          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_18_RC_TP_IN_14       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_17 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_GPIO_17           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_EBI_CLK_IN        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_PM_GPIO_17        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_TP_IN_13          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_17_RC_TP_IN_13       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_16 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_GPIO_16           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_EBI_WE1B          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_PM_GPIO_16        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_TP_IN_12          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_16_RC_TP_IN_12       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_15 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_GPIO_15           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_EBI_TAB           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_PM_GPIO_15        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_TP_IN_11          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_15_RC_TP_IN_11       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_14 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_GPIO_14           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_EBI_ADDR14        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_LED_KD1           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_MII_COL           3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_PM_GPIO_14        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_TP_IN_10          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_14_RC_TP_IN_10       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_13 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_GPIO_13           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_EBI_ADDR13        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_LED_KD0           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_MII_RX_CLK        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_PM_GPIO_13        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_TP_IN_09          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_13_RC_TP_IN_09       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_12 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_GPIO_12           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_EBI_ADDR12        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_LED_LS4           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_MII_RX_ER         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_PM_GPIO_12        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_TP_IN_08          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_12_RC_TP_IN_08       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_11 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_GPIO_11           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_EBI_ADDR11        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_LED_LS3           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_MII_MDC           3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_PM_GPIO_11        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_TP_IN_07          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_11_RC_TP_IN_07       6

/***************************************************************************
 *PIN_MUX_CTRL_3 - Pinmux control register 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_24 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_24_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_24_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_24_GPIO_24           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_24_EBI_DATA1         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_24_PM_GPIO_24        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_24_TP_IN_20          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_24_RC_TP_IN_20       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_23 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_23_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_23_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_23_GPIO_23           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_23_EBI_DATA0         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_23_PM_GPIO_23        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_23_TP_IN_19          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_23_RC_TP_IN_19       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_99 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_99_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_99_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_99_GPIO_99           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_99_EBI_CS4B          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_99_PM_GPIO_99        2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_22 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_GPIO_22           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_EBI_CS3B          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_PM_GPIO_22        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_TP_IN_18          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_22_RC_TP_IN_18       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_21 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_GPIO_21           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_EBI_CS2B          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_PM_GPIO_21        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_TP_IN_17          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_21_RC_TP_IN_17       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_20 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_GPIO_20           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_EBI_CS1B          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_PM_GPIO_20        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_TP_IN_16          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_20_RC_TP_IN_16       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_90 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_90_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_90_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_90_GPIO_90           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_90_EBI_CS0B          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_90_PM_GPIO_90        2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_19 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_GPIO_19           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_EBI_RWB           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_PM_GPIO_19        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_TP_IN_15          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_19_RC_TP_IN_15       4

/***************************************************************************
 *PIN_MUX_CTRL_4 - Pinmux control register 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_92 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_92_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_92_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_92_GPIO_92           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_92_EBI_DATA9         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_92_LED_KD3           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_92_PM_GPIO_92        3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_91 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_91_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_91_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_91_GPIO_91           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_91_EBI_DATA8         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_91_LED_KD2           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_91_PM_GPIO_91        3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_30 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_GPIO_30           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_EBI_DATA7         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_PM_GPIO_30        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_TP_IN_26          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_30_RC_TP_IN_26       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_29 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_GPIO_29           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_EBI_DATA6         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_PM_GPIO_29        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_TP_IN_25          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_29_RC_TP_IN_25       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_28 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_28_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_28_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_28_GPIO_28           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_28_EBI_DATA5         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_28_PM_GPIO_28        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_28_TP_IN_24          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_28_RC_TP_IN_24       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_27 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_27_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_27_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_27_GPIO_27           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_27_EBI_DATA4         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_27_PM_GPIO_27        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_27_TP_IN_23          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_27_RC_TP_IN_23       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_26 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_26_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_26_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_26_GPIO_26           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_26_EBI_DATA3         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_26_PM_GPIO_26        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_26_TP_IN_22          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_26_RC_TP_IN_22       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_25 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_25_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_25_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_25_GPIO_25           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_25_EBI_DATA2         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_25_PM_GPIO_25        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_25_TP_IN_21          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_25_RC_TP_IN_21       4

/***************************************************************************
 *PIN_MUX_CTRL_5 - Pinmux control register 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_32 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_32_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_32_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_32_GPIO_32           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_32_EBI_WE0B          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_32_PM_GPIO_32        2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_31 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_31_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_31_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_31_GPIO_31           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_31_EBI_RDB           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_31_PM_GPIO_31        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_31_TP_OUT_27         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_31_RC_TP_OUT_27      4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_98 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_98_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_98_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_98_GPIO_98           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_98_EBI_DATA15        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_98_SF_WPB            2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_98_PM_GPIO_98        3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_97 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_97_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_97_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_97_GPIO_97           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_97_EBI_DATA14        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_97_MII_RXD_00        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_97_SF_HOLDB          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_97_PM_GPIO_97        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_96 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_96_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_96_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_96_GPIO_96           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_96_EBI_DATA13        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_96_MII_RXD_01        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_96_EXT_IRQ1          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_96_PM_GPIO_96        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_95 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_95_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_95_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_95_GPIO_95           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_95_EBI_DATA12        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_95_MII_RX_DV         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_95_EXT_IRQ0          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_95_PM_GPIO_95        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_94 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_94_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_94_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_94_GPIO_94           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_94_EBI_DATA11        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_94_MII_MDIO          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_94_IR1_OUT           3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_94_PM_GPIO_94        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_93 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_93_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_93_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_93_GPIO_93           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_93_EBI_DATA10        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_93_MII_CRS           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_93_IR1_INT           3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_93_PM_GPIO_93        4

/***************************************************************************
 *PIN_MUX_CTRL_6 - Pinmux control register 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_40 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_40_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_40_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_40_GPIO_40           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_40_POD2CHIP_MDI3     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_40_MII_CRS           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_40_PM_GPIO_40        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_40_TP_OUT_07         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_40_RC_TP_OUT_07      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_39 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_39_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_39_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_39_GPIO_39           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_39_POD2CHIP_MDI2     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_39_MII_COL           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_39_PM_GPIO_39        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_39_TP_OUT_06         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_39_RC_TP_OUT_06      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_38 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_38_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_38_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_38_GPIO_38           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_38_POD2CHIP_MDI1     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_38_MII_RX_CLK        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_38_PM_GPIO_38        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_38_TP_OUT_05         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_38_RC_TP_OUT_05      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_37 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_37_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_37_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_37_GPIO_37           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_37_POD2CHIP_MDI0     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_37_MII_RX_ER         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_37_PM_GPIO_37        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_37_TP_OUT_04         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_37_RC_TP_OUT_04      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_36 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_36_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_36_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_36_GPIO_36           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_36_POD2CHIP_MCLKI    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_36_MII_RX_DV         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_36_POD_EBI_ADDR14    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_36_PM_GPIO_36        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_36_TP_OUT_03         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_36_RC_TP_OUT_03      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_35 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_35_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_35_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_35_GPIO_35           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_35_NAND_RBB          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_35_PM_GPIO_35        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_35_TP_OUT_02         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_35_RC_TP_OUT_02      4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_34 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_34_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_34_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_34_GPIO_34           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_34_EBI_TSB           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_34_PM_GPIO_34        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_34_TP_OUT_01         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_34_RC_TP_OUT_01      4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_33 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_33_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_33_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_33_GPIO_33           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_33_EBI_DSB           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_33_PM_GPIO_33        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_33_TP_OUT_00         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_33_RC_TP_OUT_00      4

/***************************************************************************
 *PIN_MUX_CTRL_7 - Pinmux control register 7
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_48 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_48_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_48_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_48_GPIO_48           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_48_CHIP2POD_MDO0     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_48_MII_TXD_02        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_48_POD_EBI_ADDR18    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_48_PM_GPIO_48        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_48_TP_OUT_15         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_48_RC_TP_OUT_15      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_47 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_47_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_47_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_47_GPIO_47           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_47_CHIP2POD_MCLKO    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_47_MII_TXD_03        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_47_POD_EBI_ADDR15    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_47_PM_GPIO_47        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_47_TP_OUT_14         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_47_RC_TP_OUT_14      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_46 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_46_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_46_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_46_GPIO_46           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_46_POD2CHIP_MIVAL    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_46_MII_RXD_00        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_46_PM_GPIO_46        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_46_TP_OUT_13         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_46_RC_TP_OUT_13      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_45 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_45_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_45_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_45_GPIO_45           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_45_POD2CHIP_MISTRT   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_45_MII_RXD_01        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_45_PM_GPIO_45        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_45_TP_OUT_12         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_45_RC_TP_OUT_12      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_44 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_44_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_44_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_44_GPIO_44           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_44_POD2CHIP_MDI7     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_44_MII_RXD_02        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_44_PM_GPIO_44        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_44_TP_OUT_11         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_44_RC_TP_OUT_11      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_43 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_43_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_43_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_43_GPIO_43           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_43_POD2CHIP_MDI6     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_43_MII_RXD_03        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_43_PM_GPIO_43        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_43_TP_OUT_10         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_43_RC_TP_OUT_10      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_42 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_42_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_42_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_42_GPIO_42           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_42_POD2CHIP_MDI5     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_42_MII_TX_CLK        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_42_PM_GPIO_42        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_42_TP_OUT_09         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_42_RC_TP_OUT_09      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_41 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_41_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_41_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_41_GPIO_41           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_41_POD2CHIP_MDI4     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_41_MII_MDIO          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_41_PM_GPIO_41        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_41_TP_OUT_08         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_41_RC_TP_OUT_08      5

/***************************************************************************
 *PIN_MUX_CTRL_8 - Pinmux control register 8
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_56 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_56_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_56_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_56_GPIO_56           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_56_CHIP2POD_MOSTRT   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_56_SC1_RST           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_56_POD_EBI_ADDR17    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_56_PM_GPIO_56        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_56_TP_OUT_23         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_56_RC_TP_OUT_23      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_55 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_55_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_55_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_55_GPIO_55           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_55_CHIP2POD_MDO7     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_55_SC1_CLK           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_55_POD_EBI_ADDR25    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_55_PM_GPIO_55        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_55_TP_OUT_22         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_55_RC_TP_OUT_22      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_54 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_54_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_54_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_54_GPIO_54           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_54_CHIP2POD_MDO6     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_54_SC1_VCC           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_54_POD_EBI_ADDR24    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_54_PM_GPIO_54        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_54_TP_OUT_21         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_54_RC_TP_OUT_21      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_53 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_53_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_53_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_53_GPIO_53           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_53_CHIP2POD_MDO5     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_53_MII_MDC           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_53_POD_EBI_ADDR23    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_53_PM_GPIO_53        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_53_TP_OUT_20         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_53_RC_TP_OUT_20      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_52 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_52_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_52_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_52_GPIO_52           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_52_CHIP2POD_MDO4     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_52_MII_TX_ER         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_52_POD_EBI_ADDR22    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_52_PM_GPIO_52        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_52_TP_OUT_19         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_52_RC_TP_OUT_19      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_51 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_51_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_51_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_51_GPIO_51           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_51_CHIP2POD_MDO3     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_51_MII_TX_EN         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_51_POD_EBI_ADDR21    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_51_PM_GPIO_51        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_51_TP_OUT_18         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_51_RC_TP_OUT_18      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_50 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_50_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_50_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_50_GPIO_50           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_50_CHIP2POD_MDO2     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_50_MII_TXD_00        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_50_POD_EBI_ADDR20    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_50_PM_GPIO_50        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_50_TP_OUT_17         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_50_RC_TP_OUT_17      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_49 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_49_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_49_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_49_GPIO_49           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_49_CHIP2POD_MDO1     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_49_MII_TXD_01        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_49_POD_EBI_ADDR19    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_49_PM_GPIO_49        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_49_TP_OUT_16         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_49_RC_TP_OUT_16      6

/***************************************************************************
 *PIN_MUX_CTRL_9 - Pinmux control register 9
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_64 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_64_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_64_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_64_GPIO_64           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_64_RMX0_CLK          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_64_PKT2_CLK          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_64_PM_GPIO_64        3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_63 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_63_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_63_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_63_GPIO_63           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_63_MPOD_M_SDI        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_63_UART_RX2          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_63_PM_GPIO_63        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_63_TP_IN_27          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_63_RC_TP_IN_27       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_62 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_62_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_62_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_62_GPIO_62           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_62_MPOD_M_SDO        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_62_UART_TX2          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_62_POD_EBI_ADDR0     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_62_PM_GPIO_62        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_62_TP_OUT_26         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_62_RC_TP_OUT_26      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_61 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_61_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_61_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_61_GPIO_61           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_61_MPOD_SCLK         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_61_RO_OBSRV          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_61_POD_EBI_ADDR1     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_61_PM_GPIO_61        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_60 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_60_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_60_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_60_GPIO_60           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_60_MPOD_SCTL         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_60_PWM1              2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_60_POD_EBI_ADDR2     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_60_PM_GPIO_60        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_59 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_59_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_59_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_59_GPIO_59           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_59_CHIP2POD_MOCLK    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_59_PWM0              2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_59_POD_EBI_ADDR12    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_59_PM_GPIO_59        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_58 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_58_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_58_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_58_GPIO_58           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_58_POD2CHIP_MICLK    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_58_SC1_PRES          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_58_POD_EBI_ADDR13    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_58_PM_GPIO_58        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_58_TP_OUT_25         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_58_RC_TP_OUT_25      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_57 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_57_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_57_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_57_GPIO_57           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_57_CHIP2POD_MOVAL    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_57_SC1_IO            2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_57_POD_EBI_ADDR16    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_57_PM_GPIO_57        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_57_TP_OUT_24         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_57_RC_TP_OUT_24      6

/***************************************************************************
 *PIN_MUX_CTRL_10 - Pinmux control register 10
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_72 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_72_MASK             0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_72_SHIFT            28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_72_GPIO_72          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_72_NDS_SC_IO        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_72_SC0_IO           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_72_AUD_FS_CLK0      3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_72_MAIN_PLL_LOCK    4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_72_PM_GPIO_72       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_71 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_71_MASK             0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_71_SHIFT            24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_71_GPIO_71          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_71_NDS_SC_RST       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_71_SC0_RST          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_71_I2S_LR0_IN       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_71_PM_GPIO_71       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_70 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_70_MASK             0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_70_SHIFT            20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_70_GPIO_70          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_70_NDS_SC_CLK       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_70_SC0_CLK          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_70_I2S_DATA0_IN     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_70_PM_GPIO_70       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_69 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_69_MASK             0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_69_SHIFT            16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_69_GPIO_69          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_69_NDS_SC_VCC       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_69_SC0_VCC          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_69_I2S_CLK0_IN      3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_69_PM_GPIO_69       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_68 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_68_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_68_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_68_GPIO_68          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_68_RMX0_PAUSE       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_68_PKT2_ERROR       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_68_PM_GPIO_68       3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_67 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_67_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_67_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_67_GPIO_67          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_67_RMX0_VALID       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_67_PKT2_VALID       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_67_PM_GPIO_67       3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_66 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_66_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_66_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_66_GPIO_66          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_66_RMX0_SYNC        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_66_PKT2_SYNC        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_66_PM_GPIO_66       3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_65 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_65_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_65_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_65_GPIO_65          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_65_RMX0_DATA        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_65_PKT2_DATA        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_65_PM_GPIO_65       3

/***************************************************************************
 *PIN_MUX_CTRL_11 - Pinmux control register 11
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_80 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_80_MASK             0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_80_SHIFT            28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_80_GPIO_80          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_80_PKT1_VALID       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_80_SPI_M_SS0B       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_80_VEC_HSYNC        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_80_PM_GPIO_80       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_79 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_79_MASK             0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_79_SHIFT            24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_79_GPIO_79          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_79_PKT1_SYNC        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_79_SPI_M_SCK        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_79_EXT_IRQ2         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_79_PM_GPIO_79       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_78 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_78_MASK             0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_78_SHIFT            20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_78_GPIO_78          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_78_PKT1_DATA        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_78_SPI_M_MISO       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_78_UART_RX1         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_78_PM_GPIO_78       4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_78_TP_IN_28         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_78_RC_TP_IN_28      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_77 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_77_MASK             0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_77_SHIFT            16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_77_GPIO_77          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_77_PKT1_CLK         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_77_SPI_M_MOSI       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_77_UART_TX1         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_77_PM_GPIO_77       4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_77_TP_OUT_28        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_77_RC_TP_OUT_28     6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_76 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_76_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_76_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_76_GPIO_76          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_76_NDS_SC_VPP       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_76_POD_EBI_DSB      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_76_DCLK_F1B_ADC     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_76_IR1_IN           4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_76_PM_GPIO_76       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_75 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_75_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_75_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_75_GPIO_75          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_75_NDS_SC_AUX1      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_75_POD_EBI_WE0B     2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_75_THD_DELSIG       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_75_VEC_VSYNC        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_75_PM_GPIO_75       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_74 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_74_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_74_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_74_GPIO_74          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_74_NDS_SC_AUX0      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_74_POD_EBI_RDB      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_74_THD_RAGC_DELSIG  3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_74_VEC_HSYNC        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_74_PM_GPIO_74       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_73 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_73_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_73_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_73_GPIO_73          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_73_NDS_SC_PRES      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_73_SC0_PRES         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_73_THD_IAGC_DELSIG  3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_73_DS_DELSIG        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_73_PM_GPIO_73       5

/***************************************************************************
 *PIN_MUX_CTRL_12 - Pinmux control register 12
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_83 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_83_MASK             0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_83_SHIFT            28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_83_GPIO_83          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_83_UART_RX0         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_83_PM_GPIO_83       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_83_TP_IN_29         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_83_RC_TP_IN_29      4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_82 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_82_MASK             0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_82_SHIFT            24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_82_GPIO_82          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_82_UART_TX0         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_82_PM_GPIO_82       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_82_TP_OUT_29        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_82_RC_TP_OUT_29     4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_104 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_MASK            0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_SHIFT           20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_GPIO_104        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_PKT2_ERROR      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_EBI_ADDR25      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_104_PM_GPIO_104     3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_103 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_MASK            0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_SHIFT           16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_GPIO_103        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_PKT2_VALID      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_EBI_ADDR24      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_103_PM_GPIO_103     3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_102 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_MASK            0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_SHIFT           12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_GPIO_102        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_PKT2_SYNC       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_EBI_ADDR23      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_102_PM_GPIO_102     3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_101 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_MASK            0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_SHIFT           8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_GPIO_101        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PKT2_DATA       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_EBI_ADDR22      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_101_PM_GPIO_101     3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_100 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_MASK            0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_SHIFT           4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_GPIO_100        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PKT2_CLK        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_EBI_ADDR21      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_100_PM_GPIO_100     3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_81 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_81_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_81_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_81_GPIO_81          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_81_PKT1_ERROR       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_81_SPI_M_SS1B       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_81_VEC_VSYNC        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_81_POD2CHIP_MCLKI   4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_81_PM_GPIO_81       5

/***************************************************************************
 *PIN_MUX_CTRL_13 - Pinmux control register 13
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: sgpio_01 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_01_MASK            0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_01_SHIFT           28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_01_SGPIO_01        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_01_BSC_M0_SDA      1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: sgpio_00 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_00_MASK            0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_00_SHIFT           24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_00_SGPIO_00        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_sgpio_00_BSC_M0_SCL      1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_89 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_89_MASK             0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_89_SHIFT            20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_89_GPIO_89          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_89_SF_WPB           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_89_EBI_ADDR20       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_89_IR1_IN           3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_89_EXT_IRQ1         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_89_PM_GPIO_89       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_88 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_88_MASK             0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_88_SHIFT            16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_88_GPIO_88          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_88_SF_HOLDB         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_88_EBI_ADDR19       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_88_RMX0_PAUSE       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_88_SPI_M_SS1B       4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_88_EXT_IRQ1         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_88_PM_GPIO_88       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_87 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_87_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_87_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_87_GPIO_87          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_87_UART_RX2         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_87_EBI_ADDR18       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_87_RMX0_VALID       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_87_SPI_M_SS0B       4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_87_PM_GPIO_87       5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_87_TP_IN_31         6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_87_RC_TP_IN_31      7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_86 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_86_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_86_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_86_GPIO_86          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_86_UART_TX2         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_86_EBI_ADDR17       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_86_RMX0_SYNC        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_86_SPI_M_SCK        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_86_PM_GPIO_86       5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_86_TP_OUT_31        6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_86_RC_TP_OUT_31     7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_85 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_85_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_85_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_85_GPIO_85          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_85_UART_RX1         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_85_EBI_ADDR16       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_85_RMX0_DATA        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_85_SPI_M_MISO       4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_85_PM_GPIO_85       5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_85_TP_IN_30         6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_85_RC_TP_IN_30      7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_84 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_84_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_84_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_84_GPIO_84          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_84_UART_TX1         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_84_EBI_ADDR15       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_84_RMX0_CLK         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_84_SPI_M_MOSI       4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_84_PM_GPIO_84       5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_84_TP_OUT_30        6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_84_RC_TP_OUT_30     7

/***************************************************************************
 *PIN_MUX_CTRL_14 - Pinmux control register 14
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_reserved0_MASK           0xffff0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_reserved0_SHIFT          16

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_05 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_05_MASK            0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_05_SHIFT           12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_05_SGPIO_05        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_05_BSC_M2_SDA      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_05_EXT_IRQ0        2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_04 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_04_MASK            0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_04_SHIFT           8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_04_SGPIO_04        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_04_BSC_M2_SCL      1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_03 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_03_MASK            0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_03_SHIFT           4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_03_SGPIO_03        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_03_BSC_M1_SDA      1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_02 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_02_MASK            0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_02_SHIFT           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_02_SGPIO_02        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_02_BSC_M1_SCL      1

/***************************************************************************
 *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: byp_avd_clk_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_avd_clk_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_avd_clk_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_avd_clk_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_avd_clk_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_avd_clk_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: byp_sys_clk_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_sys_clk_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_sys_clk_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_sys_clk_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_sys_clk_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_sys_clk_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: byp_mips_nco_clk_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_mips_nco_clk_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_mips_nco_clk_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_mips_nco_clk_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_mips_nco_clk_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_byp_mips_nco_clk_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ejtag_ce1_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_ce1_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_ce1_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_ce1_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_ce1_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_ce1_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ejtag_ce0_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_ce0_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_ce0_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_ce0_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_ce0_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_ce0_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ejtag_trstb_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_trstb_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_trstb_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_trstb_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_trstb_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_trstb_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ejtag_tms_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tms_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tms_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tms_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tms_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tms_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ejtag_tdi_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tdi_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tdi_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tdi_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tdi_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tdi_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: ejtag_tck_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tck_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tck_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tck_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tck_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_ejtag_tck_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nmib_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nmib_pad_ctrl_MASK    0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nmib_pad_ctrl_SHIFT   10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nmib_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nmib_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nmib_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: resetb_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_resetb_pad_ctrl_MASK  0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_resetb_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_resetb_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_resetb_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_resetb_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reset_outb_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reset_outb_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reset_outb_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reset_outb_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reset_outb_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reset_outb_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_sck_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_MASK  0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_sck_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_mosi_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_mosi_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: sf_miso_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_sf_miso_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ring_osc_dis_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ring_osc_dis_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ring_osc_dis_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ring_osc_dis_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ring_osc_dis_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ring_osc_dis_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ir_reset_outb_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ir_reset_outb_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ir_reset_outb_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ir_reset_outb_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ir_reset_outb_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ir_reset_outb_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: power_cntrl_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_power_cntrl_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_power_cntrl_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_power_cntrl_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_power_cntrl_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_power_cntrl_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: led_out_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_led_out_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_led_out_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_led_out_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_led_out_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_led_out_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: pwr_button_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pwr_button_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pwr_button_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pwr_button_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pwr_button_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_pwr_button_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: ir_in_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ir_in_pad_ctrl_MASK   0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ir_in_pad_ctrl_SHIFT  18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ir_in_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ir_in_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_ir_in_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: usb_pwron_2_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwron_2_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwron_2_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwron_2_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwron_2_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwron_2_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: usb_pwron_1_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwron_1_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwron_1_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwron_1_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwron_1_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwron_1_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: usb_pwrflt_2_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwrflt_2_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwrflt_2_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwrflt_2_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwrflt_2_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwrflt_2_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: usb_pwrflt_1_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwrflt_1_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwrflt_1_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwrflt_1_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwrflt_1_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_usb_pwrflt_1_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: aud_spdif_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_aud_spdif_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_aud_spdif_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_aud_spdif_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_aud_spdif_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_aud_spdif_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: hdmi_htplg_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hdmi_htplg_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hdmi_htplg_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hdmi_htplg_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hdmi_htplg_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hdmi_htplg_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spi_s_ssb_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spi_s_ssb_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spi_s_ssb_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spi_s_ssb_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spi_s_ssb_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spi_s_ssb_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spi_s_miso_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spi_s_miso_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spi_s_miso_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spi_s_miso_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spi_s_miso_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spi_s_miso_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: byp_27_clk_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_byp_27_clk_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_byp_27_clk_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_byp_27_clk_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_byp_27_clk_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_byp_27_clk_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_14_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_14_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_14_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_14_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_14_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_14_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_13_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_13_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_13_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_13_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_13_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_13_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_12_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_12_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_12_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_12_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_12_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_12_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_11_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_11_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_11_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_11_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_11_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_11_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_10_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_10_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_10_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_10_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_10_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_10_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_09_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_09_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_09_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_09_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_09_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_09_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_08_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_08_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_08_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_08_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_08_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_08_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_07_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_07_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_07_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_07_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_07_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_07_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_06_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_06_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_06_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_06_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_06_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_06_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_05_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_05_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_05_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_05_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_05_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_05_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_04_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_04_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_04_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_04_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_04_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_04_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_03_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_03_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_03_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_03_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_03_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_03_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_02_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_02_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_02_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_02_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_02_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_02_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_01_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_01_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_01_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_01_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_01_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_01_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_00_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_00_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_00_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_00_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_00_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_00_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_27_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_27_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_27_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_27_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_27_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_27_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_26_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_26_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_26_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_26_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_26_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_26_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_25_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_25_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_25_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_25_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_25_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_25_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_24_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_24_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_24_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_24_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_24_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_24_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_23_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_23_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_23_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_23_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_23_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_23_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_99_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_99_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_99_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_99_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_99_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_99_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_22_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_22_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_22_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_22_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_22_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_22_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_21_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_21_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_21_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_21_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_21_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_21_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_20_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_20_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_20_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_20_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_20_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_20_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_90_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_90_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_90_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_90_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_90_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_90_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_19_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_19_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_19_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_19_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_19_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_19_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_18_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_18_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_18_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_18_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_18_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_18_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_17_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_17_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_17_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_17_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_17_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_17_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_16_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_16_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_16_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_16_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_16_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_16_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_15_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_15_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_15_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_15_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_15_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_15_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_34_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_34_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_34_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_34_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_34_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_34_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_33_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_33_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_33_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_33_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_33_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_33_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_32_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_32_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_32_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_32_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_32_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_32_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_31_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_31_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_31_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_31_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_31_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_31_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_98_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_98_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_98_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_98_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_98_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_98_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_97_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_97_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_97_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_97_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_97_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_97_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_96_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_96_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_96_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_96_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_96_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_96_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_95_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_95_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_95_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_95_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_95_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_95_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_94_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_94_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_94_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_94_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_94_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_94_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_93_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_93_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_93_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_93_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_93_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_93_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_92_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_92_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_92_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_92_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_92_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_92_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_91_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_91_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_91_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_91_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_91_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_91_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_30_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_30_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_30_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_30_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_30_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_30_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_29_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_29_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_29_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_29_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_29_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_29_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_28_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_28_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_28_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_28_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_28_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_28_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_49_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_49_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_49_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_49_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_49_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_49_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_48_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_48_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_48_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_48_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_48_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_48_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_47_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_47_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_47_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_47_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_47_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_47_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_46_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_46_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_46_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_46_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_46_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_46_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_45_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_45_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_45_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_45_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_45_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_45_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_44_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_44_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_44_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_44_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_44_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_44_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_43_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_43_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_43_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_43_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_43_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_43_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_42_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_42_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_42_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_42_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_42_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_42_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_41_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_41_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_41_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_41_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_41_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_41_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_40_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_40_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_40_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_40_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_40_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_40_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_39_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_39_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_39_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_39_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_39_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_39_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_38_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_38_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_38_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_38_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_38_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_38_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_37_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_37_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_37_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_37_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_37_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_37_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_36_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_36_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_36_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_36_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_36_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_36_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_35_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_35_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_35_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_35_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_35_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_35_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_64_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_64_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_64_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_64_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_64_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_64_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_63_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_63_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_63_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_63_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_63_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_63_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_62_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_62_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_62_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_62_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_62_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_62_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_61_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_61_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_61_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_61_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_61_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_61_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_60_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_60_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_60_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_60_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_60_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_60_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_59_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_59_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_59_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_59_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_59_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_59_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_58_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_58_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_58_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_58_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_58_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_58_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_57_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_57_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_57_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_57_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_57_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_57_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_56_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_56_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_56_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_56_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_56_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_56_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_55_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_55_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_55_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_55_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_55_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_55_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_54_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_54_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_54_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_54_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_54_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_54_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_53_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_53_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_53_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_53_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_53_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_53_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_52_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_52_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_52_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_52_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_52_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_52_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_51_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_51_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_51_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_51_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_51_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_51_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_50_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_50_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_50_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_50_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_50_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_50_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_79_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_79_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_79_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_79_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_79_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_79_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_78_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_78_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_78_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_78_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_78_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_78_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_77_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_77_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_77_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_77_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_77_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_77_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_76_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_76_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_76_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_76_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_76_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_76_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_75_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_75_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_75_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_75_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_75_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_75_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_74_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_74_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_74_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_74_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_74_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_74_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_73_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_73_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_73_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_73_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_73_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_73_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_72_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_72_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_72_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_72_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_72_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_72_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_71_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_71_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_71_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_71_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_71_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_71_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_70_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_70_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_70_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_70_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_70_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_70_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_69_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_69_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_69_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_69_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_69_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_69_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_68_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_68_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_68_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_68_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_68_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_68_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_67_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_67_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_67_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_67_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_67_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_67_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_66_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_66_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_66_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_66_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_66_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_66_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_65_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_65_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_65_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_65_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_65_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_65_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_89_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_89_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_89_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_89_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_89_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_89_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_88_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_88_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_88_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_88_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_88_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_88_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_87_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_87_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_87_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_87_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_87_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_87_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_86_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_86_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_86_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_86_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_86_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_86_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_85_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_85_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_85_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_85_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_85_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_85_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_84_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_84_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_84_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_84_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_84_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_84_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_83_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_83_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_83_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_83_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_83_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_83_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_82_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_82_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_82_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_82_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_82_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_82_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_104_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_104_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_104_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_104_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_104_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_104_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_103_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_103_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_103_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_103_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_103_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_103_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_102_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_102_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_102_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_102_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_102_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_102_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_101_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_101_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_101_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_101_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_101_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_101_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_100_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_100_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_100_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_100_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_100_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_100_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_81_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_81_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_81_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_81_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_81_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_81_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_80_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_80_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_80_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_80_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_80_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_80_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved0 [31:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_MASK        0xffffc000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved0_SHIFT       14

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: reserved1 [11:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved1_MASK        0x00000fff
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_reserved1_SHIFT       0

/***************************************************************************
 *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:17] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfffe0000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       17

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_104 [16:16] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_104_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_104_SHIFT 16

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_103 [15:15] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_103_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_103_SHIFT 15

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_102 [14:14] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_102_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_102_SHIFT 14

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_101 [13:13] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_101_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_101_SHIFT 13

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_100 [12:12] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_100_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_100_SHIFT 12

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_67 [11:11] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_67_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_67_SHIFT 11

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_66 [10:10] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_66_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_66_SHIFT 10

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_65 [09:09] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_65_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_65_SHIFT 9

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_64 [08:08] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_64_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_64_SHIFT 8

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_32 [07:07] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_32_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_32_SHIFT 7

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_98 [06:06] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_98_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_98_SHIFT 6

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_02 [05:05] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_02_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_02_SHIFT 5

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_00 [04:04] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_00_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_00_SHIFT 4

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_27_clk [03:03] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_27_clk_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_27_clk_SHIFT 3

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_avd_clk [02:02] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_avd_clk_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_avd_clk_SHIFT 2

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_sys_clk [01:01] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_sys_clk_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_sys_clk_SHIFT 1

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_mips_nco_clk [00:00] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_mips_nco_clk_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_mips_nco_clk_SHIFT 0

/***************************************************************************
 *TEST_PORT_CTRL - Test port control
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sundry_local_tp_out_sel [31:28] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MASK 0xf0000000
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SHIFT 28
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_0 0
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_1 1
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_FP_RST_CNT 2
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MISC_TEST 3
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SSP 4
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_OUT_POKE_REG 5
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_IN 6
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_7 7
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_8 8
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_9 9
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_PWR_CTRL_STATUS 10
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_PWR_CTRL_IRQ_IN 11
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UPG_TP_OUT 12
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TOP_AUX_TP_OUT 15

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_THD     0
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_ENET    1
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     2
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     3
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SUN     4
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    5
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    6
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    7
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVND    8
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     9
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     10
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     11
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HDMI    12
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB     13
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC    14
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DDR23_APHY 15
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RPTD    16
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DS_TOP  17
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UNUSED_127 127

/***************************************************************************
 *TEST_PORT_OUT_PEEK - Testport peek register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0

/***************************************************************************
 *TEST_PORT_OUT_POKE - Testport poke register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0

/***************************************************************************
 *TEST_PORT_IN_PEEK - Testport peek register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0

/***************************************************************************
 *TEST_PORT_IN_POKE - Testport poke register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0

/***************************************************************************
 *EJTAG_INPUT_EN - EJTAG input bus enables
 ***************************************************************************/
/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:03] */
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff8
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           3

/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [02:00] */
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x00000007
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AUDIO_ZSP_CPU_ONE_HOT 4

/***************************************************************************
 *EJTAG_OUTPUT_SEL - EJTAG output select
 ***************************************************************************/
/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffffc
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         2

/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [01:00] */
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000003
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AUDIO_ZSP_CPU 2

/***************************************************************************
 *UART_ROUTER_SEL - UART Router select
 ***************************************************************************/
/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_l0 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_ll 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_l0 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_ll 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_l0 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_ll 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_l0 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_ll 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_l0 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_ll 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15

/***************************************************************************
 *SSP_CONFIG - Serial Slave Port configuration register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11

/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7

/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3

/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2

/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1

/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0

/***************************************************************************
 *SERS_REV - SERS Revision Register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16

/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8

/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0

/***************************************************************************
 *SERS_CFG - SERS Configuration Register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29

/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1

/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27

/* union - case mapped_buffer_mode [26:08] */
/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8

/* union - case cmd_fifo_mode [26:08] */
/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8

/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1

/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0

/***************************************************************************
 *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
 ***************************************************************************/
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404328
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32

/***************************************************************************
 *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0


/***************************************************************************
 *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
 ***************************************************************************/
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404348
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32

/***************************************************************************
 *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0


/***************************************************************************
 *RO_TEST_BLOCK_SEL - Block select for RO testmode
 ***************************************************************************/
/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5

/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [04:03] */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x00000018
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 3

/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [02:00] */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000007
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_CLK_RO_TEST_ID 1
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_XPT_RO_TEST_ID 2
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MIPS_RO_TEST_ID 3
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 4
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 5

/***************************************************************************
 *TEST_MODE_CTRL - Test_mode control register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_MODE_CTRL :: reserved0 [31:01] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_reserved0_SHIFT           1

/* SUN_TOP_CTRL :: TEST_MODE_CTRL :: use_test_mode_reg_src [00:00] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_use_test_mode_reg_src_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_use_test_mode_reg_src_SHIFT 0

/***************************************************************************
 *TEST_MODE - Register source for test_mode
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_MODE :: reserved0 [31:04] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_MASK                 0xfffffff0
#define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_SHIFT                4

/* SUN_TOP_CTRL :: TEST_MODE :: test_mode [03:00] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_MASK                 0x0000000f
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_SHIFT                0

/***************************************************************************
 *SUB_TEST_MODE - Register source for sub_test_mode
 ***************************************************************************/
/* SUN_TOP_CTRL :: SUB_TEST_MODE :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_reserved0_MASK             0xffffff00
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_reserved0_SHIFT            8

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_2 [07:07] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_2_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_2_SHIFT 7

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [06:06] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT 6

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [05:05] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT 5

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_ecc_disable [04:04] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_ecc_disable_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_ecc_disable_SHIFT 4

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [03:03] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT 3

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [02:02] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 2

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [01:01] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 1

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [00:00] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 0

/***************************************************************************
 *LATCHED_TEST_MODE - Final latched testmode value
 ***************************************************************************/
/* SUN_TOP_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
#define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT 0

/***************************************************************************
 *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
 ***************************************************************************/
/* SUN_TOP_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
#define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0

/***************************************************************************
 *PM_CTRL - Control register for Power Controller
 ***************************************************************************/
/* SUN_TOP_CTRL :: PM_CTRL :: pm_wait_count_upper_bits [31:20] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_count_upper_bits_MASK    0xfff00000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_count_upper_bits_SHIFT   20

/* SUN_TOP_CTRL :: PM_CTRL :: pm_wait_counter_active [19:19] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_counter_active_MASK      0x00080000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_counter_active_SHIFT     19

/* SUN_TOP_CTRL :: PM_CTRL :: pm_rst_clock_div [18:18] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_rst_clock_div_MASK            0x00040000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_rst_clock_div_SHIFT           18

/* SUN_TOP_CTRL :: PM_CTRL :: pm_pwrdn_pll_req [17:17] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pwrdn_pll_req_MASK            0x00020000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pwrdn_pll_req_SHIFT           17

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_cml_clocks [16:16] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cml_clocks_MASK           0x00010000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cml_clocks_SHIFT          16

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_all_clocks [15:15] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_all_clocks_MASK           0x00008000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_all_clocks_SHIFT          15

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_cpu_clock [14:14] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cpu_clock_MASK            0x00004000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cpu_clock_SHIFT           14

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_avd_rptd_clock [13:13] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_avd_rptd_clock_MASK       0x00002000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_avd_rptd_clock_SHIFT      13

/* SUN_TOP_CTRL :: PM_CTRL :: pm_pll_lock [12:12] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pll_lock_MASK                 0x00001000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pll_lock_SHIFT                12

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dram_ready_for_pwrdn [11:11] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dram_ready_for_pwrdn_MASK     0x00000800
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dram_ready_for_pwrdn_SHIFT    11

/* SUN_TOP_CTRL :: PM_CTRL :: pm_bsp_ready_for_pwrdn [10:10] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_MASK      0x00000400
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_SHIFT     10

/* SUN_TOP_CTRL :: PM_CTRL :: pm_mips_ready_for_pwrdn [09:09] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_mips_ready_for_pwrdn_MASK     0x00000200
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_mips_ready_for_pwrdn_SHIFT    9

/* SUN_TOP_CTRL :: PM_CTRL :: pm_sec_avd_rptd_clk_disable [08:08] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_sec_avd_rptd_clk_disable_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_sec_avd_rptd_clk_disable_SHIFT 8

/* SUN_TOP_CTRL :: PM_CTRL :: pm_state [07:04] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_MASK                    0x000000f0
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_SHIFT                   4
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_ACTIVE               0
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_PWRDN_RDY            1
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_DISABLE_AVD_RPTD     2
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_DISABLE_CPU          3
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_TRANSITION_TO_STANDBY 4
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_STANDBY              5
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_STANDBY_WITH_PLLS_ON 6
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_RESET_216_108_CLKS   7
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_TRANSITION_TO_ACTIVE 8

/* SUN_TOP_CTRL :: PM_CTRL :: pm_power_ctrl_disable [03:03] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_power_ctrl_disable_MASK       0x00000008
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_power_ctrl_disable_SHIFT      3

/* SUN_TOP_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK      0x00000004
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT     2

/* SUN_TOP_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK         0x00000002
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT        1

/* SUN_TOP_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_start_pwrdn_MASK              0x00000001
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT             0

/***************************************************************************
 *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
 ***************************************************************************/
/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: reserved0 [31:01] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_reserved0_MASK       0xfffffffe
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_reserved0_SHIFT      1

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: spare_wakeup_event_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_spare_wakeup_event_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_spare_wakeup_event_0_SHIFT 0

/***************************************************************************
 *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
 ***************************************************************************/
/* SUN_TOP_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK        0xffff0000
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT       16

/* SUN_TOP_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK 0x0000ffff
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0

#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */

/* End of File */