/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Thu Jul 23 05:16:46 2009
 *                 MD5 Checksum         a8d3dda5e1ef15dc0f3282d30e99ced5
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7550/rdb/a0/bchp_hif_cpu_intr1.h $
 * 
 * Hydra_Software_Devel/4   7/23/09 6:24p nitinb
 * PR54730: Updated headers for CRDB updates on 16 July 2009
 *
 ***************************************************************************/

#ifndef BCHP_HIF_CPU_INTR1_H__
#define BCHP_HIF_CPU_INTR1_H__

/***************************************************************************
 *HIF_CPU_INTR1 - HIF CPU Thread Processor 0 Level 1 Interrupt Controller Registers
 ***************************************************************************/
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS        0x00001400 /* Interrupt Status Register */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS        0x00001404 /* Interrupt Status Register */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS        0x00001408 /* Interrupt Status Register */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS   0x0000140c /* Interrupt Mask Status Register */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS   0x00001410 /* Interrupt Mask Status Register */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS   0x00001414 /* Interrupt Mask Status Register */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET      0x00001418 /* Interrupt Mask Set Register */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET      0x0000141c /* Interrupt Mask Set Register */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET      0x00001420 /* Interrupt Mask Set Register */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR    0x00001424 /* Interrupt Mask Clear Register */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR    0x00001428 /* Interrupt Mask Clear Register */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR    0x0000142c /* Interrupt Mask Clear Register */

/***************************************************************************
 *INTR_W0_STATUS - Interrupt Status Register
 ***************************************************************************/
/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: reserved0 [31:26] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_reserved0_MASK           0xfc000000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_reserved0_SHIFT          26

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AVD0_CPU_INTR [25:25] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AVD0_CPU_INTR_MASK       0x02000000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AVD0_CPU_INTR_SHIFT      25

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: USB_CPU_INTR [24:24] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_USB_CPU_INTR_MASK        0x01000000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_USB_CPU_INTR_SHIFT       24

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: SUN_CPU_INTR [23:23] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SUN_CPU_INTR_MASK        0x00800000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_SUN_CPU_INTR_SHIFT       23

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: MC_CPU_INTR [22:22] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MC_CPU_INTR_MASK         0x00400000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MC_CPU_INTR_SHIFT        22

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: UPG_SC_CPU_INTR [21:21] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_SC_CPU_INTR_MASK     0x00200000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_SC_CPU_INTR_SHIFT    21

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: UPG_UART0_CPU_INTR [20:20] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_UART0_CPU_INTR_MASK  0x00100000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_UART0_CPU_INTR_SHIFT 20

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: UPG_SPI_CPU_INTR [19:19] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_SPI_CPU_INTR_MASK    0x00080000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_SPI_CPU_INTR_SHIFT   19

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: UPG_BSC_CPU_INTR [18:18] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_BSC_CPU_INTR_MASK    0x00040000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_BSC_CPU_INTR_SHIFT   18

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: UPG_TMR_CPU_INTR [17:17] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_TMR_CPU_INTR_MASK    0x00020000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_TMR_CPU_INTR_SHIFT   17

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: UPG_GPIO_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_GPIO_CPU_INTR_MASK   0x00010000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_GPIO_CPU_INTR_SHIFT  16

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: UPG_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_MASK        0x00008000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT       15

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: ENET_EMAC1_CPU_INTR [14:14] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_ENET_EMAC1_CPU_INTR_MASK 0x00004000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_ENET_EMAC1_CPU_INTR_SHIFT 14

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: MEMC_0_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC_0_CPU_INTR_MASK     0x00002000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_MEMC_0_CPU_INTR_SHIFT    13

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_CPU_INTR_5 [12:12] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_5_MASK     0x00001000
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_5_SHIFT    12

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_CPU_INTR_1 [11:11] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_1_MASK     0x00000800
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_1_SHIFT    11

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNF_CPU_INTR_0 [10:10] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_0_MASK     0x00000400
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_0_SHIFT    10

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: BVNB_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_CPU_INTR_MASK       0x00000200
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_BVNB_CPU_INTR_SHIFT      9

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: VEC_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_VEC_CPU_INTR_MASK        0x00000100
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_VEC_CPU_INTR_SHIFT       8

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: DVP_HT_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_DVP_HT_CPU_INTR_MASK     0x00000080
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_DVP_HT_CPU_INTR_SHIFT    7

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: RPTD_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_RPTD_CPU_INTR_MASK       0x00000040
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_RPTD_CPU_INTR_SHIFT      6

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK        0x00000020
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT       5

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: XPT_ICAM_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_XPT_ICAM_CPU_INTR_MASK   0x00000010
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_XPT_ICAM_CPU_INTR_SHIFT  4

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: XPT_RAV_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_XPT_RAV_CPU_INTR_MASK    0x00000008
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_XPT_RAV_CPU_INTR_SHIFT   3

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: XPT_STATUS_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_XPT_STATUS_CPU_INTR_SHIFT 2

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK    0x00000002
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT   1

/* HIF_CPU_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK        0x00000001
#define BCHP_HIF_CPU_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT       0

/***************************************************************************
 *INTR_W1_STATUS - Interrupt Status Register
 ***************************************************************************/
/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: reserved0 [31:14] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_MASK           0xffffc000
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_reserved0_SHIFT          14

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: XPT_FE_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_XPT_FE_CPU_INTR_MASK     0x00002000
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_XPT_FE_CPU_INTR_SHIFT    13

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: XPT_PCR_CPU_INTR [12:12] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_XPT_PCR_CPU_INTR_MASK    0x00001000
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_XPT_PCR_CPU_INTR_SHIFT   12

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: USB_OHCI_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB_OHCI_CPU_INTR_MASK   0x00000800
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB_OHCI_CPU_INTR_SHIFT  11

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: USB_EHCI_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB_EHCI_CPU_INTR_MASK   0x00000400
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_USB_EHCI_CPU_INTR_SHIFT  10

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK       0x00000200
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT      9

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK       0x00000100
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT      8

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_7_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_7_CPU_INTR_MASK  0x00000080
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_7_CPU_INTR_SHIFT 7

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_6_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_6_CPU_INTR_MASK  0x00000040
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_6_CPU_INTR_SHIFT 6

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_5_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_5_CPU_INTR_MASK  0x00000020
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_5_CPU_INTR_SHIFT 5

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_4_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_4_CPU_INTR_MASK  0x00000010
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_4_CPU_INTR_SHIFT 4

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_3_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_3_CPU_INTR_MASK  0x00000008
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_3_CPU_INTR_SHIFT 3

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_2_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_2_CPU_INTR_MASK  0x00000004
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_2_CPU_INTR_SHIFT 2

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_1_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_1_CPU_INTR_MASK  0x00000002
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_1_CPU_INTR_SHIFT 1

/* HIF_CPU_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_0_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_0_CPU_INTR_MASK  0x00000001
#define BCHP_HIF_CPU_INTR1_INTR_W1_STATUS_EXT_IRQ_0_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W2_STATUS - Interrupt Status Register
 ***************************************************************************/
/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: reserved0 [31:14] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_MASK           0xffffc000
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_reserved0_SHIFT          14

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_7_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_7_CPU_INTR_MASK    0x00002000
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_7_CPU_INTR_SHIFT   13

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_6_CPU_INTR [12:12] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_6_CPU_INTR_MASK    0x00001000
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_6_CPU_INTR_SHIFT   12

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_5_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_5_CPU_INTR_MASK    0x00000800
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_5_CPU_INTR_SHIFT   11

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_4_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_4_CPU_INTR_MASK    0x00000400
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_4_CPU_INTR_SHIFT   10

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_3_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_3_CPU_INTR_MASK    0x00000200
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_3_CPU_INTR_SHIFT   9

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_2_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_2_CPU_INTR_MASK    0x00000100
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_2_CPU_INTR_SHIFT   8

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_1_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_1_CPU_INTR_MASK    0x00000080
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_1_CPU_INTR_SHIFT   7

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: SPARE_0_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_0_CPU_INTR_MASK    0x00000040
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_SPARE_0_CPU_INTR_SHIFT   6

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: DS2_CPU_INTR_2 [05:05] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_DS2_CPU_INTR_2_MASK      0x00000020
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_DS2_CPU_INTR_2_SHIFT     5

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: DS1_CPU_INTR_1 [04:04] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_DS1_CPU_INTR_1_MASK      0x00000010
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_DS1_CPU_INTR_1_SHIFT     4

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: DS0_CPU_INTR_0 [03:03] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_DS0_CPU_INTR_0_MASK      0x00000008
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_DS0_CPU_INTR_0_SHIFT     3

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: THD_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_THD_CPU_INTR_MASK        0x00000004
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_THD_CPU_INTR_SHIFT       2

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK  0x00000002
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 1

/* HIF_CPU_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK  0x00000001
#define BCHP_HIF_CPU_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
 ***************************************************************************/
/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: reserved0 [31:26] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_reserved0_MASK      0xfc000000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_reserved0_SHIFT     26

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AVD0_CPU_INTR [25:25] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AVD0_CPU_INTR_MASK  0x02000000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AVD0_CPU_INTR_SHIFT 25

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: USB_CPU_INTR [24:24] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_USB_CPU_INTR_MASK   0x01000000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_USB_CPU_INTR_SHIFT  24

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: SUN_CPU_INTR [23:23] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SUN_CPU_INTR_MASK   0x00800000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_SUN_CPU_INTR_SHIFT  23

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: MC_CPU_INTR [22:22] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MC_CPU_INTR_MASK    0x00400000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MC_CPU_INTR_SHIFT   22

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: UPG_SC_CPU_INTR [21:21] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x00200000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 21

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: UPG_UART0_CPU_INTR [20:20] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00100000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 20

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: UPG_SPI_CPU_INTR [19:19] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x00080000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 19

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: UPG_BSC_CPU_INTR [18:18] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00040000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 18

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: UPG_TMR_CPU_INTR [17:17] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x00020000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 17

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: UPG_GPIO_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_GPIO_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_GPIO_CPU_INTR_SHIFT 16

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: UPG_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_CPU_INTR_MASK   0x00008000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_UPG_CPU_INTR_SHIFT  15

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: ENET_EMAC1_CPU_INTR [14:14] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_ENET_EMAC1_CPU_INTR_MASK 0x00004000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_ENET_EMAC1_CPU_INTR_SHIFT 14

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: MEMC_0_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC_0_CPU_INTR_MASK 0x00002000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_MEMC_0_CPU_INTR_SHIFT 13

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_CPU_INTR_5 [12:12] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_CPU_INTR_5_MASK 0x00001000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_CPU_INTR_5_SHIFT 12

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_CPU_INTR_1 [11:11] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_CPU_INTR_1_MASK 0x00000800
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_CPU_INTR_1_SHIFT 11

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_CPU_INTR_0 [10:10] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_CPU_INTR_0_MASK 0x00000400
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNF_CPU_INTR_0_SHIFT 10

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_CPU_INTR_MASK  0x00000200
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_BVNB_CPU_INTR_SHIFT 9

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: VEC_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_VEC_CPU_INTR_MASK   0x00000100
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_VEC_CPU_INTR_SHIFT  8

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: DVP_HT_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_DVP_HT_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_DVP_HT_CPU_INTR_SHIFT 7

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: RPTD_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_RPTD_CPU_INTR_MASK  0x00000040
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_RPTD_CPU_INTR_SHIFT 6

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK   0x00000020
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT  5

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: XPT_ICAM_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_XPT_ICAM_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_XPT_ICAM_CPU_INTR_SHIFT 4

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: XPT_RAV_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 3

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: XPT_STATUS_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 2

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 1

/* HIF_CPU_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK   0x00000001
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT  0

/***************************************************************************
 *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
 ***************************************************************************/
/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: reserved0 [31:14] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_reserved0_MASK      0xffffc000
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_reserved0_SHIFT     14

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: XPT_FE_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x00002000
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 13

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: XPT_PCR_CPU_INTR [12:12] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x00001000
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 12

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: USB_OHCI_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB_OHCI_CPU_INTR_MASK 0x00000800
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB_OHCI_CPU_INTR_SHIFT 11

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: USB_EHCI_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB_EHCI_CPU_INTR_MASK 0x00000400
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_USB_EHCI_CPU_INTR_SHIFT 10

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK  0x00000200
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 9

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK  0x00000100
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 8

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_7_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_7_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_7_CPU_INTR_SHIFT 7

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_6_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_6_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_6_CPU_INTR_SHIFT 6

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_5_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_5_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_5_CPU_INTR_SHIFT 5

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_4_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_4_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_4_CPU_INTR_SHIFT 4

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_3_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_3_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_3_CPU_INTR_SHIFT 3

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_2_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_2_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_2_CPU_INTR_SHIFT 2

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_1_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_1_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_1_CPU_INTR_SHIFT 1

/* HIF_CPU_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_0_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_0_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_0_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
 ***************************************************************************/
/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:14] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK      0xffffc000
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT     14

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_7_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_7_CPU_INTR_MASK 0x00002000
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_7_CPU_INTR_SHIFT 13

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_6_CPU_INTR [12:12] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_6_CPU_INTR_MASK 0x00001000
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_6_CPU_INTR_SHIFT 12

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_5_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_5_CPU_INTR_MASK 0x00000800
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_5_CPU_INTR_SHIFT 11

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_4_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_4_CPU_INTR_MASK 0x00000400
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_4_CPU_INTR_SHIFT 10

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_3_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_3_CPU_INTR_MASK 0x00000200
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_3_CPU_INTR_SHIFT 9

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_2_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_2_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_2_CPU_INTR_SHIFT 8

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_1_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_1_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_1_CPU_INTR_SHIFT 7

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: SPARE_0_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_0_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_SPARE_0_CPU_INTR_SHIFT 6

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: DS2_CPU_INTR_2 [05:05] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_DS2_CPU_INTR_2_MASK 0x00000020
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_DS2_CPU_INTR_2_SHIFT 5

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: DS1_CPU_INTR_1 [04:04] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_DS1_CPU_INTR_1_MASK 0x00000010
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_DS1_CPU_INTR_1_SHIFT 4

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: DS0_CPU_INTR_0 [03:03] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_DS0_CPU_INTR_0_MASK 0x00000008
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_DS0_CPU_INTR_0_SHIFT 3

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: THD_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_THD_CPU_INTR_MASK   0x00000004
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_THD_CPU_INTR_SHIFT  2

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 1

/* HIF_CPU_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W0_MASK_SET - Interrupt Mask Set Register
 ***************************************************************************/
/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: reserved0 [31:26] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_reserved0_MASK         0xfc000000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_reserved0_SHIFT        26

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AVD0_CPU_INTR [25:25] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AVD0_CPU_INTR_MASK     0x02000000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AVD0_CPU_INTR_SHIFT    25

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: USB_CPU_INTR [24:24] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_USB_CPU_INTR_MASK      0x01000000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_USB_CPU_INTR_SHIFT     24

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: SUN_CPU_INTR [23:23] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SUN_CPU_INTR_MASK      0x00800000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_SUN_CPU_INTR_SHIFT     23

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: MC_CPU_INTR [22:22] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MC_CPU_INTR_MASK       0x00400000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MC_CPU_INTR_SHIFT      22

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: UPG_SC_CPU_INTR [21:21] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_SC_CPU_INTR_MASK   0x00200000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_SC_CPU_INTR_SHIFT  21

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: UPG_UART0_CPU_INTR [20:20] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00100000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 20

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: UPG_SPI_CPU_INTR [19:19] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_SPI_CPU_INTR_MASK  0x00080000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 19

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: UPG_BSC_CPU_INTR [18:18] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_BSC_CPU_INTR_MASK  0x00040000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 18

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: UPG_TMR_CPU_INTR [17:17] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_TMR_CPU_INTR_MASK  0x00020000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 17

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: UPG_GPIO_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_GPIO_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_GPIO_CPU_INTR_SHIFT 16

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: UPG_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_CPU_INTR_MASK      0x00008000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_UPG_CPU_INTR_SHIFT     15

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: ENET_EMAC1_CPU_INTR [14:14] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_ENET_EMAC1_CPU_INTR_MASK 0x00004000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_ENET_EMAC1_CPU_INTR_SHIFT 14

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: MEMC_0_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC_0_CPU_INTR_MASK   0x00002000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_MEMC_0_CPU_INTR_SHIFT  13

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_CPU_INTR_5 [12:12] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_CPU_INTR_5_MASK   0x00001000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_CPU_INTR_5_SHIFT  12

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_CPU_INTR_1 [11:11] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_CPU_INTR_1_MASK   0x00000800
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_CPU_INTR_1_SHIFT  11

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNF_CPU_INTR_0 [10:10] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_CPU_INTR_0_MASK   0x00000400
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNF_CPU_INTR_0_SHIFT  10

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: BVNB_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_CPU_INTR_MASK     0x00000200
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_BVNB_CPU_INTR_SHIFT    9

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: VEC_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_VEC_CPU_INTR_MASK      0x00000100
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_VEC_CPU_INTR_SHIFT     8

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: DVP_HT_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_DVP_HT_CPU_INTR_MASK   0x00000080
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_DVP_HT_CPU_INTR_SHIFT  7

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: RPTD_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_RPTD_CPU_INTR_MASK     0x00000040
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_RPTD_CPU_INTR_SHIFT    6

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK      0x00000020
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT     5

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: XPT_ICAM_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_XPT_ICAM_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_XPT_ICAM_CPU_INTR_SHIFT 4

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: XPT_RAV_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_XPT_RAV_CPU_INTR_MASK  0x00000008
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 3

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: XPT_STATUS_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 2

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK  0x00000002
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 1

/* HIF_CPU_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK      0x00000001
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT     0

/***************************************************************************
 *INTR_W1_MASK_SET - Interrupt Mask Set Register
 ***************************************************************************/
/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: reserved0 [31:14] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_reserved0_MASK         0xffffc000
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_reserved0_SHIFT        14

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: XPT_FE_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_XPT_FE_CPU_INTR_MASK   0x00002000
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_XPT_FE_CPU_INTR_SHIFT  13

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: XPT_PCR_CPU_INTR [12:12] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_XPT_PCR_CPU_INTR_MASK  0x00001000
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 12

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: USB_OHCI_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB_OHCI_CPU_INTR_MASK 0x00000800
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB_OHCI_CPU_INTR_SHIFT 11

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: USB_EHCI_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB_EHCI_CPU_INTR_MASK 0x00000400
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_USB_EHCI_CPU_INTR_SHIFT 10

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK     0x00000200
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT    9

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK     0x00000100
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT    8

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_7_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_7_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_7_CPU_INTR_SHIFT 7

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_6_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_6_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_6_CPU_INTR_SHIFT 6

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_5_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_5_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_5_CPU_INTR_SHIFT 5

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_4_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_4_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_4_CPU_INTR_SHIFT 4

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_3_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_3_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_3_CPU_INTR_SHIFT 3

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_2_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_2_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_2_CPU_INTR_SHIFT 2

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_1_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_1_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_1_CPU_INTR_SHIFT 1

/* HIF_CPU_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_0_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_0_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_SET_EXT_IRQ_0_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W2_MASK_SET - Interrupt Mask Set Register
 ***************************************************************************/
/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:14] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_MASK         0xffffc000
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT        14

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_7_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_7_CPU_INTR_MASK  0x00002000
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_7_CPU_INTR_SHIFT 13

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_6_CPU_INTR [12:12] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_6_CPU_INTR_MASK  0x00001000
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_6_CPU_INTR_SHIFT 12

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_5_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_5_CPU_INTR_MASK  0x00000800
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_5_CPU_INTR_SHIFT 11

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_4_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_4_CPU_INTR_MASK  0x00000400
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_4_CPU_INTR_SHIFT 10

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_3_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_3_CPU_INTR_MASK  0x00000200
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_3_CPU_INTR_SHIFT 9

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_2_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_2_CPU_INTR_MASK  0x00000100
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_2_CPU_INTR_SHIFT 8

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_1_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_1_CPU_INTR_MASK  0x00000080
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_1_CPU_INTR_SHIFT 7

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: SPARE_0_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_0_CPU_INTR_MASK  0x00000040
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_SPARE_0_CPU_INTR_SHIFT 6

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: DS2_CPU_INTR_2 [05:05] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_DS2_CPU_INTR_2_MASK    0x00000020
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_DS2_CPU_INTR_2_SHIFT   5

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: DS1_CPU_INTR_1 [04:04] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_DS1_CPU_INTR_1_MASK    0x00000010
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_DS1_CPU_INTR_1_SHIFT   4

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: DS0_CPU_INTR_0 [03:03] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_DS0_CPU_INTR_0_MASK    0x00000008
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_DS0_CPU_INTR_0_SHIFT   3

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: THD_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_THD_CPU_INTR_MASK      0x00000004
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_THD_CPU_INTR_SHIFT     2

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 1

/* HIF_CPU_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
 ***************************************************************************/
/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: reserved0 [31:26] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_reserved0_MASK       0xfc000000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_reserved0_SHIFT      26

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AVD0_CPU_INTR [25:25] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AVD0_CPU_INTR_MASK   0x02000000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AVD0_CPU_INTR_SHIFT  25

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: USB_CPU_INTR [24:24] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_USB_CPU_INTR_MASK    0x01000000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_USB_CPU_INTR_SHIFT   24

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: SUN_CPU_INTR [23:23] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SUN_CPU_INTR_MASK    0x00800000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_SUN_CPU_INTR_SHIFT   23

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: MC_CPU_INTR [22:22] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MC_CPU_INTR_MASK     0x00400000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MC_CPU_INTR_SHIFT    22

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_SC_CPU_INTR [21:21] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x00200000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 21

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_UART0_CPU_INTR [20:20] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00100000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 20

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_SPI_CPU_INTR [19:19] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x00080000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 19

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_BSC_CPU_INTR [18:18] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00040000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 18

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_TMR_CPU_INTR [17:17] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x00020000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 17

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_GPIO_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_GPIO_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_GPIO_CPU_INTR_SHIFT 16

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_CPU_INTR_MASK    0x00008000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_UPG_CPU_INTR_SHIFT   15

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: ENET_EMAC1_CPU_INTR [14:14] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_ENET_EMAC1_CPU_INTR_MASK 0x00004000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_ENET_EMAC1_CPU_INTR_SHIFT 14

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC_0_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC_0_CPU_INTR_MASK 0x00002000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_MEMC_0_CPU_INTR_SHIFT 13

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_CPU_INTR_5 [12:12] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_CPU_INTR_5_MASK 0x00001000
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_CPU_INTR_5_SHIFT 12

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_CPU_INTR_1 [11:11] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_CPU_INTR_1_MASK 0x00000800
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_CPU_INTR_1_SHIFT 11

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_CPU_INTR_0 [10:10] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_CPU_INTR_0_MASK 0x00000400
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNF_CPU_INTR_0_SHIFT 10

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_CPU_INTR_MASK   0x00000200
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_BVNB_CPU_INTR_SHIFT  9

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: VEC_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_VEC_CPU_INTR_MASK    0x00000100
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_VEC_CPU_INTR_SHIFT   8

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: DVP_HT_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_DVP_HT_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_DVP_HT_CPU_INTR_SHIFT 7

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: RPTD_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_RPTD_CPU_INTR_MASK   0x00000040
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_RPTD_CPU_INTR_SHIFT  6

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK    0x00000020
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT   5

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: XPT_ICAM_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_XPT_ICAM_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_XPT_ICAM_CPU_INTR_SHIFT 4

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: XPT_RAV_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 3

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: XPT_STATUS_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 2

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 1

/* HIF_CPU_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK    0x00000001
#define BCHP_HIF_CPU_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT   0

/***************************************************************************
 *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
 ***************************************************************************/
/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: reserved0 [31:14] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_reserved0_MASK       0xffffc000
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_reserved0_SHIFT      14

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: XPT_FE_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x00002000
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 13

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: XPT_PCR_CPU_INTR [12:12] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x00001000
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 12

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: USB_OHCI_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB_OHCI_CPU_INTR_MASK 0x00000800
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB_OHCI_CPU_INTR_SHIFT 11

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: USB_EHCI_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB_EHCI_CPU_INTR_MASK 0x00000400
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_USB_EHCI_CPU_INTR_SHIFT 10

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK   0x00000200
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT  9

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK   0x00000100
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT  8

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_7_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_7_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_7_CPU_INTR_SHIFT 7

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_6_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_6_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_6_CPU_INTR_SHIFT 6

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_5_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_5_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_5_CPU_INTR_SHIFT 5

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_4_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_4_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_4_CPU_INTR_SHIFT 4

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_3_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_3_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_3_CPU_INTR_SHIFT 3

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_2_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_2_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_2_CPU_INTR_SHIFT 2

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_1_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_1_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_1_CPU_INTR_SHIFT 1

/* HIF_CPU_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_0_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_0_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_0_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
 ***************************************************************************/
/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:14] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK       0xffffc000
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT      14

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_7_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_7_CPU_INTR_MASK 0x00002000
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_7_CPU_INTR_SHIFT 13

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_6_CPU_INTR [12:12] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_6_CPU_INTR_MASK 0x00001000
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_6_CPU_INTR_SHIFT 12

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_5_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_5_CPU_INTR_MASK 0x00000800
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_5_CPU_INTR_SHIFT 11

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_4_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_4_CPU_INTR_MASK 0x00000400
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_4_CPU_INTR_SHIFT 10

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_3_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_3_CPU_INTR_MASK 0x00000200
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_3_CPU_INTR_SHIFT 9

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_2_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_2_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_2_CPU_INTR_SHIFT 8

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_1_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_1_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_1_CPU_INTR_SHIFT 7

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: SPARE_0_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_0_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_SPARE_0_CPU_INTR_SHIFT 6

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: DS2_CPU_INTR_2 [05:05] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_DS2_CPU_INTR_2_MASK  0x00000020
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_DS2_CPU_INTR_2_SHIFT 5

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: DS1_CPU_INTR_1 [04:04] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_DS1_CPU_INTR_1_MASK  0x00000010
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_DS1_CPU_INTR_1_SHIFT 4

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: DS0_CPU_INTR_0 [03:03] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_DS0_CPU_INTR_0_MASK  0x00000008
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_DS0_CPU_INTR_0_SHIFT 3

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: THD_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_THD_CPU_INTR_MASK    0x00000004
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_THD_CPU_INTR_SHIFT   2

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 1

/* HIF_CPU_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 0

#endif /* #ifndef BCHP_HIF_CPU_INTR1_H__ */

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