/***************************************************************************
 *     Copyright (c) 1999-2011, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Mon Jun 13 14:31:19 2011
 *                 MD5 Checksum         a14f8e7f638a7ebe759043ff756befc5
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7425/rdb/b0/bchp_clkgen.h $
 * 
 * Hydra_Software_Devel/3   6/14/11 1:13p vanessah
 * SW7425-715: 7425 B0 RDB resync
 *
 ***************************************************************************/

#ifndef BCHP_CLKGEN_H__
#define BCHP_CLKGEN_H__

/***************************************************************************
 *CLKGEN - clkgen registers
 ***************************************************************************/
#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL         0x00430004 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV             0x00430008 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 0x0043000c /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN            0x00430010 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW 0x00430014 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH 0x00430018 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC            0x0043001c /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2           0x00430020 /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS     0x00430024 /* Lock Status */
#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS          0x00430028 /* Test Status */
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET           0x0043002c /* Resets */
#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN           0x00430030 /* Powerdowns */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL         0x00430034 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV             0x00430038 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 0x0043003c /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 0x00430040 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 0x00430044 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 0x00430048 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN            0x00430050 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW 0x00430054 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH 0x00430058 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC            0x0043005c /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2           0x00430060 /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS     0x00430064 /* Lock Status */
#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS          0x00430068 /* Test Status */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET          0x0043006c /* Resets */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN          0x00430070 /* Powerdowns */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL        0x00430074 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV            0x00430078 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC           0x0043007c /* Fractional */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 0x00430080 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 0x00430084 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 0x00430088 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN           0x0043008c /* PLL GAIN */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW 0x00430090 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH 0x00430094 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC           0x00430098 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS    0x0043009c /* Lock Status */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS         0x004300a0 /* Test Status */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET         0x004300a4 /* Resets */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN         0x004300a8 /* Powerdowns */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL       0x004300ac /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV           0x004300b0 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN          0x004300b4 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW 0x004300b8 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH 0x004300bc /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS   0x004300c0 /* Lock Status */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS        0x004300c4 /* Test Status */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET          0x004300c8 /* Resets */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN          0x004300cc /* Powerdowns */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL        0x004300d0 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV            0x004300d4 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC           0x004300d8 /* Fractional */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 0x004300dc /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 0x004300e0 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 0x004300e4 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN           0x004300e8 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW 0x004300ec /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH 0x004300f0 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC           0x004300f4 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS    0x004300f8 /* Lock Status */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS         0x004300fc /* Test Status */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET         0x00430100 /* Resets */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN         0x00430104 /* Powerdowns */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL       0x00430108 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV           0x0043010c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN          0x00430110 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW 0x00430114 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH 0x00430118 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS   0x0043011c /* Lock Status */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS        0x00430120 /* Test Status */
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET            0x00430124 /* Resets */
#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN            0x00430128 /* Powerdowns */
#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL          0x0043012c /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_HIF_PLL_DIV              0x00430130 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0 0x00430134 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1 0x00430138 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN             0x0043013c /* PLL GAIN */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC             0x00430140 /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS      0x00430144 /* Lock Status */
#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS           0x00430148 /* Test Status */
#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN           0x0043014c /* Cml buffer Tristate enable */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET           0x00430150 /* Resets */
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN           0x00430154 /* Powerdowns */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL         0x00430158 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV             0x0043015c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 0x00430160 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 0x00430164 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 0x00430168 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 0x0043016c /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 0x00430170 /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 0x00430174 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN            0x00430178 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW 0x0043017c /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH 0x00430180 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC            0x00430184 /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2           0x00430188 /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS     0x0043018c /* Lock Status */
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS          0x00430190 /* Test Status */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET          0x00430194 /* Resets */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN          0x00430198 /* Powerdowns */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL        0x0043019c /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV            0x004301a0 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 0x004301a4 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 0x004301a8 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN           0x004301ac /* PLL GAIN */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW 0x004301b0 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH 0x004301b4 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC           0x004301b8 /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2          0x004301bc /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS    0x004301c0 /* Lock Status */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS         0x004301c4 /* Test Status */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET        0x004301c8 /* Resets */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN        0x004301cc /* Powerdowns */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL      0x004301d0 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV          0x004301d4 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 0x004301d8 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 0x004301dc /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 0x004301e0 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN         0x004301e4 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW 0x004301e8 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH 0x004301ec /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC         0x004301f0 /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2        0x004301f4 /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS  0x004301f8 /* Lock Status */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS       0x004301fc /* Test Status */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE 0x00430200 /* Disable VEC_AIO_TOP_INST's vec_dacadc clocks */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL         0x00430204 /* Miscellaneous Controls */
#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY 0x00430208 /* V3D_TOP inst power switch memory */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 0x0043020c /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 0x00430210 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 0x00430214 /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 0x00430218 /* PLL CHANNEL control CH 3 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 0x0043021c /* PLL CHANNEL control CH 4 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 0x00430220 /* PLL CHANNEL control CH 5 */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN            0x00430224 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW 0x00430228 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH 0x0043022c /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC            0x00430230 /* Miscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2           0x00430234 /* Miscellaneous control bus continued. */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS     0x00430238 /* Lock Status */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS          0x0043023c /* Test Status */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET          0x00430240 /* Resets */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN          0x00430244 /* Powerdowns */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL        0x00430248 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV            0x0043024c /* Pre multiplier */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC           0x00430250 /* Fractional */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 0x00430254 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 0x00430258 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 0x0043025c /* PLL CHANNEL control CH 2 */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN           0x00430260 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW 0x00430264 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH 0x00430268 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC           0x0043026c /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS    0x00430270 /* Lock Status */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS         0x00430274 /* Test Status */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET             0x00430278 /* Resets */
#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN             0x0043027c /* Powerdowns */
#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL           0x00430280 /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_SC_PLL_DIV               0x00430284 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0 0x00430288 /* PLL CHANNEL control CH 0 */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN              0x0043028c /* PLL GAIN */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW 0x00430290 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH 0x00430294 /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC              0x00430298 /* Mscellaneous control bus. */
#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS       0x0043029c /* Lock Status */
#define BCHP_CLKGEN_PLL_SC_PLL_STATUS            0x004302a0 /* Test Status */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET         0x004302a4 /* Resets */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN         0x004302a8 /* Powerdowns */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL       0x004302ac /* Miscellaneous Controls */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV           0x004302b0 /* Pre multiplier */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN          0x004302b4 /* PLL GAIN */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW 0x004302b8 /* Lower bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH 0x004302bc /* Higher bits of Spread Spectrum mode control */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS   0x004302c0 /* Lock Status */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS        0x004302c4 /* Test Status */
#define BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY 0x004302c8 /* Avd1 top inst power switch memory */
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK  0x004302cc /* Uhfr top inst observe clock */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE   0x004302d0 /* Core xpt inst clock enable */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC 0x004302d4 /* Vec aio top inst clock enable vec */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE  0x004302dc /* Disable SYS_CTRL_INST's clocks */
#define BCHP_CLKGEN_PAD_MUX_SELECT               0x004302e0 /* Mux selects for Pad clocks */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE    0x004302e4 /* Disable DVP_HT_INST's clocks */
#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE 0x004302e8 /* Core xpt inst memory standby enable */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE  0x004302ec /* Disable ZCPU_TOP_INST's clocks */
#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY 0x004302f0 /* Sys ctrl inst power switch memory */
#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE 0x004302f4 /* Uhfr top inst memory standby enable */
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE      0x004302f8 /* Disable USB0_INST's clocks */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE            0x004302fc /* Disable PAD's clocks */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT         0x00430300 /* Mux selects for Smartcard clocks */
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE   0x00430304 /* Uhfr top inst clock enable */
#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE 0x0043030c /* Hif inst memory standby enable */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE  0x00430310 /* Disable CORE_XPT_INST's clocks */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT          0x00430314 /* Mux selects for Internal clocks */
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK  0x00430318 /* Moca top inst observe clock */
#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE 0x0043031c /* Graphics inst memory standby enable */
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK  0x00430320 /* Sys ctrl inst observe clock */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE 0x00430324 /* Disable VEC_AIO_TOP_INST's clocks */
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE  0x00430328 /* Disable UHFR_TOP_INST's clocks */
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION        0x0043032c /* Select observation clk */
#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE 0x00430330 /* Disable GRAPHICS_INST's m2mc clock */
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE      0x00430334 /* Disable USB1_INST's clocks */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE 0x00430338 /* Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE       0x0043033c /* Hif inst clock disable */
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE       0x00430340 /* Usb0 inst clock enable */
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE      0x00430344 /* Vice2 inst clock enable */
#define BCHP_CLKGEN_SCRATCH0                     0x00430348 /* clkgen  Scratch register */
#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE 0x0043034c /* Usb1 inst memory standby enable */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B 0x00430350 /* Dual genet top dual rgmii inst power switch memory b */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE 0x00430354 /* Memsys 32 0 inst clock enable */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY 0x00430358 /* Memsys 32 1 inst power switch memory */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE   0x0043035c /* Svd0 top inst clock enable */
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK      0x00430360 /* Usb0 inst observe clock */
#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY 0x00430364 /* Core xpt inst power switch memory */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK 0x00430368 /* Vec aio top inst observe clock */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A 0x0043036c /* Dual genet top dual rgmii inst memory standby enable a */
#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY 0x00430370 /* Vice2 inst power switch memory */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK    0x00430374 /* Dvp hr inst observe clock */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT  0x00430378 /* Sata3 top inst clock select */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY 0x0043037c /* Raaga dsp top inst power switch memory */
#define BCHP_CLKGEN_AVD1_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430380 /* Avd0 top inst memory standby enable */
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK      0x00430384 /* Usb1 inst observe clock */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK 0x00430388 /* Memsys 32 1 inst observe clock */
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE 0x0043038c /* BVN_MCVP_TOP inst memory standby enable */
#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY 0x00430390 /* Moca top inst power switch memory */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK 0x00430394 /* Memsys 32 0 inst observe clock */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430398 /* Raaga dsp top inst memory standby enable */
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE 0x0043039c /* BVN_MCVP_TOP inst clock enable */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY 0x004303a0 /* Memsys 32 0 inst power switch memory */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE 0x004303a4 /* Memsys 32 0 inst memory standby enable */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE 0x004303a8 /* Memsys 32 1 inst clock enable */
#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE 0x004303ac /* Sata3 top inst memory standby enable */
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK  0x004303b0 /* Zcpu top inst observe clock */
#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE 0x004303b4 /* V3D_TOP inst memory standby enable */
#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY 0x004303b8 /* Dvp hr inst power switch memory */
#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY 0x004303bc /* Usb1 inst power switch memory */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK 0x004303c0 /* Dual genet top dual rgmii inst observe clock */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE     0x004303c4 /* Dvp ht inst clock enable */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE   0x004303c8 /* Graphics inst clock enable */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK  0x004303cc /* Graphics inst observe clock */
#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY 0x004303d0 /* Bvn top inst power switch memory */
#define BCHP_CLKGEN_TESTPORT                     0x004303d4 /* Special Testport Controls */
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION   0x004303d8 /* Select observation clk */
#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION  0x004303dc /* Select observation clk */
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL       0x004303e0 /* Select clocks that can stay alive during power management standby mode. */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO 0x004303e4 /* Vec aio top inst clock enable aio */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE 0x004303e8 /* Vec aio top inst clock enable */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK    0x004303ec /* Sectop inst observe clock */
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE   0x004303f0 /* Avd0 top inst clock enable */
#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE 0x004303f4 /* Dvp ht inst memory standby enable */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE  0x004303f8 /* Sata3 top inst clock enable */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE    0x004303fc /* Bvn top inst clock enable */
#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK  0x00430400 /* Avd0 top inst observe clock */
#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY 0x00430404 /* Usb0 inst power switch memory */
#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY 0x00430408 /* Graphics inst power switch memory */
#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE 0x0043040c /* Vice2 inst memory standby enable */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK  0x00430410 /* Core xpt inst observe clock */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO 0x00430414 /* Vec aio top inst memory standby enable aio */
#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE 0x00430418 /* Sys ctrl inst memory standby enable */
#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY 0x0043041c /* Hif inst power switch memory */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE 0x00430420 /* Memsys 32 1 inst memory standby enable */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO 0x00430424 /* Vec aio top inst power switch memory aio */
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK       0x00430428 /* Hif inst observe clock */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE    0x0043042c /* V3D_TOP inst clock enable */
#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430430 /* Moca top inst memory standby enable */
#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY 0x00430434 /* Svd0 top inst power switch memory */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT 0x00430438 /* Dual genet top dual rgmii inst clock select */
#define BCHP_CLKGEN_ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE 0x0043043c /* Zcpu top inst memory standby enable */
#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY 0x00430440 /* Uhfr top inst power switch memory */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC 0x00430444 /* Vec aio top inst power switch memory vec */
#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE 0x00430448 /* Dvp hr inst memory standby enable */
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK 0x0043044c /* Sata3 top inst observe clock */
#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE 0x00430450 /* Usb0 inst memory standby enable */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC 0x00430454 /* Vec aio top inst memory standby enable vec */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE     0x00430458 /* Dvp hr inst clock enable */
#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY 0x0043045c /* Dvp ht inst power switch memory */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE 0x00430460 /* Dual genet top dual rgmii inst clock enable */
#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY 0x00430464 /* Sata3 top inst power switch memory */
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE   0x00430468 /* Moca top inst clock enable */
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY 0x0043046c /* BVN_MCVP_TOP inst power switch memory */
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK   0x00430470 /* Sys aon inst observe clock */
#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430474 /* Bvn top inst memory standby enable */
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION       0x00430478 /* Select observation clk */
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE       0x0043047c /* Usb1 inst clock enable */
#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE 0x00430480 /* Svd0 top inst memory standby enable */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A 0x00430484 /* Dual genet top dual rgmii inst power switch memory a */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK    0x00430488 /* Dvp ht inst observe clock */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA 0x0043048c /* Sectop inst clock enable */
#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE 0x00430490 /* Sectop inst memory standby enable */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE   0x00430494 /* Zcpu top inst clock enable */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE 0x00430498 /* Raaga dsp top inst clock enable */
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS    0x0043049c /* Resets status */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS  0x004304a0 /* Resets status */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS  0x004304a4 /* Resets status */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS  0x004304a8 /* Resets status */
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS    0x004304ac /* Resets status */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS   0x004304b0 /* Resets status */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS    0x004304b4 /* Resets status */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS   0x004304b8 /* Resets status */
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS     0x004304bc /* Resets status */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS   0x004304c0 /* Resets status */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS 0x004304c4 /* Resets status */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS   0x004304c8 /* Resets status */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS      0x004304cc /* Resets status */
#define BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT 0x004304d0 /* Memsys_0 32 power management */
#define BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT 0x004304d4 /* Memsys_1 32 power management */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x004304d8 /* pll alive in standby mode */
#define BCHP_CLKGEN_SPI_CLOCK_SELECT             0x004304dc /* spi clock control */
#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS      0x004304e0 /* Lock Status */
#define BCHP_CLKGEN_PLL_MIPS_CTRL                0x004304e4 /* Mips PLL Control Register */
#define BCHP_CLKGEN_SCRATCH1                     0x004304e8 /* clkgen  Scratch register */
#define BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE 0x004304ec /* V3d_top inst V3D clock enable */
#define BCHP_CLKGEN_SCRATCH2                     0x004304f4 /* clkgen  Scratch register */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1 0x004304f8 /* PLL CHANNEL control CH 1 */
#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE     0x00430504 /* Disable SATA3_TOP_INST's clocks */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK 0x00430508 /* Raaga Dsp top inst observe clock */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL        0x0043050c /* Clock Monitor Control */
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT      0x00430510 /* Clock Monitor Max Reference Count */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER    0x00430514 /* Clock Monitor Reference Counter */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE       0x00430518 /* Clock Monitor Reference Counter */
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER   0x0043051c /* Clock Monitor View Counter */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP           0x00430520 /* Power management LDO PLL */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM        0x00430524 /* Power management LDO PLL state machine */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS 0x00430528 /* Bypass GENET_TOP_DUAL_RGMII_INST's cl;ocks */

/***************************************************************************
 *PLL_MIPS_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_reserved0_SHIFT           1

/* CLKGEN :: PLL_MIPS_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_SHIFT             0
#define BCHP_CLKGEN_PLL_MIPS_PLL_CONTROL_REF_SEL_DEFAULT           0

/***************************************************************************
 *PLL_MIPS_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_DIV :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_MASK                0xfffffff8
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_reserved0_SHIFT               3

/* CLKGEN :: PLL_MIPS_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_MASK                     0x00000007
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_SHIFT                    0
#define BCHP_CLKGEN_PLL_MIPS_PLL_DIV_PDIV_DEFAULT                  3

/***************************************************************************
 *PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:06] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 6

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_MIPS_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_MIPS_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_MASK               0xff000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_reserved0_SHIFT              24

/* CLKGEN :: PLL_MIPS_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6

/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_MIPS_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
#define BCHP_CLKGEN_PLL_MIPS_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2

/***************************************************************************
 *PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_MIPS_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_MIPS_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_MASK               0x80000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_reserved0_SHIFT              31

/* CLKGEN :: PLL_MIPS_PLL_MISC :: LDO_REF_SEL [30:30] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_SHIFT            30
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_LDO_REF_SEL_DEFAULT          0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: POR_BYPASS [29:29] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_MASK              0x20000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_SHIFT             29
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_POR_BYPASS_DEFAULT           0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: NDIV_RELOCK [28:28] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_SHIFT            28
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_NDIV_RELOCK_DEFAULT          0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: FAST_LOCK [27:27] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_MASK               0x08000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_SHIFT              27
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_FAST_LOCK_DEFAULT            0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCODIV2 [26:26] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_MASK                 0x04000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_SHIFT                26
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCODIV2_DEFAULT              0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: VCO_DLY [25:24] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_MASK                 0x03000000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_SHIFT                24
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_VCO_DLY_DEFAULT              0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: PWM_RATE [23:22] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_MASK                0x00c00000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_SHIFT               22
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_PWM_RATE_DEFAULT             0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_MODE [21:20] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_MASK               0x00300000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_SHIFT              20
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_MODE_DEFAULT            0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: AUX_CTRL [19:19] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_MASK                0x00080000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_SHIFT               19
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_AUX_CTRL_DEFAULT             0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_MASK               0x00040000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_SHIFT              18
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_REFCLKOUT_DEFAULT            0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_UPDATE [17:17] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_MASK             0x00020000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_SHIFT            17
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_UPDATE_DEFAULT          0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_SELECT [16:14] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_MASK             0x0001c000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_SHIFT            14
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_SELECT_DEFAULT          0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: STAT_RESET_ [13:13] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__MASK             0x00002000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__SHIFT            13
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_STAT_RESET__DEFAULT          0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_MIPS_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0

/***************************************************************************
 *PLL_MIPS_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_reserved0_SHIFT             1

/* CLKGEN :: PLL_MIPS_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_SHIFT                 0
#define BCHP_CLKGEN_PLL_MIPS_PLL_MISC2_SPARE_DEFAULT               0

/***************************************************************************
 *PLL_MIPS_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK [01:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_SHIFT            1

/* CLKGEN :: PLL_MIPS_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0

/***************************************************************************
 *PLL_MIPS_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_MIPS_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_MIPS_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_AVD1_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_reserved0_SHIFT             2

/* CLKGEN :: PLL_AVD1_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETD_MASK                 0x00000002
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETD_SHIFT                1
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETD_DEFAULT              0

/* CLKGEN :: PLL_AVD1_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETA_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETA_SHIFT                0
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_RESETA_DEFAULT              0

/***************************************************************************
 *PLL_AVD1_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_reserved0_SHIFT             1

/* CLKGEN :: PLL_AVD1_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_PWRDN_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_AVD1_PLL_PWRDN_PWRDN_PLL_DEFAULT           0

/***************************************************************************
 *PLL_AVD1_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_reserved0_SHIFT           1

/* CLKGEN :: PLL_AVD1_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_REF_SEL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_REF_SEL_SHIFT             0
#define BCHP_CLKGEN_PLL_AVD1_PLL_CONTROL_REF_SEL_DEFAULT           0

/***************************************************************************
 *PLL_AVD1_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_reserved0_MASK                0xffffe000
#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_reserved0_SHIFT               13

/* CLKGEN :: PLL_AVD1_PLL_DIV :: NDIV_INT [12:03] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_NDIV_INT_MASK                 0x00001ff8
#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_NDIV_INT_SHIFT                3
#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_NDIV_INT_DEFAULT              164

/* CLKGEN :: PLL_AVD1_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_PDIV_MASK                     0x00000007
#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_PDIV_SHIFT                    0
#define BCHP_CLKGEN_PLL_AVD1_PLL_DIV_PDIV_DEFAULT                  3

/***************************************************************************
 *PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  6
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 7

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 9

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 7

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD1_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0

/***************************************************************************
 *PLL_AVD1_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_reserved0_MASK               0xff000000
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_reserved0_SHIFT              24

/* CLKGEN :: PLL_AVD1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6

/* CLKGEN :: PLL_AVD1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_AVD1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
#define BCHP_CLKGEN_PLL_AVD1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2

/***************************************************************************
 *PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AVD1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_AVD1_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_reserved0_MASK               0x80000000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_reserved0_SHIFT              31

/* CLKGEN :: PLL_AVD1_PLL_MISC :: LDO_REF_SEL [30:30] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_LDO_REF_SEL_SHIFT            30
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_LDO_REF_SEL_DEFAULT          0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: POR_BYPASS [29:29] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_POR_BYPASS_MASK              0x20000000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_POR_BYPASS_SHIFT             29
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_POR_BYPASS_DEFAULT           0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: NDIV_RELOCK [28:28] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_NDIV_RELOCK_SHIFT            28
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_NDIV_RELOCK_DEFAULT          0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: FAST_LOCK [27:27] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_FAST_LOCK_MASK               0x08000000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_FAST_LOCK_SHIFT              27
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_FAST_LOCK_DEFAULT            0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: VCODIV2 [26:26] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCODIV2_MASK                 0x04000000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCODIV2_SHIFT                26
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCODIV2_DEFAULT              0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: VCO_DLY [25:24] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCO_DLY_MASK                 0x03000000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCO_DLY_SHIFT                24
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_VCO_DLY_DEFAULT              0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: PWM_RATE [23:22] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_PWM_RATE_MASK                0x00c00000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_PWM_RATE_SHIFT               22
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_PWM_RATE_DEFAULT             0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_MODE [21:20] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_MODE_MASK               0x00300000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_MODE_SHIFT              20
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_MODE_DEFAULT            0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: AUX_CTRL [19:19] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_AUX_CTRL_MASK                0x00080000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_AUX_CTRL_SHIFT               19
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_AUX_CTRL_DEFAULT             0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_REFCLKOUT_MASK               0x00040000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_REFCLKOUT_SHIFT              18
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_REFCLKOUT_DEFAULT            0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_UPDATE [17:17] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_UPDATE_MASK             0x00020000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_UPDATE_SHIFT            17
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_UPDATE_DEFAULT          0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_SELECT [16:14] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_SELECT_MASK             0x0001c000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_SELECT_SHIFT            14
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_SELECT_DEFAULT          0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: STAT_RESET_ [13:13] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_RESET__MASK             0x00002000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_RESET__SHIFT            13
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_STAT_RESET__DEFAULT          0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_AVD1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0

/***************************************************************************
 *PLL_AVD1_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_reserved0_SHIFT             1

/* CLKGEN :: PLL_AVD1_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_SPARE_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_SPARE_SHIFT                 0
#define BCHP_CLKGEN_PLL_AVD1_PLL_MISC2_SPARE_DEFAULT               0

/***************************************************************************
 *PLL_AVD1_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_AVD1_PLL_LOCK_STATUS :: LOCK [01:01] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_SHIFT            1

/* CLKGEN :: PLL_AVD1_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
#define BCHP_CLKGEN_PLL_AVD1_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0

/***************************************************************************
 *PLL_AVD1_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_AVD1_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_AVD1_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_VCXO2_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETD_DEFAULT             0

/* CLKGEN :: PLL_VCXO2_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_RESETA_DEFAULT             0

/***************************************************************************
 *PLL_VCXO2_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_reserved0_SHIFT            1

/* CLKGEN :: PLL_VCXO2_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_PWRDN_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_PWRDN_PWRDN_PLL_DEFAULT          0

/***************************************************************************
 *PLL_VCXO2_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_reserved0_SHIFT          1

/* CLKGEN :: PLL_VCXO2_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_REF_SEL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_REF_SEL_SHIFT            0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CONTROL_REF_SEL_DEFAULT          0

/***************************************************************************
 *PLL_VCXO2_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_MASK               0xffffe000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_reserved0_SHIFT              13

/* CLKGEN :: PLL_VCXO2_PLL_DIV :: NDIV_INT [12:03] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_MASK                0x00001ff8
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_SHIFT               3
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_NDIV_INT_DEFAULT             64

/* CLKGEN :: PLL_VCXO2_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_MASK                    0x00000007
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_SHIFT                   0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_DIV_PDIV_DEFAULT                 2

/***************************************************************************
 *PLL_VCXO2_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_MASK              0xfff00000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_reserved0_SHIFT             20

/* CLKGEN :: PLL_VCXO2_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_FRAC_FRAC_CONTROL_DEFAULT        0

/***************************************************************************
 *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x00003fc0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 64

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x00003fc0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 250

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x00003fc0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 75

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_VCXO2_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_MASK              0xff000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_reserved0_SHIFT             24

/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8

/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_VCXO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000007
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   1

/***************************************************************************
 *PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_VCXO2_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_MISC :: reserved0 [31:30] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_reserved0_MASK              0xc0000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_reserved0_SHIFT             30

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: MDIV_RELOCK [29:29] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_MDIV_RELOCK_MASK            0x20000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_MDIV_RELOCK_SHIFT           29
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_MDIV_RELOCK_DEFAULT         0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: FAST_LOCK [28:28] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_MASK              0x10000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_SHIFT             28
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_FAST_LOCK_DEFAULT           0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCODIV2 [27:27] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_MASK                0x08000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_SHIFT               27
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_DEFAULT             0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCO_DLY [26:25] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DLY_MASK                0x06000000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DLY_SHIFT               25
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCO_DLY_DEFAULT             0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: PWM_RATE [24:23] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_MASK               0x01800000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_SHIFT              23
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_PWM_RATE_DEFAULT            0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_MODE [22:21] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_MASK              0x00600000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_SHIFT             21
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_MODE_DEFAULT           0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: VCODIV2_POST [20:20] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_POST_MASK           0x00100000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_POST_SHIFT          20
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_VCODIV2_POST_DEFAULT        0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: AUX_CTRL [19:19] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_MASK               0x00080000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_SHIFT              19
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_AUX_CTRL_DEFAULT            0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REFCLKOUT_MASK              0x00040000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REFCLKOUT_SHIFT             18
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_REFCLKOUT_DEFAULT           0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_UPDATE [17:17] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_MASK            0x00020000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_SHIFT           17
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_UPDATE_DEFAULT         0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_SELECT [16:14] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_MASK            0x0001c000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_SHIFT           14
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_SELECT_DEFAULT         0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: STAT_RESET_ [13:13] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET__MASK            0x00002000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET__SHIFT           13
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_STAT_RESET__DEFAULT         0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_VCXO2_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0

/***************************************************************************
 *PLL_VCXO2_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_reserved0_SHIFT      1

/* CLKGEN :: PLL_VCXO2_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_LOCK_STATUS_LOCK_SHIFT           0

/***************************************************************************
 *PLL_VCXO2_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_VCXO2_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_VCXO2_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_AUDIO1_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_reserved0_SHIFT           2

/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_MASK               0x00000002
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_SHIFT              1
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETD_DEFAULT            0

/* CLKGEN :: PLL_AUDIO1_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_SHIFT              0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_RESETA_DEFAULT            0

/***************************************************************************
 *PLL_AUDIO1_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_reserved0_SHIFT           1

/* CLKGEN :: PLL_AUDIO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_PWRDN_PWRDN_PLL_DEFAULT         0

/***************************************************************************
 *PLL_AUDIO1_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_reserved0_SHIFT         1

/* CLKGEN :: PLL_AUDIO1_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_CONTROL_REF_SEL_DEFAULT         0

/***************************************************************************
 *PLL_AUDIO1_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_MASK              0xfffffff8
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_reserved0_SHIFT             3

/* CLKGEN :: PLL_AUDIO1_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_MASK                   0x00000007
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_SHIFT                  0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_DIV_PDIV_DEFAULT                1

/***************************************************************************
 *PLL_AUDIO1_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_MASK             0xff000000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_reserved0_SHIFT            24

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_AUDIO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000007
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1

/***************************************************************************
 *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO1_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_reserved0_SHIFT     1

/* CLKGEN :: PLL_AUDIO1_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_LOCK_STATUS_LOCK_SHIFT          0

/***************************************************************************
 *PLL_AUDIO1_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_MASK           0xfffff000
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_reserved0_SHIFT          12

/* CLKGEN :: PLL_AUDIO1_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_STATUS_TEST_STATUS_SHIFT        0

/***************************************************************************
 *PLL_VCXO1_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETD_DEFAULT             0

/* CLKGEN :: PLL_VCXO1_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_RESETA_DEFAULT             0

/***************************************************************************
 *PLL_VCXO1_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_reserved0_SHIFT            1

/* CLKGEN :: PLL_VCXO1_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_PWRDN_PWRDN_PLL_DEFAULT          0

/***************************************************************************
 *PLL_VCXO1_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_reserved0_SHIFT          1

/* CLKGEN :: PLL_VCXO1_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_SHIFT            0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CONTROL_REF_SEL_DEFAULT          0

/***************************************************************************
 *PLL_VCXO1_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_MASK               0xffffe000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_reserved0_SHIFT              13

/* CLKGEN :: PLL_VCXO1_PLL_DIV :: NDIV_INT [12:03] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_MASK                0x00001ff8
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_SHIFT               3
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_NDIV_INT_DEFAULT             64

/* CLKGEN :: PLL_VCXO1_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_MASK                    0x00000007
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_SHIFT                   0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_DIV_PDIV_DEFAULT                 2

/***************************************************************************
 *PLL_VCXO1_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_MASK              0xfff00000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_reserved0_SHIFT             20

/* CLKGEN :: PLL_VCXO1_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_FRAC_FRAC_CONTROL_DEFAULT        0

/***************************************************************************
 *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x00003fc0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 64

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x00003fc0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 250

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x00003fc0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 75

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_VCXO1_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_MASK              0xff000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_reserved0_SHIFT             24

/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8

/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_VCXO1_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000007
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   1

/***************************************************************************
 *PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_VCXO1_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_MISC :: reserved0 [31:30] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_reserved0_MASK              0xc0000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_reserved0_SHIFT             30

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: MDIV_RELOCK [29:29] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_MASK            0x20000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_SHIFT           29
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_MDIV_RELOCK_DEFAULT         0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: FAST_LOCK [28:28] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_MASK              0x10000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_SHIFT             28
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_FAST_LOCK_DEFAULT           0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCODIV2 [27:27] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_MASK                0x08000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_SHIFT               27
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_DEFAULT             0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCO_DLY [26:25] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_MASK                0x06000000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_SHIFT               25
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCO_DLY_DEFAULT             0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: PWM_RATE [24:23] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_MASK               0x01800000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_SHIFT              23
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_PWM_RATE_DEFAULT            0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_MODE [22:21] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_MASK              0x00600000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_SHIFT             21
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_MODE_DEFAULT           0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: VCODIV2_POST [20:20] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_MASK           0x00100000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_SHIFT          20
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_VCODIV2_POST_DEFAULT        0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: AUX_CTRL [19:19] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_MASK               0x00080000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_SHIFT              19
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_AUX_CTRL_DEFAULT            0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_MASK              0x00040000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_SHIFT             18
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_REFCLKOUT_DEFAULT           0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_UPDATE [17:17] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_MASK            0x00020000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_SHIFT           17
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_UPDATE_DEFAULT         0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_SELECT [16:14] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_MASK            0x0001c000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_SHIFT           14
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_SELECT_DEFAULT         0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: STAT_RESET_ [13:13] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__MASK            0x00002000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__SHIFT           13
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_STAT_RESET__DEFAULT         0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_VCXO1_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0

/***************************************************************************
 *PLL_VCXO1_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_reserved0_SHIFT      1

/* CLKGEN :: PLL_VCXO1_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_LOCK_STATUS_LOCK_SHIFT           0

/***************************************************************************
 *PLL_VCXO1_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_VCXO1_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_VCXO1_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_AUDIO2_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_reserved0_SHIFT           2

/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_MASK               0x00000002
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_SHIFT              1
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETD_DEFAULT            0

/* CLKGEN :: PLL_AUDIO2_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_SHIFT              0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_RESETA_DEFAULT            0

/***************************************************************************
 *PLL_AUDIO2_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_reserved0_SHIFT           1

/* CLKGEN :: PLL_AUDIO2_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_PWRDN_PLL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_PWRDN_PWRDN_PLL_DEFAULT         0

/***************************************************************************
 *PLL_AUDIO2_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_reserved0_SHIFT         1

/* CLKGEN :: PLL_AUDIO2_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_REF_SEL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_REF_SEL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_CONTROL_REF_SEL_DEFAULT         0

/***************************************************************************
 *PLL_AUDIO2_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_DIV :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_MASK              0xfffffff8
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_reserved0_SHIFT             3

/* CLKGEN :: PLL_AUDIO2_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_MASK                   0x00000007
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_SHIFT                  0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_DIV_PDIV_DEFAULT                1

/***************************************************************************
 *PLL_AUDIO2_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_MASK             0xff000000
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_reserved0_SHIFT            24

/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7

/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_AUDIO2_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000007
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1

/***************************************************************************
 *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO2_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_reserved0_SHIFT     1

/* CLKGEN :: PLL_AUDIO2_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_LOCK_STATUS_LOCK_SHIFT          0

/***************************************************************************
 *PLL_AUDIO2_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_MASK           0xfffff000
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_reserved0_SHIFT          12

/* CLKGEN :: PLL_AUDIO2_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_STATUS_TEST_STATUS_SHIFT        0

/***************************************************************************
 *PLL_HIF_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_HIF_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_reserved0_SHIFT              2

/* CLKGEN :: PLL_HIF_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETD_MASK                  0x00000002
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETD_SHIFT                 1
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETD_DEFAULT               0

/* CLKGEN :: PLL_HIF_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETA_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETA_SHIFT                 0
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_RESETA_DEFAULT               0

/***************************************************************************
 *PLL_HIF_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_HIF_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_reserved0_MASK               0xfffffffe
#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_reserved0_SHIFT              1

/* CLKGEN :: PLL_HIF_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_PWRDN_PLL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_PWRDN_PLL_SHIFT              0
#define BCHP_CLKGEN_PLL_HIF_PLL_PWRDN_PWRDN_PLL_DEFAULT            0

/***************************************************************************
 *PLL_HIF_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_HIF_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_reserved0_SHIFT            1

/* CLKGEN :: PLL_HIF_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_REF_SEL_MASK               0x00000001
#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_REF_SEL_SHIFT              0
#define BCHP_CLKGEN_PLL_HIF_PLL_CONTROL_REF_SEL_DEFAULT            0

/***************************************************************************
 *PLL_HIF_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_HIF_PLL_DIV :: reserved0 [31:11] */
#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_reserved0_MASK                 0xfffff800
#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_reserved0_SHIFT                11

/* CLKGEN :: PLL_HIF_PLL_DIV :: NDIV_INT [10:03] */
#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_NDIV_INT_MASK                  0x000007f8
#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_NDIV_INT_SHIFT                 3
#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_NDIV_INT_DEFAULT               50

/* CLKGEN :: PLL_HIF_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_PDIV_MASK                      0x00000007
#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_PDIV_SHIFT                     0
#define BCHP_CLKGEN_PLL_HIF_PLL_DIV_PDIV_DEFAULT                   1

/***************************************************************************
 *PLL_HIF_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:15] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK   0xffff8000
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT  15

/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: CML_CLOCK_EN_CH0 [14:14] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CML_CLOCK_EN_CH0_MASK 0x00004000
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CML_CLOCK_EN_CH0_SHIFT 14
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CML_CLOCK_EN_CH0_DEFAULT 1

/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK    0x00003fc0
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT   6
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 27

/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_HIF_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:15] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK   0xffff8000
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT  15

/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: CML_CLOCK_EN_CH1 [14:14] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_CML_CLOCK_EN_CH1_MASK 0x00004000
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_CML_CLOCK_EN_CH1_SHIFT 14
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_CML_CLOCK_EN_CH1_DEFAULT 1

/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK    0x00003fc0
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT   6
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 103

/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_HIF_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_HIF_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_HIF_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_HIF_PLL_GAIN :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_reserved0_MASK                0xfffffc00
#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_reserved0_SHIFT               10

/* CLKGEN :: PLL_HIF_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8

/* CLKGEN :: PLL_HIF_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3

/* CLKGEN :: PLL_HIF_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK        0x00000007
#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT       0
#define BCHP_CLKGEN_PLL_HIF_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT     3

/***************************************************************************
 *PLL_HIF_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_HIF_PLL_MISC :: reserved0 [31:28] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_reserved0_MASK                0xf0000000
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_reserved0_SHIFT               28

/* CLKGEN :: PLL_HIF_PLL_MISC :: DIGITAL_LDO_CONTROL [27:26] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DIGITAL_LDO_CONTROL_MASK      0x0c000000
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DIGITAL_LDO_CONTROL_SHIFT     26
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DIGITAL_LDO_CONTROL_DEFAULT   1

/* CLKGEN :: PLL_HIF_PLL_MISC :: ANALOG_LDO_CONTROL [25:24] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_ANALOG_LDO_CONTROL_MASK       0x03000000
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_ANALOG_LDO_CONTROL_SHIFT      24
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_ANALOG_LDO_CONTROL_DEFAULT    1

/* CLKGEN :: PLL_HIF_PLL_MISC :: LDO_CONTROL [23:22] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_LDO_CONTROL_MASK              0x00c00000
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_LDO_CONTROL_SHIFT             22
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_LDO_CONTROL_DEFAULT           1

/* CLKGEN :: PLL_HIF_PLL_MISC :: HYST_EN [21:21] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_HYST_EN_MASK                  0x00200000
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_HYST_EN_SHIFT                 21
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_HYST_EN_DEFAULT               0

/* CLKGEN :: PLL_HIF_PLL_MISC :: VCODIV2 [20:20] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_VCODIV2_MASK                  0x00100000
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_VCODIV2_SHIFT                 20
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_VCODIV2_DEFAULT               0

/* CLKGEN :: PLL_HIF_PLL_MISC :: AUX_CTRL [19:19] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_AUX_CTRL_MASK                 0x00080000
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_AUX_CTRL_SHIFT                19
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_AUX_CTRL_DEFAULT              0

/* CLKGEN :: PLL_HIF_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_REFCLKOUT_MASK                0x00040000
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_REFCLKOUT_SHIFT               18
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_REFCLKOUT_DEFAULT             0

/* CLKGEN :: PLL_HIF_PLL_MISC :: STAT_UPDATE [17:17] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_UPDATE_MASK              0x00020000
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_UPDATE_SHIFT             17
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_UPDATE_DEFAULT           0

/* CLKGEN :: PLL_HIF_PLL_MISC :: STAT_SELECT [16:14] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_SELECT_MASK              0x0001c000
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_SELECT_SHIFT             14
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_SELECT_DEFAULT           0

/* CLKGEN :: PLL_HIF_PLL_MISC :: STAT_RESET_ [13:13] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_RESET__MASK              0x00002000
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_RESET__SHIFT             13
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_STAT_RESET__DEFAULT           0

/* CLKGEN :: PLL_HIF_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK   0x00001000
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT  12
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_HIF_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_SHIFT         0
#define BCHP_CLKGEN_PLL_HIF_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT       0

/***************************************************************************
 *PLL_HIF_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_HIF_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_reserved0_SHIFT        1

/* CLKGEN :: PLL_HIF_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_LOCK_MASK              0x00000001
#define BCHP_CLKGEN_PLL_HIF_PLL_LOCK_STATUS_LOCK_SHIFT             0

/***************************************************************************
 *PLL_HIF_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_HIF_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_reserved0_MASK              0xfffff000
#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_reserved0_SHIFT             12

/* CLKGEN :: PLL_HIF_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_TEST_STATUS_MASK            0x00000fff
#define BCHP_CLKGEN_PLL_HIF_PLL_STATUS_TEST_STATUS_SHIFT           0

/***************************************************************************
 *PLL_HIF_PLL_TRI_EN - Cml buffer Tristate enable
 ***************************************************************************/
/* CLKGEN :: PLL_HIF_PLL_TRI_EN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_reserved0_SHIFT             1

/* CLKGEN :: PLL_HIF_PLL_TRI_EN :: TRI_EN [00:00] */
#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_TRI_EN_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_TRI_EN_SHIFT                0
#define BCHP_CLKGEN_PLL_HIF_PLL_TRI_EN_TRI_EN_DEFAULT              0

/***************************************************************************
 *PLL_MOCA_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_reserved0_SHIFT             2

/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_MASK                 0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_SHIFT                1
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETD_DEFAULT              0

/* CLKGEN :: PLL_MOCA_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_SHIFT                0
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_RESETA_DEFAULT              0

/***************************************************************************
 *PLL_MOCA_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_reserved0_SHIFT             1

/* CLKGEN :: PLL_MOCA_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_SHIFT             0
#define BCHP_CLKGEN_PLL_MOCA_PLL_PWRDN_PWRDN_PLL_DEFAULT           0

/***************************************************************************
 *PLL_MOCA_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_reserved0_SHIFT           1

/* CLKGEN :: PLL_MOCA_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_SHIFT             0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CONTROL_REF_SEL_DEFAULT           0

/***************************************************************************
 *PLL_MOCA_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_MASK                0xffffe000
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_reserved0_SHIFT               13

/* CLKGEN :: PLL_MOCA_PLL_DIV :: NDIV_INT [12:03] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_MASK                 0x00001ff8
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_SHIFT                3
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_NDIV_INT_DEFAULT              200

/* CLKGEN :: PLL_MOCA_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_MASK                     0x00000007
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_SHIFT                    0
#define BCHP_CLKGEN_PLL_MOCA_PLL_DIV_PDIV_DEFAULT                  3

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT  6
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 12

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 36

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 72

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [13:06] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  6
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 36

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [05:05] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00000020
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 5
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [04:04] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000010
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 4
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [03:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [13:06] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  6
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 72

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [05:05] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00000020
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 5
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [04:04] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000010
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 4
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [03:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 1
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_MASK               0xff000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_reserved0_SHIFT              24

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 3

/* CLKGEN :: PLL_MOCA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
#define BCHP_CLKGEN_PLL_MOCA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    2

/***************************************************************************
 *PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_MOCA_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_MASK               0x80000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_reserved0_SHIFT              31

/* CLKGEN :: PLL_MOCA_PLL_MISC :: LDO_REF_SEL [30:30] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_SHIFT            30
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_LDO_REF_SEL_DEFAULT          0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: POR_BYPASS [29:29] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_MASK              0x20000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_SHIFT             29
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_POR_BYPASS_DEFAULT           0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: NDIV_RELOCK [28:28] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_SHIFT            28
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_NDIV_RELOCK_DEFAULT          0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: FAST_LOCK [27:27] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_MASK               0x08000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_SHIFT              27
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_FAST_LOCK_DEFAULT            0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCODIV2 [26:26] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_MASK                 0x04000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_SHIFT                26
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCODIV2_DEFAULT              1

/* CLKGEN :: PLL_MOCA_PLL_MISC :: VCO_DLY [25:24] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_MASK                 0x03000000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_SHIFT                24
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_VCO_DLY_DEFAULT              0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: PWM_RATE [23:22] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_MASK                0x00c00000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_SHIFT               22
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_PWM_RATE_DEFAULT             2

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_MODE [21:20] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_MASK               0x00300000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_SHIFT              20
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_MODE_DEFAULT            0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: AUX_CTRL [19:19] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_MASK                0x00080000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_SHIFT               19
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_AUX_CTRL_DEFAULT             0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_MASK               0x00040000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_SHIFT              18
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_REFCLKOUT_DEFAULT            0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_UPDATE [17:17] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_MASK             0x00020000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_SHIFT            17
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_UPDATE_DEFAULT          0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_SELECT [16:14] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_MASK             0x0001c000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_SHIFT            14
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_SELECT_DEFAULT          0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: STAT_RESET_ [13:13] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__MASK             0x00002000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__SHIFT            13
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_STAT_RESET__DEFAULT          0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_MOCA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0

/***************************************************************************
 *PLL_MOCA_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_reserved0_SHIFT             1

/* CLKGEN :: PLL_MOCA_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_SHIFT                 0
#define BCHP_CLKGEN_PLL_MOCA_PLL_MISC2_SPARE_DEFAULT               0

/***************************************************************************
 *PLL_MOCA_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_SHIFT            1

/* CLKGEN :: PLL_MOCA_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0

/***************************************************************************
 *PLL_MOCA_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_MOCA_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_MOCA_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_RAAGA_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETD_DEFAULT             0

/* CLKGEN :: PLL_RAAGA_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_RESETA_DEFAULT             0

/***************************************************************************
 *PLL_RAAGA_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_reserved0_SHIFT            1

/* CLKGEN :: PLL_RAAGA_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_PWRDN_PWRDN_PLL_DEFAULT          0

/***************************************************************************
 *PLL_RAAGA_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_reserved0_SHIFT          1

/* CLKGEN :: PLL_RAAGA_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_SHIFT            0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CONTROL_REF_SEL_DEFAULT          0

/***************************************************************************
 *PLL_RAAGA_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_MASK               0xffffe000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_reserved0_SHIFT              13

/* CLKGEN :: PLL_RAAGA_PLL_DIV :: NDIV_INT [12:03] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_MASK                0x00001ff8
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_SHIFT               3
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_NDIV_INT_DEFAULT             143

/* CLKGEN :: PLL_RAAGA_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_MASK                    0x00000007
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_SHIFT                   0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_DIV_PDIV_DEFAULT                 2

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x00003fc0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 11

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x00003fc0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 7

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_RAAGA_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_MASK              0xff000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_reserved0_SHIFT             24

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 9

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4

/* CLKGEN :: PLL_RAAGA_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000007
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   2

/***************************************************************************
 *PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_RAAGA_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_MASK              0x80000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_reserved0_SHIFT             31

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: LDO_REF_SEL [30:30] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_MASK            0x40000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_SHIFT           30
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_LDO_REF_SEL_DEFAULT         0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: POR_BYPASS [29:29] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_MASK             0x20000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_SHIFT            29
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_POR_BYPASS_DEFAULT          0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: NDIV_RELOCK [28:28] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_MASK            0x10000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_SHIFT           28
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_NDIV_RELOCK_DEFAULT         0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: FAST_LOCK [27:27] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_MASK              0x08000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_SHIFT             27
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_FAST_LOCK_DEFAULT           0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCODIV2 [26:26] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_MASK                0x04000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_SHIFT               26
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCODIV2_DEFAULT             1

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: VCO_DLY [25:24] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_MASK                0x03000000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_SHIFT               24
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_VCO_DLY_DEFAULT             0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: PWM_RATE [23:22] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_MASK               0x00c00000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_SHIFT              22
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_PWM_RATE_DEFAULT            2

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_MODE [21:20] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_MASK              0x00300000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_SHIFT             20
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_MODE_DEFAULT           0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: AUX_CTRL [19:19] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_MASK               0x00080000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_SHIFT              19
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_AUX_CTRL_DEFAULT            0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_MASK              0x00040000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_SHIFT             18
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_REFCLKOUT_DEFAULT           0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_UPDATE [17:17] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_MASK            0x00020000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_SHIFT           17
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_UPDATE_DEFAULT         0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_SELECT [16:14] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_MASK            0x0001c000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_SHIFT           14
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_SELECT_DEFAULT         0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: STAT_RESET_ [13:13] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__MASK            0x00002000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__SHIFT           13
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_STAT_RESET__DEFAULT         0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_RAAGA_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0

/***************************************************************************
 *PLL_RAAGA_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_reserved0_SHIFT            1

/* CLKGEN :: PLL_RAAGA_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_MASK                 0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_SHIFT                0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_MISC2_SPARE_DEFAULT              0

/***************************************************************************
 *PLL_RAAGA_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_MASK            0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_SHIFT           1

/* CLKGEN :: PLL_RAAGA_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_MASK       0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_LOCK_STATUS_LOCK_LOST_SHIFT      0

/***************************************************************************
 *PLL_RAAGA_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_RAAGA_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_RAAGA_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_NETWORK_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_MASK           0xfffffffc
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_reserved0_SHIFT          2

/* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_MASK              0x00000002
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_SHIFT             1
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETD_DEFAULT           0

/* CLKGEN :: PLL_NETWORK_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_MASK              0x00000001
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_SHIFT             0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_RESETA_DEFAULT           0

/***************************************************************************
 *PLL_NETWORK_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_reserved0_SHIFT          1

/* CLKGEN :: PLL_NETWORK_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_PWRDN_PLL_MASK           0x00000001
#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_PWRDN_PLL_SHIFT          0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_PWRDN_PWRDN_PLL_DEFAULT        0

/***************************************************************************
 *PLL_NETWORK_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_reserved0_MASK         0xfffffffe
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_reserved0_SHIFT        1

/* CLKGEN :: PLL_NETWORK_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_REF_SEL_MASK           0x00000001
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_REF_SEL_SHIFT          0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CONTROL_REF_SEL_DEFAULT        0

/***************************************************************************
 *PLL_NETWORK_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_MASK             0xffffe000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_reserved0_SHIFT            13

/* CLKGEN :: PLL_NETWORK_PLL_DIV :: NDIV_INT [12:03] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_MASK              0x00001ff8
#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_SHIFT             3
#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_NDIV_INT_DEFAULT           125

/* CLKGEN :: PLL_NETWORK_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_MASK                  0x00000007
#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_SHIFT                 0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_DIV_PDIV_DEFAULT               3

/***************************************************************************
 *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK 0x00003fc0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 9

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK 0x00003fc0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 18

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK 0x00003fc0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 90

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_NETWORK_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_MASK            0xff000000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_reserved0_SHIFT           24

/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 6

/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_NETWORK_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK    0x00000007
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT   0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT 2

/***************************************************************************
 *PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_NETWORK_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_reserved0_MASK            0x80000000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_reserved0_SHIFT           31

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: LDO_REF_SEL [30:30] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_LDO_REF_SEL_MASK          0x40000000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_LDO_REF_SEL_SHIFT         30
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_LDO_REF_SEL_DEFAULT       0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: POR_BYPASS [29:29] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POR_BYPASS_MASK           0x20000000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POR_BYPASS_SHIFT          29
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_POR_BYPASS_DEFAULT        0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: NDIV_RELOCK [28:28] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_MASK          0x10000000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_SHIFT         28
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_NDIV_RELOCK_DEFAULT       0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: FAST_LOCK [27:27] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_MASK            0x08000000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_SHIFT           27
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_FAST_LOCK_DEFAULT         0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCODIV2 [26:26] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCODIV2_MASK              0x04000000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCODIV2_SHIFT             26
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCODIV2_DEFAULT           0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: VCO_DLY [25:24] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_DLY_MASK              0x03000000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_DLY_SHIFT             24
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_VCO_DLY_DEFAULT           0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: PWM_RATE [23:22] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_MASK             0x00c00000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_SHIFT            22
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_PWM_RATE_DEFAULT          0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_MODE [21:20] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_MASK            0x00300000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_SHIFT           20
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_MODE_DEFAULT         0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: AUX_CTRL [19:19] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_AUX_CTRL_MASK             0x00080000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_AUX_CTRL_SHIFT            19
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_AUX_CTRL_DEFAULT          0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_REFCLKOUT_MASK            0x00040000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_REFCLKOUT_SHIFT           18
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_REFCLKOUT_DEFAULT         0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_UPDATE [17:17] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_MASK          0x00020000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_SHIFT         17
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_UPDATE_DEFAULT       0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_SELECT [16:14] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_MASK          0x0001c000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_SHIFT         14
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_SELECT_DEFAULT       0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: STAT_RESET_ [13:13] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET__MASK          0x00002000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET__SHIFT         13
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_STAT_RESET__DEFAULT       0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_NETWORK_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_MASK      0x00000fff
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_SHIFT     0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT   0

/***************************************************************************
 *PLL_NETWORK_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_reserved0_SHIFT          1

/* CLKGEN :: PLL_NETWORK_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_SPARE_MASK               0x00000001
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_SPARE_SHIFT              0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_MISC2_SPARE_DEFAULT            0

/***************************************************************************
 *PLL_NETWORK_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_reserved0_SHIFT    2

/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK [01:01] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_MASK          0x00000002
#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_SHIFT         1

/* CLKGEN :: PLL_NETWORK_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_MASK     0x00000001
#define BCHP_CLKGEN_PLL_NETWORK_PLL_LOCK_STATUS_LOCK_LOST_SHIFT    0

/***************************************************************************
 *PLL_NETWORK_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_MASK          0xfffff000
#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_reserved0_SHIFT         12

/* CLKGEN :: PLL_NETWORK_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_MASK        0x00000fff
#define BCHP_CLKGEN_PLL_NETWORK_PLL_STATUS_TEST_STATUS_SHIFT       0

/***************************************************************************
 *VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's vec_dacadc clocks
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE :: DISABLE_VEC_DACADC_CLOCK [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_VEC_DACADC_CLOCK_DISABLE_DISABLE_VEC_DACADC_CLOCK_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_reserved0_SHIFT           1

/* CLKGEN :: PLL_SYS0_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_MASK              0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_SHIFT             0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CONTROL_REF_SEL_DEFAULT           0

/***************************************************************************
 *V3D_TOP_INST_POWER_SWITCH_MEMORY - V3D_TOP inst power switch memory
 ***************************************************************************/
/* CLKGEN :: V3D_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: V3D_TOP_INST_POWER_SWITCH_MEMORY :: V3D_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_V3D_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_V3D_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_V3D_TOP_INST_POWER_SWITCH_MEMORY_V3D_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:06] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 6

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT  6
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 10

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT  6
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 10

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 - PLL CHANNEL control CH 3
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: MDIV_CH3 [13:06] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_SHIFT  6
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_MDIV_CH3_DEFAULT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_LOAD_EN_CH3 [05:05] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_MASK 0x00000020
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_SHIFT 5
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_LOAD_EN_CH3_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: POST_DIVIDER_HOLD_CH3 [04:04] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_MASK 0x00000010
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_SHIFT 4
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_POST_DIVIDER_HOLD_CH3_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: PHASE_OFFSET_CH3 [03:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_SHIFT 1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_PHASE_OFFSET_CH3_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_3 :: CLOCK_DIS_CH3 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_3_CLOCK_DIS_CH3_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 - PLL CHANNEL control CH 4
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: MDIV_CH4 [13:06] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_SHIFT  6
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_MDIV_CH4_DEFAULT 81

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_LOAD_EN_CH4 [05:05] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_MASK 0x00000020
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_SHIFT 5
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_LOAD_EN_CH4_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: POST_DIVIDER_HOLD_CH4 [04:04] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_MASK 0x00000010
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_SHIFT 4
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_POST_DIVIDER_HOLD_CH4_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: PHASE_OFFSET_CH4 [03:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_SHIFT 1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_PHASE_OFFSET_CH4_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_4 :: CLOCK_DIS_CH4 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_4_CLOCK_DIS_CH4_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 - PLL CHANNEL control CH 5
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_MASK  0xffffc000
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_reserved0_SHIFT 14

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: MDIV_CH5 [13:06] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_MASK   0x00003fc0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_SHIFT  6
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_MDIV_CH5_DEFAULT 12

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_LOAD_EN_CH5 [05:05] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_MASK 0x00000020
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_SHIFT 5
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_LOAD_EN_CH5_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: POST_DIVIDER_HOLD_CH5 [04:04] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_MASK 0x00000010
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_SHIFT 4
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_POST_DIVIDER_HOLD_CH5_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: PHASE_OFFSET_CH5 [03:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_SHIFT 1
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_PHASE_OFFSET_CH5_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_CHANNEL_CTRL_CH_5 :: CLOCK_DIS_CH5 [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_CHANNEL_CTRL_CH_5_CLOCK_DIS_CH5_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_MASK               0xff000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_reserved0_SHIFT              24

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 10

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 4

/* CLKGEN :: PLL_SYS0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK       0x00000007
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT      0
#define BCHP_CLKGEN_PLL_SYS0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT    3

/***************************************************************************
 *PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_SYS0_PLL_MISC - Miscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_MISC :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_MASK               0x80000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_reserved0_SHIFT              31

/* CLKGEN :: PLL_SYS0_PLL_MISC :: LDO_REF_SEL [30:30] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_MASK             0x40000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_SHIFT            30
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_LDO_REF_SEL_DEFAULT          0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: POR_BYPASS [29:29] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_MASK              0x20000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_SHIFT             29
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_POR_BYPASS_DEFAULT           0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: NDIV_RELOCK [28:28] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_MASK             0x10000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_SHIFT            28
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_NDIV_RELOCK_DEFAULT          0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: FAST_LOCK [27:27] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_MASK               0x08000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_SHIFT              27
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_FAST_LOCK_DEFAULT            0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCODIV2 [26:26] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_MASK                 0x04000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_SHIFT                26
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCODIV2_DEFAULT              1

/* CLKGEN :: PLL_SYS0_PLL_MISC :: VCO_DLY [25:24] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_MASK                 0x03000000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_SHIFT                24
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_VCO_DLY_DEFAULT              0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: PWM_RATE [23:22] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_MASK                0x00c00000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_SHIFT               22
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_PWM_RATE_DEFAULT             2

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_MODE [21:20] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_MASK               0x00300000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_SHIFT              20
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_MODE_DEFAULT            0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: AUX_CTRL [19:19] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_MASK                0x00080000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_SHIFT               19
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_AUX_CTRL_DEFAULT             0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_MASK               0x00040000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_SHIFT              18
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_REFCLKOUT_DEFAULT            0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_UPDATE [17:17] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_MASK             0x00020000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_SHIFT            17
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_UPDATE_DEFAULT          0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_SELECT [16:14] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_MASK             0x0001c000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_SHIFT            14
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_SELECT_DEFAULT          0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: STAT_RESET_ [13:13] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__MASK             0x00002000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__SHIFT            13
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_STAT_RESET__DEFAULT          0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK  0x00001000
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_SYS0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT        0
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT      0

/***************************************************************************
 *PLL_SYS0_PLL_MISC2 - Miscellaneous control bus continued.
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_reserved0_SHIFT             1

/* CLKGEN :: PLL_SYS0_PLL_MISC2 :: SPARE [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_MASK                  0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_SHIFT                 0
#define BCHP_CLKGEN_PLL_SYS0_PLL_MISC2_SPARE_DEFAULT               0

/***************************************************************************
 *PLL_SYS0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK [01:01] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_MASK             0x00000002
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_SHIFT            1

/* CLKGEN :: PLL_SYS0_PLL_LOCK_STATUS :: LOCK_LOST [00:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_MASK        0x00000001
#define BCHP_CLKGEN_PLL_SYS0_PLL_LOCK_STATUS_LOCK_LOST_SHIFT       0

/***************************************************************************
 *PLL_SYS0_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_SYS0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_MASK             0xfffff000
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_reserved0_SHIFT            12

/* CLKGEN :: PLL_SYS0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_SYS0_PLL_STATUS_TEST_STATUS_SHIFT          0

/***************************************************************************
 *PLL_VCXO0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_MASK             0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_reserved0_SHIFT            2

/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_MASK                0x00000002
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_SHIFT               1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETD_DEFAULT             0

/* CLKGEN :: PLL_VCXO0_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_MASK                0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_SHIFT               0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_RESETA_DEFAULT             0

/***************************************************************************
 *PLL_VCXO0_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_reserved0_SHIFT            1

/* CLKGEN :: PLL_VCXO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_SHIFT            0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_PWRDN_PWRDN_PLL_DEFAULT          0

/***************************************************************************
 *PLL_VCXO0_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_reserved0_MASK           0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_reserved0_SHIFT          1

/* CLKGEN :: PLL_VCXO0_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_MASK             0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_SHIFT            0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CONTROL_REF_SEL_DEFAULT          0

/***************************************************************************
 *PLL_VCXO0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_MASK               0xffffe000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_reserved0_SHIFT              13

/* CLKGEN :: PLL_VCXO0_PLL_DIV :: NDIV_INT [12:03] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_MASK                0x00001ff8
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_SHIFT               3
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_NDIV_INT_DEFAULT             64

/* CLKGEN :: PLL_VCXO0_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_MASK                    0x00000007
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_SHIFT                   0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_DIV_PDIV_DEFAULT                 2

/***************************************************************************
 *PLL_VCXO0_PLL_FRAC - Fractional
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: reserved0 [31:20] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_MASK              0xfff00000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_reserved0_SHIFT             20

/* CLKGEN :: PLL_VCXO0_PLL_FRAC :: FRAC_CONTROL [19:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_MASK           0x000fffff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_SHIFT          0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_FRAC_FRAC_CONTROL_DEFAULT        0

/***************************************************************************
 *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK  0x00003fc0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT 64

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK  0x00003fc0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT 250

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 - PLL CHANNEL control CH 2
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_MASK 0xffffc000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_reserved0_SHIFT 14

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: MDIV_CH2 [13:06] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_MASK  0x00003fc0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_MDIV_CH2_DEFAULT 75

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_LOAD_EN_CH2 [05:05] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_MASK 0x00000020
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_SHIFT 5
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_LOAD_EN_CH2_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: POST_DIVIDER_HOLD_CH2 [04:04] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_MASK 0x00000010
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_SHIFT 4
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_POST_DIVIDER_HOLD_CH2_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: PHASE_OFFSET_CH2 [03:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_PHASE_OFFSET_CH2_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2 :: CLOCK_DIS_CH2 [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_CHANNEL_CTRL_CH_2_CLOCK_DIS_CH2_DEFAULT 0

/***************************************************************************
 *PLL_VCXO0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_MASK              0xff000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_reserved0_SHIFT             24

/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 8

/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_VCXO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK      0x00000007
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT     0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT   1

/***************************************************************************
 *PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_VCXO0_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_MISC :: reserved0 [31:30] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_reserved0_MASK              0xc0000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_reserved0_SHIFT             30

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: MDIV_RELOCK [29:29] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_MASK            0x20000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_SHIFT           29
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_MDIV_RELOCK_DEFAULT         0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: FAST_LOCK [28:28] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_MASK              0x10000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_SHIFT             28
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_FAST_LOCK_DEFAULT           0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCODIV2 [27:27] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_MASK                0x08000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_SHIFT               27
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_DEFAULT             0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCO_DLY [26:25] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_MASK                0x06000000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_SHIFT               25
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCO_DLY_DEFAULT             0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: PWM_RATE [24:23] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_MASK               0x01800000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_SHIFT              23
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_PWM_RATE_DEFAULT            0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_MODE [22:21] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_MASK              0x00600000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_SHIFT             21
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_MODE_DEFAULT           0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: VCODIV2_POST [20:20] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_MASK           0x00100000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_SHIFT          20
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_VCODIV2_POST_DEFAULT        0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: AUX_CTRL [19:19] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_MASK               0x00080000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_SHIFT              19
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_AUX_CTRL_DEFAULT            0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_MASK              0x00040000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_SHIFT             18
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_REFCLKOUT_DEFAULT           0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_UPDATE [17:17] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_MASK            0x00020000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_SHIFT           17
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_UPDATE_DEFAULT         0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_SELECT [16:14] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_MASK            0x0001c000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_SHIFT           14
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_SELECT_DEFAULT         0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: STAT_RESET_ [13:13] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__MASK            0x00002000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__SHIFT           13
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_STAT_RESET__DEFAULT         0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT 12
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_VCXO0_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_MASK        0x00000fff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_SHIFT       0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT     0

/***************************************************************************
 *PLL_VCXO0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_reserved0_SHIFT      1

/* CLKGEN :: PLL_VCXO0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_MASK            0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_LOCK_STATUS_LOCK_SHIFT           0

/***************************************************************************
 *PLL_VCXO0_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_MASK            0xfffff000
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_reserved0_SHIFT           12

/* CLKGEN :: PLL_VCXO0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_MASK          0x00000fff
#define BCHP_CLKGEN_PLL_VCXO0_PLL_STATUS_TEST_STATUS_SHIFT         0

/***************************************************************************
 *PLL_SC_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_MASK                0xfffffffc
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_reserved0_SHIFT               2

/* CLKGEN :: PLL_SC_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_MASK                   0x00000002
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_SHIFT                  1
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETD_DEFAULT                0

/* CLKGEN :: PLL_SC_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_MASK                   0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_SHIFT                  0
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_RESETA_DEFAULT                0

/***************************************************************************
 *PLL_SC_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_MASK                0xfffffffe
#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_reserved0_SHIFT               1

/* CLKGEN :: PLL_SC_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_SHIFT               0
#define BCHP_CLKGEN_PLL_SC_PLL_PWRDN_PWRDN_PLL_DEFAULT             0

/***************************************************************************
 *PLL_SC_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_reserved0_SHIFT             1

/* CLKGEN :: PLL_SC_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_MASK                0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_SHIFT               0
#define BCHP_CLKGEN_PLL_SC_PLL_CONTROL_REF_SEL_DEFAULT             0

/***************************************************************************
 *PLL_SC_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_DIV :: reserved0 [31:13] */
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_MASK                  0xffffe000
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_reserved0_SHIFT                 13

/* CLKGEN :: PLL_SC_PLL_DIV :: NDIV_INT [12:03] */
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_MASK                   0x00001ff8
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_SHIFT                  3
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_NDIV_INT_DEFAULT                64

/* CLKGEN :: PLL_SC_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_MASK                       0x00000007
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_SHIFT                      0
#define BCHP_CLKGEN_PLL_SC_PLL_DIV_PDIV_DEFAULT                    1

/***************************************************************************
 *PLL_SC_PLL_CHANNEL_CTRL_CH_0 - PLL CHANNEL control CH 0
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_MASK    0xffffc000
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_reserved0_SHIFT   14

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: MDIV_CH0 [13:06] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_MASK     0x00003fc0
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_SHIFT    6
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_MDIV_CH0_DEFAULT  48

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_LOAD_EN_CH0 [05:05] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_MASK 0x00000020
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_SHIFT 5
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_LOAD_EN_CH0_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: POST_DIVIDER_HOLD_CH0 [04:04] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_MASK 0x00000010
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_SHIFT 4
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_POST_DIVIDER_HOLD_CH0_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: PHASE_OFFSET_CH0 [03:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_SHIFT 1
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_PHASE_OFFSET_CH0_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_0 :: CLOCK_DIS_CH0 [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_SHIFT 0
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_0_CLOCK_DIS_CH0_DEFAULT 0

/***************************************************************************
 *PLL_SC_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_MASK                 0xff000000
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_reserved0_SHIFT                24

/* CLKGEN :: PLL_SC_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7

/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_SC_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK         0x00000007
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT        0
#define BCHP_CLKGEN_PLL_SC_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT      1

/***************************************************************************
 *PLL_SC_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK  0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_SC_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_SC_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_SC_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_SC_PLL_MISC - Mscellaneous control bus.
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_MISC :: reserved0 [31:30] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_MASK                 0xc0000000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_reserved0_SHIFT                30

/* CLKGEN :: PLL_SC_PLL_MISC :: MDIV_RELOCK [29:29] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_MASK               0x20000000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_SHIFT              29
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_MDIV_RELOCK_DEFAULT            0

/* CLKGEN :: PLL_SC_PLL_MISC :: FAST_LOCK [28:28] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_MASK                 0x10000000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_SHIFT                28
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_FAST_LOCK_DEFAULT              0

/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2 [27:27] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_MASK                   0x08000000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_SHIFT                  27
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_DEFAULT                0

/* CLKGEN :: PLL_SC_PLL_MISC :: VCO_DLY [26:25] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_MASK                   0x06000000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_SHIFT                  25
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCO_DLY_DEFAULT                0

/* CLKGEN :: PLL_SC_PLL_MISC :: PWM_RATE [24:23] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_MASK                  0x01800000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_SHIFT                 23
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_PWM_RATE_DEFAULT               0

/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_MODE [22:21] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_MASK                 0x00600000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_SHIFT                21
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_MODE_DEFAULT              0

/* CLKGEN :: PLL_SC_PLL_MISC :: VCODIV2_POST [20:20] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_MASK              0x00100000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_SHIFT             20
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_VCODIV2_POST_DEFAULT           0

/* CLKGEN :: PLL_SC_PLL_MISC :: AUX_CTRL [19:19] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_MASK                  0x00080000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_SHIFT                 19
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_AUX_CTRL_DEFAULT               0

/* CLKGEN :: PLL_SC_PLL_MISC :: REFCLKOUT [18:18] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_MASK                 0x00040000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_SHIFT                18
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_REFCLKOUT_DEFAULT              0

/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_UPDATE [17:17] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_MASK               0x00020000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_SHIFT              17
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_UPDATE_DEFAULT            0

/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_SELECT [16:14] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_MASK               0x0001c000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_SHIFT              14
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_SELECT_DEFAULT            0

/* CLKGEN :: PLL_SC_PLL_MISC :: STAT_RESET_ [13:13] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__MASK               0x00002000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__SHIFT              13
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_STAT_RESET__DEFAULT            0

/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS_ENABLE [12:12] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_MASK    0x00001000
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_SHIFT   12
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_MISC :: DCO_CTRL_BYPASS [11:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_MASK           0x00000fff
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_SHIFT          0
#define BCHP_CLKGEN_PLL_SC_PLL_MISC_DCO_CTRL_BYPASS_DEFAULT        0

/***************************************************************************
 *PLL_SC_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_reserved0_SHIFT         1

/* CLKGEN :: PLL_SC_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_MASK               0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_LOCK_STATUS_LOCK_SHIFT              0

/***************************************************************************
 *PLL_SC_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_MASK               0xfffff000
#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_reserved0_SHIFT              12

/* CLKGEN :: PLL_SC_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_MASK             0x00000fff
#define BCHP_CLKGEN_PLL_SC_PLL_STATUS_TEST_STATUS_SHIFT            0

/***************************************************************************
 *PLL_AUDIO0_PLL_RESET - Resets
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_MASK            0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_reserved0_SHIFT           2

/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_MASK               0x00000002
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_SHIFT              1
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETD_DEFAULT            0

/* CLKGEN :: PLL_AUDIO0_PLL_RESET :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_MASK               0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_SHIFT              0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_RESETA_DEFAULT            0

/***************************************************************************
 *PLL_AUDIO0_PLL_PWRDN - Powerdowns
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_MASK            0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_reserved0_SHIFT           1

/* CLKGEN :: PLL_AUDIO0_PLL_PWRDN :: PWRDN_PLL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_PWRDN_PWRDN_PLL_DEFAULT         0

/***************************************************************************
 *PLL_AUDIO0_PLL_CONTROL - Miscellaneous Controls
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_reserved0_SHIFT         1

/* CLKGEN :: PLL_AUDIO0_PLL_CONTROL :: REF_SEL [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_MASK            0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_SHIFT           0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_CONTROL_REF_SEL_DEFAULT         0

/***************************************************************************
 *PLL_AUDIO0_PLL_DIV - Pre multiplier
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_MASK              0xfffffff8
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_reserved0_SHIFT             3

/* CLKGEN :: PLL_AUDIO0_PLL_DIV :: PDIV [02:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_MASK                   0x00000007
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_SHIFT                  0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_DIV_PDIV_DEFAULT                1

/***************************************************************************
 *PLL_AUDIO0_PLL_GAIN - PLL GAIN
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_MASK             0xff000000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_reserved0_SHIFT            24

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: EIGHT_PHASE_OUTPUT_ENABLE [23:23] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_MASK 0x00800000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_SHIFT 23
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_EIGHT_PHASE_OUTPUT_ENABLE_DEFAULT 0

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK [22:11] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_MASK 0x007ff800
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_SHIFT 11
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_PROG_PHASE_OFFSET_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK [10:10] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_MASK 0x00000400
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_SHIFT 10
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_ENABLE_PHASE_MATCH_REF_AND_FEEDBACK_CLOCK_DEFAULT 0

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_PROPORTIONAL_IN_PHASE [09:06] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_MASK 0x000003c0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_SHIFT 6
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_PROPORTIONAL_IN_PHASE_DEFAULT 7

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_INTEGRATOR_IN_PHASE [05:03] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_MASK 0x00000038
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_SHIFT 3
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_INTEGRATOR_IN_PHASE_DEFAULT 2

/* CLKGEN :: PLL_AUDIO0_PLL_GAIN :: LOOP_GAIN_IN_FREQ [02:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_MASK     0x00000007
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_SHIFT    0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_GAIN_LOOP_GAIN_IN_FREQ_DEFAULT  1

/***************************************************************************
 *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW - Lower bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: reserved0 [31:23] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_MASK 0xff800000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_reserved0_SHIFT 23

/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_LIMIT [22:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_MASK 0x007ffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_SHIFT 1
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_LIMIT_DEFAULT 0

/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW :: SSC_MODE [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_MASK 0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_LOW_SSC_MODE_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH - Higher bits of Spread Spectrum mode control
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_reserved0_SHIFT 16

/* CLKGEN :: PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH :: SSC_STEP [15:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_MASK 0x0000ffff
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_SHIFT 0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_SSC_MODE_CONTROL_HIGH_SSC_STEP_DEFAULT 0

/***************************************************************************
 *PLL_AUDIO0_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_reserved0_SHIFT     1

/* CLKGEN :: PLL_AUDIO0_PLL_LOCK_STATUS :: LOCK [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_MASK           0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_LOCK_STATUS_LOCK_SHIFT          0

/***************************************************************************
 *PLL_AUDIO0_PLL_STATUS - Test Status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: reserved0 [31:12] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_MASK           0xfffff000
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_reserved0_SHIFT          12

/* CLKGEN :: PLL_AUDIO0_PLL_STATUS :: TEST_STATUS [11:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_MASK         0x00000fff
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_STATUS_TEST_STATUS_SHIFT        0

/***************************************************************************
 *AVD1_TOP_INST_POWER_SWITCH_MEMORY - Avd1 top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: AVD1_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: AVD1_TOP_INST_POWER_SWITCH_MEMORY :: AVD1_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY_AVD1_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY_AVD1_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_AVD1_TOP_INST_POWER_SWITCH_MEMORY_AVD1_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *UHFR_TOP_INST_OBSERVE_CLOCK - Uhfr top inst observe clock
 ***************************************************************************/
/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: UHFR_TOP_INST_OBSERVE_CLOCK :: UHFR_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UHFR_TOP_INST_OBSERVE_CLOCK_UHFR_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *CORE_XPT_INST_CLOCK_ENABLE - Core xpt inst clock enable
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_reserved0_SHIFT     2

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: CORE_XPT_INST_CLOCK_ENABLE :: XPT_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_ENABLE_XPT_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC - Vec aio top inst clock enable vec
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: reserved0 [31:06] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_reserved0_SHIFT 6

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_AIO_CLK_324_ENABLE_VEC [05:05] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_AIO_CLK_324_ENABLE_VEC_MASK 0x00000020
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_AIO_CLK_324_ENABLE_VEC_SHIFT 5
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_AIO_CLK_324_ENABLE_VEC_DEFAULT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_SCB_CLOCK_ENABLE_VEC [04:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_SHIFT 4
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_SCB_CLOCK_ENABLE_VEC_DEFAULT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_QDAC_216_CLOCK_ENABLE_VEC [03:03] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_MASK 0x00000008
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_SHIFT 3
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_QDAC_216_CLOCK_ENABLE_VEC_DEFAULT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_ALTERNATE_216_CLOCK_ENABLE_VEC [02:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_SHIFT 2
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_ALTERNATE_216_CLOCK_ENABLE_VEC_DEFAULT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_216_CLOCK_ENABLE_VEC [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_216_CLOCK_ENABLE_VEC_DEFAULT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC :: VEC_108_CLOCK_ENABLE_VEC [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_VEC_108_CLOCK_ENABLE_VEC_DEFAULT 1

/***************************************************************************
 *SYS_CTRL_INST_CLOCK_DISABLE - Disable SYS_CTRL_INST's clocks
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffff0
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_reserved0_SHIFT    4

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_UPG_CLOCK [03:03] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_SHIFT 3
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_UPG_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SYSCTRL_SOFTMODEM_CLOCK [02:02] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_SHIFT 2
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SYSCTRL_SOFTMODEM_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC1_CLOCK [01:01] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_SHIFT 1
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC1_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_CTRL_INST_CLOCK_DISABLE :: DISABLE_SC0_CLOCK [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_INST_CLOCK_DISABLE_DISABLE_SC0_CLOCK_DEFAULT 0

/***************************************************************************
 *PAD_MUX_SELECT - Mux selects for Pad clocks
 ***************************************************************************/
/* CLKGEN :: PAD_MUX_SELECT :: reserved0 [31:04] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_MASK                  0xfffffff0
#define BCHP_CLKGEN_PAD_MUX_SELECT_reserved0_SHIFT                 4

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_VCXO27_CLOCK [03:02] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_MASK    0x0000000c
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_SHIFT   2
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_OBSERVE_PLL_CLOCK [01:01] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_OBSERVE_PLL_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_OBSERVE_PLL_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_OBSERVE_PLL_CLOCK_DEFAULT 0

/* CLKGEN :: PAD_MUX_SELECT :: PAD_OUTPUT_CLK27_CLOCK [00:00] */
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_MASK     0x00000001
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_SHIFT    0
#define BCHP_CLKGEN_PAD_MUX_SELECT_PAD_OUTPUT_CLK27_CLOCK_DEFAULT  0

/***************************************************************************
 *DVP_HT_INST_CLOCK_DISABLE - Disable DVP_HT_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_MASK       0xfffffffe
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_reserved0_SHIFT      1

/* CLKGEN :: DVP_HT_INST_CLOCK_DISABLE :: DISABLE_DVPHT_IIC_MASTER_CLOCK [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_DISABLE_DISABLE_DVPHT_IIC_MASTER_CLOCK_DEFAULT 0

/***************************************************************************
 *CORE_XPT_INST_MEMORY_STANDBY_ENABLE - Core xpt inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: CORE_XPT_INST_MEMORY_STANDBY_ENABLE :: XPT_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_INST_MEMORY_STANDBY_ENABLE_XPT_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *ZCPU_TOP_INST_CLOCK_DISABLE - Disable ZCPU_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1

/* CLKGEN :: ZCPU_TOP_INST_CLOCK_DISABLE :: DISABLE_ZMIPS_FUNC_BYP_CLOCK [00:00] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_SHIFT 0
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_DISABLE_DISABLE_ZMIPS_FUNC_BYP_CLOCK_DEFAULT 0

/***************************************************************************
 *SYS_CTRL_INST_POWER_SWITCH_MEMORY - Sys ctrl inst power switch memory
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: SYS_CTRL_INST_POWER_SWITCH_MEMORY :: SYS_CTRL_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_INST_POWER_SWITCH_MEMORY_SYS_CTRL_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *UHFR_TOP_INST_MEMORY_STANDBY_ENABLE - Uhfr top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: UHFR_TOP_INST_MEMORY_STANDBY_ENABLE :: UHFR_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UHFR_TOP_INST_MEMORY_STANDBY_ENABLE_UHFR_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *USB0_INST_CLOCK_DISABLE - Disable USB0_INST's clocks
 ***************************************************************************/
/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_reserved0_SHIFT        2

/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_54_FREERUN_CLOCK [01:01] */
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_SHIFT 1
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_FREERUN_CLOCK_DEFAULT 0

/* CLKGEN :: USB0_INST_CLOCK_DISABLE :: DISABLE_USB0_54_MDIO_CLOCK [00:00] */
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB0_INST_CLOCK_DISABLE_DISABLE_USB0_54_MDIO_CLOCK_DEFAULT 0

/***************************************************************************
 *PAD_CLOCK_DISABLE - Disable PAD's clocks
 ***************************************************************************/
/* CLKGEN :: PAD_CLOCK_DISABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_MASK               0xffffffe0
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_reserved0_SHIFT              5

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_SC_CLOCK [04:04] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_SHIFT 4
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_SC_CLOCK_DEFAULT 0

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_VCXO27_CLOCK [03:03] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_SHIFT 3
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_VCXO27_CLOCK_DEFAULT 0

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK [02:02] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_SHIFT 2
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_OBSERVE_PLL_CLOCK_DEFAULT 0

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK [01:01] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_SHIFT 1
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CODECMCLK_CLOCK_DEFAULT 0

/* CLKGEN :: PAD_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_CLK27_CLOCK [00:00] */
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_SHIFT 0
#define BCHP_CLKGEN_PAD_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_CLK27_CLOCK_DEFAULT 0

/***************************************************************************
 *SMARTCARD_MUX_SELECT - Mux selects for Smartcard clocks
 ***************************************************************************/
/* CLKGEN :: SMARTCARD_MUX_SELECT :: reserved0 [31:11] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_MASK            0xfffff800
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_reserved0_SHIFT           11

/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC_OUT_CLOCK [10:08] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_MASK         0x00000700
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_SHIFT        8
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC_OUT_CLOCK_DEFAULT      0

/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC1_CLOCK [07:05] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_MASK            0x000000e0
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_SHIFT           5
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC1_CLOCK_DEFAULT         0

/* CLKGEN :: SMARTCARD_MUX_SELECT :: SC0_CLOCK [04:02] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_MASK            0x0000001c
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_SHIFT           2
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_SC0_CLOCK_DEFAULT         0

/* CLKGEN :: SMARTCARD_MUX_SELECT :: PLLSC_REFERENCE_CLOCK [01:00] */
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_MASK 0x00000003
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SMARTCARD_MUX_SELECT_PLLSC_REFERENCE_CLOCK_DEFAULT 0

/***************************************************************************
 *UHFR_TOP_INST_CLOCK_ENABLE - Uhfr top inst clock enable
 ***************************************************************************/
/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1

/* CLKGEN :: UHFR_TOP_INST_CLOCK_ENABLE :: UHFR_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_ENABLE_UHFR_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *HIF_INST_MEMORY_STANDBY_ENABLE - Hif inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK  0xfffffffe
#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: HIF_INST_MEMORY_STANDBY_ENABLE :: HIF_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_HIF_INST_MEMORY_STANDBY_ENABLE_HIF_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *CORE_XPT_INST_CLOCK_DISABLE - Disable CORE_XPT_INST's clocks
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_MASK     0xffffffe0
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_reserved0_SHIFT    5

/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_81_CLOCK [04:04] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_SHIFT 4
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_81_CLOCK_DEFAULT 0

/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_54_CLOCK [03:03] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_SHIFT 3
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_54_CLOCK_DEFAULT 0

/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_40P5_CLOCK [02:02] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_SHIFT 2
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_40P5_CLOCK_DEFAULT 0

/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_27_CLOCK [01:01] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_SHIFT 1
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_27_CLOCK_DEFAULT 0

/* CLKGEN :: CORE_XPT_INST_CLOCK_DISABLE :: DISABLE_XPT_20P25_CLOCK [00:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_INST_CLOCK_DISABLE_DISABLE_XPT_20P25_CLOCK_DEFAULT 0

/***************************************************************************
 *INTERNAL_MUX_SELECT - Mux selects for Internal clocks
 ***************************************************************************/
/* CLKGEN :: INTERNAL_MUX_SELECT :: reserved0 [31:10] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_MASK             0xfffffc00
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_reserved0_SHIFT            10

/* CLKGEN :: INTERNAL_MUX_SELECT :: VECAIO_ITU656_1_CLOCK [09:08] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_VECAIO_ITU656_1_CLOCK_MASK 0x00000300
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_VECAIO_ITU656_1_CLOCK_SHIFT 8
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_VECAIO_ITU656_1_CLOCK_DEFAULT 0

/* CLKGEN :: INTERNAL_MUX_SELECT :: VECAIO_ITU656_0_CLOCK [07:06] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_VECAIO_ITU656_0_CLOCK_MASK 0x000000c0
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_VECAIO_ITU656_0_CLOCK_SHIFT 6
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_VECAIO_ITU656_0_CLOCK_DEFAULT 0

/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO2_REFERENCE_CLOCK [05:04] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_MASK 0x00000030
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO2_REFERENCE_CLOCK_DEFAULT 0

/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO1_REFERENCE_CLOCK [03:02] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_MASK 0x0000000c
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_SHIFT 2
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO1_REFERENCE_CLOCK_DEFAULT 0

/* CLKGEN :: INTERNAL_MUX_SELECT :: PLLAUDIO0_REFERENCE_CLOCK [01:00] */
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_MASK 0x00000003
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_INTERNAL_MUX_SELECT_PLLAUDIO0_REFERENCE_CLOCK_DEFAULT 0

/***************************************************************************
 *MOCA_TOP_INST_OBSERVE_CLOCK - Moca top inst observe clock
 ***************************************************************************/
/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: MOCA_TOP_INST_OBSERVE_CLOCK :: MOCA_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MOCA_TOP_INST_OBSERVE_CLOCK_MOCA_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *GRAPHICS_INST_MEMORY_STANDBY_ENABLE - Graphics inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: GRAPHICS_INST_MEMORY_STANDBY_ENABLE :: GFX_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_MEMORY_STANDBY_ENABLE_GFX_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *SYS_CTRL_INST_OBSERVE_CLOCK - Sys ctrl inst observe clock
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_CTRL_INST_OBSERVE_CLOCK :: UPG_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_INST_OBSERVE_CLOCK_UPG_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_DISABLE - Disable VEC_AIO_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_MASK  0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_1_CLOCK [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_1_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_1_CLOCK_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_1_CLOCK_DEFAULT 0

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_DISABLE :: DISABLE_VEC_ITU656_0_CLOCK [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_DISABLE_DISABLE_VEC_ITU656_0_CLOCK_DEFAULT 0

/***************************************************************************
 *UHFR_TOP_INST_CLOCK_DISABLE - Disable UHFR_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_MASK     0xfffffffe
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_reserved0_SHIFT    1

/* CLKGEN :: UHFR_TOP_INST_CLOCK_DISABLE :: DISABLE_UHFR_ALWAYSON_CLOCK [00:00] */
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_SHIFT 0
#define BCHP_CLKGEN_UHFR_TOP_INST_CLOCK_DISABLE_DISABLE_UHFR_ALWAYSON_CLOCK_DEFAULT 0

/***************************************************************************
 *PAD_CLK27_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CLK27_OBSERVATION :: reserved0 [31:09] */
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_MASK           0xfffffe00
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_reserved0_SHIFT          9

/* CLKGEN :: PAD_CLK27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_MASK  0x00000100
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0

/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_MASK  0x000000fe
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0

/* CLKGEN :: PAD_CLK27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK  0x00000001
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CLK27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0

/***************************************************************************
 *GRAPHICS_INST_M2MC_CLOCK_ENABLE - Disable GRAPHICS_INST's m2mc clock
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_M2MC_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: GRAPHICS_INST_M2MC_CLOCK_ENABLE :: GFX_M2MC_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_M2MC_CLOCK_ENABLE_GFX_M2MC_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *USB1_INST_CLOCK_DISABLE - Disable USB1_INST's clocks
 ***************************************************************************/
/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_reserved0_SHIFT        2

/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_54_FREERUN_CLOCK [01:01] */
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_SHIFT 1
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_FREERUN_CLOCK_DEFAULT 0

/* CLKGEN :: USB1_INST_CLOCK_DISABLE :: DISABLE_USB1_54_MDIO_CLOCK [00:00] */
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB1_INST_CLOCK_DISABLE_DISABLE_USB1_54_MDIO_CLOCK_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE - Disable DUAL_GENET_TOP_DUAL_RGMII_INST's clocks
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_MASK 0xffffffe0
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_reserved0_SHIFT 5

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET_ALWAYSON_CLOCK [04:04] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET_ALWAYSON_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_SLOW_CLOCK [03:03] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_MASK 0x00000008
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_SHIFT 3
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_SLOW_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET1_SYSTEM_PM_CLOCK [02:02] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_SHIFT 2
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET1_SYSTEM_PM_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_SLOW_CLOCK [01:01] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_SHIFT 1
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_SLOW_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE :: DISABLE_GENET0_SYSTEM_PM_CLOCK [00:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_DISABLE_DISABLE_GENET0_SYSTEM_PM_CLOCK_DEFAULT 0

/***************************************************************************
 *HIF_INST_CLOCK_DISABLE - Hif inst clock disable
 ***************************************************************************/
/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_MASK          0xffffffe0
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_reserved0_SHIFT         5

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CARD_CLOCK [04:04] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_SHIFT 4
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CARD_CLOCK_DEFAULT 0

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: HIF_PAD_BT_CLOCK_DISABLE [03:03] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_HIF_PAD_BT_CLOCK_DISABLE_MASK 0x00000008
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_HIF_PAD_BT_CLOCK_DISABLE_SHIFT 3
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_HIF_PAD_BT_CLOCK_DISABLE_DEFAULT 0

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_PAD_OUTPUT_EBI_CLOCK [02:02] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_MASK 0x00000004
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_SHIFT 2
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_PAD_OUTPUT_EBI_CLOCK_DEFAULT 0

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SPI_CLOCK [01:01] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_MASK 0x00000002
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_SHIFT 1
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SPI_CLOCK_DEFAULT 0

/* CLKGEN :: HIF_INST_CLOCK_DISABLE :: DISABLE_HIF_SDIO_CLOCK [00:00] */
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_MASK 0x00000001
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_SHIFT 0
#define BCHP_CLKGEN_HIF_INST_CLOCK_DISABLE_DISABLE_HIF_SDIO_CLOCK_DEFAULT 0

/***************************************************************************
 *USB0_INST_CLOCK_ENABLE - Usb0 inst clock enable
 ***************************************************************************/
/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_reserved0_SHIFT         2

/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: USB0_INST_CLOCK_ENABLE :: USB_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USB0_INST_CLOCK_ENABLE_USB_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *VICE2_INST_CLOCK_ENABLE - Vice2 inst clock enable
 ***************************************************************************/
/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_reserved0_MASK         0xfffffff0
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_reserved0_SHIFT        4

/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_GISB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_GISB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_GISB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_GISB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_CORE_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_CORE_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_CORE_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_CORE_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: VICE2_INST_CLOCK_ENABLE :: VICE_BVB_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_BVB_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_BVB_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_VICE2_INST_CLOCK_ENABLE_VICE_BVB_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *SCRATCH0 - clkgen  Scratch register
 ***************************************************************************/
/* CLKGEN :: SCRATCH0 :: VALUE [31:00] */
#define BCHP_CLKGEN_SCRATCH0_VALUE_MASK                            0xffffffff
#define BCHP_CLKGEN_SCRATCH0_VALUE_SHIFT                           0
#define BCHP_CLKGEN_SCRATCH0_VALUE_DEFAULT                         0

/***************************************************************************
 *USB1_INST_MEMORY_STANDBY_ENABLE - Usb1 inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: USB1_INST_MEMORY_STANDBY_ENABLE :: USB1_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USB1_INST_MEMORY_STANDBY_ENABLE_USB1_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B - Dual genet top dual rgmii inst power switch memory b
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B :: reserved0 [31:02] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B_reserved0_SHIFT 2

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B :: GENET1_POWER_SWITCH_MEMORY_B [01:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B_GENET1_POWER_SWITCH_MEMORY_B_MASK 0x00000003
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B_GENET1_POWER_SWITCH_MEMORY_B_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_B_GENET1_POWER_SWITCH_MEMORY_B_DEFAULT 0

/***************************************************************************
 *MEMSYS_32_0_INST_CLOCK_ENABLE - Memsys 32 0 inst clock enable
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_reserved0_SHIFT  2

/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: DDR0_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: MEMSYS_32_0_INST_CLOCK_ENABLE :: DDR0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_0_INST_CLOCK_ENABLE_DDR0_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *MEMSYS_32_1_INST_POWER_SWITCH_MEMORY - Memsys 32 1 inst power switch memory
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: MEMSYS_32_1_INST_POWER_SWITCH_MEMORY :: DDR1_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_1_INST_POWER_SWITCH_MEMORY_DDR1_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *SVD0_TOP_INST_CLOCK_ENABLE - Svd0 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff0
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     4

/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_CPU_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CPU_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CPU_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CPU_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_CORE_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CORE_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CORE_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_CORE_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: SVD0_TOP_INST_CLOCK_ENABLE :: SVD0_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SVD0_TOP_INST_CLOCK_ENABLE_SVD0_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *USB0_INST_OBSERVE_CLOCK - Usb0 inst observe clock
 ***************************************************************************/
/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_reserved0_SHIFT        6

/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: USB0_INST_OBSERVE_CLOCK :: USB0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB0_INST_OBSERVE_CLOCK_USB0_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *CORE_XPT_INST_POWER_SWITCH_MEMORY - Core xpt inst power switch memory
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: CORE_XPT_INST_POWER_SWITCH_MEMORY :: XPT_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_INST_POWER_SWITCH_MEMORY_XPT_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_OBSERVE_CLOCK - Vec aio top inst observe clock
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: VEC_AIO_TOP_INST_OBSERVE_CLOCK :: AIO_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_OBSERVE_CLOCK_AIO_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A - Dual genet top dual rgmii inst memory standby enable a
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: reserved0 [31:02] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_reserved0_SHIFT 2

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET1_MEMORY_STANDBY_ENABLE_A [01:01] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET1_MEMORY_STANDBY_ENABLE_A_MASK 0x00000002
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET1_MEMORY_STANDBY_ENABLE_A_SHIFT 1
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET1_MEMORY_STANDBY_ENABLE_A_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A :: GENET0_MEMORY_STANDBY_ENABLE_A [00:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_MASK 0x00000001
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_MEMORY_STANDBY_ENABLE_A_GENET0_MEMORY_STANDBY_ENABLE_A_DEFAULT 0

/***************************************************************************
 *VICE2_INST_POWER_SWITCH_MEMORY - Vice2 inst power switch memory
 ***************************************************************************/
/* CLKGEN :: VICE2_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_reserved0_MASK  0xfffffffc
#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: VICE2_INST_POWER_SWITCH_MEMORY :: VICE_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_VICE_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_VICE_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_VICE2_INST_POWER_SWITCH_MEMORY_VICE_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *DVP_HR_INST_OBSERVE_CLOCK - Dvp hr inst observe clock
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_reserved0_SHIFT      6

/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: DVP_HR_INST_OBSERVE_CLOCK :: DVPHR_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HR_INST_OBSERVE_CLOCK_DVPHR_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *SATA3_TOP_INST_CLOCK_SELECT - Sata3 top inst clock select
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: reserved0 [31:01] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_MASK     0xfffffffe
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_reserved0_SHIFT    1

/* CLKGEN :: SATA3_TOP_INST_CLOCK_SELECT :: SATA3_REF_CLOCK_SELECT [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_SELECT_SATA3_REF_CLOCK_SELECT_DEFAULT 1

/***************************************************************************
 *RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY - Raaga dsp top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY :: RAAGA_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_POWER_SWITCH_MEMORY_RAAGA_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *AVD1_TOP_INST_MEMORY_STANDBY_ENABLE - Avd0 top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: AVD1_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_AVD1_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_AVD1_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: AVD1_TOP_INST_MEMORY_STANDBY_ENABLE :: AVD1_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_AVD1_TOP_INST_MEMORY_STANDBY_ENABLE_AVD1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_AVD1_TOP_INST_MEMORY_STANDBY_ENABLE_AVD1_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_AVD1_TOP_INST_MEMORY_STANDBY_ENABLE_AVD1_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *USB1_INST_OBSERVE_CLOCK - Usb1 inst observe clock
 ***************************************************************************/
/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_MASK         0xffffffc0
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_reserved0_SHIFT        6

/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: USB1_INST_OBSERVE_CLOCK :: USB1_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_USB1_INST_OBSERVE_CLOCK_USB1_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *MEMSYS_32_1_INST_OBSERVE_CLOCK - Memsys 32 1 inst observe clock
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: DDR1_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: MEMSYS_32_1_INST_OBSERVE_CLOCK :: DDR1_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_1_INST_OBSERVE_CLOCK_DDR1_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE - BVN_MCVP_TOP inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MCVP_TOP_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MCVP_TOP_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MCVP_TOP_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MCVP_TOP_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *MOCA_TOP_INST_POWER_SWITCH_MEMORY - Moca top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: MOCA_TOP_INST_POWER_SWITCH_MEMORY :: MOCA_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_MOCA_TOP_INST_POWER_SWITCH_MEMORY_MOCA_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *MEMSYS_32_0_INST_OBSERVE_CLOCK - Memsys 32 0 inst observe clock
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_MASK  0xffffffc0
#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: DDR0_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: MEMSYS_32_0_INST_OBSERVE_CLOCK :: DDR0_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_0_INST_OBSERVE_CLOCK_DDR0_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE - Raaga dsp top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE :: RAAGA_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_MEMORY_STANDBY_ENABLE_RAAGA_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *BVN_MCVP_TOP_INST_CLOCK_ENABLE - BVN_MCVP_TOP inst clock enable
 ***************************************************************************/
/* CLKGEN :: BVN_MCVP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_reserved0_MASK  0xfffffff8
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3

/* CLKGEN :: BVN_MCVP_TOP_INST_CLOCK_ENABLE :: BVND_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: BVN_MCVP_TOP_INST_CLOCK_ENABLE :: BVND_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: BVN_MCVP_TOP_INST_CLOCK_ENABLE :: BVND_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_CLOCK_ENABLE_BVND_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *MEMSYS_32_0_INST_POWER_SWITCH_MEMORY - Memsys 32 0 inst power switch memory
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: MEMSYS_32_0_INST_POWER_SWITCH_MEMORY :: DDR0_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_DDR0_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_DDR0_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_0_INST_POWER_SWITCH_MEMORY_DDR0_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE - Memsys 32 0 inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE :: DDR0_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_DDR0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_DDR0_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_0_INST_MEMORY_STANDBY_ENABLE_DDR0_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *MEMSYS_32_1_INST_CLOCK_ENABLE - Memsys 32 1 inst clock enable
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_reserved0_SHIFT  2

/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: DDR1_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: MEMSYS_32_1_INST_CLOCK_ENABLE :: DDR1_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_1_INST_CLOCK_ENABLE_DDR1_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *SATA3_TOP_INST_MEMORY_STANDBY_ENABLE - Sata3 top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: SATA3_TOP_INST_MEMORY_STANDBY_ENABLE :: SATA3_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_INST_MEMORY_STANDBY_ENABLE_SATA3_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *ZCPU_TOP_INST_OBSERVE_CLOCK - Zcpu top inst observe clock
 ***************************************************************************/
/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: ZCPU_TOP_INST_OBSERVE_CLOCK :: ZMIPS_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_ZCPU_TOP_INST_OBSERVE_CLOCK_ZMIPS_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *V3D_TOP_INST_MEMORY_STANDBY_ENABLE - V3D_TOP inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: V3D_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: V3D_TOP_INST_MEMORY_STANDBY_ENABLE :: V3D_TOP_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_V3D_TOP_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_V3D_TOP_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_V3D_TOP_INST_MEMORY_STANDBY_ENABLE_V3D_TOP_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *DVP_HR_INST_POWER_SWITCH_MEMORY - Dvp hr inst power switch memory
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: DVP_HR_INST_POWER_SWITCH_MEMORY :: DVPHR_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_DVP_HR_INST_POWER_SWITCH_MEMORY_DVPHR_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *USB1_INST_POWER_SWITCH_MEMORY - Usb1 inst power switch memory
 ***************************************************************************/
/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2

/* CLKGEN :: USB1_INST_POWER_SWITCH_MEMORY :: USB1_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_USB1_INST_POWER_SWITCH_MEMORY_USB1_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK - Dual genet top dual rgmii inst observe clock
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK :: GENET_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_OBSERVE_CLOCK_GENET_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *DVP_HT_INST_CLOCK_ENABLE - Dvp ht inst clock enable
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: reserved0 [31:06] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_MASK        0xffffffc0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_reserved0_SHIFT       6

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_CLK_VEC_ENABLE [05:05] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_SHIFT 5
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_VEC_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_CLK_MAX_ENABLE [04:04] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_SHIFT 4
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_CLK_MAX_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_216_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_ALTERNATE_108_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HT_INST_CLOCK_ENABLE :: DVPHT_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_CLOCK_ENABLE_DVPHT_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *GRAPHICS_INST_CLOCK_ENABLE - Graphics inst clock enable
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_MASK      0xffffffe0
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_reserved0_SHIFT     5

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_SCB_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_ALTERNATE_216_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_ALTERNATE_108_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: GRAPHICS_INST_CLOCK_ENABLE :: GFX_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_CLOCK_ENABLE_GFX_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *GRAPHICS_INST_OBSERVE_CLOCK - Graphics inst observe clock
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: GRAPHICS_INST_OBSERVE_CLOCK :: GFX_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_OBSERVE_CLOCK_GFX_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *BVN_TOP_INST_POWER_SWITCH_MEMORY - Bvn top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: BVN_TOP_INST_POWER_SWITCH_MEMORY :: BVN_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_BVN_TOP_INST_POWER_SWITCH_MEMORY_BVN_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *TESTPORT - Special Testport Controls
 ***************************************************************************/
/* CLKGEN :: TESTPORT :: reserved0 [31:04] */
#define BCHP_CLKGEN_TESTPORT_reserved0_MASK                        0xfffffff0
#define BCHP_CLKGEN_TESTPORT_reserved0_SHIFT                       4

/* CLKGEN :: TESTPORT :: PLL_TEST_STATUS_SELECT [03:00] */
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_MASK           0x0000000f
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_SHIFT          0
#define BCHP_CLKGEN_TESTPORT_PLL_TEST_STATUS_SELECT_DEFAULT        0

/***************************************************************************
 *PAD_CODEC_MCLK_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: reserved0 [31:09] */
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_MASK      0xfffffe00
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_reserved0_SHIFT     9

/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0

/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0

/* CLKGEN :: PAD_CODEC_MCLK_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_CODEC_MCLK_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0

/***************************************************************************
 *PAD_OBSERVE_PLL_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: reserved0 [31:09] */
#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_reserved0_MASK     0xfffffe00
#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_reserved0_SHIFT    9

/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0

/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0

/* CLKGEN :: PAD_OBSERVE_PLL_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_OBSERVE_PLL_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0

/***************************************************************************
 *PM_CLOCK_216_ALIVE_SEL - Select clocks that can stay alive during power management standby mode.
 ***************************************************************************/
/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_reserved0_SHIFT         1

/* CLKGEN :: PM_CLOCK_216_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_MASK   0x00000001
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT  0
#define BCHP_CLKGEN_PM_CLOCK_216_ALIVE_SEL_CLOCK_216_CG_XPT_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO - Vec aio top inst clock enable aio
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: reserved0 [31:03] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_reserved0_SHIFT 3

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO [02:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_MASK 0x00000004
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_SHIFT 2
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE_SCB_CLOCK_ENABLE_AIO_DEFAULT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO [01:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_MASK 0x00000002
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_SHIFT 1
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_216_CLOCK_ENABLE_AIO_DEFAULT 1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO :: AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_AIO_AIO_ALTERNATE2_108_CLOCK_ENABLE_AIO_DEFAULT 1

/***************************************************************************
 *VEC_AIO_TOP_INST_CLOCK_ENABLE - Vec aio top inst clock enable
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT  1

/* CLKGEN :: VEC_AIO_TOP_INST_CLOCK_ENABLE :: VEC_AIO_ALTERNATE_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_CLOCK_ENABLE_VEC_AIO_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *SECTOP_INST_OBSERVE_CLOCK - Sectop inst observe clock
 ***************************************************************************/
/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_reserved0_SHIFT      6

/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SECTOP_INST_OBSERVE_CLOCK :: SECTOP_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SECTOP_INST_OBSERVE_CLOCK_SECTOP_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *AVD1_TOP_INST_CLOCK_ENABLE - Avd0 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: AVD1_TOP_INST_CLOCK_ENABLE :: reserved0 [31:04] */
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffff0
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     4

/* CLKGEN :: AVD1_TOP_INST_CLOCK_ENABLE :: AVD1_SCB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_SCB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_SCB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: AVD1_TOP_INST_CLOCK_ENABLE :: AVD1_CPU_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_CPU_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_CPU_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_CPU_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: AVD1_TOP_INST_CLOCK_ENABLE :: AVD1_CORE_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_CORE_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_CORE_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_CORE_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: AVD1_TOP_INST_CLOCK_ENABLE :: AVD1_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_AVD1_TOP_INST_CLOCK_ENABLE_AVD1_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *DVP_HT_INST_MEMORY_STANDBY_ENABLE - Dvp ht inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: DVP_HT_INST_MEMORY_STANDBY_ENABLE :: DVPHT_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_MEMORY_STANDBY_ENABLE_DVPHT_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *SATA3_TOP_INST_CLOCK_ENABLE - Sata3 top inst clock enable
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT    2

/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: SATA3_TOP_INST_CLOCK_ENABLE :: SATA3_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_INST_CLOCK_ENABLE_SATA3_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *BVN_TOP_INST_CLOCK_ENABLE - Bvn top inst clock enable
 ***************************************************************************/
/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffff8
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      3

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: BVN_TOP_INST_CLOCK_ENABLE :: BVN_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BVN_TOP_INST_CLOCK_ENABLE_BVN_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *AVD1_TOP_INST_OBSERVE_CLOCK - Avd0 top inst observe clock
 ***************************************************************************/
/* CLKGEN :: AVD1_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: AVD1_TOP_INST_OBSERVE_CLOCK :: AVD1_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: AVD1_TOP_INST_OBSERVE_CLOCK :: AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: AVD1_TOP_INST_OBSERVE_CLOCK :: AVD1_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_AVD1_TOP_INST_OBSERVE_CLOCK_AVD1_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *USB0_INST_POWER_SWITCH_MEMORY - Usb0 inst power switch memory
 ***************************************************************************/
/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_MASK   0xfffffffc
#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT  2

/* CLKGEN :: USB0_INST_POWER_SWITCH_MEMORY :: USB0_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_USB0_INST_POWER_SWITCH_MEMORY_USB0_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *GRAPHICS_INST_POWER_SWITCH_MEMORY - Graphics inst power switch memory
 ***************************************************************************/
/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: GRAPHICS_INST_POWER_SWITCH_MEMORY :: GFX_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_GRAPHICS_INST_POWER_SWITCH_MEMORY_GFX_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *VICE2_INST_MEMORY_STANDBY_ENABLE - Vice2 inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: VICE2_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: VICE2_INST_MEMORY_STANDBY_ENABLE :: VICE_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_VICE_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_VICE_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_VICE2_INST_MEMORY_STANDBY_ENABLE_VICE_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *CORE_XPT_INST_OBSERVE_CLOCK - Core xpt inst observe clock
 ***************************************************************************/
/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_MASK     0xffffffc0
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_reserved0_SHIFT    6

/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: CORE_XPT_INST_OBSERVE_CLOCK :: XPT_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_CORE_XPT_INST_OBSERVE_CLOCK_XPT_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO - Vec aio top inst memory standby enable aio
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO :: AIO_MEMORY_STANDBY_ENABLE_AIO [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_AIO_AIO_MEMORY_STANDBY_ENABLE_AIO_DEFAULT 0

/***************************************************************************
 *SYS_CTRL_INST_MEMORY_STANDBY_ENABLE - Sys ctrl inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: SYS_CTRL_INST_MEMORY_STANDBY_ENABLE :: SYS_CTRL_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SYS_CTRL_INST_MEMORY_STANDBY_ENABLE_SYS_CTRL_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *HIF_INST_POWER_SWITCH_MEMORY - Hif inst power switch memory
 ***************************************************************************/
/* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT   2

/* CLKGEN :: HIF_INST_POWER_SWITCH_MEMORY :: HIF_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_HIF_INST_POWER_SWITCH_MEMORY_HIF_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE - Memsys 32 1 inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE :: DDR1_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_32_1_INST_MEMORY_STANDBY_ENABLE_DDR1_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO - Vec aio top inst power switch memory aio
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO :: AIO_POWER_SWITCH_MEMORY_AIO [01:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_MASK 0x00000003
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_AIO_AIO_POWER_SWITCH_MEMORY_AIO_DEFAULT 0

/***************************************************************************
 *HIF_INST_OBSERVE_CLOCK - Hif inst observe clock
 ***************************************************************************/
/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_MASK          0xffffffc0
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_reserved0_SHIFT         6

/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: HIF_INST_OBSERVE_CLOCK :: HIF_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_HIF_INST_OBSERVE_CLOCK_HIF_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *V3D_TOP_INST_CLOCK_ENABLE - V3D_TOP inst clock enable
 ***************************************************************************/
/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT      2

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: V3D_TOP_INST_CLOCK_ENABLE :: V3D_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_V3D_TOP_INST_CLOCK_ENABLE_V3D_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *MOCA_TOP_INST_MEMORY_STANDBY_ENABLE - Moca top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: MOCA_TOP_INST_MEMORY_STANDBY_ENABLE :: MOCA_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MOCA_TOP_INST_MEMORY_STANDBY_ENABLE_MOCA_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *SVD0_TOP_INST_POWER_SWITCH_MEMORY - Svd0 top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: SVD0_TOP_INST_POWER_SWITCH_MEMORY :: SVD0_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD0_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD0_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_SVD0_TOP_INST_POWER_SWITCH_MEMORY_SVD0_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT - Dual genet top dual rgmii inst clock select
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: reserved0 [31:04] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_reserved0_MASK 0xfffffff0
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_reserved0_SHIFT 4

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET1_GMII_CLOCK_SELECT [03:03] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_MASK 0x00000008
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_SHIFT 3
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_GMII_CLOCK_SELECT_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET1_CLOCK_SELECT [02:02] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_MASK 0x00000004
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_SHIFT 2
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET1_CLOCK_SELECT_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET0_GMII_CLOCK_SELECT [01:01] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_MASK 0x00000002
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_SHIFT 1
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_GMII_CLOCK_SELECT_DEFAULT 0

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT :: GENET0_CLOCK_SELECT [00:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_MASK 0x00000001
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_SELECT_GENET0_CLOCK_SELECT_DEFAULT 0

/***************************************************************************
 *ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE - Zcpu top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE :: ZMIPS_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE_ZMIPS_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE_ZMIPS_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_ZCPU_TOP_INST_MEMORY_STANDBY_ENABLE_ZMIPS_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *UHFR_TOP_INST_POWER_SWITCH_MEMORY - Uhfr top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: UHFR_TOP_INST_POWER_SWITCH_MEMORY :: UHFR_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_UHFR_TOP_INST_POWER_SWITCH_MEMORY_UHFR_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC - Vec aio top inst power switch memory vec
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_reserved0_SHIFT 2

/* CLKGEN :: VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC :: VEC_POWER_SWITCH_MEMORY_VEC [01:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_MASK 0x00000003
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_POWER_SWITCH_MEMORY_VEC_VEC_POWER_SWITCH_MEMORY_VEC_DEFAULT 0

/***************************************************************************
 *DVP_HR_INST_MEMORY_STANDBY_ENABLE - Dvp hr inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: DVP_HR_INST_MEMORY_STANDBY_ENABLE :: DVPHR_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HR_INST_MEMORY_STANDBY_ENABLE_DVPHR_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *SATA3_TOP_INST_OBSERVE_CLOCK - Sata3 top inst observe clock
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_MASK    0xffffffc0
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT   6

/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SATA3_TOP_INST_OBSERVE_CLOCK :: SATA3_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_INST_OBSERVE_CLOCK_SATA3_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *USB0_INST_MEMORY_STANDBY_ENABLE - Usb0 inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: USB0_INST_MEMORY_STANDBY_ENABLE :: USB0_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USB0_INST_MEMORY_STANDBY_ENABLE_USB0_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC - Vec aio top inst memory standby enable vec
 ***************************************************************************/
/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: reserved0 [31:01] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_reserved0_SHIFT 1

/* CLKGEN :: VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC :: VEC_MEMORY_STANDBY_ENABLE_VEC [00:00] */
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_MASK 0x00000001
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_SHIFT 0
#define BCHP_CLKGEN_VEC_AIO_TOP_INST_MEMORY_STANDBY_ENABLE_VEC_VEC_MEMORY_STANDBY_ENABLE_VEC_DEFAULT 0

/***************************************************************************
 *DVP_HR_INST_CLOCK_ENABLE - Dvp hr inst clock enable
 ***************************************************************************/
/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: reserved0 [31:05] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_MASK        0xffffffe0
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_reserved0_SHIFT       5

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_CLK_324_ENABLE [04:04] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_CLK_324_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_CLK_324_ENABLE_SHIFT 4
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_CLK_324_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_ALTERNATE_216_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_ALTERNATE_108_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_108_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_108_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_ALTERNATE_108_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_216_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_216_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DVP_HR_INST_CLOCK_ENABLE :: DVPHR_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DVP_HR_INST_CLOCK_ENABLE_DVPHR_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *DVP_HT_INST_POWER_SWITCH_MEMORY - Dvp ht inst power switch memory
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: DVP_HT_INST_POWER_SWITCH_MEMORY :: DVPHT_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_POWER_SWITCH_MEMORY_DVPHT_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE - Dual genet top dual rgmii inst clock enable
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: reserved0 [31:16] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_MASK 0xffff0000
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_reserved0_SHIFT 16

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_SCB_CLOCK_ENABLE [15:15] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_MASK 0x00008000
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_SHIFT 15
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET_108_CLOCK_ENABLE [14:14] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_MASK 0x00004000
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_SHIFT 14
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET_108_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE [13:13] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00002000
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 13
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE [12:12] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00001000
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 12
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_L2INTR_CLOCK_ENABLE [11:11] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_MASK 0x00000800
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_SHIFT 11
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_L2INTR_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_HFB_CLOCK_ENABLE [10:10] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_MASK 0x00000400
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_SHIFT 10
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_HFB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_GMII_CLOCK_ENABLE [09:09] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_MASK 0x00000200
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_SHIFT 9
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_GMII_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_EEE_CLOCK_ENABLE [08:08] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_MASK 0x00000100
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_SHIFT 8
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_EEE_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET1_CLK_250_CLOCK_ENABLE [07:07] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_MASK 0x00000080
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_SHIFT 7
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET1_CLK_250_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE [06:06] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_MASK 0x00000040
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_SHIFT 6
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_TX_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE [05:05] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_MASK 0x00000020
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_SHIFT 5
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_UNIMAC_SYS_RX_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_L2INTR_CLOCK_ENABLE [04:04] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_MASK 0x00000010
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_SHIFT 4
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_L2INTR_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_HFB_CLOCK_ENABLE [03:03] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_MASK 0x00000008
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_SHIFT 3
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_HFB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_GMII_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_GMII_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_EEE_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_EEE_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE :: GENET0_CLK_250_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_ENABLE_GENET0_CLK_250_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *SATA3_TOP_INST_POWER_SWITCH_MEMORY - Sata3 top inst power switch memory
 ***************************************************************************/
/* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: SATA3_TOP_INST_POWER_SWITCH_MEMORY :: SATA3_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_SATA3_TOP_INST_POWER_SWITCH_MEMORY_SATA3_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *MOCA_TOP_INST_CLOCK_ENABLE - Moca top inst clock enable
 ***************************************************************************/
/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     2

/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: MOCA_TOP_INST_CLOCK_ENABLE :: MOCA_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_MOCA_TOP_INST_CLOCK_ENABLE_MOCA_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY - BVN_MCVP_TOP inst power switch memory
 ***************************************************************************/
/* CLKGEN :: BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY :: reserved0 [31:02] */
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY_reserved0_SHIFT 2

/* CLKGEN :: BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY :: BVN_MCVP_TOP_POWER_SWITCH_MEMORY [01:00] */
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY_BVN_MCVP_TOP_POWER_SWITCH_MEMORY_MASK 0x00000003
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY_BVN_MCVP_TOP_POWER_SWITCH_MEMORY_SHIFT 0
#define BCHP_CLKGEN_BVN_MCVP_TOP_INST_POWER_SWITCH_MEMORY_BVN_MCVP_TOP_POWER_SWITCH_MEMORY_DEFAULT 0

/***************************************************************************
 *SYS_AON_INST_OBSERVE_CLOCK - Sys aon inst observe clock
 ***************************************************************************/
/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_MASK      0xffffffc0
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_reserved0_SHIFT     6

/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: SYS_AON_INST_OBSERVE_CLOCK :: UPG_AON_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_SYS_AON_INST_OBSERVE_CLOCK_UPG_AON_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *BVN_TOP_INST_MEMORY_STANDBY_ENABLE - Bvn top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: BVN_TOP_INST_MEMORY_STANDBY_ENABLE :: BVN_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_BVN_TOP_INST_MEMORY_STANDBY_ENABLE_BVN_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *PAD_VCXO27_OBSERVATION - Select observation clk
 ***************************************************************************/
/* CLKGEN :: PAD_VCXO27_OBSERVATION :: reserved0 [31:09] */
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_MASK          0xfffffe00
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_reserved0_SHIFT         9

/* CLKGEN :: PAD_VCXO27_OBSERVATION :: SELECT_OBSERVE_CLK [08:08] */
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_MASK 0x00000100
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_SHIFT 8
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_SELECT_OBSERVE_CLK_DEFAULT 0

/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_MUX_SELECT [07:01] */
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_MASK 0x000000fe
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_SHIFT 1
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_MUX_SELECT_DEFAULT 0

/* CLKGEN :: PAD_VCXO27_OBSERVATION :: OBSERVE_DIV_ENABLE [00:00] */
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_SHIFT 0
#define BCHP_CLKGEN_PAD_VCXO27_OBSERVATION_OBSERVE_DIV_ENABLE_DEFAULT 0

/***************************************************************************
 *USB1_INST_CLOCK_ENABLE - Usb1 inst clock enable
 ***************************************************************************/
/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_MASK          0xfffffffc
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_reserved0_SHIFT         2

/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_SCB_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: USB1_INST_CLOCK_ENABLE :: USB1_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_USB1_INST_CLOCK_ENABLE_USB1_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *SVD0_TOP_INST_MEMORY_STANDBY_ENABLE - Svd0 top inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: SVD0_TOP_INST_MEMORY_STANDBY_ENABLE :: SVD0_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD0_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD0_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SVD0_TOP_INST_MEMORY_STANDBY_ENABLE_SVD0_MEMORY_STANDBY_ENABLE_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A - Dual genet top dual rgmii inst power switch memory a
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A :: reserved0 [31:02] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_MASK 0xfffffffc
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_reserved0_SHIFT 2

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A :: GENET0_POWER_SWITCH_MEMORY_A [01:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_MASK 0x00000003
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_POWER_SWITCH_MEMORY_A_GENET0_POWER_SWITCH_MEMORY_A_DEFAULT 0

/***************************************************************************
 *DVP_HT_INST_OBSERVE_CLOCK - Dvp ht inst observe clock
 ***************************************************************************/
/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_MASK       0xffffffc0
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_reserved0_SHIFT      6

/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: DVP_HT_INST_OBSERVE_CLOCK :: DVPHT_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_DVP_HT_INST_OBSERVE_CLOCK_DVPHT_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *SECTOP_INST_CLOCK_ENABLE_M2MDMA - Sectop inst clock enable
 ***************************************************************************/
/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: reserved0 [31:01] */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_reserved0_SHIFT 1

/* CLKGEN :: SECTOP_INST_CLOCK_ENABLE_M2MDMA :: M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA [00:00] */
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_MASK 0x00000001
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_SHIFT 0
#define BCHP_CLKGEN_SECTOP_INST_CLOCK_ENABLE_M2MDMA_M2MDMA_ALTERNATE_SCB_CLOCK_ENABLE_M2MDMA_DEFAULT 1

/***************************************************************************
 *SECTOP_INST_MEMORY_STANDBY_ENABLE - Sectop inst memory standby enable
 ***************************************************************************/
/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_reserved0_SHIFT 1

/* CLKGEN :: SECTOP_INST_MEMORY_STANDBY_ENABLE :: SEC_MEMORY_STANDBY_ENABLE [00:00] */
#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_SHIFT 0
#define BCHP_CLKGEN_SECTOP_INST_MEMORY_STANDBY_ENABLE_SEC_MEMORY_STANDBY_ENABLE_DEFAULT 1

/***************************************************************************
 *ZCPU_TOP_INST_CLOCK_ENABLE - Zcpu top inst clock enable
 ***************************************************************************/
/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_reserved0_MASK      0xfffffffe
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT     1

/* CLKGEN :: ZCPU_TOP_INST_CLOCK_ENABLE :: ZMIPS_SCB_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_ZCPU_TOP_INST_CLOCK_ENABLE_ZMIPS_SCB_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *RAAGA_DSP_TOP_INST_CLOCK_ENABLE - Raaga dsp top inst clock enable
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: reserved0 [31:03] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_MASK 0xfffffff8
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_reserved0_SHIFT 3

/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_SCB_CLOCK_ENABLE [02:02] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_MASK 0x00000004
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_SHIFT 2
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_SCB_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_DSP_CLOCK_ENABLE [01:01] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_MASK 0x00000002
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_SHIFT 1
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_DSP_CLOCK_ENABLE_DEFAULT 1

/* CLKGEN :: RAAGA_DSP_TOP_INST_CLOCK_ENABLE :: RAAGA_108_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_CLOCK_ENABLE_RAAGA_108_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *PLL_MIPS_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_MASK          0x00000002
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_SHIFT         1
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETD_DEFAULT       1

/* CLKGEN :: PLL_MIPS_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_MASK          0x00000001
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_SHIFT         0
#define BCHP_CLKGEN_PLL_MIPS_PLL_RESET_STATUS_RESETA_DEFAULT       1

/***************************************************************************
 *PLL_AUDIO0_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_reserved0_SHIFT    2

/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_MASK        0x00000002
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_SHIFT       1
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETD_DEFAULT     1

/* CLKGEN :: PLL_AUDIO0_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_MASK        0x00000001
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_SHIFT       0
#define BCHP_CLKGEN_PLL_AUDIO0_PLL_RESET_STATUS_RESETA_DEFAULT     1

/***************************************************************************
 *PLL_AUDIO1_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_reserved0_SHIFT    2

/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_MASK        0x00000002
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_SHIFT       1
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETD_DEFAULT     1

/* CLKGEN :: PLL_AUDIO1_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_MASK        0x00000001
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_SHIFT       0
#define BCHP_CLKGEN_PLL_AUDIO1_PLL_RESET_STATUS_RESETA_DEFAULT     1

/***************************************************************************
 *PLL_AUDIO2_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_MASK     0xfffffffc
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_reserved0_SHIFT    2

/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_RESETD_MASK        0x00000002
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_RESETD_SHIFT       1
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_RESETD_DEFAULT     1

/* CLKGEN :: PLL_AUDIO2_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_RESETA_MASK        0x00000001
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_RESETA_SHIFT       0
#define BCHP_CLKGEN_PLL_AUDIO2_PLL_RESET_STATUS_RESETA_DEFAULT     1

/***************************************************************************
 *PLL_AVD1_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_AVD1_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_AVD1_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_RESETD_MASK          0x00000002
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_RESETD_SHIFT         1
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_RESETD_DEFAULT       1

/* CLKGEN :: PLL_AVD1_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_RESETA_MASK          0x00000001
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_RESETA_SHIFT         0
#define BCHP_CLKGEN_PLL_AVD1_PLL_RESET_STATUS_RESETA_DEFAULT       1

/***************************************************************************
 *PLL_VCXO2_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_RESETD_MASK         0x00000002
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_RESETD_SHIFT        1
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_RESETD_DEFAULT      1

/* CLKGEN :: PLL_VCXO2_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_RESETA_MASK         0x00000001
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_RESETA_SHIFT        0
#define BCHP_CLKGEN_PLL_VCXO2_PLL_RESET_STATUS_RESETA_DEFAULT      1

/***************************************************************************
 *PLL_MOCA_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_MASK       0xfffffffc
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_reserved0_SHIFT      2

/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_MASK          0x00000002
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_SHIFT         1
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETD_DEFAULT       1

/* CLKGEN :: PLL_MOCA_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_MASK          0x00000001
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_SHIFT         0
#define BCHP_CLKGEN_PLL_MOCA_PLL_RESET_STATUS_RESETA_DEFAULT       1

/***************************************************************************
 *PLL_VCXO1_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_RESETD_MASK         0x00000002
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_RESETD_SHIFT        1
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_RESETD_DEFAULT      1

/* CLKGEN :: PLL_VCXO1_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_RESETA_MASK         0x00000001
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_RESETA_SHIFT        0
#define BCHP_CLKGEN_PLL_VCXO1_PLL_RESET_STATUS_RESETA_DEFAULT      1

/***************************************************************************
 *PLL_HIF_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_HIF_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_reserved0_MASK        0xfffffffc
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_reserved0_SHIFT       2

/* CLKGEN :: PLL_HIF_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_RESETD_MASK           0x00000002
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_RESETD_SHIFT          1
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_RESETD_DEFAULT        1

/* CLKGEN :: PLL_HIF_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_RESETA_MASK           0x00000001
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_RESETA_SHIFT          0
#define BCHP_CLKGEN_PLL_HIF_PLL_RESET_STATUS_RESETA_DEFAULT        1

/***************************************************************************
 *PLL_RAAGA_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_MASK         0x00000002
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_SHIFT        1
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETD_DEFAULT      1

/* CLKGEN :: PLL_RAAGA_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_MASK         0x00000001
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_SHIFT        0
#define BCHP_CLKGEN_PLL_RAAGA_PLL_RESET_STATUS_RESETA_DEFAULT      1

/***************************************************************************
 *PLL_NETWORK_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_MASK    0xfffffffc
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_reserved0_SHIFT   2

/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_RESETD_MASK       0x00000002
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_RESETD_SHIFT      1
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_RESETD_DEFAULT    1

/* CLKGEN :: PLL_NETWORK_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_RESETA_MASK       0x00000001
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_RESETA_SHIFT      0
#define BCHP_CLKGEN_PLL_NETWORK_PLL_RESET_STATUS_RESETA_DEFAULT    1

/***************************************************************************
 *PLL_VCXO0_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_MASK      0xfffffffc
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_reserved0_SHIFT     2

/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_RESETD_MASK         0x00000002
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_RESETD_SHIFT        1
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_RESETD_DEFAULT      1

/* CLKGEN :: PLL_VCXO0_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_RESETA_MASK         0x00000001
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_RESETA_SHIFT        0
#define BCHP_CLKGEN_PLL_VCXO0_PLL_RESET_STATUS_RESETA_DEFAULT      1

/***************************************************************************
 *PLL_SC_PLL_RESET_STATUS - Resets status
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: RESETD [01:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_MASK            0x00000002
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_SHIFT           1
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETD_DEFAULT         1

/* CLKGEN :: PLL_SC_PLL_RESET_STATUS :: RESETA [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_MASK            0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_SHIFT           0
#define BCHP_CLKGEN_PLL_SC_PLL_RESET_STATUS_RESETA_DEFAULT         1

/***************************************************************************
 *MEMSYS_0_32_POWER_MANAGEMENT - Memsys_0 32 power management
 ***************************************************************************/
/* CLKGEN :: MEMSYS_0_32_POWER_MANAGEMENT :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_reserved0_SHIFT   1

/* CLKGEN :: MEMSYS_0_32_POWER_MANAGEMENT :: MEMSYS_PLL_PWRDN_POWER_MANAGEMENT [00:00] */
#define BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_DEFAULT 0

/***************************************************************************
 *MEMSYS_1_32_POWER_MANAGEMENT - Memsys_1 32 power management
 ***************************************************************************/
/* CLKGEN :: MEMSYS_1_32_POWER_MANAGEMENT :: reserved0 [31:01] */
#define BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT_reserved0_MASK    0xfffffffe
#define BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT_reserved0_SHIFT   1

/* CLKGEN :: MEMSYS_1_32_POWER_MANAGEMENT :: MEMSYS_PLL_PWRDN_POWER_MANAGEMENT [00:00] */
#define BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK 0x00000001
#define BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_SHIFT 0
#define BCHP_CLKGEN_MEMSYS_1_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_DEFAULT 0

/***************************************************************************
 *PM_PLL_ALIVE_SEL - pll alive in standby mode
 ***************************************************************************/
/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:04] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff0
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               4

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_DDR1 [03:03] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR1_MASK                 0x00000008
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR1_SHIFT                3
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR1_DEFAULT              0

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_DDR0 [02:02] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR0_MASK                 0x00000004
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR0_SHIFT                2
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_DDR0_DEFAULT              0

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_MIPS [01:01] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_MASK                 0x00000002
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_SHIFT                1
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_MIPS_DEFAULT              0

/* CLKGEN :: PM_PLL_ALIVE_SEL :: PLL_SYS0 [00:00] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_MASK                 0x00000001
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_SHIFT                0
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_PLL_SYS0_DEFAULT              0

/***************************************************************************
 *SPI_CLOCK_SELECT - spi clock control
 ***************************************************************************/
/* CLKGEN :: SPI_CLOCK_SELECT :: reserved0 [31:03] */
#define BCHP_CLKGEN_SPI_CLOCK_SELECT_reserved0_MASK                0xfffffff8
#define BCHP_CLKGEN_SPI_CLOCK_SELECT_reserved0_SHIFT               3

/* CLKGEN :: SPI_CLOCK_SELECT :: SPI_CLOCK_FREQ_SEL [02:01] */
#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_MASK       0x00000006
#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_SHIFT      1
#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_FREQ_SEL_DEFAULT    0

/* CLKGEN :: SPI_CLOCK_SELECT :: SPI_CLOCK_OVERRIDE_STRAP [00:00] */
#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_MASK 0x00000001
#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_SHIFT 0
#define BCHP_CLKGEN_SPI_CLOCK_SELECT_SPI_CLOCK_OVERRIDE_STRAP_DEFAULT 0

/***************************************************************************
 *PLL_DDR_PLL_LOCK_STATUS - Lock Status
 ***************************************************************************/
/* CLKGEN :: PLL_DDR_PLL_LOCK_STATUS :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_reserved0_SHIFT        2

/* CLKGEN :: PLL_DDR_PLL_LOCK_STATUS :: DDR1_LOCK [01:01] */
#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR1_LOCK_MASK         0x00000002
#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR1_LOCK_SHIFT        1

/* CLKGEN :: PLL_DDR_PLL_LOCK_STATUS :: DDR0_LOCK [00:00] */
#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR0_LOCK_MASK         0x00000001
#define BCHP_CLKGEN_PLL_DDR_PLL_LOCK_STATUS_DDR0_LOCK_SHIFT        0

/***************************************************************************
 *PLL_MIPS_CTRL - Mips PLL Control Register
 ***************************************************************************/
/* CLKGEN :: PLL_MIPS_CTRL :: reserved0 [31:31] */
#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved0_MASK                   0x80000000
#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved0_SHIFT                  31

/* CLKGEN :: PLL_MIPS_CTRL :: BYPASS_PLL_RQ [30:30] */
#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_MASK               0x40000000
#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_SHIFT              30
#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_RQ_DEFAULT            0

/* CLKGEN :: PLL_MIPS_CTRL :: BYPASS_PLL_STATE [29:29] */
#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_MASK            0x20000000
#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_SHIFT           29
#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_DEFAULT         0
#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_normal_PLL_mode 0
#define BCHP_CLKGEN_PLL_MIPS_CTRL_BYPASS_PLL_STATE_bypassed_PLL_mode 1

/* union - case normal_PLL_mode [28:23] */
/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: A_RST_PLL [28:28] */
#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_MASK   0x10000000
#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_SHIFT  28
#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_A_RST_PLL_DEFAULT 0

/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: D_RST_PLL [27:27] */
#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_MASK   0x08000000
#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_SHIFT  27
#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_D_RST_PLL_DEFAULT 0

/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: CPU_FREQ [26:24] */
#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_MASK    0x07000000
#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_SHIFT   24
#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_CPU_FREQ_DEFAULT 0

/* CLKGEN :: PLL_MIPS_CTRL :: normal_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [23:23] */
#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00800000
#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 23
#define BCHP_CLKGEN_PLL_MIPS_CTRL_normal_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_DEFAULT 0

/* union - case bypassed_PLL_mode [28:23] */
/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: A_RST_PLL [28:28] */
#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_MASK 0x10000000
#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_SHIFT 28
#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_A_RST_PLL_DEFAULT 0

/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: D_RST_PLL [27:27] */
#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_MASK 0x08000000
#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_SHIFT 27
#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_D_RST_PLL_DEFAULT 0

/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: CPU_FREQ [26:24] */
#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_MASK  0x07000000
#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_SHIFT 24
#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_CPU_FREQ_DEFAULT 0

/* CLKGEN :: PLL_MIPS_CTRL :: bypassed_PLL_mode :: OVERRIDE_CPU_FREQ_PIN_STRAP [23:23] */
#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_MASK 0x00800000
#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_SHIFT 23
#define BCHP_CLKGEN_PLL_MIPS_CTRL_bypassed_PLL_mode_OVERRIDE_CPU_FREQ_PIN_STRAP_DEFAULT 0

/* CLKGEN :: PLL_MIPS_CTRL :: reserved1 [22:00] */
#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved1_MASK                   0x007fffff
#define BCHP_CLKGEN_PLL_MIPS_CTRL_reserved1_SHIFT                  0

/***************************************************************************
 *SCRATCH1 - clkgen  Scratch register
 ***************************************************************************/
/* CLKGEN :: SCRATCH1 :: VALUE [31:00] */
#define BCHP_CLKGEN_SCRATCH1_VALUE_MASK                            0xffffffff
#define BCHP_CLKGEN_SCRATCH1_VALUE_SHIFT                           0
#define BCHP_CLKGEN_SCRATCH1_VALUE_DEFAULT                         0

/***************************************************************************
 *V3D_TOP_INST_V3D_CLOCK_ENABLE - V3d_top inst V3D clock enable
 ***************************************************************************/
/* CLKGEN :: V3D_TOP_INST_V3D_CLOCK_ENABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE_reserved0_MASK   0xfffffffe
#define BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE_reserved0_SHIFT  1

/* CLKGEN :: V3D_TOP_INST_V3D_CLOCK_ENABLE :: V3D_CLOCK_ENABLE [00:00] */
#define BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE_V3D_CLOCK_ENABLE_MASK 0x00000001
#define BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE_V3D_CLOCK_ENABLE_SHIFT 0
#define BCHP_CLKGEN_V3D_TOP_INST_V3D_CLOCK_ENABLE_V3D_CLOCK_ENABLE_DEFAULT 1

/***************************************************************************
 *SCRATCH2 - clkgen  Scratch register
 ***************************************************************************/
/* CLKGEN :: SCRATCH2 :: VALUE [31:00] */
#define BCHP_CLKGEN_SCRATCH2_VALUE_MASK                            0xffffffff
#define BCHP_CLKGEN_SCRATCH2_VALUE_SHIFT                           0
#define BCHP_CLKGEN_SCRATCH2_VALUE_DEFAULT                         0

/***************************************************************************
 *PLL_SC_PLL_CHANNEL_CTRL_CH_1 - PLL CHANNEL control CH 1
 ***************************************************************************/
/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_MASK    0xffffc000
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_reserved0_SHIFT   14

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: MDIV_CH1 [13:06] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_MASK     0x00003fc0
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_SHIFT    6
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_MDIV_CH1_DEFAULT  48

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_LOAD_EN_CH1 [05:05] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_MASK 0x00000020
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_SHIFT 5
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_LOAD_EN_CH1_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: POST_DIVIDER_HOLD_CH1 [04:04] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_MASK 0x00000010
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_SHIFT 4
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_POST_DIVIDER_HOLD_CH1_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: PHASE_OFFSET_CH1 [03:01] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_MASK 0x0000000e
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_SHIFT 1
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_PHASE_OFFSET_CH1_DEFAULT 0

/* CLKGEN :: PLL_SC_PLL_CHANNEL_CTRL_CH_1 :: CLOCK_DIS_CH1 [00:00] */
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_MASK 0x00000001
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_SHIFT 0
#define BCHP_CLKGEN_PLL_SC_PLL_CHANNEL_CTRL_CH_1_CLOCK_DIS_CH1_DEFAULT 0

/***************************************************************************
 *SATA3_INST_CLOCK_DISABLE - Disable SATA3_TOP_INST's clocks
 ***************************************************************************/
/* CLKGEN :: SATA3_INST_CLOCK_DISABLE :: reserved0 [31:01] */
#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_reserved0_MASK        0xfffffffe
#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_reserved0_SHIFT       1

/* CLKGEN :: SATA3_INST_CLOCK_DISABLE :: DISABLE_27_FUNC_CLK_30 [00:00] */
#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_MASK 0x00000001
#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_SHIFT 0
#define BCHP_CLKGEN_SATA3_INST_CLOCK_DISABLE_DISABLE_27_FUNC_CLK_30_DEFAULT 1

/***************************************************************************
 *RAAGA_DSP_TOP_INST_OBSERVE_CLOCK - Raaga Dsp top inst observe clock
 ***************************************************************************/
/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: reserved0 [31:06] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_MASK 0xffffffc0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_reserved0_SHIFT 6

/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_OBSERVE_CLOCK [05:05] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_MASK 0x00000020
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_SHIFT 5
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK [04:04] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_MASK 0x00000010
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_SHIFT 4
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_ENABLE_DIVIDER_OBSERVE_CLOCK_DEFAULT 0

/* CLKGEN :: RAAGA_DSP_TOP_INST_OBSERVE_CLOCK :: RAAGA_CONTROL_OBSERVE_CLOCK [03:00] */
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_MASK 0x0000000f
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_SHIFT 0
#define BCHP_CLKGEN_RAAGA_DSP_TOP_INST_OBSERVE_CLOCK_RAAGA_CONTROL_OBSERVE_CLOCK_DEFAULT 0

/***************************************************************************
 *CLOCK_MONITOR_CONTROL - Clock Monitor Control
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_CONTROL :: reserved0 [31:04] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_MASK           0xfffffff0
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_reserved0_SHIFT          4

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_VIEW_COUNTER [03:03] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_MASK   0x00000008
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_SHIFT  3
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_VIEW_COUNTER_DEFAULT 1

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: STOP_REF_COUNTER [02:02] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_MASK    0x00000004
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_SHIFT   2
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_STOP_REF_COUNTER_DEFAULT 1

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: RESET_COUNTERS [01:01] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_MASK      0x00000002
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_SHIFT     1
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_RESET_COUNTERS_DEFAULT   1

/* CLKGEN :: CLOCK_MONITOR_CONTROL :: LAUNCH_AUTO_REF_COUNT [00:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_MASK 0x00000001
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_SHIFT 0
#define BCHP_CLKGEN_CLOCK_MONITOR_CONTROL_LAUNCH_AUTO_REF_COUNT_DEFAULT 1

/***************************************************************************
 *CLOCK_MONITOR_MAX_COUNT - Clock Monitor Max Reference Count
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_MAX_COUNT :: SET_MAX_REF_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_MASK 0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_SHIFT 0
#define BCHP_CLKGEN_CLOCK_MONITOR_MAX_COUNT_SET_MAX_REF_COUNT_DEFAULT 4294967295

/***************************************************************************
 *CLOCK_MONITOR_REF_COUNTER - Clock Monitor Reference Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_REF_COUNTER :: READ_MAX_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_MASK  0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_COUNTER_READ_MAX_COUNT_SHIFT 0

/***************************************************************************
 *CLOCK_MONITOR_REF_DONE - Clock Monitor Reference Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: reserved0 [31:01] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_MASK          0xfffffffe
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_reserved0_SHIFT         1

/* CLKGEN :: CLOCK_MONITOR_REF_DONE :: REF_COUNT_DONE [00:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_MASK     0x00000001
#define BCHP_CLKGEN_CLOCK_MONITOR_REF_DONE_REF_COUNT_DONE_SHIFT    0

/***************************************************************************
 *CLOCK_MONITOR_VIEW_COUNTER - Clock Monitor View Counter
 ***************************************************************************/
/* CLKGEN :: CLOCK_MONITOR_VIEW_COUNTER :: READ_MAX_COUNT [31:00] */
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_MASK 0xffffffff
#define BCHP_CLKGEN_CLOCK_MONITOR_VIEW_COUNTER_READ_MAX_COUNT_SHIFT 0

/***************************************************************************
 *PM_PLL_LDO_POWERUP - Power management LDO PLL
 ***************************************************************************/
/* CLKGEN :: PM_PLL_LDO_POWERUP :: reserved0 [31:04] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_MASK              0xfffffff0
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_reserved0_SHIFT             4

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_MOCA [03:03] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_MASK     0x00000008
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_SHIFT    3
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_MOCA_DEFAULT  1

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_RAAGA [02:02] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_MASK    0x00000004
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_SHIFT   2
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_RAAGA_DEFAULT 1

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_NETWORK [01:01] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_MASK  0x00000002
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_SHIFT 1
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_NETWORK_DEFAULT 1

/* CLKGEN :: PM_PLL_LDO_POWERUP :: ISO_CLOCK_PLL_AVD [00:00] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_MASK      0x00000001
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_SHIFT     0
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_ISO_CLOCK_PLL_AVD_DEFAULT   1

/***************************************************************************
 *PM_PLL_LDO_POWERUP_SM - Power management LDO PLL state machine
 ***************************************************************************/
/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: reserved0 [31:27] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_MASK           0xf8000000
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_reserved0_SHIFT          27

/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_POWERUP_WAIT_TIME [26:14] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_MASK 0x07ffc000
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_SHIFT 14
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_POWERUP_WAIT_TIME_DEFAULT 5400

/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: PLL_CLK_STOP_WAIT_TIME [13:01] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_MASK 0x00003ffe
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_SHIFT 1
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_PLL_CLK_STOP_WAIT_TIME_DEFAULT 200

/* CLKGEN :: PM_PLL_LDO_POWERUP_SM :: GISB_OVERRIDE_SM [00:00] */
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_MASK    0x00000001
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_SHIFT   0
#define BCHP_CLKGEN_PM_PLL_LDO_POWERUP_SM_GISB_OVERRIDE_SM_DEFAULT 0

/***************************************************************************
 *DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS - Bypass GENET_TOP_DUAL_RGMII_INST's cl;ocks
 ***************************************************************************/
/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: reserved0 [31:01] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_MASK 0xfffffffe
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_reserved0_SHIFT 1

/* CLKGEN :: DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS :: EEE_25_CLOCK_BYPASS [00:00] */
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_MASK 0x00000001
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_SHIFT 0
#define BCHP_CLKGEN_DUAL_GENET_TOP_DUAL_RGMII_INST_CLOCK_BYPASS_EEE_25_CLOCK_BYPASS_DEFAULT 0

#endif /* #ifndef BCHP_CLKGEN_H__ */

/* End of File */