/***************************************************************************
 *     Copyright (c) 1999-2010, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Wed Aug  4 16:28:20 2010
 *                 MD5 Checksum         27c5a1259680e8176595e9e88d9958c6
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7408/rdb/b0/bchp_vcxo_ctl_misc.h $
 * 
 * Hydra_Software_Devel/1   8/4/10 10:04p pntruong
 * SW7408-118: Initial version.
 *
 ***************************************************************************/

#ifndef BCHP_VCXO_CTL_MISC_H__
#define BCHP_VCXO_CTL_MISC_H__

/***************************************************************************
 *VCXO_CTL_MISC - VCXO Core Registers
 ***************************************************************************/
#define BCHP_VCXO_CTL_MISC_VC0_CTRL              0x00462800 /* VCXO 0 PLL reset, ndiv_mode, powerdown */
#define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1    0x00462804 /* VCXO 0  clock outputs enable */
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1      0x00462808 /* VCXO 0 channel 1 powerdown post divider */
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2      0x0046280c /* VCXO 0 channel 2 powerdown post divider */
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3      0x00462810 /* VCXO 0 channel 3 powerdown post divider */
#define BCHP_VCXO_CTL_MISC_AC0_CTRL              0x00462818 /* Audio PLL 0 reset and powerdown */
#define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1    0x0046281c /* Audio PLL 0  clock outputs enable */
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1      0x00462820 /* Audio PLL 0 channel 1 powerdown post divider */
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2      0x00462824 /* Audio PLL 0 channel 2 powerdown post divider */
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3      0x00462828 /* Audio PLL 0 channel 3 powerdown post divider */
#define BCHP_VCXO_CTL_MISC_LOCK                  0x0046289c /* VCXO core lock status */
#define BCHP_VCXO_CTL_MISC_VC0_DIV               0x004628a0 /* VCXO 0 PLL divider settings */
#define BCHP_VCXO_CTL_MISC_VCXO_CTLBUS_HI        0x004628a4 /* VCXO PLL control bus higher word */
#define BCHP_VCXO_CTL_MISC_VCXO_CTLBUS_LO        0x004628a8 /* VCXO PLL control bus lower word */
#define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET       0x004628c0 /* VCXO Lock Counter Reset */
#define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT          0x004628c4 /* VCXO 0 PLL Lock Counter */
#define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT          0x004628c8 /* Audio PLL 0 Lock Counter */
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL          0x004628ec /* TOP LEVEL PLLs test select */

/***************************************************************************
 *VC0_CTRL - VCXO 0 PLL reset, ndiv_mode, powerdown
 ***************************************************************************/
/* VCXO_CTL_MISC :: VC0_CTRL :: reserved0 [31:07] */
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_reserved0_MASK                 0xffffff80
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_reserved0_SHIFT                7

/* VCXO_CTL_MISC :: VC0_CTRL :: NDIV_MODE [06:04] */
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_NDIV_MODE_MASK                 0x00000070
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_NDIV_MODE_SHIFT                4

/* VCXO_CTL_MISC :: VC0_CTRL :: POWERDOWN [03:03] */
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_MASK                 0x00000008
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_SHIFT                3
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_Powerdown            1
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_POWERDOWN_Normal               0

/* VCXO_CTL_MISC :: VC0_CTRL :: RESERVED [02:02] */
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_RESERVED_MASK                  0x00000004
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_RESERVED_SHIFT                 2

/* VCXO_CTL_MISC :: VC0_CTRL :: DRESET [01:01] */
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_MASK                    0x00000002
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_SHIFT                   1
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_Reset                   1
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_DRESET_Normal                  0

/* VCXO_CTL_MISC :: VC0_CTRL :: ARESET [00:00] */
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_MASK                    0x00000001
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_SHIFT                   0
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_Reset                   1
#define BCHP_VCXO_CTL_MISC_VC0_CTRL_ARESET_Normal                  0

/***************************************************************************
 *VC0_PM_CLOCK_ENA_1 - VCXO 0  clock outputs enable
 ***************************************************************************/
/* VCXO_CTL_MISC :: VC0_PM_CLOCK_ENA_1 :: reserved0 [31:01] */
#define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1_reserved0_MASK       0xfffffffe
#define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1_reserved0_SHIFT      1

/* VCXO_CTL_MISC :: VC0_PM_CLOCK_ENA_1 :: CLOCK_ENA [00:00] */
#define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1_CLOCK_ENA_MASK       0x00000001
#define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1_CLOCK_ENA_SHIFT      0
#define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1_CLOCK_ENA_Enable     1
#define BCHP_VCXO_CTL_MISC_VC0_PM_CLOCK_ENA_1_CLOCK_ENA_Disable    0

/***************************************************************************
 *VC0_PM_DIS_CHL_1 - VCXO 0 channel 1 powerdown post divider
 ***************************************************************************/
/* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_1 :: reserved0 [31:01] */
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_reserved0_MASK         0xfffffffe
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_reserved0_SHIFT        1

/* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_1 :: DIS_CH [00:00] */
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_DIS_CH_MASK            0x00000001
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_1_DIS_CH_SHIFT           0

/***************************************************************************
 *VC0_PM_DIS_CHL_2 - VCXO 0 channel 2 powerdown post divider
 ***************************************************************************/
/* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_2 :: reserved0 [31:01] */
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2_reserved0_MASK         0xfffffffe
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2_reserved0_SHIFT        1

/* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_2 :: DIS_CH [00:00] */
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2_DIS_CH_MASK            0x00000001
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_2_DIS_CH_SHIFT           0

/***************************************************************************
 *VC0_PM_DIS_CHL_3 - VCXO 0 channel 3 powerdown post divider
 ***************************************************************************/
/* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_3 :: reserved0 [31:01] */
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3_reserved0_MASK         0xfffffffe
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3_reserved0_SHIFT        1

/* VCXO_CTL_MISC :: VC0_PM_DIS_CHL_3 :: DIS_CH [00:00] */
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3_DIS_CH_MASK            0x00000001
#define BCHP_VCXO_CTL_MISC_VC0_PM_DIS_CHL_3_DIS_CH_SHIFT           0

/***************************************************************************
 *AC0_CTRL - Audio PLL 0 reset and powerdown
 ***************************************************************************/
/* VCXO_CTL_MISC :: AC0_CTRL :: reserved0 [31:03] */
#define BCHP_VCXO_CTL_MISC_AC0_CTRL_reserved0_MASK                 0xfffffff8
#define BCHP_VCXO_CTL_MISC_AC0_CTRL_reserved0_SHIFT                3

/* VCXO_CTL_MISC :: AC0_CTRL :: POWERDOWN [02:02] */
#define BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_MASK                 0x00000004
#define BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_SHIFT                2
#define BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_Powerdown            1
#define BCHP_VCXO_CTL_MISC_AC0_CTRL_POWERDOWN_Normal               0

/* VCXO_CTL_MISC :: AC0_CTRL :: RESET [01:01] */
#define BCHP_VCXO_CTL_MISC_AC0_CTRL_RESET_MASK                     0x00000002
#define BCHP_VCXO_CTL_MISC_AC0_CTRL_RESET_SHIFT                    1
#define BCHP_VCXO_CTL_MISC_AC0_CTRL_RESET_Reset                    1
#define BCHP_VCXO_CTL_MISC_AC0_CTRL_RESET_Normal                   0

/* VCXO_CTL_MISC :: AC0_CTRL :: RESERVED [00:00] */
#define BCHP_VCXO_CTL_MISC_AC0_CTRL_RESERVED_MASK                  0x00000001
#define BCHP_VCXO_CTL_MISC_AC0_CTRL_RESERVED_SHIFT                 0

/***************************************************************************
 *AC0_PM_CLOCK_ENA_1 - Audio PLL 0  clock outputs enable
 ***************************************************************************/
/* VCXO_CTL_MISC :: AC0_PM_CLOCK_ENA_1 :: reserved0 [31:01] */
#define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1_reserved0_MASK       0xfffffffe
#define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1_reserved0_SHIFT      1

/* VCXO_CTL_MISC :: AC0_PM_CLOCK_ENA_1 :: CLOCK_ENA [00:00] */
#define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1_CLOCK_ENA_MASK       0x00000001
#define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1_CLOCK_ENA_SHIFT      0
#define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1_CLOCK_ENA_Enable     1
#define BCHP_VCXO_CTL_MISC_AC0_PM_CLOCK_ENA_1_CLOCK_ENA_Disable    0

/***************************************************************************
 *AC0_PM_DIS_CHL_1 - Audio PLL 0 channel 1 powerdown post divider
 ***************************************************************************/
/* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_1 :: reserved0 [31:01] */
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1_reserved0_MASK         0xfffffffe
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1_reserved0_SHIFT        1

/* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_1 :: DIS_CH [00:00] */
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1_DIS_CH_MASK            0x00000001
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_1_DIS_CH_SHIFT           0

/***************************************************************************
 *AC0_PM_DIS_CHL_2 - Audio PLL 0 channel 2 powerdown post divider
 ***************************************************************************/
/* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_2 :: reserved0 [31:01] */
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2_reserved0_MASK         0xfffffffe
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2_reserved0_SHIFT        1

/* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_2 :: DIS_CH [00:00] */
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2_DIS_CH_MASK            0x00000001
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_2_DIS_CH_SHIFT           0

/***************************************************************************
 *AC0_PM_DIS_CHL_3 - Audio PLL 0 channel 3 powerdown post divider
 ***************************************************************************/
/* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_3 :: reserved0 [31:01] */
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3_reserved0_MASK         0xfffffffe
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3_reserved0_SHIFT        1

/* VCXO_CTL_MISC :: AC0_PM_DIS_CHL_3 :: DIS_CH [00:00] */
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3_DIS_CH_MASK            0x00000001
#define BCHP_VCXO_CTL_MISC_AC0_PM_DIS_CHL_3_DIS_CH_SHIFT           0

/***************************************************************************
 *LOCK - VCXO core lock status
 ***************************************************************************/
/* VCXO_CTL_MISC :: LOCK :: reserved0 [31:02] */
#define BCHP_VCXO_CTL_MISC_LOCK_reserved0_MASK                     0xfffffffc
#define BCHP_VCXO_CTL_MISC_LOCK_reserved0_SHIFT                    2

/* VCXO_CTL_MISC :: LOCK :: AC0 [01:01] */
#define BCHP_VCXO_CTL_MISC_LOCK_AC0_MASK                           0x00000002
#define BCHP_VCXO_CTL_MISC_LOCK_AC0_SHIFT                          1

/* VCXO_CTL_MISC :: LOCK :: VC0 [00:00] */
#define BCHP_VCXO_CTL_MISC_LOCK_VC0_MASK                           0x00000001
#define BCHP_VCXO_CTL_MISC_LOCK_VC0_SHIFT                          0

/***************************************************************************
 *VC0_DIV - VCXO 0 PLL divider settings
 ***************************************************************************/
/* VCXO_CTL_MISC :: VC0_DIV :: reserved0 [31:26] */
#define BCHP_VCXO_CTL_MISC_VC0_DIV_reserved0_MASK                  0xfc000000
#define BCHP_VCXO_CTL_MISC_VC0_DIV_reserved0_SHIFT                 26

/* VCXO_CTL_MISC :: VC0_DIV :: VCORNG [25:24] */
#define BCHP_VCXO_CTL_MISC_VC0_DIV_VCORNG_MASK                     0x03000000
#define BCHP_VCXO_CTL_MISC_VC0_DIV_VCORNG_SHIFT                    24

/* VCXO_CTL_MISC :: VC0_DIV :: M3DIV [23:16] */
#define BCHP_VCXO_CTL_MISC_VC0_DIV_M3DIV_MASK                      0x00ff0000
#define BCHP_VCXO_CTL_MISC_VC0_DIV_M3DIV_SHIFT                     16

/* VCXO_CTL_MISC :: VC0_DIV :: M2DIV [15:08] */
#define BCHP_VCXO_CTL_MISC_VC0_DIV_M2DIV_MASK                      0x0000ff00
#define BCHP_VCXO_CTL_MISC_VC0_DIV_M2DIV_SHIFT                     8

/* VCXO_CTL_MISC :: VC0_DIV :: M1DIV [07:00] */
#define BCHP_VCXO_CTL_MISC_VC0_DIV_M1DIV_MASK                      0x000000ff
#define BCHP_VCXO_CTL_MISC_VC0_DIV_M1DIV_SHIFT                     0

/***************************************************************************
 *VCXO_CTLBUS_HI - VCXO PLL control bus higher word
 ***************************************************************************/
/* VCXO_CTL_MISC :: VCXO_CTLBUS_HI :: reserved0 [31:06] */
#define BCHP_VCXO_CTL_MISC_VCXO_CTLBUS_HI_reserved0_MASK           0xffffffc0
#define BCHP_VCXO_CTL_MISC_VCXO_CTLBUS_HI_reserved0_SHIFT          6

/* VCXO_CTL_MISC :: VCXO_CTLBUS_HI :: CTL_BITS_37_32 [05:00] */
#define BCHP_VCXO_CTL_MISC_VCXO_CTLBUS_HI_CTL_BITS_37_32_MASK      0x0000003f
#define BCHP_VCXO_CTL_MISC_VCXO_CTLBUS_HI_CTL_BITS_37_32_SHIFT     0

/***************************************************************************
 *VCXO_CTLBUS_LO - VCXO PLL control bus lower word
 ***************************************************************************/
/* VCXO_CTL_MISC :: VCXO_CTLBUS_LO :: CTL_BITS_31_0 [31:00] */
#define BCHP_VCXO_CTL_MISC_VCXO_CTLBUS_LO_CTL_BITS_31_0_MASK       0xffffffff
#define BCHP_VCXO_CTL_MISC_VCXO_CTLBUS_LO_CTL_BITS_31_0_SHIFT      0

/***************************************************************************
 *LOCK_CNTR_RESET - VCXO Lock Counter Reset
 ***************************************************************************/
/* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: reserved0 [31:02] */
#define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_reserved0_MASK          0xfffffffc
#define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_reserved0_SHIFT         2

/* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: AC0 [01:01] */
#define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_AC0_MASK                0x00000002
#define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_AC0_SHIFT               1

/* VCXO_CTL_MISC :: LOCK_CNTR_RESET :: VC0 [00:00] */
#define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_VC0_MASK                0x00000001
#define BCHP_VCXO_CTL_MISC_LOCK_CNTR_RESET_VC0_SHIFT               0

/***************************************************************************
 *VC0_LOCK_CNT - VCXO 0 PLL Lock Counter
 ***************************************************************************/
/* VCXO_CTL_MISC :: VC0_LOCK_CNT :: reserved0 [31:12] */
#define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT_reserved0_MASK             0xfffff000
#define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT_reserved0_SHIFT            12

/* VCXO_CTL_MISC :: VC0_LOCK_CNT :: COUNT [11:00] */
#define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT_COUNT_MASK                 0x00000fff
#define BCHP_VCXO_CTL_MISC_VC0_LOCK_CNT_COUNT_SHIFT                0

/***************************************************************************
 *AC0_LOCK_CNT - Audio PLL 0 Lock Counter
 ***************************************************************************/
/* VCXO_CTL_MISC :: AC0_LOCK_CNT :: reserved0 [31:12] */
#define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT_reserved0_MASK             0xfffff000
#define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT_reserved0_SHIFT            12

/* VCXO_CTL_MISC :: AC0_LOCK_CNT :: COUNT [11:00] */
#define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT_COUNT_MASK                 0x00000fff
#define BCHP_VCXO_CTL_MISC_AC0_LOCK_CNT_COUNT_SHIFT                0

/***************************************************************************
 *PLL_TEST_SEL - TOP LEVEL PLLs test select
 ***************************************************************************/
/* VCXO_CTL_MISC :: PLL_TEST_SEL :: reserved0 [31:12] */
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_reserved0_MASK             0xfffff000
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_reserved0_SHIFT            12

/* VCXO_CTL_MISC :: PLL_TEST_SEL :: reserved_for_eco1 [11:07] */
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_reserved_for_eco1_MASK     0x00000f80
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_reserved_for_eco1_SHIFT    7

/* VCXO_CTL_MISC :: PLL_TEST_SEL :: PLL_SEL [06:04] */
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_PLL_SEL_MASK               0x00000070
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_PLL_SEL_SHIFT              4
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_PLL_SEL_RESERVED0          7
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_PLL_SEL_MIPS_PLL           6
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_PLL_SEL_RESERVED1          5
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_PLL_SEL_AC0_PLL            4
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_PLL_SEL_VC0_PLL            3
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_PLL_SEL_SYSTEM_PLL1        2
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_PLL_SEL_SYSTEM_PLL0        1
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_PLL_SEL_None               0

/* VCXO_CTL_MISC :: PLL_TEST_SEL :: SUB_SEL [03:00] */
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_SUB_SEL_MASK               0x0000000f
#define BCHP_VCXO_CTL_MISC_PLL_TEST_SEL_SUB_SEL_SHIFT              0

#endif /* #ifndef BCHP_VCXO_CTL_MISC_H__ */

/* End of File */