* Renesas R-Car Display Unit (DU)

Required Properties:

  - compatible: must be one of the following.
    - "renesas,du-r8a7779" for R8A7779 (R-Car H1) compatible DU
    - "renesas,du-r8a7790" for R8A7790 (R-Car H2) compatible DU
    - "renesas,du-r8a7791" for R8A7791 (R-Car M2) compatible DU

  - reg: A list of base address and length of each memory resource, one for
    each entry in the reg-names property.
  - reg-names: Name of the memory resources. The DU requires one memory
    resource for the DU core (named "du") and one memory resource for each
    LVDS encoder (named "lvds.x" with "x" being the LVDS controller numerical
    index).

  - interrupt-parent: phandle of the parent interrupt controller.
  - interrupts: Interrupt specifiers for the DU interrupts.

  - clocks: A list of phandles + clock-specifier pairs, one for each entry in
    the clock-names property.
  - clock-names: Name of the clocks. This property is model-dependent.
    - R8A7779 uses a single functional clock. The clock doesn't need to be
      named.
    - R8A7790 and R8A7791 use one functional clock per channel and one clock
      per LVDS encoder. The functional clocks must be named "du.x" with "x"
      being the channel numerical index. The LVDS clocks must be named
      "lvds.x" with "x" being the LVDS encoder numerical index.

Required nodes:

The connections to the DU output video ports are modeled using the OF graph
bindings specified in Documentation/devicetree/bindings/graph.txt.

The following table lists for each supported model the port number
corresponding to each DU output.

		Port 0		Port1		Port2
-----------------------------------------------------------------------------
 R8A7779 (H1)	DPAD 0		DPAD 1		-
 R8A7790 (H2)	DPAD		LVDS 0		LVDS 1
 R8A7791 (M2)	DPAD		LVDS 0		-


Example: R8A7790 (R-Car H2) DU

	du: du@feb00000 {
		compatible = "renesas,du-r8a7790";
		reg = <0 0xfeb00000 0 0x70000>,
		      <0 0xfeb90000 0 0x1c>,
		      <0 0xfeb94000 0 0x1c>;
		reg-names = "du", "lvds.0", "lvds.1";
		interrupt-parent = <&gic>;
		interrupts = <0 256 IRQ_TYPE_LEVEL_HIGH>,
			     <0 268 IRQ_TYPE_LEVEL_HIGH>,
			     <0 269 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&mstp7_clks R8A7790_CLK_DU0>,
		         <&mstp7_clks R8A7790_CLK_DU1>,
		         <&mstp7_clks R8A7790_CLK_DU2>,
		         <&mstp7_clks R8A7790_CLK_LVDS0>,
		         <&mstp7_clks R8A7790_CLK_LVDS1>;
		clock-names = "du.0", "du.1", "du.2", "lvds.0", "lvds.1";

		ports {
			#address-cells = <1>;
			#size-cells = <0>;

			port@0 {
				reg = <0>;
				du_out_rgb: endpoint {
				};
			};
			port@1 {
				reg = <1>;
				du_out_lvds0: endpoint {
				};
			};
			port@2 {
				reg = <2>;
				du_out_lvds1: endpoint {
				};
			};
		};
	};