/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Wed Nov 18 01:21:03 2009
 *                 MD5 Checksum         8e4822e2d8c445f841e653dc06da5e41
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7340/rdb/b0/bchp_sun_top_ctrl.h $
 * 
 * Hydra_Software_Devel/1   11/18/09 10:16a albertl
 * SW7340-102: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_SUN_TOP_CTRL_H__
#define BCHP_SUN_TOP_CTRL_H__

/***************************************************************************
 *SUN_TOP_CTRL - Top Control registers
 ***************************************************************************/
#define BCHP_SUN_TOP_CTRL_PROD_REVISION          0x00404000 /* Product Revision ID */
#define BCHP_SUN_TOP_CTRL_SUN_REVISION           0x00404004 /* Sundry Revision ID */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00404008 /* Reset control */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL               0x00404010 /* Control register for NMI */
#define BCHP_SUN_TOP_CTRL_SW_RESET               0x00404014 /* Software reset register */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00404018 /* Reset history */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0040401c /* Strapping values */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00404020 /* Strapping values */
#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00404024 /* Bond option value register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00404028 /* OTP option test register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0040402c /* OTP option test register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00404030 /* OTP option status register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00404034 /* OTP option status register */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00404038 /* Semaphore channel 0 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0040403c /* Semaphore channel 1 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00404040 /* Semaphore channel 2 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00404044 /* Semaphore channel 3 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00404048 /* Semaphore channel 4 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0040404c /* Semaphore channel 5 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00404050 /* Semaphore channel 6 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00404054 /* Semaphore channel 7 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00404058 /* Semaphore channel 8 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0040405c /* Semaphore channel 9 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00404060 /* Semaphore channel 10 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00404064 /* Semaphore channel 11 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00404068 /* Semaphore channel 12 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0040406c /* Semaphore channel 13 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00404070 /* Semaphore channel 14 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00404074 /* Semaphore channel 15 */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00404078 /* General watchdog timer 0 */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0040407c /* General watchdog timer 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00404080 /* General control register 0 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00404084 /* General control register 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00404088 /* General control register 2 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0040408c /* General control register 3 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00404090 /* General control register 4 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00404094 /* General control register 5 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00404098 /* General status register 0 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0040409c /* General status register 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x004040a0 /* General status register 2 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */
#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x004040bc /* Scratch register */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x004040c0 /* Spare control bits reserved for future use */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00404100 /* Pinmux control register 0 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00404104 /* Pinmux control register 1 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00404108 /* Pinmux control register 2 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0040410c /* Pinmux control register 3 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00404110 /* Pinmux control register 4 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00404114 /* Pinmux control register 5 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00404118 /* Pinmux control register 6 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0040411c /* Pinmux control register 7 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00404120 /* Pinmux control register 8 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00404124 /* Pinmux control register 9 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10        0x00404128 /* Pinmux control register 10 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11        0x0040412c /* Pinmux control register 11 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12        0x00404130 /* Pinmux control register 12 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13        0x00404134 /* Pinmux control register 13 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14        0x00404138 /* Pinmux control register 14 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15        0x0040413c /* Pinmux control register 15 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16        0x00404140 /* Pinmux control register 16 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17        0x00404144 /* Pinmux control register 17 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18        0x00404148 /* Pinmux control register 18 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x0040414c /* Pad pull-up/pull-down control register 0 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00404150 /* Pad pull-up/pull-down control register 1 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00404154 /* Pad pull-up/pull-down control register 2 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x00404158 /* Pad pull-up/pull-down control register 3 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x0040415c /* Pad pull-up/pull-down control register 4 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00404160 /* Pad pull-up/pull-down control register 5 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00404164 /* Pad pull-up/pull-down control register 6 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7     0x00404168 /* Pad pull-up/pull-down control register 7 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8     0x0040416c /* Pad pull-up/pull-down control register 8 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9     0x00404170 /* Pad pull-up/pull-down control register 9 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10    0x00404174 /* Pad pull-up/pull-down control register 10 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11    0x00404178 /* Pad pull-up/pull-down control register 11 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12    0x0040417c /* Pad pull-up/pull-down control register 12 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13    0x00404180 /* Pad pull-up/pull-down control register 13 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14    0x00404184 /* Pad pull-up/pull-down control register 14 */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00404188 /* Bypass clock unselect register 0 */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00404200 /* Test port control */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00404204 /* Testport peek register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00404208 /* Testport poke register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0040420c /* Testport peek register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00404210 /* Testport poke register */
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00404214 /* EJTAG input bus enables */
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00404218 /* EJTAG output select */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0040421c /* UART Router select */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00404300 /* Serial Slave Port configuration register */
#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00404320 /* SERS Revision Register */
#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00404324 /* SERS Configuration Register */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00404400 /* Block select for RO testmode */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL         0x00404500 /* Test_mode control register */
#define BCHP_SUN_TOP_CTRL_TEST_MODE              0x00404504 /* Register source for test_mode */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE          0x00404508 /* Register source for sub_test_mode */
#define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE      0x0040450c /* Final latched testmode value */
#define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE  0x00404510 /* Final latched sub-testmode value */
#define BCHP_SUN_TOP_CTRL_PM_CTRL                0x00404600 /* Control register for Power Controller */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS    0x00404604 /* Power Management IRQ input status */
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT     0x00404608 /* Power Management Wait counter in place of Wait for MIPS IRQ */

/***************************************************************************
 *PROD_REVISION - Product Revision ID
 ***************************************************************************/
/* SUN_TOP_CTRL :: PROD_REVISION :: product_revision [31:00] */
#define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_MASK      0xffffffff
#define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_SHIFT     0

/***************************************************************************
 *SUN_REVISION - Sundry Revision ID
 ***************************************************************************/
/* SUN_TOP_CTRL :: SUN_REVISION :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_MASK              0xffff0000
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_SHIFT             16

/* SUN_TOP_CTRL :: SUN_REVISION :: sundry_revision [15:00] */
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_MASK        0x0000ffff
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_SHIFT       0

/***************************************************************************
 *RESET_CTRL - Reset control
 ***************************************************************************/
/* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_monitor [31:31] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_MASK       0x80000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_SHIFT      31

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_monitor [30:30] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_MASK 0x40000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_SHIFT 30

/* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_def_val_monitor [29:29] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_def_val_monitor_MASK 0x20000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_def_val_monitor_SHIFT 29

/* SUN_TOP_CTRL :: RESET_CTRL :: reset_ext_mode_monitor [28:28] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_ext_mode_monitor_MASK   0x10000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_ext_mode_monitor_SHIFT  28

/* SUN_TOP_CTRL :: RESET_CTRL :: reset_timer_205_monitor [27:27] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_205_monitor_MASK  0x08000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_205_monitor_SHIFT 27

/* SUN_TOP_CTRL :: RESET_CTRL :: reset_timer_200_monitor [26:26] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_200_monitor_MASK  0x04000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_200_monitor_SHIFT 26

/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [25:12] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0x03fff000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               12

/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [11:11] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000800
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     11

/* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable_lock [10:10] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_SHIFT 10

/* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable [09:09] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_SHIFT 9

/* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable_lock [08:08] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_SHIFT 8

/* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable [07:07] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_MASK    0x00000080
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_SHIFT   7

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [06:06] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 6

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable [05:05] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT 5

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_polarity [04:04] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT 4

/* SUN_TOP_CTRL :: RESET_CTRL :: master_reset_en [03:03] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_MASK          0x00000008
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_SHIFT         3

/* SUN_TOP_CTRL :: RESET_CTRL :: reserved1 [02:02] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_MASK                0x00000004
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_SHIFT               2

/* SUN_TOP_CTRL :: RESET_CTRL :: sc_insert_reset_en [01:00] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_MASK       0x00000003
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_SHIFT      0

/***************************************************************************
 *NMI_CTRL - Control register for NMI
 ***************************************************************************/
/* SUN_TOP_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_config_lock_MASK            0x80000000
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_config_lock_SHIFT           31

/* SUN_TOP_CTRL :: NMI_CTRL :: reserved0 [30:03] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_reserved0_MASK                  0x7ffffff8
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_reserved0_SHIFT                 3

/* SUN_TOP_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_pad_monitor_MASK            0x00000004
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT           2

/* SUN_TOP_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_config_nmi_polarity_MASK        0x00000002
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT       1

/* SUN_TOP_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_disable_pad_nmi_MASK            0x00000001
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT           0

/***************************************************************************
 *SW_RESET - Software reset register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SW_RESET :: chip_master_reset [31:31] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_MASK          0x80000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_SHIFT         31

/* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_1shot [30:30] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_MASK         0x40000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_SHIFT        30

/* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_1shot [29:29] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_MASK        0x20000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_SHIFT       29

/* SUN_TOP_CTRL :: SW_RESET :: pci_rstb_out_sw_reset [28:28] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_pci_rstb_out_sw_reset_MASK      0x10000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_pci_rstb_out_sw_reset_SHIFT     28

/* SUN_TOP_CTRL :: SW_RESET :: reserved0 [27:26] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_MASK                  0x0c000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_SHIFT                 26

/* SUN_TOP_CTRL :: SW_RESET :: avd0_sw_reset [25:25] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_MASK              0x02000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_SHIFT             25

/* SUN_TOP_CTRL :: SW_RESET :: aio_sw_reset [24:24] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_aio_sw_reset_MASK               0x01000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_aio_sw_reset_SHIFT              24

/* SUN_TOP_CTRL :: SW_RESET :: rptd_sw_reset [23:23] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_rptd_sw_reset_MASK              0x00800000
#define BCHP_SUN_TOP_CTRL_SW_RESET_rptd_sw_reset_SHIFT             23

/* SUN_TOP_CTRL :: SW_RESET :: reserved1 [22:22] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved1_MASK                  0x00400000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved1_SHIFT                 22

/* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_level [21:21] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_MASK        0x00200000
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_SHIFT       21

/* SUN_TOP_CTRL :: SW_RESET :: usb_sw_reset [20:20] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_usb_sw_reset_MASK               0x00100000
#define BCHP_SUN_TOP_CTRL_SW_RESET_usb_sw_reset_SHIFT              20

/* SUN_TOP_CTRL :: SW_RESET :: reserved2 [19:19] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved2_MASK                  0x00080000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved2_SHIFT                 19

/* SUN_TOP_CTRL :: SW_RESET :: memc_sw_reset [18:18] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_memc_sw_reset_MASK              0x00040000
#define BCHP_SUN_TOP_CTRL_SW_RESET_memc_sw_reset_SHIFT             18

/* SUN_TOP_CTRL :: SW_RESET :: memc_gfx_sw_reset [17:17] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_memc_gfx_sw_reset_MASK          0x00020000
#define BCHP_SUN_TOP_CTRL_SW_RESET_memc_gfx_sw_reset_SHIFT         17

/* SUN_TOP_CTRL :: SW_RESET :: reserved3 [16:14] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved3_MASK                  0x0001c000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved3_SHIFT                 14

/* SUN_TOP_CTRL :: SW_RESET :: xpt_sw_reset [13:13] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_MASK               0x00002000
#define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_SHIFT              13

/* SUN_TOP_CTRL :: SW_RESET :: ddr_sw_reset [12:12] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ddr_sw_reset_MASK               0x00001000
#define BCHP_SUN_TOP_CTRL_SW_RESET_ddr_sw_reset_SHIFT              12

/* SUN_TOP_CTRL :: SW_RESET :: vec_sw_reset [11:11] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_vec_sw_reset_MASK               0x00000800
#define BCHP_SUN_TOP_CTRL_SW_RESET_vec_sw_reset_SHIFT              11

/* SUN_TOP_CTRL :: SW_RESET :: bvn_sw_reset [10:10] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_sw_reset_MASK               0x00000400
#define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_sw_reset_SHIFT              10

/* SUN_TOP_CTRL :: SW_RESET :: hdmi_sw_reset [09:09] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_hdmi_sw_reset_MASK              0x00000200
#define BCHP_SUN_TOP_CTRL_SW_RESET_hdmi_sw_reset_SHIFT             9

/* SUN_TOP_CTRL :: SW_RESET :: sds0_t_sw_reset [08:08] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_sds0_t_sw_reset_MASK            0x00000100
#define BCHP_SUN_TOP_CTRL_SW_RESET_sds0_t_sw_reset_SHIFT           8

/* SUN_TOP_CTRL :: SW_RESET :: moca_sw_reset [07:07] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_moca_sw_reset_MASK              0x00000080
#define BCHP_SUN_TOP_CTRL_SW_RESET_moca_sw_reset_SHIFT             7

/* SUN_TOP_CTRL :: SW_RESET :: reserved4 [06:06] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved4_MASK                  0x00000040
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved4_SHIFT                 6

/* SUN_TOP_CTRL :: SW_RESET :: jtag_otp_sw_reset [05:05] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_MASK          0x00000020
#define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_SHIFT         5

/* SUN_TOP_CTRL :: SW_RESET :: enet_sw_reset [04:04] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_enet_sw_reset_MASK              0x00000010
#define BCHP_SUN_TOP_CTRL_SW_RESET_enet_sw_reset_SHIFT             4

/* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_level [03:03] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_MASK         0x00000008
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_SHIFT        3

/* SUN_TOP_CTRL :: SW_RESET :: ebi_sw_reset [02:02] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ebi_sw_reset_MASK               0x00000004
#define BCHP_SUN_TOP_CTRL_SW_RESET_ebi_sw_reset_SHIFT              2

/* SUN_TOP_CTRL :: SW_RESET :: pci_sw_reset [01:01] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_pci_sw_reset_MASK               0x00000002
#define BCHP_SUN_TOP_CTRL_SW_RESET_pci_sw_reset_SHIFT              1

/* SUN_TOP_CTRL :: SW_RESET :: sundry_sw_reset [00:00] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_MASK            0x00000001
#define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_SHIFT           0

/***************************************************************************
 *RESET_HISTORY - Reset history
 ***************************************************************************/
/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:12] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffff000
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            12

/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset [11:11] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_MASK   0x00000800
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_SHIFT  11

/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_sft_sft_rst_b [10:10] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_SHIFT 10

/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_hrd_sft_rst_b [09:09] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_SHIFT 9

/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [08:08] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 8

/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset [07:07] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_MASK  0x00000080
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_SHIFT 7

/* SUN_TOP_CTRL :: RESET_HISTORY :: special_sw_reset [06:06] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_MASK      0x00000040
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_SHIFT     6

/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved1 [05:05] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_MASK             0x00000020
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_SHIFT            5

/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [04:04] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000010
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 4

/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [03:03] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 3

/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [02:02] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 2

/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1

/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0

/***************************************************************************
 *STRAP_VALUE_0 - Strapping values
 ***************************************************************************/
/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffff0000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            16

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_xtal_bypass [15:15] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_bypass_MASK     0x00008000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_bypass_SHIFT    15

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_xtal_highpass_up [14:14] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_highpass_up_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_highpass_up_SHIFT 14

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_rom_size [13:12] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_rom_size_MASK    0x00003000
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_rom_size_SHIFT   12

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_ebi_boot_memory [11:11] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_boot_memory_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_ebi_boot_memory_SHIFT 11

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_xtal_bias_ctrl [10:09] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_bias_ctrl_MASK  0x00000600
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_bias_ctrl_SHIFT 9

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [08:08] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 8

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pci_memwin_size [07:06] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_memwin_size_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_memwin_size_SHIFT 6

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pci_memwin2_en [05:05] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_memwin2_en_MASK  0x00000020
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_memwin2_en_SHIFT 5

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pci_memwin1_en [04:04] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_memwin1_en_MASK  0x00000010
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_memwin1_en_SHIFT 4

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_pci_client [03:03] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_client_MASK      0x00000008
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_pci_client_SHIFT     3

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_mips_freq [02:02] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_mips_freq_MASK       0x00000004
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_mips_freq_SHIFT      2

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_nand_flash [01:01] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_nand_flash_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_nand_flash_SHIFT     1

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_reset_outb_def_val [00:00] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_reset_outb_def_val_SHIFT 0

/***************************************************************************
 *STRAP_VALUE_1 - Strapping values
 ***************************************************************************/
/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:04] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff0
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            4

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_3 [03:03] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_3_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_3_SHIFT 3

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_2 [02:02] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_SHIFT 2

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_spi_nor_mode [01:01] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_spi_nor_mode_MASK    0x00000002
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_spi_nor_mode_SHIFT   1

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_spi_nor_flash [00:00] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_spi_nor_flash_MASK   0x00000001
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_spi_nor_flash_SHIFT  0

/***************************************************************************
 *BOND_STATUS - Bond option value register
 ***************************************************************************/
/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1

/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0

/***************************************************************************
 *OTP_OPTION_TEST_0 - OTP option test register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [31:26] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK         0xfc000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT        26

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [25:25] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x02000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 25

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_temp_sensor_disable [24:24] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_MASK 0x01000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_temp_sensor_disable_SHIFT 24

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb1_disable [23:23] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_MASK 0x00800000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb1_disable_SHIFT 23

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb0_disable [22:22] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb0_disable_MASK 0x00400000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb0_disable_SHIFT 22

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_3d_disable [21:21] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_3d_disable_MASK 0x00200000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_3d_disable_SHIFT 21

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_moca_disable [20:20] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_MASK 0x00100000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_moca_disable_SHIFT 20

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_disable [19:19] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_disable_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_disable_SHIFT 19

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tuner_disable [18:18] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner_disable_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tuner_disable_SHIFT 18

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_sds_disable [17:17] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds_disable_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_sds_disable_SHIFT 17

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_ldpc_disable [16:16] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_ldpc_disable_SHIFT 16

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_tfec_disable [15:15] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_tfec_disable_SHIFT 15

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_qpsk_disable [14:14] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_qpsk_disable_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_qpsk_disable_SHIFT 14

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_directv_disable [13:13] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_directv_disable_SHIFT 13

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [12:11] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00001800
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 11

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_pci_ebi [10:10] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_pci_ebi_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_pci_ebi_SHIFT 10

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [09:09] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 9

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hd_display_enable [08:08] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_enable_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hd_display_enable_SHIFT 8

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [07:07] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 7

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_int_daa_disable [06:06] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_int_daa_disable_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_int_daa_disable_SHIFT 6

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [05:05] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 5

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_enable [04:04] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_enable_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_enable_SHIFT 4

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_product_id [03:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_product_id_MASK 0x0000000f
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_product_id_SHIFT 0

/***************************************************************************
 *OTP_OPTION_TEST_1 - OTP option test register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: reserved0 [31:20] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved0_MASK         0xfff00000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved0_SHIFT        20

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_mii_disable [19:19] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_mii_disable_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_mii_disable_SHIFT 19

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_2 [18:18] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_2_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_2_SHIFT 18

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_1 [17:17] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_1_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_1_SHIFT 17

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_0 [16:16] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_0_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_0_SHIFT 16

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: reserved1 [15:04] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved1_MASK         0x0000fff0
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved1_SHIFT        4

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_3 [03:03] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_3_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_3_SHIFT 3

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_2 [02:02] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_2_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_2_SHIFT 2

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_1_SHIFT 1

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_0_SHIFT 0

/***************************************************************************
 *OTP_OPTION_STATUS_0 - OTP option status register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [31:26] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK       0xfc000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT      26

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [25:25] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x02000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 25

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_temp_sensor_disable [24:24] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_MASK 0x01000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_temp_sensor_disable_SHIFT 24

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb1_disable [23:23] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb1_disable_MASK 0x00800000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb1_disable_SHIFT 23

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb0_disable [22:22] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb0_disable_MASK 0x00400000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb0_disable_SHIFT 22

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_3d_disable [21:21] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_3d_disable_MASK 0x00200000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_3d_disable_SHIFT 21

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_moca_disable [20:20] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_MASK 0x00100000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_moca_disable_SHIFT 20

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_disable [19:19] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_disable_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_disable_SHIFT 19

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tuner_disable [18:18] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner_disable_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tuner_disable_SHIFT 18

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_sds_disable [17:17] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds_disable_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_sds_disable_SHIFT 17

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_ldpc_disable [16:16] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_ldpc_disable_SHIFT 16

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_tfec_disable [15:15] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_tfec_disable_SHIFT 15

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_qpsk_disable [14:14] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_qpsk_disable_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_qpsk_disable_SHIFT 14

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_directv_disable [13:13] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_directv_disable_SHIFT 13

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [12:11] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00001800
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 11

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_pci_ebi [10:10] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_pci_ebi_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_pci_ebi_SHIFT 10

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [09:09] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 9

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hd_display_enable [08:08] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_enable_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hd_display_enable_SHIFT 8

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [07:07] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 7

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_int_daa_disable [06:06] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_int_daa_disable_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_int_daa_disable_SHIFT 6

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [05:05] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 5

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_enable [04:04] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_enable_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_enable_SHIFT 4

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_product_id [03:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_product_id_MASK 0x0000000f
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_product_id_SHIFT 0

/***************************************************************************
 *OTP_OPTION_STATUS_1 - OTP option status register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: reserved0 [31:20] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved0_MASK       0xfff00000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved0_SHIFT      20

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_mii_disable [19:19] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_mii_disable_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_mii_disable_SHIFT 19

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_2 [18:18] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_2_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_2_SHIFT 18

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_1 [17:17] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_1_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_1_SHIFT 17

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_0 [16:16] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_0_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_0_SHIFT 16

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: reserved1 [15:04] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved1_MASK       0x0000fff0
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved1_SHIFT      4

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_3 [03:03] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_3_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_3_SHIFT 3

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_2 [02:02] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_2_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_2_SHIFT 2

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_1_SHIFT 1

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_0_SHIFT 0

/***************************************************************************
 *SEMAPHORE_0 - Semaphore channel 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_1 - Semaphore channel 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_2 - Semaphore channel 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_3 - Semaphore channel 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_4 - Semaphore channel 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_5 - Semaphore channel 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_6 - Semaphore channel 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_7 - Semaphore channel 7
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_8 - Semaphore channel 8
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_9 - Semaphore channel 9
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_10 - Semaphore channel 10
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_11 - Semaphore channel 11
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_12 - Semaphore channel 12
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_13 - Semaphore channel 13
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_14 - Semaphore channel 14
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_15 - Semaphore channel 15
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *GEN_WATCHDOG_0 - General watchdog timer 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0

/***************************************************************************
 *GEN_WATCHDOG_1 - General watchdog timer 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_0 - General control register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_31 [31:31] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_MASK     0x80000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_31_SHIFT    31

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_30 [30:30] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_MASK     0x40000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_30_SHIFT    30

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_29 [29:29] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_MASK     0x20000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_29_SHIFT    29

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_28 [28:28] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_MASK     0x10000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_28_SHIFT    28

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_27 [27:27] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_MASK     0x08000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_27_SHIFT    27

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_26 [26:26] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_MASK     0x04000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_26_SHIFT    26

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_25 [25:25] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_MASK     0x02000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_25_SHIFT    25

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_24 [24:24] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_MASK     0x01000000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_24_SHIFT    24

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_23 [23:23] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_MASK     0x00800000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_23_SHIFT    23

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_22 [22:22] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_MASK     0x00400000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_22_SHIFT    22

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_21 [21:21] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_MASK     0x00200000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_21_SHIFT    21

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_20 [20:20] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_MASK     0x00100000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_20_SHIFT    20

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_19 [19:19] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_MASK     0x00080000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_19_SHIFT    19

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_18 [18:18] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_MASK     0x00040000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_18_SHIFT    18

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_17 [17:17] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_MASK     0x00020000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_17_SHIFT    17

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_16 [16:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_MASK     0x00010000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_16_SHIFT    16

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_15 [15:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_MASK     0x00008000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_15_SHIFT    15

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_14 [14:14] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_MASK     0x00004000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_14_SHIFT    14

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_13 [13:13] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_MASK     0x00002000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_13_SHIFT    13

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_12 [12:12] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_MASK     0x00001000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_12_SHIFT    12

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_11 [11:11] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_MASK     0x00000800
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_11_SHIFT    11

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_10 [10:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_MASK     0x00000400
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_10_SHIFT    10

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_9 [09:09] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_MASK      0x00000200
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_9_SHIFT     9

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_8 [08:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_MASK      0x00000100
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_8_SHIFT     8

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_7 [07:07] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_MASK      0x00000080
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_7_SHIFT     7

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_6 [06:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_MASK      0x00000040
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_6_SHIFT     6

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_5 [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_MASK      0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_5_SHIFT     5

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_4 [04:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_MASK      0x00000010
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_4_SHIFT     4

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_3 [03:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_MASK      0x00000008
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_3_SHIFT     3

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_2 [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_MASK      0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_2_SHIFT     2

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: mii_resync_enable [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_resync_enable_MASK    0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_mii_resync_enable_SHIFT   0

/***************************************************************************
 *GENERAL_CTRL_1 - General control register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xffff0000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           16

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: mips_mbist_tm0_reg [11:11] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_mips_mbist_tm0_reg_MASK   0x00000800
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_mips_mbist_tm0_reg_SHIFT  11

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: mips_mbist_tm1_reg [10:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_mips_mbist_tm1_reg_MASK   0x00000400
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_mips_mbist_tm1_reg_SHIFT  10

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: daa_testmode [09:09] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_testmode_MASK         0x00000200
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_testmode_SHIFT        9

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: daa_bypass [08:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_bypass_MASK           0x00000100
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_daa_bypass_SHIFT          8

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_7 [07:07] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_MASK      0x00000080
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_SHIFT     7

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_6 [06:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_MASK      0x00000040
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_SHIFT     6

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_5 [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_MASK      0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_SHIFT     5

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_4 [04:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_MASK      0x00000010
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_SHIFT     4

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0

/***************************************************************************
 *GENERAL_CTRL_2 - General control register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2

/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0

/***************************************************************************
 *GENERAL_CTRL_3 - General control register 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0

/***************************************************************************
 *GENERAL_CTRL_4 - General control register 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2

/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0

/***************************************************************************
 *GENERAL_CTRL_5 - General control register 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2

/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0

/***************************************************************************
 *GENERAL_STATUS_0 - General status register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xffff0000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         16

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_15 [15:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_15_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_15_SHIFT 15

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_14 [14:14] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_14_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_14_SHIFT 14

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_13 [13:13] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_13_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_13_SHIFT 13

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_12 [12:12] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_12_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_12_SHIFT 12

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_11 [11:11] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_11_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_11_SHIFT 11

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_10 [10:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_10_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_10_SHIFT 10

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_09 [09:09] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_09_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_09_SHIFT 9

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_08 [08:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_08_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_08_SHIFT 8

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_07 [07:07] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_07_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_07_SHIFT 7

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_06 [06:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_06_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_06_SHIFT 6

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_05 [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_05_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_05_SHIFT 5

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_04 [04:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_04_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_04_SHIFT 4

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_03 [03:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_03_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_03_SHIFT 3

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_02 [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_02_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_02_SHIFT 2

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_01 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_01_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_01_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0

/***************************************************************************
 *GENERAL_STATUS_1 - General status register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xffff0000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         16

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_15 [15:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_15_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_15_SHIFT 15

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_14 [14:14] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_14_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_14_SHIFT 14

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_13 [13:13] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_13_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_13_SHIFT 13

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_12 [12:12] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_12_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_12_SHIFT 12

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_11 [11:11] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_11_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_11_SHIFT 11

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_10 [10:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_10_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_10_SHIFT 10

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_09 [09:09] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_09_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_09_SHIFT 9

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_08 [08:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_08_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_08_SHIFT 8

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_07 [07:07] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_07_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_07_SHIFT 7

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_06 [06:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_06_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_06_SHIFT 6

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_05 [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_05_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_05_SHIFT 5

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_04 [04:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_04_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_04_SHIFT 4

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_03 [03:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_03_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_03_SHIFT 3

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_02 [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_02_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_02_SHIFT 2

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_01 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_01_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_01_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_00 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_00_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_00_SHIFT 0

/***************************************************************************
 *GENERAL_STATUS_2 - General status register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xffff0000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         16

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_15 [15:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_15_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_15_SHIFT 15

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_14 [14:14] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_14_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_14_SHIFT 14

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_13 [13:13] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_13_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_13_SHIFT 13

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_12 [12:12] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_12_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_12_SHIFT 12

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_11 [11:11] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_11_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_11_SHIFT 11

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_10 [10:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_10_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_10_SHIFT 10

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_09 [09:09] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_09_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_09_SHIFT 9

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_08 [08:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_08_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_08_SHIFT 8

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_07 [07:07] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_07_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_07_SHIFT 7

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_06 [06:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_06_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_06_SHIFT 6

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_05 [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_05_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_05_SHIFT 5

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_04 [04:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_04_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_04_SHIFT 4

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_03 [03:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_03_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_03_SHIFT 3

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_02 [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_02_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_02_SHIFT 2

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_01 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_01_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_01_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_00 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_00_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_00_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0

/***************************************************************************
 *UNCLEARED_SCRATCH - Scratch register
 ***************************************************************************/
/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0

/***************************************************************************
 *SPARE_CTRL - Spare control bits reserved for future use
 ***************************************************************************/
/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0

/***************************************************************************
 *PIN_MUX_CTRL_0 - Pinmux control register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad05 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad05_MASK             0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad05_SHIFT            28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad05_PCI_AD05         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad05_ALT_TP_IN_05     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad05_RC_ALT_TP_IN_05  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad04 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad04_MASK             0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad04_SHIFT            24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad04_PCI_AD04         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad04_ALT_TP_IN_04     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad04_RC_ALT_TP_IN_04  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad03 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad03_MASK             0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad03_SHIFT            20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad03_PCI_AD03         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad03_ALT_TP_IN_03     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad03_RC_ALT_TP_IN_03  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad02 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad02_MASK             0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad02_SHIFT            16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad02_PCI_AD02         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad02_ALT_TP_IN_02     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad02_RC_ALT_TP_IN_02  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad01 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad01_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad01_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad01_PCI_AD01         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad01_ALT_TP_IN_01     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad01_RC_ALT_TP_IN_01  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: pci_ad00 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad00_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad00_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad00_PCI_AD00         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad00_ALT_TP_IN_00     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_pci_ad00_RC_ALT_TP_IN_00  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: usb0_pwron [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_usb0_pwron_MASK           0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_usb0_pwron_SHIFT          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_usb0_pwron_USB0_PWRON     0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_usb0_pwron_TP_OUT_20      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_usb0_pwron_RC_TP_OUT_20   2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: aud_spdif [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aud_spdif_MASK            0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aud_spdif_SHIFT           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aud_spdif_AUD_SPDIF       0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aud_spdif_RO_TEST_OUT     1

/***************************************************************************
 *PIN_MUX_CTRL_1 - Pinmux control register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad13 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad13_MASK             0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad13_SHIFT            28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad13_PCI_AD13         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad13_ALT_TP_IN_13     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad13_RC_ALT_TP_IN_13  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad12 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad12_MASK             0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad12_SHIFT            24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad12_PCI_AD12         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad12_ALT_TP_IN_12     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad12_RC_ALT_TP_IN_12  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad11 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad11_MASK             0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad11_SHIFT            20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad11_PCI_AD11         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad11_ALT_TP_IN_11     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad11_RC_ALT_TP_IN_11  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad10 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad10_MASK             0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad10_SHIFT            16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad10_PCI_AD10         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad10_ALT_TP_IN_10     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad10_RC_ALT_TP_IN_10  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad09 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad09_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad09_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad09_PCI_AD09         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad09_ALT_TP_IN_09     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad09_RC_ALT_TP_IN_09  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad08 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad08_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad08_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad08_PCI_AD08         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad08_ALT_TP_IN_08     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad08_RC_ALT_TP_IN_08  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad07 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad07_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad07_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad07_PCI_AD07         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad07_ALT_TP_IN_07     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad07_RC_ALT_TP_IN_07  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: pci_ad06 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad06_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad06_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad06_PCI_AD06         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad06_ALT_TP_IN_06     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_pci_ad06_RC_ALT_TP_IN_06  2

/***************************************************************************
 *PIN_MUX_CTRL_2 - Pinmux control register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad21 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad21_MASK             0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad21_SHIFT            28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad21_PCI_AD21         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad21_ALT_TP_IN_21     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad21_RC_ALT_TP_IN_21  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad20 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad20_MASK             0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad20_SHIFT            24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad20_PCI_AD20         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad20_ALT_TP_IN_20     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad20_RC_ALT_TP_IN_20  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad19 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad19_MASK             0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad19_SHIFT            20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad19_PCI_AD19         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad19_ALT_TP_IN_19     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad19_RC_ALT_TP_IN_19  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad18 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad18_MASK             0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad18_SHIFT            16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad18_PCI_AD18         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad18_ALT_TP_IN_18     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad18_RC_ALT_TP_IN_18  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad17 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad17_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad17_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad17_PCI_AD17         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad17_ALT_TP_IN_17     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad17_RC_ALT_TP_IN_17  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad16 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad16_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad16_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad16_PCI_AD16         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad16_ALT_TP_IN_16     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad16_RC_ALT_TP_IN_16  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad15 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad15_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad15_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad15_PCI_AD15         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad15_ALT_TP_IN_15     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad15_RC_ALT_TP_IN_15  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: pci_ad14 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad14_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad14_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad14_PCI_AD14         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad14_ALT_TP_IN_14     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_pci_ad14_RC_ALT_TP_IN_14  2

/***************************************************************************
 *PIN_MUX_CTRL_3 - Pinmux control register 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad29 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad29_MASK             0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad29_SHIFT            28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad29_PCI_AD29         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad29_ALT_TP_IN_29     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad29_RC_ALT_TP_IN_29  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad28 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad28_MASK             0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad28_SHIFT            24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad28_PCI_AD28         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad28_ALT_TP_OUT_28    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad28_RC_ALT_TP_OUT_28 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad27 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad27_MASK             0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad27_SHIFT            20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad27_PCI_AD27         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad27_ALT_TP_IN_27     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad27_RC_ALT_TP_IN_27  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad26 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad26_MASK             0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad26_SHIFT            16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad26_PCI_AD26         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad26_ALT_TP_IN_26     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad26_RC_ALT_TP_IN_26  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad25 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad25_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad25_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad25_PCI_AD25         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad25_ALT_TP_IN_25     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad25_RC_ALT_TP_IN_25  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad24 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad24_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad24_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad24_PCI_AD24         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad24_ALT_TP_OUT_24    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad24_RC_ALT_TP_OUT_24 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad23 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad23_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad23_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad23_PCI_AD23         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad23_ALT_TP_IN_23     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad23_RC_ALT_TP_IN_23  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: pci_ad22 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad22_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad22_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad22_PCI_AD22         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad22_ALT_TP_IN_22     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_pci_ad22_RC_ALT_TP_IN_22  2

/***************************************************************************
 *PIN_MUX_CTRL_4 - Pinmux control register 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_05 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_05_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_05_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_05_GPIO_05           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_05_CHIP2CI_MDO_1     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_05_PPKT_O_DATA_1     2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_05_SDS0_O_DATA_1     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_05_PM_GPIO_05        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_05_TP_IN_05          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_05_RC_TP_IN_05       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_04 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_04_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_04_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_04_GPIO_04           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_04_CHIP2CI_MDO_0     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_04_PPKT_O_DATA_0     2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_04_SDS0_O_DATA_0     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_04_PM_GPIO_04        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_04_TP_IN_04          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_04_RC_TP_IN_04       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_03 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_03_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_03_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_03_GPIO_03           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_03_LED_KD_3          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_03_EXT_IRQB_5        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_03_UART_RTSCB        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_03_PM_GPIO_03        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_03_TP_IN_03          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_03_RC_TP_IN_03       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_02 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_02_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_02_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_02_GPIO_02           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_02_LED_KD_2          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_02_EXT_IRQB_4        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_02_UART_CTSCB        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_02_PM_GPIO_02        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_02_TP_IN_02          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_02_RC_TP_IN_02       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_01 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_01_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_01_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_01_GPIO_01           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_01_LED_KD_1          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_01_EXT_IRQB_3        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_01_UART_TXDC         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_01_PM_GPIO_01        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_01_TP_IN_01          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_01_RC_TP_IN_01       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_00 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_00_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_00_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_00_GPIO_00           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_00_LED_KD_0          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_00_EXT_IRQB_2        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_00_UART_RXDC         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_00_PM_GPIO_00        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_00_TP_IN_00          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_00_RC_TP_IN_00       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: pci_ad31 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad31_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad31_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad31_PCI_AD31         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad31_ALT_TP_IN_31     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad31_RC_ALT_TP_IN_31  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: pci_ad30 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad30_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad30_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad30_PCI_AD30         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad30_ALT_TP_IN_30     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_pci_ad30_RC_ALT_TP_IN_30  2

/***************************************************************************
 *PIN_MUX_CTRL_5 - Pinmux control register 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_13 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_13_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_13_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_13_GPIO_13           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_13_CHIP2CI_MOVAL     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_13_PPKT_O_VALID      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_13_SDS0_O_VALID      3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_13_PM_GPIO_13        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_13_TP_IN_13          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_13_RC_TP_IN_13       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_12 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_12_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_12_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_12_GPIO_12           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_12_CHIP2CI_MOSTRT    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_12_PPKT_O_SYNC       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_12_SDS0_O_SYNC       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_12_PM_GPIO_12        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_12_TP_IN_12          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_12_RC_TP_IN_12       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_11 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_GPIO_11           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_CHIP2CI_MDO_7     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_PPKT_O_DATA_7     2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_SDS0_O_DATA_7     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_PM_GPIO_11        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_TP_IN_11          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_11_RC_TP_IN_11       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_10 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_GPIO_10           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_CHIP2CI_MDO_6     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_PPKT_O_DATA_6     2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_SDS0_O_DATA_6     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_PM_GPIO_10        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_TP_IN_10          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_10_RC_TP_IN_10       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_09 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_GPIO_09           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_CHIP2CI_MDO_5     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_PPKT_O_DATA_5     2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_SDS0_O_DATA_5     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_I2S_BIDIR_CLK     4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_PM_GPIO_09        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_TP_IN_09          6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_09_RC_TP_IN_09       7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_08 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_GPIO_08           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_CHIP2CI_MDO_4     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_PPKT_O_DATA_4     2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_SDS0_O_DATA_4     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_I2S_BIDIR_SYNC    4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_PM_GPIO_08        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_TP_IN_08          6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_08_RC_TP_IN_08       7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_07 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_GPIO_07           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_CHIP2CI_MDO_3     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_PPKT_O_DATA_3     2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_SDS0_O_DATA_3     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_I2S_BIDIR_DATA    4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_PM_GPIO_07        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_TP_IN_07          6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_07_RC_TP_IN_07       7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_06 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_GPIO_06           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_CHIP2CI_MDO_2     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_PPKT_O_DATA_2     2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_SDS0_O_DATA_2     3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_PM_GPIO_06        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_TP_IN_06          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_06_RC_TP_IN_06       6

/***************************************************************************
 *PIN_MUX_CTRL_6 - Pinmux control register 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_21 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_21_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_21_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_21_GPIO_21           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_21_I2S_O_SYNC        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_21_RMX_VALID0        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_21_PM_GPIO_21        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_21_TP_IN_21          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_21_RC_TP_IN_21       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_20 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_20_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_20_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_20_GPIO_20           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_20_I2S_O_DATA        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_20_RMX_PAUSE0        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_20_PM_GPIO_20        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_20_TP_IN_20          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_20_RC_TP_IN_20       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_19 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_19_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_19_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_19_GPIO_19           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_19_CI2CHIP_MICLK     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_19_PPKT_I_CLK        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_19_PM_GPIO_19        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_19_TP_IN_19          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_19_RC_TP_IN_19       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_18 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_18_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_18_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_18_GPIO_18           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_18_CI2CHIP_MCLKI     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_18_PPKT_I_ERROR      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_18_PM_GPIO_18        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_18_TP_IN_18          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_18_RC_TP_IN_18       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_17 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_17_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_17_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_17_GPIO_17           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_17_CI2CHIP_MIVAL     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_17_PPKT_I_VALID      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_17_PM_GPIO_17        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_17_TP_IN_17          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_17_RC_TP_IN_17       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_16 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_16_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_16_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_16_GPIO_16           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_16_CI2CHIP_MISTRT    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_16_PPKT_I_SYNC       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_16_PM_GPIO_16        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_16_TP_IN_16          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_16_RC_TP_IN_16       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_15 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_15_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_15_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_15_GPIO_15           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_15_CHIP2CI_MOCLK     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_15_PPKT_O_CLK        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_15_SDS0_O_CLK        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_15_PM_GPIO_15        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_15_TP_IN_15          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_15_RC_TP_IN_15       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_14 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_14_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_14_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_14_GPIO_14           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_14_CHIP2CI_MCLKO     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_14_EXT_SC_CLK        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_14_SDS0_O_ERROR      3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_14_PM_GPIO_14        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_14_TP_IN_14          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_14_RC_TP_IN_14       6

/***************************************************************************
 *PIN_MUX_CTRL_7 - Pinmux control register 7
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_29 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_GPIO_29           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_EXT_IRQB_8        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_LED_LS_2          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_NDS_SC_AUX_0      3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_RMX_SYNC1         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_PM_GPIO_29        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_TP_IN_29          6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_29_RC_TP_IN_29       7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_28 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_GPIO_28           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_EXT_IRQB_7        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_LED_LS_1          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_NDS_SC_VCC_ALT    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_RMX_DATA1         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_PM_GPIO_28        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_TP_IN_28          6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_28_RC_TP_IN_28       7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_27 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_27_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_27_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_27_GPIO_27           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_27_EXT_IRQB_6        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_27_LED_LS_0          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_27_MEM_IO_WRB        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_27_RMX_CLK1          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_27_NDS_SC_PRES       5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_27_PM_GPIO_27        6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_27_TP_IN_27          7
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_27_RC_TP_IN_27       8

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_26 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_26_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_26_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_26_GPIO_26           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_26_AIO_EXTMCLK1      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_26_NDS_SC_RST_ALT    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_26_PM_GPIO_26        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_26_TP_IN_26          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_26_RC_TP_IN_26       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_25 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_25_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_25_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_25_GPIO_25           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_25_AIO_EXTMCLK0      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_25_NDS_SC_CLK_ALT    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_25_PM_GPIO_25        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_25_TP_IN_25          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_25_RC_TP_IN_25       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_24 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_24_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_24_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_24_GPIO_24           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_24_NDS_SC_IO         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_24_PM_GPIO_24        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_24_TP_IN_24          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_24_RC_TP_IN_24       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_23 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_23_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_23_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_23_GPIO_23           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_23_SPI_S_MISO        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_23_PWM_3             2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_23_PM_GPIO_23        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_23_TP_IN_23          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_23_RC_TP_IN_23       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_22 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_22_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_22_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_22_GPIO_22           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_22_SPI_S_SS0B        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_22_PWM_2             2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_22_PM_GPIO_22        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_22_TP_IN_22          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_22_RC_TP_IN_22       5

/***************************************************************************
 *PIN_MUX_CTRL_8 - Pinmux control register 8
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_37 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_GPIO_37           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_MII_ENET_RX_EN    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_MII_MOCA_RX_EN    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_EXT_IRQB_12       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_PM_GPIO_37        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_TP_OUT_05         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_37_RC_TP_OUT_05      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_36 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_GPIO_36           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_MII_ENET_RX_ER    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_MII_MOCA_RX_ER    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_EXT_IRQB_11       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_PM_GPIO_36        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_TP_OUT_04         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_36_RC_TP_OUT_04      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_35 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_35_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_35_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_35_GPIO_35           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_35_MII_ENET_RXD_00   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_35_MII_MOCA_RXD_00   2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_35_VEC_HSYNC_1       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_35_PM_GPIO_35        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_35_TP_OUT_03         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_35_RC_TP_OUT_03      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_34 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_34_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_34_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_34_GPIO_34           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_34_MII_ENET_RXD_01   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_34_MII_MOCA_RXD_01   2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_34_VEC_HSYNC_0       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_34_PM_GPIO_34        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_34_TP_OUT_02         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_34_RC_TP_OUT_02      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_33 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_33_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_33_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_33_GPIO_33           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_33_MII_ENET_RXD_02   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_33_MII_MOCA_RXD_02   2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_33_VEC_VSYNC_1       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_33_PM_GPIO_33        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_33_TP_OUT_01         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_33_RC_TP_OUT_01      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_32 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_32_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_32_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_32_GPIO_32           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_32_MII_ENET_RXD_03   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_32_MII_MOCA_RXD_03   2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_32_VEC_VSYNC_0       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_32_PM_GPIO_32        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_32_TP_OUT_00         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_32_RC_TP_OUT_00      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_31 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_31_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_31_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_31_GPIO_31           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_31_EXT_IRQB_10       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_31_IR_INT            2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_31_NDS_SC_VPP_ALT    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_31_RMX_VALID1        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_31_PM_GPIO_31        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_31_TP_IN_31          6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_31_RC_TP_IN_31       7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_30 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_30_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_30_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_30_GPIO_30           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_30_EXT_IRQB_9        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_30_LED_LS_3          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_30_NDS_SC_AUX_1      3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_30_RMX_PAUSE1        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_30_PM_GPIO_30        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_30_TP_IN_30          6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_30_RC_TP_IN_30       7

/***************************************************************************
 *PIN_MUX_CTRL_9 - Pinmux control register 9
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_45 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_45_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_45_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_45_GPIO_45           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_45_MII_ENET_TX_ER    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_45_MII_MOCA_TX_ER    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_45_PM_GPIO_45        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_45_TP_OUT_13         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_45_RC_TP_OUT_13      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_44 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_44_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_44_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_44_GPIO_44           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_44_MII_ENET_TX_EN    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_44_MII_MOCA_TX_EN    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_44_FSK_RX_DATA_BYP   3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_44_PM_GPIO_44        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_44_TP_OUT_12         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_44_RC_TP_OUT_12      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_43 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_43_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_43_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_43_GPIO_43           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_43_MII_ENET_TX_CLK   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_43_MII_MOCA_TX_CLK   2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_43_FSK_UART_MAN_DATA 3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_43_PM_GPIO_43        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_43_TP_OUT_11         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_43_RC_TP_OUT_11      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_42 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_42_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_42_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_42_GPIO_42           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_42_MII_ENET_MDC      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_42_MII_MOCA_MDC      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_42_PM_GPIO_42        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_42_TP_OUT_10         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_42_RC_TP_OUT_10      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_41 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_41_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_41_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_41_GPIO_41           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_41_MII_ENET_MDIO     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_41_MII_MOCA_MDIO     2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_41_PM_GPIO_41        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_41_TP_OUT_09         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_41_RC_TP_OUT_09      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_40 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_40_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_40_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_40_GPIO_40           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_40_MII_ENET_RX_CLK   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_40_MII_MOCA_RX_CLK   2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_40_PM_GPIO_40        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_40_TP_OUT_08         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_40_RC_TP_OUT_08      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_39 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_39_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_39_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_39_GPIO_39           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_39_MII_ENET_COL      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_39_MII_MOCA_COL      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_39_PM_GPIO_39        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_39_TP_OUT_07         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_39_RC_TP_OUT_07      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_38 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_38_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_38_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_38_GPIO_38           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_38_MII_ENET_CRS      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_38_MII_MOCA_CRS      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_38_PM_GPIO_38        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_38_TP_OUT_06         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_38_RC_TP_OUT_06      5

/***************************************************************************
 *PIN_MUX_CTRL_10 - Pinmux control register 10
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_54 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_54_MASK             0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_54_SHIFT            28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_54_GPIO_54          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_54_NDS_SC_CLK       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_54_CI2CHIP_MDI_1    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_54_PPKT_I_DATA_1    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_54_SC_CLK_OUT_0     4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_54_PM_GPIO_54       5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_54_TP_OUT_22        6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_54_RC_TP_OUT_22     7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_53 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_53_MASK             0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_53_SHIFT            24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_53_GPIO_53          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_53_NDS_SC_IO        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_53_CI2CHIP_MDI_0    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_53_PPKT_I_DATA_0    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_53_SC_IO_0          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_53_PM_GPIO_53       5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_53_TP_OUT_21        6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_53_RC_TP_OUT_21     7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_51 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_51_MASK             0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_51_SHIFT            20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_51_GPIO_51          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_51_PWM_1            1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_51_PM_GPIO_51       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_51_TP_OUT_19        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_51_RC_TP_OUT_19     4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_50 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_50_MASK             0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_50_SHIFT            16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_50_GPIO_50          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_50_PWM_0            1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_50_PM_GPIO_50       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_50_TP_OUT_18        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_50_RC_TP_OUT_18     4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_49 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_49_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_49_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_49_GPIO_49          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_49_MII_ENET_TXD_00  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_49_MII_MOCA_TXD_00  2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_49_EXT_IRQB_14      3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_49_PM_GPIO_49       4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_49_TP_OUT_17        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_49_RC_TP_OUT_17     6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_48 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_48_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_48_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_48_GPIO_48          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_48_MII_ENET_TXD_01  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_48_MII_MOCA_TXD_01  2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_48_EXT_IRQB_13      3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_48_PM_GPIO_48       4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_48_TP_OUT_16        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_48_RC_TP_OUT_16     6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_47 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_47_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_47_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_47_GPIO_47          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_47_MII_ENET_TXD_02  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_47_MII_MOCA_TXD_02  2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_47_PM_GPIO_47       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_47_TP_OUT_15        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_47_RC_TP_OUT_15     5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_10 :: gpio_46 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_46_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_46_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_46_GPIO_46          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_46_MII_ENET_TXD_03  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_46_MII_MOCA_TXD_03  2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_46_PM_GPIO_46       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_46_TP_OUT_14        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_10_gpio_46_RC_TP_OUT_14     5

/***************************************************************************
 *PIN_MUX_CTRL_11 - Pinmux control register 11
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_62 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_62_MASK             0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_62_SHIFT            28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_62_GPIO_62          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_62_SC_CLK_OUT_1     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_62_PM_GPIO_62       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_62_TP_OUT_30        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_62_RC_TP_OUT_30     4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_61 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_61_MASK             0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_61_SHIFT            24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_61_GPIO_61          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_61_SC_IO_1          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_61_PM_GPIO_61       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_61_TP_OUT_29        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_61_RC_TP_OUT_29     4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_60 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_60_MASK             0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_60_SHIFT            20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_60_GPIO_60          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_60_NDS_SC_VPP       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_60_CI2CHIP_MDI_7    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_60_PPKT_I_DATA_7    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_60_PM_GPIO_60       4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_60_TP_OUT_28        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_60_RC_TP_OUT_28     6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_59 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_59_MASK             0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_59_SHIFT            16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_59_GPIO_59          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_59_NDS_SC_AUX_1     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_59_CI2CHIP_MDI_6    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_59_PPKT_I_DATA_6    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_59_PM_GPIO_59       4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_59_TP_OUT_27        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_59_RC_TP_OUT_27     6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_58 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_58_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_58_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_58_GPIO_58          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_58_NDS_SC_AUX_0     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_58_CI2CHIP_MDI_5    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_58_PPKT_I_DATA_5    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_58_PM_GPIO_58       4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_58_TP_OUT_26        5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_58_RC_TP_OUT_26     6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_57 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_57_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_57_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_57_GPIO_57          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_57_NDS_SC_VCC       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_57_CI2CHIP_MDI_4    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_57_PPKT_I_DATA_4    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_57_SC_VCC_0         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_57_PM_GPIO_57       5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_57_TP_OUT_25        6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_57_RC_TP_OUT_25     7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_56 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_56_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_56_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_56_GPIO_56          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_56_NDS_SC_PRES      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_56_CI2CHIP_MDI_3    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_56_PPKT_I_DATA_3    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_56_SC_PRES_0        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_56_PM_GPIO_56       5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_56_TP_OUT_24        6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_56_RC_TP_OUT_24     7

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_11 :: gpio_55 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_55_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_55_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_55_GPIO_55          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_55_NDS_SC_RST       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_55_CI2CHIP_MDI_2    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_55_PPKT_I_DATA_2    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_55_SC_RST_0         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_55_PM_GPIO_55       5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_55_TP_OUT_23        6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_11_gpio_55_RC_TP_OUT_23     7

/***************************************************************************
 *PIN_MUX_CTRL_12 - Pinmux control register 12
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_70 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_70_MASK             0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_70_SHIFT            28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_70_GPIO_70          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_70_PKT_ERROR1       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_70_QPSK_DEMOD_ERROR 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_70_QPSK_BERT_ERROR  3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_70_I2S_O_CLK        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_70_SDS0_DEMOD_ERROR_ALT 5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_70_PM_GPIO_70       6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_70_ALT_TP_OUT_07    7
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_70_RC_ALT_TP_OUT_07 8

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_69 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_69_MASK             0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_69_SHIFT            24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_69_GPIO_69          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_69_PKT_VALID1       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_69_QPSK_DEMOD_VALID 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_69_QPSK_BERT_VALID  3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_69_SPARE0_ON_GPIO_69 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_69_SDS0_DEMOD_VALID_ALT 5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_69_PM_GPIO_69       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_68 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_68_MASK             0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_68_SHIFT            20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_68_GPIO_68          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_68_PKT_SYNC1        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_68_QPSK_DEMOD_SYNC  2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_68_QPSK_BERT_SYNC   3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_68_SPARE0_ON_GPIO_68 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_68_SDS0_DEMOD_SYNC_ALT 5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_68_PM_GPIO_68       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_67 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_67_MASK             0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_67_SHIFT            16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_67_GPIO_67          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_67_PKT_DATA1        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_67_QPSK_DEMOD_DATA  2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_67_QPSK_BERT_DATA   3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_67_SPARE0_ON_GPIO_67 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_67_SDS0_DEMOD_DATA_ALT 5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_67_PM_GPIO_67       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_66 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_66_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_66_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_66_GPIO_66          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_66_PKT_CLK1         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_66_QPSK_DEMOD_CLK   2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_66_QPSK_BERT_CLK    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_66_SPARE0_ON_GPIO_66 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_66_SDS0_DEMOD_CLK_ALT 5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_66_PM_GPIO_66       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_65 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_65_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_65_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_65_GPIO_65          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_65_SC_VCC_1         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_65_PM_GPIO_65       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_65_ALT_TP_OUT_01    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_65_RC_ALT_TP_OUT_01 4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_64 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_64_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_64_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_64_GPIO_64          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_64_SC_PRES_1        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_64_PM_GPIO_64       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_64_ALT_TP_OUT_00    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_64_RC_ALT_TP_OUT_00 4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_12 :: gpio_63 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_63_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_63_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_63_GPIO_63          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_63_SC_RST_1         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_63_PM_GPIO_63       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_63_TP_OUT_31        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_12_gpio_63_RC_TP_OUT_31     4

/***************************************************************************
 *PIN_MUX_CTRL_13 - Pinmux control register 13
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_77 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_77_MASK             0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_77_SHIFT            28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_77_GPIO_77          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_77_EPHY_ACTIVITY    1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_77_MOCA_ACTIVE_N    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_77_PM_GPIO_77       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_77_ALT_TP_OUT_14    4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_77_RC_ALT_TP_OUT_14 5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_52 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_52_MASK             0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_52_SHIFT            24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_52_GPIO_52          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_52_EPHY_LINK        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_52_MOCA_LINK_N      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_52_PM_GPIO_52       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_52_ALT_TP_OUT_13    4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_52_RC_ALT_TP_OUT_13 5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_76 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_76_MASK             0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_76_SHIFT            20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_76_GPIO_76          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_76_SDS0_RF_AGC      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_76_PM_GPIO_76       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_76_ALT_TP_OUT_12    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_76_RC_ALT_TP_OUT_12 4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_75 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_75_MASK             0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_75_SHIFT            16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_75_GPIO_75          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_75_SDS0_IF_AGC      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_75_PM_GPIO_75       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_75_ALT_TP_OUT_11    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_75_RC_ALT_TP_OUT_11 4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_74 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_74_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_74_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_74_GPIO_74          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_74_QPSK_RF_AGC      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_74_PM_GPIO_74       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_74_ALT_TP_OUT_10    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_74_RC_ALT_TP_OUT_10 4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_73 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_73_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_73_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_73_GPIO_73          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_73_QPSK_IF_AGC      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_73_PM_GPIO_73       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_73_ALT_TP_OUT_09    3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_73_RC_ALT_TP_OUT_09 4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_72 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_72_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_72_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_72_GPIO_72          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_72_IR_IN1           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_72_UHF_LNA_PWRDN    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_72_PM_GPIO_72       3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_13 :: gpio_71 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_71_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_71_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_71_GPIO_71          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_71_IR_IN0           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_71_UHF_LNA_PWRDN    2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_71_PM_GPIO_71       3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_71_ALT_TP_OUT_08    4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_13_gpio_71_RC_ALT_TP_OUT_08 5

/***************************************************************************
 *PIN_MUX_CTRL_14 - Pinmux control register 14
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_07 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_07_MASK            0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_07_SHIFT           28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_07_SGPIO_07        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_07_BSC_M3_SDA      1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_06 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_06_MASK            0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_06_SHIFT           24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_06_SGPIO_06        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_06_BSC_M3_SCL      1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_05 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_05_MASK            0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_05_SHIFT           20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_05_SGPIO_05        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_05_BSC_M2_SDA      1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_04 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_04_MASK            0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_04_SHIFT           16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_04_SGPIO_04        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_04_BSC_M2_SCL      1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_03 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_03_MASK            0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_03_SHIFT           12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_03_SGPIO_03        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_03_BSC_M1_SDA      1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_02 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_02_MASK            0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_02_SHIFT           8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_02_SGPIO_02        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_02_BSC_M1_SCL      1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_01 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_MASK            0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_SHIFT           4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_SGPIO_01        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_01_BSC_M0_SDA      1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_14 :: sgpio_00 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_MASK            0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_SHIFT           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_SGPIO_00        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_14_sgpio_00_BSC_M0_SCL      1

/***************************************************************************
 *PIN_MUX_CTRL_15 - Pinmux control register 15
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: rmx_sync0 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_sync0_MASK           0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_sync0_SHIFT          28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_sync0_RMX_SYNC0      0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_sync0_ALT_TP_OUT_17  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_sync0_RC_ALT_TP_OUT_17 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: rmx_data0 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_data0_MASK           0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_data0_SHIFT          24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_data0_RMX_DATA0      0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_data0_ALT_TP_OUT_16  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_data0_RC_ALT_TP_OUT_16 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: rmx_clk0 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_clk0_MASK            0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_clk0_SHIFT           20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_clk0_RMX_CLK0        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_clk0_ALT_TP_OUT_15   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_rmx_clk0_RC_ALT_TP_OUT_15 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: pkt_error0 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_error0_MASK          0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_error0_SHIFT         16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_error0_PKT_ERROR0    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_error0_SDS0_DEMOD_ERROR 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_error0_SDS0_BERT_ERROR 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_error0_SPARE0_ON_PKT_ERROR0 3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_error0_QPSK_DEMOD_ERROR_ALT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_error0_PM_PKT_ERROR0 5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: pkt_valid0 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_valid0_MASK          0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_valid0_SHIFT         12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_valid0_PKT_VALID0    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_valid0_SDS0_DEMOD_VALID 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_valid0_SDS0_BERT_VALID 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_valid0_TSPI_MOCA_RSTB 3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_valid0_QPSK_DEMOD_VALID_ALT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_valid0_PM_PKT_VALID0 5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: pkt_sync0 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_sync0_MASK           0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_sync0_SHIFT          8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_sync0_PKT_SYNC0      0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_sync0_SDS0_DEMOD_SYNC 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_sync0_SDS0_BERT_SYNC 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_sync0_TSPI_MOCA_SCL  3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_sync0_QPSK_DEMOD_SYNC_ALT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_sync0_PM_PKT_SYNC0   5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: pkt_data0 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_data0_MASK           0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_data0_SHIFT          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_data0_PKT_DATA0      0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_data0_SDS0_DEMOD_DATA 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_data0_SDS0_BERT_DATA 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_data0_TSPI_MOCA_SSB  3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_data0_QPSK_DEMOD_DATA_ALT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_data0_PM_PKT_DATA0   5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_15 :: pkt_clk0 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_clk0_MASK            0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_clk0_SHIFT           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_clk0_PKT_CLK0        0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_clk0_SDS0_DEMOD_CLK  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_clk0_SDS0_BERT_CLK   2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_clk0_TSPI_MOCA_MOSI  3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_clk0_QPSK_DEMOD_CLK_ALT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_15_pkt_clk0_PM_PKT_CLK0     5

/***************************************************************************
 *PIN_MUX_CTRL_16 - Pinmux control register 16
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: codec_mclk [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_MASK          0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_SHIFT         28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_CODEC_MCLK    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_PM_CODEC_MCLK 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_ALT_TP_OUT_19 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_codec_mclk_RC_ALT_TP_OUT_19 3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: ir_out [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_IR_OUT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_ALT_TP_OUT_18     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_ir_out_RC_ALT_TP_OUT_18  2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: spi_m_ss2b [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss2b_MASK          0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss2b_SHIFT         20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss2b_SPI_M_SS2B    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss2b_PM_SPI_M_SS2B 1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: spi_m_ss1b [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss1b_MASK          0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss1b_SHIFT         16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss1b_SPI_M_SS1B    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss1b_PM_SPI_M_SS1B 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss1b_ALT_TP_OUT_06 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss1b_RC_ALT_TP_OUT_06 3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: spi_m_ss0b [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss0b_MASK          0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss0b_SHIFT         12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss0b_SPI_M_SS0B    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss0b_PM_SPI_M_SS0B 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss0b_ALT_TP_OUT_05 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_ss0b_RC_ALT_TP_OUT_05 3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: spi_m_miso [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_miso_MASK          0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_miso_SHIFT         8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_miso_SPI_M_MISO    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_miso_PM_SPI_M_MISO 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_miso_ALT_TP_OUT_04 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_miso_RC_ALT_TP_OUT_04 3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: spi_m_mosi [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_mosi_MASK          0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_mosi_SHIFT         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_mosi_SPI_M_MOSI    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_mosi_PM_SPI_M_MOSI 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_mosi_ALT_TP_OUT_03 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_mosi_RC_ALT_TP_OUT_03 3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_16 :: spi_m_sck [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_sck_MASK           0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_sck_SHIFT          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_sck_SPI_M_SCK      0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_sck_PM_SPI_M_SCK   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_sck_ALT_TP_OUT_02  2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_16_spi_m_sck_RC_ALT_TP_OUT_02 3

/***************************************************************************
 *PIN_MUX_CTRL_17 - Pinmux control register 17
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_rtsab [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_MASK          0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_SHIFT         28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_UART_RTSAB    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_ALT_TP_OUT_27 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rtsab_RC_ALT_TP_OUT_27 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_ctsab [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_MASK          0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_SHIFT         24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_UART_CTSAB    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_ALT_TP_OUT_26 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_ctsab_RC_ALT_TP_OUT_26 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_txda [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_MASK           0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_SHIFT          20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_UART_TXDA      0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_ALT_TP_OUT_25  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_txda_RC_ALT_TP_OUT_25 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: uart_rxda [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_MASK           0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_SHIFT          16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_UART_RXDA      0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_ALT_TP_IN_24   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_uart_rxda_RC_ALT_TP_IN_24 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: codec_fsync [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_MASK         0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_SHIFT        12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_CODEC_FSYNC  0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_PM_CODEC_FSYNC 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_ALT_TP_OUT_23 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_fsync_RC_ALT_TP_OUT_23 3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: codec_sdo [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_MASK           0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_SHIFT          8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_CODEC_SDO      0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_PM_CODEC_SDO   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_ALT_TP_OUT_22  2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdo_RC_ALT_TP_OUT_22 3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: codec_sdi [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdi_MASK           0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdi_SHIFT          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdi_CODEC_SDI      0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdi_PM_CODEC_SDI   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdi_ALT_TP_OUT_21  2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sdi_RC_ALT_TP_OUT_21 3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_17 :: codec_sclk [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sclk_MASK          0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sclk_SHIFT         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sclk_CODEC_SCLK    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sclk_PM_CODEC_SCLK 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sclk_ALT_TP_OUT_20 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_17_codec_sclk_RC_ALT_TP_OUT_20 3

/***************************************************************************
 *PIN_MUX_CTRL_18 - Pinmux control register 18
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: reserved0 [31:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_MASK           0xfff00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_reserved0_SHIFT          20

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: nmib [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_nmib_MASK                0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_nmib_SHIFT               16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_nmib_NMIB                0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_nmib_TSPI_MOCA_MISO      1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: uart_rtsbb [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_MASK          0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_SHIFT         12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_UART_RTSBB    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_ALT_TP_OUT_31 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rtsbb_RC_ALT_TP_OUT_31 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: uart_ctsbb [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_MASK          0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_SHIFT         8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_UART_CTSBB    0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_ALT_TP_OUT_30 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_ctsbb_RC_ALT_TP_OUT_30 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: uart_txdb [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_txdb_MASK           0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_txdb_SHIFT          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_txdb_UART_TXDB      0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_txdb_ALT_TP_OUT_29  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_txdb_RC_ALT_TP_OUT_29 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_18 :: uart_rxdb [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rxdb_MASK           0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rxdb_SHIFT          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rxdb_UART_RXDB      0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rxdb_ALT_TP_IN_28   1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_18_uart_rxdb_RC_ALT_TP_IN_28 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [29:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x3fffffff
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0

/***************************************************************************
 *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3fffffff
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       0

/***************************************************************************
 *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: reserved0 [29:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_MASK        0x3fffffff
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_reserved0_SHIFT       0

/***************************************************************************
 *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: reserved0 [29:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_MASK        0x3fffffff
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_reserved0_SHIFT       0

/***************************************************************************
 *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: reserved0 [29:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_MASK        0x3fffffff
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_reserved0_SHIFT       0

/***************************************************************************
 *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_01_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_01_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_00_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_00_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [25:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK        0x03ffffff
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT       0

/***************************************************************************
 *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_16_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_16_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_15_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_15_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_14_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_14_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_14_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_14_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_14_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_14_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_13_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_13_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_13_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_13_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_13_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_13_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_12_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_12_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_12_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_12_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_12_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_12_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_11_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_11_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_11_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_11_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_11_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_11_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_10_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_10_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_10_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_10_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_10_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_10_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_09_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_09_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_09_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_09_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_09_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_09_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_08_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_08_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_08_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_08_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_08_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_08_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_07_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_07_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_07_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_07_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_07_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_07_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_06_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_06_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_06_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_06_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_06_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_06_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_05_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_05_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_05_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_05_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_05_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_05_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_04_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_04_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_04_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_04_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_04_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_04_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_03_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_03_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_03_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_03_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_03_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_03_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: gpio_02_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_02_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_02_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_02_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_02_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_gpio_02_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_7 - Pad pull-up/pull-down control register 7
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: spare_pad_ctrl_7 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_spare_pad_ctrl_7_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_31_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_31_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_31_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_31_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_31_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_31_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_30_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_30_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_30_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_30_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_30_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_30_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_29_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_29_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_29_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_29_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_29_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_29_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_28_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_28_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_28_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_28_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_28_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_28_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_27_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_27_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_27_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_27_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_27_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_27_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_26_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_26_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_26_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_26_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_26_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_26_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_25_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_25_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_25_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_25_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_25_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_25_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_24_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_24_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_24_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_24_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_24_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_24_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_23_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_23_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_23_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_23_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_23_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_23_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_22_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_22_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_22_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_22_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_22_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_22_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_21_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_21_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_21_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_21_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_21_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_21_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_20_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_20_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_20_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_20_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_20_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_20_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_19_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_19_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_19_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_19_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_19_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_19_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_18_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_18_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_18_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_18_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_18_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_18_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_7 :: gpio_17_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_17_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_17_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_17_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_17_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_7_gpio_17_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_8 - Pad pull-up/pull-down control register 8
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: spare_pad_ctrl_8 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_spare_pad_ctrl_8_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_46_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_46_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_46_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_46_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_46_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_46_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_45_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_45_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_45_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_45_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_45_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_45_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_44_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_44_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_44_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_44_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_44_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_44_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_43_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_43_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_43_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_43_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_43_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_43_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_42_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_42_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_42_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_42_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_42_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_42_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_41_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_41_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_41_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_41_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_41_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_41_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_40_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_40_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_40_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_40_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_40_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_40_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_39_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_39_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_39_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_39_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_39_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_39_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_38_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_38_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_38_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_38_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_38_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_38_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_37_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_37_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_37_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_37_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_37_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_37_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_36_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_36_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_36_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_36_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_36_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_36_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_35_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_35_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_35_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_35_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_35_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_35_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_34_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_34_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_34_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_34_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_34_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_34_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_33_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_33_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_33_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_33_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_33_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_33_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_8 :: gpio_32_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_32_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_32_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_32_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_32_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_8_gpio_32_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_9 - Pad pull-up/pull-down control register 9
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: spare_pad_ctrl_9 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_spare_pad_ctrl_9_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_62_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_62_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_61_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_61_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_60_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_60_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_59_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_59_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_58_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_58_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_57_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_57_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_56_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_56_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_56_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_56_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_56_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_56_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_55_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_55_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_55_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_55_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_55_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_55_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_54_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_54_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_54_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_54_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_54_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_54_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_53_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_53_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_53_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_53_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_53_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_53_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_51_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_51_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_51_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_51_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_51_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_51_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_50_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_50_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_50_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_50_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_50_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_50_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_49_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_49_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_49_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_49_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_49_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_49_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_48_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_48_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_48_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_48_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_48_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_48_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_9 :: gpio_47_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_47_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_47_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_47_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_47_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_9_gpio_47_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_10 - Pad pull-up/pull-down control register 10
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: spare_pad_ctrl_10 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_spare_pad_ctrl_10_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_52_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_52_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_52_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_52_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_52_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_52_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_76_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_76_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_76_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_76_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_76_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_76_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_75_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_75_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_75_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_75_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_75_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_75_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_74_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_74_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_74_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_74_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_74_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_74_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_73_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_73_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_73_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_73_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_73_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_73_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_72_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_72_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_72_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_72_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_72_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_72_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_71_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_71_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_71_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_71_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_71_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_71_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_70_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_70_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_70_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_70_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_70_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_70_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_69_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_69_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_69_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_69_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_69_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_69_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_68_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_68_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_68_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_68_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_68_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_68_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_67_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_67_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_67_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_67_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_67_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_67_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_66_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_66_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_65_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_65_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_65_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_65_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_65_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_65_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_64_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_64_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_64_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_64_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_64_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_64_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_10 :: gpio_63_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_63_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_63_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_63_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_63_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_10_gpio_63_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_11 - Pad pull-up/pull-down control register 11
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: spare_pad_ctrl_11 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_spare_pad_ctrl_11_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: reserved0 [29:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_MASK       0x3ffffffc
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_reserved0_SHIFT      2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_11 :: gpio_77_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_77_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_77_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_77_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_77_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_11_gpio_77_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_12 - Pad pull-up/pull-down control register 12
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: spare_pad_ctrl_12 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_spare_pad_ctrl_12_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_12 :: reserved0 [29:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_MASK       0x3fffffff
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_12_reserved0_SHIFT      0

/***************************************************************************
 *PIN_MUX_PAD_CTRL_13 - Pad pull-up/pull-down control register 13
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: spare_pad_ctrl_13 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_spare_pad_ctrl_13_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_13 :: reserved0 [29:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved0_MASK       0x3fffffff
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_13_reserved0_SHIFT      0

/***************************************************************************
 *PIN_MUX_PAD_CTRL_14 - Pad pull-up/pull-down control register 14
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_14 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_reserved0_MASK       0xffffff00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_reserved0_SHIFT      8

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_14 :: spare_pad_ctrl_14 [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_spare_pad_ctrl_14_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_14 :: reserved1 [05:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_reserved1_MASK       0x0000003f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_14_reserved1_SHIFT      0

/***************************************************************************
 *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:24] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xff000000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       24

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_test_rsvd_4 [23:23] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_test_rsvd_4_MASK 0x00800000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_test_rsvd_4_SHIFT 23

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_test_rsvd_3 [22:22] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_test_rsvd_3_MASK 0x00400000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_test_rsvd_3_SHIFT 22

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_test_rsvd_2 [21:21] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_test_rsvd_2_MASK 0x00200000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_test_rsvd_2_SHIFT 21

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_test_rsvd_1 [20:20] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_test_rsvd_1_MASK 0x00100000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_test_rsvd_1_SHIFT 20

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_test_rsvd_0 [19:19] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_test_rsvd_0_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_test_rsvd_0_SHIFT 19

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_spi_m_ss2b [18:18] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_spi_m_ss2b_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_spi_m_ss2b_SHIFT 18

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pkt_valid0 [17:17] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_valid0_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_valid0_SHIFT 17

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pkt_clk0 [16:16] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_clk0_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pkt_clk0_SHIFT 16

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_72 [15:15] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_72_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_72_SHIFT 15

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_69 [14:14] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_69_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_69_SHIFT 14

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_68 [13:13] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_68_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_68_SHIFT 13

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_67 [12:12] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_67_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_67_SHIFT 12

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_66 [11:11] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_66_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_66_SHIFT 11

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_cs3b [10:10] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_cs3b_SHIFT 10

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_ebi_nand_rbb [09:09] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_rbb_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_ebi_nand_rbb_SHIFT 9

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pci_gnt2b [08:08] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_gnt2b_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_gnt2b_SHIFT 8

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pci_req2b [07:07] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_req2b_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_req2b_SHIFT 7

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pci_gnt1b [06:06] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_gnt1b_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_gnt1b_SHIFT 6

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pci_int_a2 [05:05] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_int_a2_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_int_a2_SHIFT 5

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_pci_int_a1 [04:04] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_int_a1_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_pci_int_a1_SHIFT 4

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_cpu_clk [03:03] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_SHIFT 3

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_moca_clk [02:02] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_moca_clk_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_moca_clk_SHIFT 2

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_clk_acc [01:01] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_clk_acc_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_clk_acc_SHIFT 1

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_vcxo27 [00:00] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_vcxo27_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_vcxo27_SHIFT 0

/***************************************************************************
 *TEST_PORT_CTRL - Test port control
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sundry_local_tp_out_sel [31:28] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MASK 0xf0000000
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SHIFT 28
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_0 0
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_1 1
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_FP_RST_CNT 2
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MISC_TEST 3
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SSP 4
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_OUT_POKE_REG 5
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_IN 6
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UHFR_TP 7
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_DAA_TP 8
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SOFT_MODEM_TP 9
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_PWR_CTRL_STATUS 10
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_PWR_CTRL_IRQ_IN 11
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UPG_TP_OUT 12
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TOP_AUX_TP_OUT 15

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_ENET    0
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     1
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_A  2
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_R  3
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_QPSK_R  4
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SDS0_T  5
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK     6
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     7
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_GFX     8
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     9
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB     10
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SUN     11
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MAD     12
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     13
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RPTD    14
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     15
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    16
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     17
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    18
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HDMI    19
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    20
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_FTM     21
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC    22
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCA    23
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MOCAD   24
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DDR_APHY 25
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CG_MIPS 26
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UNUSED_31 31

/***************************************************************************
 *TEST_PORT_OUT_PEEK - Testport peek register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0

/***************************************************************************
 *TEST_PORT_OUT_POKE - Testport poke register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0

/***************************************************************************
 *TEST_PORT_IN_PEEK - Testport peek register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0

/***************************************************************************
 *TEST_PORT_IN_POKE - Testport poke register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0

/***************************************************************************
 *EJTAG_INPUT_EN - EJTAG input bus enables
 ***************************************************************************/
/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:04] */
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff0
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           4

/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [03:00] */
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x0000000f
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AUDIO_ZSP_CPU_ONE_HOT 4
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MOCA_CPU_ONE_HOT 8

/***************************************************************************
 *EJTAG_OUTPUT_SEL - EJTAG output select
 ***************************************************************************/
/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:03] */
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff8
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         3

/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [02:00] */
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x00000007
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AUDIO_ZSP_CPU 2
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MOCA_CPU 3

/***************************************************************************
 *UART_ROUTER_SEL - UART Router select
 ***************************************************************************/
/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15

/***************************************************************************
 *SSP_CONFIG - Serial Slave Port configuration register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11

/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7

/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3

/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2

/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1

/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0

/***************************************************************************
 *SERS_REV - SERS Revision Register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16

/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8

/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0

/***************************************************************************
 *SERS_CFG - SERS Configuration Register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29

/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1

/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27

/* union - case mapped_buffer_mode [26:08] */
/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8

/* union - case cmd_fifo_mode [26:08] */
/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8

/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1

/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0

/***************************************************************************
 *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
 ***************************************************************************/
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00404328
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32

/***************************************************************************
 *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0


/***************************************************************************
 *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
 ***************************************************************************/
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00404348
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32

/***************************************************************************
 *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0


/***************************************************************************
 *RO_TEST_BLOCK_SEL - Block select for RO testmode
 ***************************************************************************/
/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5

/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [04:03] */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x00000018
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 3

/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [02:00] */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000007
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_USB_RO_TEST_ID 1
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SUN_RO_TEST_ID 2
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC0_RO_TEST_ID 3
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_PROD_OSC1_RO_TEST_ID 4
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SDS_RCVR_RO_TEST_ID 5
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_FTM_RO_TEST_ID 6
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MIPS_RO_TEST_ID 7

/***************************************************************************
 *TEST_MODE_CTRL - Test_mode control register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_MODE_CTRL :: reserved0 [31:01] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_reserved0_SHIFT           1

/* SUN_TOP_CTRL :: TEST_MODE_CTRL :: use_test_mode_reg_src [00:00] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_use_test_mode_reg_src_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_use_test_mode_reg_src_SHIFT 0

/***************************************************************************
 *TEST_MODE - Register source for test_mode
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_MODE :: reserved0 [31:04] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_MASK                 0xfffffff0
#define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_SHIFT                4

/* SUN_TOP_CTRL :: TEST_MODE :: test_mode [03:00] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_MASK                 0x0000000f
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_SHIFT                0

/***************************************************************************
 *SUB_TEST_MODE - Register source for sub_test_mode
 ***************************************************************************/
/* SUN_TOP_CTRL :: SUB_TEST_MODE :: reserved0 [31:09] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_reserved0_MASK             0xfffffe00
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_reserved0_SHIFT            9

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [08:08] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT 8

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_ecc_disable [07:07] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_ecc_disable_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_ecc_disable_SHIFT 7

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_d2cdiff_ac [06:06] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_SHIFT 6

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT 5

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT 0

/***************************************************************************
 *LATCHED_TEST_MODE - Final latched testmode value
 ***************************************************************************/
/* SUN_TOP_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
#define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT 0

/***************************************************************************
 *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
 ***************************************************************************/
/* SUN_TOP_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
#define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0

/***************************************************************************
 *PM_CTRL - Control register for Power Controller
 ***************************************************************************/
/* SUN_TOP_CTRL :: PM_CTRL :: pm_wait_count_upper_bits [31:20] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_count_upper_bits_MASK    0xfff00000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_count_upper_bits_SHIFT   20

/* SUN_TOP_CTRL :: PM_CTRL :: pm_wait_counter_active [19:19] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_counter_active_MASK      0x00080000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_counter_active_SHIFT     19

/* SUN_TOP_CTRL :: PM_CTRL :: pm_rst_clock_div [18:18] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_rst_clock_div_MASK            0x00040000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_rst_clock_div_SHIFT           18

/* SUN_TOP_CTRL :: PM_CTRL :: pm_pwrdn_pll_req [17:17] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pwrdn_pll_req_MASK            0x00020000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pwrdn_pll_req_SHIFT           17

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_cml_clocks [16:16] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cml_clocks_MASK           0x00010000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cml_clocks_SHIFT          16

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_all_clocks [15:15] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_all_clocks_MASK           0x00008000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_all_clocks_SHIFT          15

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_cpu_clock [14:14] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cpu_clock_MASK            0x00004000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cpu_clock_SHIFT           14

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_avd_rptd_clock [13:13] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_avd_rptd_clock_MASK       0x00002000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_avd_rptd_clock_SHIFT      13

/* SUN_TOP_CTRL :: PM_CTRL :: pm_pll_lock [12:12] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pll_lock_MASK                 0x00001000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pll_lock_SHIFT                12

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dram_ready_for_pwrdn [11:11] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dram_ready_for_pwrdn_MASK     0x00000800
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dram_ready_for_pwrdn_SHIFT    11

/* SUN_TOP_CTRL :: PM_CTRL :: pm_bsp_ready_for_pwrdn [10:10] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_MASK      0x00000400
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_SHIFT     10

/* SUN_TOP_CTRL :: PM_CTRL :: pm_mips_ready_for_pwrdn [09:09] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_mips_ready_for_pwrdn_MASK     0x00000200
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_mips_ready_for_pwrdn_SHIFT    9

/* SUN_TOP_CTRL :: PM_CTRL :: pm_sec_avd_rptd_clk_disable [08:08] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_sec_avd_rptd_clk_disable_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_sec_avd_rptd_clk_disable_SHIFT 8

/* SUN_TOP_CTRL :: PM_CTRL :: pm_state [07:04] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_MASK                    0x000000f0
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_SHIFT                   4
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_ACTIVE               0
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_PWRDN_RDY            1
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_DISABLE_AVD_RPTD     2
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_DISABLE_CPU          3
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_TRANSITION_TO_STANDBY 4
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_STANDBY              5
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_STANDBY_WITH_PLLS_ON 6
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_RESET_216_108_CLKS   7
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_TRANSITION_TO_ACTIVE 8

/* SUN_TOP_CTRL :: PM_CTRL :: pm_power_ctrl_disable [03:03] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_power_ctrl_disable_MASK       0x00000008
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_power_ctrl_disable_SHIFT      3

/* SUN_TOP_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK      0x00000004
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT     2

/* SUN_TOP_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK         0x00000002
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT        1

/* SUN_TOP_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_start_pwrdn_MASK              0x00000001
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT             0

/***************************************************************************
 *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
 ***************************************************************************/
/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: reserved0 [31:18] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_reserved0_MASK       0xfffc0000
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_reserved0_SHIFT      18

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: spare_wakeup_event_0 [17:17] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_spare_wakeup_event_0_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_spare_wakeup_event_0_SHIFT 17

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: xpt_pmu_wakeup [16:16] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_xpt_pmu_wakeup_MASK  0x00010000
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_xpt_pmu_wakeup_SHIFT 16

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: ftm_wakeup [15:15] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_ftm_wakeup_MASK      0x00008000
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_ftm_wakeup_SHIFT     15

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: qpsk_rcvr_1_wakeup [14:14] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_qpsk_rcvr_1_wakeup_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_qpsk_rcvr_1_wakeup_SHIFT 14

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: qpsk_rcvr_0_wakeup [13:13] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_qpsk_rcvr_0_wakeup_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_qpsk_rcvr_0_wakeup_SHIFT 13

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: sds0_afec_wakeup [12:12] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_sds0_afec_wakeup_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_sds0_afec_wakeup_SHIFT 12

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: sds0_tfec_wakeup [11:11] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_sds0_tfec_wakeup_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_sds0_tfec_wakeup_SHIFT 11

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: sds0_rcvr_1_wakeup [10:10] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_sds0_rcvr_1_wakeup_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_sds0_rcvr_1_wakeup_SHIFT 10

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: sds0_rcvr_0_wakeup [09:09] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_sds0_rcvr_0_wakeup_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_sds0_rcvr_0_wakeup_SHIFT 9

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: wol_enet_wakeup [08:08] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_wol_enet_wakeup_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_wol_enet_wakeup_SHIFT 8

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: wol_moca_wakeup [07:07] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_wol_moca_wakeup_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_wol_moca_wakeup_SHIFT 7

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: uhfr_wakeup [06:06] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_uhfr_wakeup_MASK     0x00000040
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_uhfr_wakeup_SHIFT    6

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: gpio_wakeup [05:05] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_gpio_wakeup_MASK     0x00000020
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_gpio_wakeup_SHIFT    5

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: nmi_wakeup [04:04] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_nmi_wakeup_MASK      0x00000010
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_nmi_wakeup_SHIFT     4

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: timer_wakeup [03:03] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_timer_wakeup_MASK    0x00000008
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_timer_wakeup_SHIFT   3

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: kpd_wakeup [02:02] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_kpd_wakeup_MASK      0x00000004
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_kpd_wakeup_SHIFT     2

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: irr_wakeup [01:01] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_irr_wakeup_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_irr_wakeup_SHIFT     1

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: cec_wakeup [00:00] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_cec_wakeup_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_cec_wakeup_SHIFT     0

/***************************************************************************
 *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
 ***************************************************************************/
/* SUN_TOP_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK        0xffff0000
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT       16

/* SUN_TOP_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK 0x0000ffff
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0

#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */

/* End of File */