/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Wed Nov 18 01:09:56 2009
 *                 MD5 Checksum         8e4822e2d8c445f841e653dc06da5e41
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7340/rdb/b0/bchp_clkgen.h $
 * 
 * Hydra_Software_Devel/1   11/18/09 5:06a albertl
 * SW7340-102: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_CLKGEN_H__
#define BCHP_CLKGEN_H__

/***************************************************************************
 *CLKGEN - Clkgen registers
 ***************************************************************************/
#define BCHP_CLKGEN_AVD_CLK_PM_CTRL              0x00040000 /* Clock Disable Control Register for AVD */
#define BCHP_CLKGEN_BVN_CLK_PM_CTRL              0x00040004 /* Clock Disable Control Register for BVN */
#define BCHP_CLKGEN_CG_CLK_PM_CTRL               0x00040008 /* Clock Disable Control Register for CLKGEN */
#define BCHP_CLKGEN_CGM_CLK_PM_CTRL              0x0004000c /* Clock Disable Control Register for CLKGEN MIPS */
#define BCHP_CLKGEN_CPU_CLK_PM_CTRL              0x00040010 /* Clock Disable Control Register for BCM MIPS */
#define BCHP_CLKGEN_DDR23APHY_CLK_PM_CTRL        0x00040014 /* Clock Disable Control Register for DDR23APHY */
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL            0x00040018 /* Clock Disable Control Register for DVPHT */
#define BCHP_CLKGEN_FTM_CLK_PM_CTRL              0x0004001c /* Clock Disable Control Register for FTM */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL            0x00040020 /* Clock Disable Control Register for GENET */
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_2D           0x00040024 /* Clock Disable Control Register for GFX */
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_3D           0x00040028 /* Clock Disable Control Register for GFX */
#define BCHP_CLKGEN_HIF_CLK_PM_CTRL              0x0004002c /* Clock Disable Control Register for HIF */
#define BCHP_CLKGEN_MEMC_CLK_PM_CTRL             0x00040030 /* Clock Disable Control Register for MEMC */
#define BCHP_CLKGEN_MISC_CLK_PM_CTRL             0x00040034 /* Clock Disable Miscellaneous clocks in the chip */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL             0x00040038 /* Clock Disable Control Register for MOCA */
#define BCHP_CLKGEN_PAD_CLK_PM_CTRL              0x0004003c /* Clock Disable Control Register for PAD Clocks */
#define BCHP_CLKGEN_QPSK_CLK_PM_CTRL             0x00040040 /* Clock Disable Control Register for QPSK */
#define BCHP_CLKGEN_RPT_AIO_CLK_PM_CTRL          0x00040044 /* Clock Disable Control Register for DSP Raptor and AIO */
#define BCHP_CLKGEN_SAFEC_CLK_PM_CTRL            0x00040048 /* Clock Disable Control Register for SAFEC */
#define BCHP_CLKGEN_SECTOP_CLK_PM_CTRL           0x0004004c /* Clock Disable Control Register for SECTOP */
#define BCHP_CLKGEN_SRCTN_CLK_PM_CTRL            0x00040050 /* Clock Disable Control Register for SRCTN */
#define BCHP_CLKGEN_STFEC_CLK_PM_CTRL            0x00040054 /* Clock Disable Control Register for STFEC */
#define BCHP_CLKGEN_SUN_CLK_PM_CTRL              0x00040058 /* Clock Disable Control Register for SUNDRY */
#define BCHP_CLKGEN_SUN_DAA_CLK_PM_CTRL          0x0004005c /* Clock Disable Control Register for DAA */
#define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL           0x00040060 /* Clock Disable Control Register for Smart Card */
#define BCHP_CLKGEN_SUN_SM_CLK_PM_CTRL           0x00040064 /* Clock Disable Control Register for Smart Modem */
#define BCHP_CLKGEN_TDAC_CLK_PM_CTRL             0x00040068 /* Clock Disable Control Register for USB */
#define BCHP_CLKGEN_UHFR_CLK_PM_CTRL             0x0004006c /* Clock Disable Control Register for USB */
#define BCHP_CLKGEN_USB_CLK_PM_CTRL              0x00040070 /* Clock Disable Control Register for USB */
#define BCHP_CLKGEN_VCXO_CLK_PM_CTRL             0x00040074 /* Clock Disable Control Register for CLKGEN VCXO WRAPPER */
#define BCHP_CLKGEN_VEC_CLK_PM_CTRL              0x00040078 /* Clock Disable Control Register for VEC */
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL              0x0004007c /* Clock Disable Control Register for XPT */
#define BCHP_CLKGEN_PAD_CLOCK                    0x00040080 /* PAD Clock Control Register */
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS           0x00040084 /* Misc clock selects in chip. */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL              0x00040090 /* D2CDIFF no_AC control */
#define BCHP_CLKGEN_DIFFOSC_TEST_CTRL            0x00040094 /* DIFFOSC_TEST_CTRL Control Register */
#define BCHP_CLKGEN_PLL_TEST_CTRL                0x000400a0 /* PLL_TEST_CTRL Control Register */
#define BCHP_CLKGEN_LOCK                         0x000400a4 /* PLL lock status */
#define BCHP_CLKGEN_LOCK_CNTR_RESET              0x000400a8 /* VCXO Lock Counter Reset */
#define BCHP_CLKGEN_MOCA_LOCK_CNT                0x000400ac /* MOCA PLL Lock Counter */
#define BCHP_CLKGEN_AVD_LOCK_CNT                 0x000400b0 /* AVD PLL Lock Counter */
#define BCHP_CLKGEN_CPU_LOCK_CNT                 0x000400b4 /* CPU PLL Lock Counter */
#define BCHP_CLKGEN_MAIN_LOCK_CNT                0x000400b8 /* MAIN PLL Lock Counter */
#define BCHP_CLKGEN_PLLMAIN_CH2_PM_CTRL          0x000400c4 /* PLL_MAIN Powderdown FSKPHY Reference */
#define BCHP_CLKGEN_PLLMAIN_CH3_PM_CTRL          0x000400c8 /* PLL_MAIN Powerdown 81MHz Main clock */
#define BCHP_CLKGEN_PLLMAIN_CH4_PM_CTRL          0x000400cc /* PLL_MAIN Powerdown 48MHz USB clock */
#define BCHP_CLKGEN_PLLMAIN_CH5_PM_CTRL          0x000400d0 /* PLL_MAIN Powerdown 33MHz PCI clock */
#define BCHP_CLKGEN_PLLMAIN_CH6_PM_CTRL          0x000400d4 /* PLL_MAIN Powerdown 32.4MHz Soft Modem clock */
#define BCHP_CLKGEN_PLLMAIN_CTRL                 0x000400d8 /* PLL_MAIN Reset Status & DLY */
#define BCHP_CLKGEN_MIPS_PLL_CTRL                0x000400e0 /* Mips PLL Control Register */
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL             0x000400e4 /* PLLAVD_RDSP PLL Reset, Enable and Powerdown Control */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH1_CTRL      0x000400e8 /* PLLAVD_RDSP Secondary 250.71MHz Satellite AFEC clock */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL      0x000400ec /* PLLAVD_RDSP 250.71MHz AVD/DSP Raptor clock */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH3_CTRL      0x000400f0 /* PLLAVD_RDSP 135MHz Satellite Analog clock */
#define BCHP_CLKGEN_PLLMOCA_CONTROL_HIGH_CTRL    0x000400f4 /* Upper 14-bits of the 38-bit PLL control word */
#define BCHP_CLKGEN_PLLMOCA_CONTROL_LOW_CTRL     0x000400f8 /* Lower 24-bits of the 38-bit PLL control word */
#define BCHP_CLKGEN_PLLMOCA_CTRL                 0x00040100 /* PLL_MOCA Reset, Powerdown and LDO controls */
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL          0x00040104 /* PLL_MOCA 225MHz CPU clock channel control */
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL          0x00040108 /* PLL_MOCA 225MHz PHY clock channel control */
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL          0x0004010c /* PLL_MOCA 50MHz USDS clock channel control */
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL          0x00040110 /* PLL_MOCA 25MHz GENET clock channel control */
#define BCHP_CLKGEN_PLLMOCA_CH5_PM_CTRL          0x00040114 /* PLL_MOCA Satellite Receiver Tuner 257MHz scan clock channel control */
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL          0x00040118 /* PLL_MOCA 100MHz MOCA clock channel control */
#define BCHP_CLKGEN_PLL_TIMER_SELECT             0x00040120 /* Select the delay after reset before using PLL */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL             0x00040124 /* Program the PLLs to be alive in standby */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL   0x00040128 /* Program the 216/108 clocks to be alive in standby */
#define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL         0x0004012c /* SMARTCARD_CLOCK_CTRL Register */
#define BCHP_CLKGEN_SCRATCH_REG                  0x00040130 /* Scratch Register */

/***************************************************************************
 *AVD_CLK_PM_CTRL - Clock Disable Control Register for AVD
 ***************************************************************************/
/* CLKGEN :: AVD_CLK_PM_CTRL :: reserved0 [31:03] */
#define BCHP_CLKGEN_AVD_CLK_PM_CTRL_reserved0_MASK                 0xfffffff8
#define BCHP_CLKGEN_AVD_CLK_PM_CTRL_reserved0_SHIFT                3

/* CLKGEN :: AVD_CLK_PM_CTRL :: DIS_CLK_250P71 [02:02] */
#define BCHP_CLKGEN_AVD_CLK_PM_CTRL_DIS_CLK_250P71_MASK            0x00000004
#define BCHP_CLKGEN_AVD_CLK_PM_CTRL_DIS_CLK_250P71_SHIFT           2

/* CLKGEN :: AVD_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_AVD_CLK_PM_CTRL_DIS_CLK_108_MASK               0x00000002
#define BCHP_CLKGEN_AVD_CLK_PM_CTRL_DIS_CLK_108_SHIFT              1

/* CLKGEN :: AVD_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_AVD_CLK_PM_CTRL_DIS_CLK_216_MASK               0x00000001
#define BCHP_CLKGEN_AVD_CLK_PM_CTRL_DIS_CLK_216_SHIFT              0

/***************************************************************************
 *BVN_CLK_PM_CTRL - Clock Disable Control Register for BVN
 ***************************************************************************/
/* CLKGEN :: BVN_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_BVN_CLK_PM_CTRL_reserved0_MASK                 0xfffffffc
#define BCHP_CLKGEN_BVN_CLK_PM_CTRL_reserved0_SHIFT                2

/* CLKGEN :: BVN_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_BVN_CLK_PM_CTRL_DIS_CLK_108_MASK               0x00000002
#define BCHP_CLKGEN_BVN_CLK_PM_CTRL_DIS_CLK_108_SHIFT              1

/* CLKGEN :: BVN_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_BVN_CLK_PM_CTRL_DIS_CLK_216_MASK               0x00000001
#define BCHP_CLKGEN_BVN_CLK_PM_CTRL_DIS_CLK_216_SHIFT              0

/***************************************************************************
 *CG_CLK_PM_CTRL - Clock Disable Control Register for CLKGEN
 ***************************************************************************/
/* CLKGEN :: CG_CLK_PM_CTRL :: reserved0 [31:12] */
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_reserved0_MASK                  0xfffff000
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_reserved0_SHIFT                 12

/* CLKGEN :: CG_CLK_PM_CTRL :: reserved_for_eco1 [11:09] */
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_reserved_for_eco1_MASK          0x00000e00
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_reserved_for_eco1_SHIFT         9

/* CLKGEN :: CG_CLK_PM_CTRL :: DIS_CLK_27X_CG [08:08] */
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_27X_CG_MASK             0x00000100
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_27X_CG_SHIFT            8

/* CLKGEN :: CG_CLK_PM_CTRL :: DIS_CLK_27_VCXO [07:07] */
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_27_VCXO_MASK            0x00000080
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_27_VCXO_SHIFT           7

/* CLKGEN :: CG_CLK_PM_CTRL :: DIS_CLK_33 [06:06] */
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_33_MASK                 0x00000040
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_33_SHIFT                6

/* CLKGEN :: CG_CLK_PM_CTRL :: DIS_CLK_40P5 [05:05] */
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_40P5_MASK               0x00000020
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_40P5_SHIFT              5

/* CLKGEN :: CG_CLK_PM_CTRL :: DIS_CLK_81 [04:04] */
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_81_MASK                 0x00000010
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_81_SHIFT                4

/* CLKGEN :: CG_CLK_PM_CTRL :: DIS_CLK_27 [03:03] */
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_27_MASK                 0x00000008
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_27_SHIFT                3

/* CLKGEN :: CG_CLK_PM_CTRL :: DIS_CLK_54 [02:02] */
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_54_MASK                 0x00000004
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_54_SHIFT                2

/* CLKGEN :: CG_CLK_PM_CTRL :: DIS_CLK_108_CG [01:01] */
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_108_CG_MASK             0x00000002
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_108_CG_SHIFT            1

/* CLKGEN :: CG_CLK_PM_CTRL :: DIS_CLK_216_CG [00:00] */
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_216_CG_MASK             0x00000001
#define BCHP_CLKGEN_CG_CLK_PM_CTRL_DIS_CLK_216_CG_SHIFT            0

/***************************************************************************
 *CGM_CLK_PM_CTRL - Clock Disable Control Register for CLKGEN MIPS
 ***************************************************************************/
/* CLKGEN :: CGM_CLK_PM_CTRL :: reserved0 [31:03] */
#define BCHP_CLKGEN_CGM_CLK_PM_CTRL_reserved0_MASK                 0xfffffff8
#define BCHP_CLKGEN_CGM_CLK_PM_CTRL_reserved0_SHIFT                3

/* CLKGEN :: CGM_CLK_PM_CTRL :: DIS_CLK_CPU [02:02] */
#define BCHP_CLKGEN_CGM_CLK_PM_CTRL_DIS_CLK_CPU_MASK               0x00000004
#define BCHP_CLKGEN_CGM_CLK_PM_CTRL_DIS_CLK_CPU_SHIFT              2

/* CLKGEN :: CGM_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_CGM_CLK_PM_CTRL_DIS_CLK_108_MASK               0x00000002
#define BCHP_CLKGEN_CGM_CLK_PM_CTRL_DIS_CLK_108_SHIFT              1

/* CLKGEN :: CGM_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_CGM_CLK_PM_CTRL_DIS_CLK_216_MASK               0x00000001
#define BCHP_CLKGEN_CGM_CLK_PM_CTRL_DIS_CLK_216_SHIFT              0

/***************************************************************************
 *CPU_CLK_PM_CTRL - Clock Disable Control Register for BCM MIPS
 ***************************************************************************/
/* CLKGEN :: CPU_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_CPU_CLK_PM_CTRL_reserved0_MASK                 0xfffffffc
#define BCHP_CLKGEN_CPU_CLK_PM_CTRL_reserved0_SHIFT                2

/* CLKGEN :: CPU_CLK_PM_CTRL :: DIS_CLK_CPU [01:01] */
#define BCHP_CLKGEN_CPU_CLK_PM_CTRL_DIS_CLK_CPU_MASK               0x00000002
#define BCHP_CLKGEN_CPU_CLK_PM_CTRL_DIS_CLK_CPU_SHIFT              1

/* CLKGEN :: CPU_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_CPU_CLK_PM_CTRL_DIS_CLK_216_MASK               0x00000001
#define BCHP_CLKGEN_CPU_CLK_PM_CTRL_DIS_CLK_216_SHIFT              0

/***************************************************************************
 *DDR23APHY_CLK_PM_CTRL - Clock Disable Control Register for DDR23APHY
 ***************************************************************************/
/* CLKGEN :: DDR23APHY_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_DDR23APHY_CLK_PM_CTRL_reserved0_MASK           0xfffffffc
#define BCHP_CLKGEN_DDR23APHY_CLK_PM_CTRL_reserved0_SHIFT          2

/* CLKGEN :: DDR23APHY_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_DDR23APHY_CLK_PM_CTRL_DIS_CLK_108_MASK         0x00000002
#define BCHP_CLKGEN_DDR23APHY_CLK_PM_CTRL_DIS_CLK_108_SHIFT        1

/* CLKGEN :: DDR23APHY_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_DDR23APHY_CLK_PM_CTRL_DIS_CLK_216_MASK         0x00000001
#define BCHP_CLKGEN_DDR23APHY_CLK_PM_CTRL_DIS_CLK_216_SHIFT        0

/***************************************************************************
 *DVPHT_CLK_PM_CTRL - Clock Disable Control Register for DVPHT
 ***************************************************************************/
/* CLKGEN :: DVPHT_CLK_PM_CTRL :: reserved0 [31:06] */
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_reserved0_MASK               0xffffffc0
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_reserved0_SHIFT              6

/* CLKGEN :: DVPHT_CLK_PM_CTRL :: DIS_CLK_27X_IIC [05:05] */
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_DIS_CLK_27X_IIC_MASK         0x00000020
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_DIS_CLK_27X_IIC_SHIFT        5

/* CLKGEN :: DVPHT_CLK_PM_CTRL :: DIS_CLK_27X_PM_HDMI [04:04] */
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_DIS_CLK_27X_PM_HDMI_MASK     0x00000010
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_DIS_CLK_27X_PM_HDMI_SHIFT    4

/* CLKGEN :: DVPHT_CLK_PM_CTRL :: reserved_for_eco1 [03:03] */
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_reserved_for_eco1_MASK       0x00000008
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_reserved_for_eco1_SHIFT      3

/* CLKGEN :: DVPHT_CLK_PM_CTRL :: DIS_CLK_108_ALTERNATE [02:02] */
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_DIS_CLK_108_ALTERNATE_MASK   0x00000004
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_DIS_CLK_108_ALTERNATE_SHIFT  2

/* CLKGEN :: DVPHT_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_DIS_CLK_108_MASK             0x00000002
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_DIS_CLK_108_SHIFT            1

/* CLKGEN :: DVPHT_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_DIS_CLK_216_MASK             0x00000001
#define BCHP_CLKGEN_DVPHT_CLK_PM_CTRL_DIS_CLK_216_SHIFT            0

/***************************************************************************
 *FTM_CLK_PM_CTRL - Clock Disable Control Register for FTM
 ***************************************************************************/
/* CLKGEN :: FTM_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_FTM_CLK_PM_CTRL_reserved0_MASK                 0xfffffffc
#define BCHP_CLKGEN_FTM_CLK_PM_CTRL_reserved0_SHIFT                2

/* CLKGEN :: FTM_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_FTM_CLK_PM_CTRL_DIS_CLK_108_MASK               0x00000002
#define BCHP_CLKGEN_FTM_CLK_PM_CTRL_DIS_CLK_108_SHIFT              1

/* CLKGEN :: FTM_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_FTM_CLK_PM_CTRL_DIS_CLK_216_MASK               0x00000001
#define BCHP_CLKGEN_FTM_CLK_PM_CTRL_DIS_CLK_216_SHIFT              0

/***************************************************************************
 *GENET_CLK_PM_CTRL - Clock Disable Control Register for GENET
 ***************************************************************************/
/* CLKGEN :: GENET_CLK_PM_CTRL :: reserved0 [31:12] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_reserved0_MASK               0xfffff000
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_reserved0_SHIFT              12

/* CLKGEN :: GENET_CLK_PM_CTRL :: DIS_CLK_UNIMAC_SYS_RX [11:11] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK   0x00000800
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_SHIFT  11

/* CLKGEN :: GENET_CLK_PM_CTRL :: DIS_CLK_UNIMAC_SYS_TX [10:10] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK   0x00000400
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_SHIFT  10

/* CLKGEN :: GENET_CLK_PM_CTRL :: reserved_for_eco1 [09:09] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_reserved_for_eco1_MASK       0x00000200
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_reserved_for_eco1_SHIFT      9

/* CLKGEN :: GENET_CLK_PM_CTRL :: DIS_CLK_L2_INTR [08:08] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK         0x00000100
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_L2_INTR_SHIFT        8

/* CLKGEN :: GENET_CLK_PM_CTRL :: DIS_CLK_HFB [07:07] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_HFB_MASK             0x00000080
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_HFB_SHIFT            7

/* CLKGEN :: GENET_CLK_PM_CTRL :: DIS_CLK_GMII [06:06] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_GMII_MASK            0x00000040
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_GMII_SHIFT           6

/* CLKGEN :: GENET_CLK_PM_CTRL :: DIS_CLK_250 [05:05] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_250_MASK             0x00000020
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_250_SHIFT            5

/* CLKGEN :: GENET_CLK_PM_CTRL :: DIS_CLK_25 [04:04] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_25_MASK              0x00000010
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_25_SHIFT             4

/* CLKGEN :: GENET_CLK_PM_CTRL :: DIS_CLK_27X_PM [03:03] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK          0x00000008
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_27X_PM_SHIFT         3

/* CLKGEN :: GENET_CLK_PM_CTRL :: DIS_CLK_54 [02:02] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_54_MASK              0x00000004
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_54_SHIFT             2

/* CLKGEN :: GENET_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_108_MASK             0x00000002
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_108_SHIFT            1

/* CLKGEN :: GENET_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_216_MASK             0x00000001
#define BCHP_CLKGEN_GENET_CLK_PM_CTRL_DIS_CLK_216_SHIFT            0

/***************************************************************************
 *GFX_CLK_PM_CTRL_2D - Clock Disable Control Register for GFX
 ***************************************************************************/
/* CLKGEN :: GFX_CLK_PM_CTRL_2D :: reserved0 [31:02] */
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_2D_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_2D_reserved0_SHIFT             2

/* CLKGEN :: GFX_CLK_PM_CTRL_2D :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_2D_DIS_CLK_108_MASK            0x00000002
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_2D_DIS_CLK_108_SHIFT           1

/* CLKGEN :: GFX_CLK_PM_CTRL_2D :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_2D_DIS_CLK_216_MASK            0x00000001
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_2D_DIS_CLK_216_SHIFT           0

/***************************************************************************
 *GFX_CLK_PM_CTRL_3D - Clock Disable Control Register for GFX
 ***************************************************************************/
/* CLKGEN :: GFX_CLK_PM_CTRL_3D :: reserved0 [31:02] */
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_3D_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_3D_reserved0_SHIFT             2

/* CLKGEN :: GFX_CLK_PM_CTRL_3D :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_3D_DIS_CLK_108_MASK            0x00000002
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_3D_DIS_CLK_108_SHIFT           1

/* CLKGEN :: GFX_CLK_PM_CTRL_3D :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_3D_DIS_CLK_216_MASK            0x00000001
#define BCHP_CLKGEN_GFX_CLK_PM_CTRL_3D_DIS_CLK_216_SHIFT           0

/***************************************************************************
 *HIF_CLK_PM_CTRL - Clock Disable Control Register for HIF
 ***************************************************************************/
/* CLKGEN :: HIF_CLK_PM_CTRL :: reserved0 [31:03] */
#define BCHP_CLKGEN_HIF_CLK_PM_CTRL_reserved0_MASK                 0xfffffff8
#define BCHP_CLKGEN_HIF_CLK_PM_CTRL_reserved0_SHIFT                3

/* CLKGEN :: HIF_CLK_PM_CTRL :: DIS_CLK_SPI [02:02] */
#define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_SPI_MASK               0x00000004
#define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_SPI_SHIFT              2

/* CLKGEN :: HIF_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_108_MASK               0x00000002
#define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_108_SHIFT              1

/* CLKGEN :: HIF_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_216_MASK               0x00000001
#define BCHP_CLKGEN_HIF_CLK_PM_CTRL_DIS_CLK_216_SHIFT              0

/***************************************************************************
 *MEMC_CLK_PM_CTRL - Clock Disable Control Register for MEMC
 ***************************************************************************/
/* CLKGEN :: MEMC_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_MEMC_CLK_PM_CTRL_reserved0_MASK                0xfffffffc
#define BCHP_CLKGEN_MEMC_CLK_PM_CTRL_reserved0_SHIFT               2

/* CLKGEN :: MEMC_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_MEMC_CLK_PM_CTRL_DIS_CLK_108_MASK              0x00000002
#define BCHP_CLKGEN_MEMC_CLK_PM_CTRL_DIS_CLK_108_SHIFT             1

/* CLKGEN :: MEMC_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_MEMC_CLK_PM_CTRL_DIS_CLK_216_MASK              0x00000001
#define BCHP_CLKGEN_MEMC_CLK_PM_CTRL_DIS_CLK_216_SHIFT             0

/***************************************************************************
 *MISC_CLK_PM_CTRL - Clock Disable Miscellaneous clocks in the chip
 ***************************************************************************/
/* CLKGEN :: MISC_CLK_PM_CTRL :: reserved_for_eco0 [31:01] */
#define BCHP_CLKGEN_MISC_CLK_PM_CTRL_reserved_for_eco0_MASK        0xfffffffe
#define BCHP_CLKGEN_MISC_CLK_PM_CTRL_reserved_for_eco0_SHIFT       1

/* CLKGEN :: MISC_CLK_PM_CTRL :: DIS_CLK_108_PINMUX [00:00] */
#define BCHP_CLKGEN_MISC_CLK_PM_CTRL_DIS_CLK_108_PINMUX_MASK       0x00000001
#define BCHP_CLKGEN_MISC_CLK_PM_CTRL_DIS_CLK_108_PINMUX_SHIFT      0

/***************************************************************************
 *MOCA_CLK_PM_CTRL - Clock Disable Control Register for MOCA
 ***************************************************************************/
/* CLKGEN :: MOCA_CLK_PM_CTRL :: reserved0 [31:14] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_reserved0_MASK                0xffffc000
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_reserved0_SHIFT               14

/* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_250_GENET_RGMII_MOCA [13:13] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_RGMII_MOCA_MASK 0x00002000
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_250_GENET_RGMII_MOCA_SHIFT 13

/* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_216_GENET_RGMII_CG [12:12] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_GENET_RGMII_CG_MASK 0x00001000
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_GENET_RGMII_CG_SHIFT 12

/* CLKGEN :: MOCA_CLK_PM_CTRL :: reserved_for_eco1 [11:10] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_reserved_for_eco1_MASK        0x00000c00
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_reserved_for_eco1_SHIFT       10

/* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_UNIMAC_SYS_RX [09:09] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_MASK    0x00000200
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_RX_SHIFT   9

/* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_UNIMAC_SYS_TX [08:08] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_MASK    0x00000100
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_UNIMAC_SYS_TX_SHIFT   8

/* CLKGEN :: MOCA_CLK_PM_CTRL :: reserved_for_eco2 [07:07] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_reserved_for_eco2_MASK        0x00000080
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_reserved_for_eco2_SHIFT       7

/* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_L2_INTR [06:06] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_L2_INTR_MASK          0x00000040
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_L2_INTR_SHIFT         6

/* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_HFB [05:05] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_HFB_MASK              0x00000020
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_HFB_SHIFT             5

/* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_GMII [04:04] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_GMII_MASK             0x00000010
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_GMII_SHIFT            4

/* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_27X_PM [03:03] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK           0x00000008
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_27X_PM_SHIFT          3

/* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_54 [02:02] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_54_MASK               0x00000004
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_54_SHIFT              2

/* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_108_MASK              0x00000002
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_108_SHIFT             1

/* CLKGEN :: MOCA_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_MASK              0x00000001
#define BCHP_CLKGEN_MOCA_CLK_PM_CTRL_DIS_CLK_216_SHIFT             0

/***************************************************************************
 *PAD_CLK_PM_CTRL - Clock Disable Control Register for PAD Clocks
 ***************************************************************************/
/* CLKGEN :: PAD_CLK_PM_CTRL :: reserved0 [31:04] */
#define BCHP_CLKGEN_PAD_CLK_PM_CTRL_reserved0_MASK                 0xfffffff0
#define BCHP_CLKGEN_PAD_CLK_PM_CTRL_reserved0_SHIFT                4

/* CLKGEN :: PAD_CLK_PM_CTRL :: PWRDN_CLK_27_CODEC_MCLOCK [03:03] */
#define BCHP_CLKGEN_PAD_CLK_PM_CTRL_PWRDN_CLK_27_CODEC_MCLOCK_MASK 0x00000008
#define BCHP_CLKGEN_PAD_CLK_PM_CTRL_PWRDN_CLK_27_CODEC_MCLOCK_SHIFT 3

/* CLKGEN :: PAD_CLK_PM_CTRL :: DIS_CLK_27_VCXO [02:02] */
#define BCHP_CLKGEN_PAD_CLK_PM_CTRL_DIS_CLK_27_VCXO_MASK           0x00000004
#define BCHP_CLKGEN_PAD_CLK_PM_CTRL_DIS_CLK_27_VCXO_SHIFT          2

/* CLKGEN :: PAD_CLK_PM_CTRL :: DIS_CLK_33_27_PCI [01:01] */
#define BCHP_CLKGEN_PAD_CLK_PM_CTRL_DIS_CLK_33_27_PCI_MASK         0x00000002
#define BCHP_CLKGEN_PAD_CLK_PM_CTRL_DIS_CLK_33_27_PCI_SHIFT        1

/* CLKGEN :: PAD_CLK_PM_CTRL :: DIS_CLK_54_40P5_ACC [00:00] */
#define BCHP_CLKGEN_PAD_CLK_PM_CTRL_DIS_CLK_54_40P5_ACC_MASK       0x00000001
#define BCHP_CLKGEN_PAD_CLK_PM_CTRL_DIS_CLK_54_40P5_ACC_SHIFT      0

/***************************************************************************
 *QPSK_CLK_PM_CTRL - Clock Disable Control Register for QPSK
 ***************************************************************************/
/* CLKGEN :: QPSK_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_QPSK_CLK_PM_CTRL_reserved0_MASK                0xfffffffc
#define BCHP_CLKGEN_QPSK_CLK_PM_CTRL_reserved0_SHIFT               2

/* CLKGEN :: QPSK_CLK_PM_CTRL :: DIS_CLK_216 [01:01] */
#define BCHP_CLKGEN_QPSK_CLK_PM_CTRL_DIS_CLK_216_MASK              0x00000002
#define BCHP_CLKGEN_QPSK_CLK_PM_CTRL_DIS_CLK_216_SHIFT             1

/* CLKGEN :: QPSK_CLK_PM_CTRL :: DIS_CLK_108 [00:00] */
#define BCHP_CLKGEN_QPSK_CLK_PM_CTRL_DIS_CLK_108_MASK              0x00000001
#define BCHP_CLKGEN_QPSK_CLK_PM_CTRL_DIS_CLK_108_SHIFT             0

/***************************************************************************
 *RPT_AIO_CLK_PM_CTRL - Clock Disable Control Register for DSP Raptor and AIO
 ***************************************************************************/
/* CLKGEN :: RPT_AIO_CLK_PM_CTRL :: reserved0 [31:03] */
#define BCHP_CLKGEN_RPT_AIO_CLK_PM_CTRL_reserved0_MASK             0xfffffff8
#define BCHP_CLKGEN_RPT_AIO_CLK_PM_CTRL_reserved0_SHIFT            3

/* CLKGEN :: RPT_AIO_CLK_PM_CTRL :: DIS_CLK_250P71_RPTD [02:02] */
#define BCHP_CLKGEN_RPT_AIO_CLK_PM_CTRL_DIS_CLK_250P71_RPTD_MASK   0x00000004
#define BCHP_CLKGEN_RPT_AIO_CLK_PM_CTRL_DIS_CLK_250P71_RPTD_SHIFT  2

/* CLKGEN :: RPT_AIO_CLK_PM_CTRL :: DIS_CLK_108_AIO [01:01] */
#define BCHP_CLKGEN_RPT_AIO_CLK_PM_CTRL_DIS_CLK_108_AIO_MASK       0x00000002
#define BCHP_CLKGEN_RPT_AIO_CLK_PM_CTRL_DIS_CLK_108_AIO_SHIFT      1

/* CLKGEN :: RPT_AIO_CLK_PM_CTRL :: DIS_CLK_216_AIO [00:00] */
#define BCHP_CLKGEN_RPT_AIO_CLK_PM_CTRL_DIS_CLK_216_AIO_MASK       0x00000001
#define BCHP_CLKGEN_RPT_AIO_CLK_PM_CTRL_DIS_CLK_216_AIO_SHIFT      0

/***************************************************************************
 *SAFEC_CLK_PM_CTRL - Clock Disable Control Register for SAFEC
 ***************************************************************************/
/* CLKGEN :: SAFEC_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_SAFEC_CLK_PM_CTRL_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_SAFEC_CLK_PM_CTRL_reserved0_SHIFT              2

/* CLKGEN :: SAFEC_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_SAFEC_CLK_PM_CTRL_DIS_CLK_108_MASK             0x00000002
#define BCHP_CLKGEN_SAFEC_CLK_PM_CTRL_DIS_CLK_108_SHIFT            1

/* CLKGEN :: SAFEC_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_SAFEC_CLK_PM_CTRL_DIS_CLK_216_MASK             0x00000001
#define BCHP_CLKGEN_SAFEC_CLK_PM_CTRL_DIS_CLK_216_SHIFT            0

/***************************************************************************
 *SECTOP_CLK_PM_CTRL - Clock Disable Control Register for SECTOP
 ***************************************************************************/
/* CLKGEN :: SECTOP_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLKGEN_SECTOP_CLK_PM_CTRL_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_SECTOP_CLK_PM_CTRL_reserved0_SHIFT             1

/* CLKGEN :: SECTOP_CLK_PM_CTRL :: DIS_CLK_216_ALTERNATE [00:00] */
#define BCHP_CLKGEN_SECTOP_CLK_PM_CTRL_DIS_CLK_216_ALTERNATE_MASK  0x00000001
#define BCHP_CLKGEN_SECTOP_CLK_PM_CTRL_DIS_CLK_216_ALTERNATE_SHIFT 0

/***************************************************************************
 *SRCTN_CLK_PM_CTRL - Clock Disable Control Register for SRCTN
 ***************************************************************************/
/* CLKGEN :: SRCTN_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_SRCTN_CLK_PM_CTRL_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_SRCTN_CLK_PM_CTRL_reserved0_SHIFT              2

/* CLKGEN :: SRCTN_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_SRCTN_CLK_PM_CTRL_DIS_CLK_108_MASK             0x00000002
#define BCHP_CLKGEN_SRCTN_CLK_PM_CTRL_DIS_CLK_108_SHIFT            1

/* CLKGEN :: SRCTN_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_SRCTN_CLK_PM_CTRL_DIS_CLK_216_MASK             0x00000001
#define BCHP_CLKGEN_SRCTN_CLK_PM_CTRL_DIS_CLK_216_SHIFT            0

/***************************************************************************
 *STFEC_CLK_PM_CTRL - Clock Disable Control Register for STFEC
 ***************************************************************************/
/* CLKGEN :: STFEC_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_STFEC_CLK_PM_CTRL_reserved0_MASK               0xfffffffc
#define BCHP_CLKGEN_STFEC_CLK_PM_CTRL_reserved0_SHIFT              2

/* CLKGEN :: STFEC_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_STFEC_CLK_PM_CTRL_DIS_CLK_108_MASK             0x00000002
#define BCHP_CLKGEN_STFEC_CLK_PM_CTRL_DIS_CLK_108_SHIFT            1

/* CLKGEN :: STFEC_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_STFEC_CLK_PM_CTRL_DIS_CLK_216_MASK             0x00000001
#define BCHP_CLKGEN_STFEC_CLK_PM_CTRL_DIS_CLK_216_SHIFT            0

/***************************************************************************
 *SUN_CLK_PM_CTRL - Clock Disable Control Register for SUNDRY
 ***************************************************************************/
/* CLKGEN :: SUN_CLK_PM_CTRL :: reserved0 [31:03] */
#define BCHP_CLKGEN_SUN_CLK_PM_CTRL_reserved0_MASK                 0xfffffff8
#define BCHP_CLKGEN_SUN_CLK_PM_CTRL_reserved0_SHIFT                3

/* CLKGEN :: SUN_CLK_PM_CTRL :: DIS_CLK_27X_PM [02:02] */
#define BCHP_CLKGEN_SUN_CLK_PM_CTRL_DIS_CLK_27X_PM_MASK            0x00000004
#define BCHP_CLKGEN_SUN_CLK_PM_CTRL_DIS_CLK_27X_PM_SHIFT           2

/* CLKGEN :: SUN_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_SUN_CLK_PM_CTRL_DIS_CLK_108_MASK               0x00000002
#define BCHP_CLKGEN_SUN_CLK_PM_CTRL_DIS_CLK_108_SHIFT              1

/* CLKGEN :: SUN_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_SUN_CLK_PM_CTRL_DIS_CLK_216_MASK               0x00000001
#define BCHP_CLKGEN_SUN_CLK_PM_CTRL_DIS_CLK_216_SHIFT              0

/***************************************************************************
 *SUN_DAA_CLK_PM_CTRL - Clock Disable Control Register for DAA
 ***************************************************************************/
/* CLKGEN :: SUN_DAA_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLKGEN_SUN_DAA_CLK_PM_CTRL_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_SUN_DAA_CLK_PM_CTRL_reserved0_SHIFT            1

/* CLKGEN :: SUN_DAA_CLK_PM_CTRL :: DIS_CLK_32P4 [00:00] */
#define BCHP_CLKGEN_SUN_DAA_CLK_PM_CTRL_DIS_CLK_32P4_MASK          0x00000001
#define BCHP_CLKGEN_SUN_DAA_CLK_PM_CTRL_DIS_CLK_32P4_SHIFT         0

/***************************************************************************
 *SUN_SC_CLK_PM_CTRL - Clock Disable Control Register for Smart Card
 ***************************************************************************/
/* CLKGEN :: SUN_SC_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL_reserved0_MASK              0xfffffffc
#define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL_reserved0_SHIFT             2

/* CLKGEN :: SUN_SC_CLK_PM_CTRL :: DIS_CLK_40_27_SC2 [01:01] */
#define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL_DIS_CLK_40_27_SC2_MASK      0x00000002
#define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL_DIS_CLK_40_27_SC2_SHIFT     1

/* CLKGEN :: SUN_SC_CLK_PM_CTRL :: DIS_CLK_40_27_SC1 [00:00] */
#define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL_DIS_CLK_40_27_SC1_MASK      0x00000001
#define BCHP_CLKGEN_SUN_SC_CLK_PM_CTRL_DIS_CLK_40_27_SC1_SHIFT     0

/***************************************************************************
 *SUN_SM_CLK_PM_CTRL - Clock Disable Control Register for Smart Modem
 ***************************************************************************/
/* CLKGEN :: SUN_SM_CLK_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLKGEN_SUN_SM_CLK_PM_CTRL_reserved0_MASK              0xfffffffe
#define BCHP_CLKGEN_SUN_SM_CLK_PM_CTRL_reserved0_SHIFT             1

/* CLKGEN :: SUN_SM_CLK_PM_CTRL :: DIS_CLK_27 [00:00] */
#define BCHP_CLKGEN_SUN_SM_CLK_PM_CTRL_DIS_CLK_27_MASK             0x00000001
#define BCHP_CLKGEN_SUN_SM_CLK_PM_CTRL_DIS_CLK_27_SHIFT            0

/***************************************************************************
 *TDAC_CLK_PM_CTRL - Clock Disable Control Register for USB
 ***************************************************************************/
/* CLKGEN :: TDAC_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_TDAC_CLK_PM_CTRL_reserved0_MASK                0xfffffffc
#define BCHP_CLKGEN_TDAC_CLK_PM_CTRL_reserved0_SHIFT               2

/* CLKGEN :: TDAC_CLK_PM_CTRL :: DIS_CLK_216_TDAC1 [01:01] */
#define BCHP_CLKGEN_TDAC_CLK_PM_CTRL_DIS_CLK_216_TDAC1_MASK        0x00000002
#define BCHP_CLKGEN_TDAC_CLK_PM_CTRL_DIS_CLK_216_TDAC1_SHIFT       1

/* CLKGEN :: TDAC_CLK_PM_CTRL :: DIS_CLK_216_TDAC0 [00:00] */
#define BCHP_CLKGEN_TDAC_CLK_PM_CTRL_DIS_CLK_216_TDAC0_MASK        0x00000001
#define BCHP_CLKGEN_TDAC_CLK_PM_CTRL_DIS_CLK_216_TDAC0_SHIFT       0

/***************************************************************************
 *UHFR_CLK_PM_CTRL - Clock Disable Control Register for USB
 ***************************************************************************/
/* CLKGEN :: UHFR_CLK_PM_CTRL :: reserved0 [31:04] */
#define BCHP_CLKGEN_UHFR_CLK_PM_CTRL_reserved0_MASK                0xfffffff0
#define BCHP_CLKGEN_UHFR_CLK_PM_CTRL_reserved0_SHIFT               4

/* CLKGEN :: UHFR_CLK_PM_CTRL :: DIS_CLK_54X_FILT_UHFR [03:03] */
#define BCHP_CLKGEN_UHFR_CLK_PM_CTRL_DIS_CLK_54X_FILT_UHFR_MASK    0x00000008
#define BCHP_CLKGEN_UHFR_CLK_PM_CTRL_DIS_CLK_54X_FILT_UHFR_SHIFT   3

/* CLKGEN :: UHFR_CLK_PM_CTRL :: DIS_CLK_54X_DIG_UHFR [02:02] */
#define BCHP_CLKGEN_UHFR_CLK_PM_CTRL_DIS_CLK_54X_DIG_UHFR_MASK     0x00000004
#define BCHP_CLKGEN_UHFR_CLK_PM_CTRL_DIS_CLK_54X_DIG_UHFR_SHIFT    2

/* CLKGEN :: UHFR_CLK_PM_CTRL :: DIS_CLK_54X_UHF [01:01] */
#define BCHP_CLKGEN_UHFR_CLK_PM_CTRL_DIS_CLK_54X_UHF_MASK          0x00000002
#define BCHP_CLKGEN_UHFR_CLK_PM_CTRL_DIS_CLK_54X_UHF_SHIFT         1

/* CLKGEN :: UHFR_CLK_PM_CTRL :: DIS_CLK_27X_UHFR [00:00] */
#define BCHP_CLKGEN_UHFR_CLK_PM_CTRL_DIS_CLK_27X_UHFR_MASK         0x00000001
#define BCHP_CLKGEN_UHFR_CLK_PM_CTRL_DIS_CLK_27X_UHFR_SHIFT        0

/***************************************************************************
 *USB_CLK_PM_CTRL - Clock Disable Control Register for USB
 ***************************************************************************/
/* CLKGEN :: USB_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_USB_CLK_PM_CTRL_reserved0_MASK                 0xfffffffc
#define BCHP_CLKGEN_USB_CLK_PM_CTRL_reserved0_SHIFT                2

/* CLKGEN :: USB_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_USB_CLK_PM_CTRL_DIS_CLK_108_MASK               0x00000002
#define BCHP_CLKGEN_USB_CLK_PM_CTRL_DIS_CLK_108_SHIFT              1

/* CLKGEN :: USB_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_USB_CLK_PM_CTRL_DIS_CLK_216_MASK               0x00000001
#define BCHP_CLKGEN_USB_CLK_PM_CTRL_DIS_CLK_216_SHIFT              0

/***************************************************************************
 *VCXO_CLK_PM_CTRL - Clock Disable Control Register for CLKGEN VCXO WRAPPER
 ***************************************************************************/
/* CLKGEN :: VCXO_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_VCXO_CLK_PM_CTRL_reserved0_MASK                0xfffffffc
#define BCHP_CLKGEN_VCXO_CLK_PM_CTRL_reserved0_SHIFT               2

/* CLKGEN :: VCXO_CLK_PM_CTRL :: DIS_CLK_216 [01:01] */
#define BCHP_CLKGEN_VCXO_CLK_PM_CTRL_DIS_CLK_216_MASK              0x00000002
#define BCHP_CLKGEN_VCXO_CLK_PM_CTRL_DIS_CLK_216_SHIFT             1

/* CLKGEN :: VCXO_CLK_PM_CTRL :: DIS_CLK_108 [00:00] */
#define BCHP_CLKGEN_VCXO_CLK_PM_CTRL_DIS_CLK_108_MASK              0x00000001
#define BCHP_CLKGEN_VCXO_CLK_PM_CTRL_DIS_CLK_108_SHIFT             0

/***************************************************************************
 *VEC_CLK_PM_CTRL - Clock Disable Control Register for VEC
 ***************************************************************************/
/* CLKGEN :: VEC_CLK_PM_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_VEC_CLK_PM_CTRL_reserved0_MASK                 0xfffffffc
#define BCHP_CLKGEN_VEC_CLK_PM_CTRL_reserved0_SHIFT                2

/* CLKGEN :: VEC_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_VEC_CLK_PM_CTRL_DIS_CLK_108_MASK               0x00000002
#define BCHP_CLKGEN_VEC_CLK_PM_CTRL_DIS_CLK_108_SHIFT              1

/* CLKGEN :: VEC_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_VEC_CLK_PM_CTRL_DIS_CLK_216_MASK               0x00000001
#define BCHP_CLKGEN_VEC_CLK_PM_CTRL_DIS_CLK_216_SHIFT              0

/***************************************************************************
 *XPT_CLK_PM_CTRL - Clock Disable Control Register for XPT
 ***************************************************************************/
/* CLKGEN :: XPT_CLK_PM_CTRL :: reserved0 [31:07] */
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_reserved0_MASK                 0xffffff80
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_reserved0_SHIFT                7

/* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_20P25 [06:06] */
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_20P25_MASK             0x00000040
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_20P25_SHIFT            6

/* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_27 [05:05] */
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_27_MASK                0x00000020
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_27_SHIFT               5

/* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_40P5 [04:04] */
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_40P5_MASK              0x00000010
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_40P5_SHIFT             4

/* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_81 [03:03] */
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_81_MASK                0x00000008
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_81_SHIFT               3

/* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_54 [02:02] */
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_54_MASK                0x00000004
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_54_SHIFT               2

/* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_108 [01:01] */
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_108_MASK               0x00000002
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_108_SHIFT              1

/* CLKGEN :: XPT_CLK_PM_CTRL :: DIS_CLK_216 [00:00] */
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_216_MASK               0x00000001
#define BCHP_CLKGEN_XPT_CLK_PM_CTRL_DIS_CLK_216_SHIFT              0

/***************************************************************************
 *PAD_CLOCK - PAD Clock Control Register
 ***************************************************************************/
/* CLKGEN :: PAD_CLOCK :: reserved0 [31:10] */
#define BCHP_CLKGEN_PAD_CLOCK_reserved0_MASK                       0xfffffc00
#define BCHP_CLKGEN_PAD_CLOCK_reserved0_SHIFT                      10

/* CLKGEN :: PAD_CLOCK :: CLOCK_ACC_TEST_SEL [09:05] */
#define BCHP_CLKGEN_PAD_CLOCK_CLOCK_ACC_TEST_SEL_MASK              0x000003e0
#define BCHP_CLKGEN_PAD_CLOCK_CLOCK_ACC_TEST_SEL_SHIFT             5

/* CLKGEN :: PAD_CLOCK :: CLOCK_ACC_TEST_DIVIDE_EN [04:04] */
#define BCHP_CLKGEN_PAD_CLOCK_CLOCK_ACC_TEST_DIVIDE_EN_MASK        0x00000010
#define BCHP_CLKGEN_PAD_CLOCK_CLOCK_ACC_TEST_DIVIDE_EN_SHIFT       4

/* CLKGEN :: PAD_CLOCK :: CLOCK_ACC_TEST_MODE [03:03] */
#define BCHP_CLKGEN_PAD_CLOCK_CLOCK_ACC_TEST_MODE_MASK             0x00000008
#define BCHP_CLKGEN_PAD_CLOCK_CLOCK_ACC_TEST_MODE_SHIFT            3

/* CLKGEN :: PAD_CLOCK :: ACC_PAD_CLOCK_SEL [02:02] */
#define BCHP_CLKGEN_PAD_CLOCK_ACC_PAD_CLOCK_SEL_MASK               0x00000004
#define BCHP_CLKGEN_PAD_CLOCK_ACC_PAD_CLOCK_SEL_SHIFT              2

/* CLKGEN :: PAD_CLOCK :: PCI_PAD_CLOCK_SEL [01:01] */
#define BCHP_CLKGEN_PAD_CLOCK_PCI_PAD_CLOCK_SEL_MASK               0x00000002
#define BCHP_CLKGEN_PAD_CLOCK_PCI_PAD_CLOCK_SEL_SHIFT              1

/* CLKGEN :: PAD_CLOCK :: VCXO_27_PAD_CLOCK_INV [00:00] */
#define BCHP_CLKGEN_PAD_CLOCK_VCXO_27_PAD_CLOCK_INV_MASK           0x00000001
#define BCHP_CLKGEN_PAD_CLOCK_VCXO_27_PAD_CLOCK_INV_SHIFT          0

/***************************************************************************
 *MISC_CLOCK_SELECTS - Misc clock selects in chip.
 ***************************************************************************/
/* CLKGEN :: MISC_CLOCK_SELECTS :: reserved0 [31:06] */
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS_reserved0_MASK              0xffffffc0
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS_reserved0_SHIFT             6

/* CLKGEN :: MISC_CLOCK_SELECTS :: CLOCK_SEL_SPI_CG_HIF [05:04] */
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_SPI_CG_HIF_MASK   0x00000030
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_SPI_CG_HIF_SHIFT  4

/* CLKGEN :: MISC_CLOCK_SELECTS :: CLOCK_SEL_ENET_CG_MOCA [03:03] */
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_ENET_CG_MOCA_MASK 0x00000008
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_ENET_CG_MOCA_SHIFT 3

/* CLKGEN :: MISC_CLOCK_SELECTS :: CLOCK_SEL_GMII_CG_MOCA [02:02] */
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_GMII_CG_MOCA_MASK 0x00000004
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_GMII_CG_MOCA_SHIFT 2

/* CLKGEN :: MISC_CLOCK_SELECTS :: CLOCK_SEL_CG_GENET [01:01] */
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_CG_GENET_MASK     0x00000002
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_CG_GENET_SHIFT    1

/* CLKGEN :: MISC_CLOCK_SELECTS :: CLOCK_SEL_GMII_CG_GENET [00:00] */
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_GMII_CG_GENET_MASK 0x00000001
#define BCHP_CLKGEN_MISC_CLOCK_SELECTS_CLOCK_SEL_GMII_CG_GENET_SHIFT 0

/***************************************************************************
 *D2CDIFF_AC_CTRL - D2CDIFF no_AC control
 ***************************************************************************/
/* CLKGEN :: D2CDIFF_AC_CTRL :: reserved0 [31:14] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_reserved0_MASK                 0xffffc000
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_reserved0_SHIFT                14

/* CLKGEN :: D2CDIFF_AC_CTRL :: CMLRPTRPTD_XOR [13:13] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_CMLRPTRPTD_XOR_MASK            0x00002000
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_CMLRPTRPTD_XOR_SHIFT           13

/* CLKGEN :: D2CDIFF_AC_CTRL :: CMLRPTMAIN_XOR [12:12] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_CMLRPTMAIN_XOR_MASK            0x00001000
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_CMLRPTMAIN_XOR_SHIFT           12

/* CLKGEN :: D2CDIFF_AC_CTRL :: MOCA_XOR [11:11] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MOCA_XOR_MASK                  0x00000800
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MOCA_XOR_SHIFT                 11

/* CLKGEN :: D2CDIFF_AC_CTRL :: MAIN_XOR [10:10] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MAIN_XOR_MASK                  0x00000400
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MAIN_XOR_SHIFT                 10

/* CLKGEN :: D2CDIFF_AC_CTRL :: MIPS_XOR [09:09] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MIPS_XOR_MASK                  0x00000200
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MIPS_XOR_SHIFT                 9

/* CLKGEN :: D2CDIFF_AC_CTRL :: AVD_XOR [08:08] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_AVD_XOR_MASK                   0x00000100
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_AVD_XOR_SHIFT                  8

/* CLKGEN :: D2CDIFF_AC_CTRL :: RPTD_XOR [07:07] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_RPTD_XOR_MASK                  0x00000080
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_RPTD_XOR_SHIFT                 7

/* CLKGEN :: D2CDIFF_AC_CTRL :: CMLRPTRPTD_STATUS [06:06] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_CMLRPTRPTD_STATUS_MASK         0x00000040
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_CMLRPTRPTD_STATUS_SHIFT        6

/* CLKGEN :: D2CDIFF_AC_CTRL :: CMLRPTMAIN_STATUS [05:05] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_CMLRPTMAIN_STATUS_MASK         0x00000020
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_CMLRPTMAIN_STATUS_SHIFT        5

/* CLKGEN :: D2CDIFF_AC_CTRL :: MOCA_STATUS [04:04] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MOCA_STATUS_MASK               0x00000010
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MOCA_STATUS_SHIFT              4

/* CLKGEN :: D2CDIFF_AC_CTRL :: MAIN_STATUS [03:03] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MAIN_STATUS_MASK               0x00000008
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MAIN_STATUS_SHIFT              3

/* CLKGEN :: D2CDIFF_AC_CTRL :: MIPS_STATUS [02:02] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MIPS_STATUS_MASK               0x00000004
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_MIPS_STATUS_SHIFT              2

/* CLKGEN :: D2CDIFF_AC_CTRL :: AVD_STATUS [01:01] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_AVD_STATUS_MASK                0x00000002
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_AVD_STATUS_SHIFT               1

/* CLKGEN :: D2CDIFF_AC_CTRL :: RPTD_STATUS [00:00] */
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_RPTD_STATUS_MASK               0x00000001
#define BCHP_CLKGEN_D2CDIFF_AC_CTRL_RPTD_STATUS_SHIFT              0

/***************************************************************************
 *DIFFOSC_TEST_CTRL - DIFFOSC_TEST_CTRL Control Register
 ***************************************************************************/
/* CLKGEN :: DIFFOSC_TEST_CTRL :: reserved0 [31:03] */
#define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_reserved0_MASK               0xfffffff8
#define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_reserved0_SHIFT              3

/* CLKGEN :: DIFFOSC_TEST_CTRL :: LIMITER_EN_DIFFOSC [02:02] */
#define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_LIMITER_EN_DIFFOSC_MASK      0x00000004
#define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_LIMITER_EN_DIFFOSC_SHIFT     2

/* CLKGEN :: DIFFOSC_TEST_CTRL :: TEST_EN_DIFFOSC [01:01] */
#define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_TEST_EN_DIFFOSC_MASK         0x00000002
#define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_TEST_EN_DIFFOSC_SHIFT        1

/* CLKGEN :: DIFFOSC_TEST_CTRL :: FREQ_DOUBLER_PWRDN [00:00] */
#define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_FREQ_DOUBLER_PWRDN_MASK      0x00000001
#define BCHP_CLKGEN_DIFFOSC_TEST_CTRL_FREQ_DOUBLER_PWRDN_SHIFT     0

/***************************************************************************
 *PLL_TEST_CTRL - PLL_TEST_CTRL Control Register
 ***************************************************************************/
/* CLKGEN :: PLL_TEST_CTRL :: reserved0 [31:21] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_reserved0_MASK                   0xffe00000
#define BCHP_CLKGEN_PLL_TEST_CTRL_reserved0_SHIFT                  21

/* CLKGEN :: PLL_TEST_CTRL :: SDS_SEL [20:18] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_SDS_SEL_MASK                     0x001c0000
#define BCHP_CLKGEN_PLL_TEST_CTRL_SDS_SEL_SHIFT                    18

/* CLKGEN :: PLL_TEST_CTRL :: SDS_ENA [17:17] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_SDS_ENA_MASK                     0x00020000
#define BCHP_CLKGEN_PLL_TEST_CTRL_SDS_ENA_SHIFT                    17

/* CLKGEN :: PLL_TEST_CTRL :: VCXO_AUDIO_SC_SEL [16:14] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_VCXO_AUDIO_SC_SEL_MASK           0x0001c000
#define BCHP_CLKGEN_PLL_TEST_CTRL_VCXO_AUDIO_SC_SEL_SHIFT          14

/* CLKGEN :: PLL_TEST_CTRL :: SC_ENA [13:13] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_SC_ENA_MASK                      0x00002000
#define BCHP_CLKGEN_PLL_TEST_CTRL_SC_ENA_SHIFT                     13

/* CLKGEN :: PLL_TEST_CTRL :: AUDIO_ENA [12:12] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_AUDIO_ENA_MASK                   0x00001000
#define BCHP_CLKGEN_PLL_TEST_CTRL_AUDIO_ENA_SHIFT                  12

/* CLKGEN :: PLL_TEST_CTRL :: VCXO_ENA [11:11] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_VCXO_ENA_MASK                    0x00000800
#define BCHP_CLKGEN_PLL_TEST_CTRL_VCXO_ENA_SHIFT                   11

/* CLKGEN :: PLL_TEST_CTRL :: MOCA_ENA [10:10] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_MOCA_ENA_MASK                    0x00000400
#define BCHP_CLKGEN_PLL_TEST_CTRL_MOCA_ENA_SHIFT                   10

/* CLKGEN :: PLL_TEST_CTRL :: MIPS_AND_MOCA_SEL [09:07] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_MIPS_AND_MOCA_SEL_MASK           0x00000380
#define BCHP_CLKGEN_PLL_TEST_CTRL_MIPS_AND_MOCA_SEL_SHIFT          7

/* CLKGEN :: PLL_TEST_CTRL :: MIPS_ENA [06:06] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_MIPS_ENA_MASK                    0x00000040
#define BCHP_CLKGEN_PLL_TEST_CTRL_MIPS_ENA_SHIFT                   6

/* CLKGEN :: PLL_TEST_CTRL :: MAIN_AVD_SEL [05:02] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_MAIN_AVD_SEL_MASK                0x0000003c
#define BCHP_CLKGEN_PLL_TEST_CTRL_MAIN_AVD_SEL_SHIFT               2

/* CLKGEN :: PLL_TEST_CTRL :: AVD_ENA [01:01] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_AVD_ENA_MASK                     0x00000002
#define BCHP_CLKGEN_PLL_TEST_CTRL_AVD_ENA_SHIFT                    1

/* CLKGEN :: PLL_TEST_CTRL :: MAIN_ENA [00:00] */
#define BCHP_CLKGEN_PLL_TEST_CTRL_MAIN_ENA_MASK                    0x00000001
#define BCHP_CLKGEN_PLL_TEST_CTRL_MAIN_ENA_SHIFT                   0

/***************************************************************************
 *LOCK - PLL lock status
 ***************************************************************************/
/* CLKGEN :: LOCK :: reserved0 [31:04] */
#define BCHP_CLKGEN_LOCK_reserved0_MASK                            0xfffffff0
#define BCHP_CLKGEN_LOCK_reserved0_SHIFT                           4

/* CLKGEN :: LOCK :: MOCA [03:03] */
#define BCHP_CLKGEN_LOCK_MOCA_MASK                                 0x00000008
#define BCHP_CLKGEN_LOCK_MOCA_SHIFT                                3

/* CLKGEN :: LOCK :: AVD [02:02] */
#define BCHP_CLKGEN_LOCK_AVD_MASK                                  0x00000004
#define BCHP_CLKGEN_LOCK_AVD_SHIFT                                 2

/* CLKGEN :: LOCK :: CPU [01:01] */
#define BCHP_CLKGEN_LOCK_CPU_MASK                                  0x00000002
#define BCHP_CLKGEN_LOCK_CPU_SHIFT                                 1

/* CLKGEN :: LOCK :: MAIN [00:00] */
#define BCHP_CLKGEN_LOCK_MAIN_MASK                                 0x00000001
#define BCHP_CLKGEN_LOCK_MAIN_SHIFT                                0

/***************************************************************************
 *LOCK_CNTR_RESET - VCXO Lock Counter Reset
 ***************************************************************************/
/* CLKGEN :: LOCK_CNTR_RESET :: reserved0 [31:04] */
#define BCHP_CLKGEN_LOCK_CNTR_RESET_reserved0_MASK                 0xfffffff0
#define BCHP_CLKGEN_LOCK_CNTR_RESET_reserved0_SHIFT                4

/* CLKGEN :: LOCK_CNTR_RESET :: MOCA [03:03] */
#define BCHP_CLKGEN_LOCK_CNTR_RESET_MOCA_MASK                      0x00000008
#define BCHP_CLKGEN_LOCK_CNTR_RESET_MOCA_SHIFT                     3

/* CLKGEN :: LOCK_CNTR_RESET :: AVD [02:02] */
#define BCHP_CLKGEN_LOCK_CNTR_RESET_AVD_MASK                       0x00000004
#define BCHP_CLKGEN_LOCK_CNTR_RESET_AVD_SHIFT                      2

/* CLKGEN :: LOCK_CNTR_RESET :: CPU [01:01] */
#define BCHP_CLKGEN_LOCK_CNTR_RESET_CPU_MASK                       0x00000002
#define BCHP_CLKGEN_LOCK_CNTR_RESET_CPU_SHIFT                      1

/* CLKGEN :: LOCK_CNTR_RESET :: MAIN [00:00] */
#define BCHP_CLKGEN_LOCK_CNTR_RESET_MAIN_MASK                      0x00000001
#define BCHP_CLKGEN_LOCK_CNTR_RESET_MAIN_SHIFT                     0

/***************************************************************************
 *MOCA_LOCK_CNT - MOCA PLL Lock Counter
 ***************************************************************************/
/* CLKGEN :: MOCA_LOCK_CNT :: reserved0 [31:12] */
#define BCHP_CLKGEN_MOCA_LOCK_CNT_reserved0_MASK                   0xfffff000
#define BCHP_CLKGEN_MOCA_LOCK_CNT_reserved0_SHIFT                  12

/* CLKGEN :: MOCA_LOCK_CNT :: COUNT [11:00] */
#define BCHP_CLKGEN_MOCA_LOCK_CNT_COUNT_MASK                       0x00000fff
#define BCHP_CLKGEN_MOCA_LOCK_CNT_COUNT_SHIFT                      0

/***************************************************************************
 *AVD_LOCK_CNT - AVD PLL Lock Counter
 ***************************************************************************/
/* CLKGEN :: AVD_LOCK_CNT :: reserved0 [31:12] */
#define BCHP_CLKGEN_AVD_LOCK_CNT_reserved0_MASK                    0xfffff000
#define BCHP_CLKGEN_AVD_LOCK_CNT_reserved0_SHIFT                   12

/* CLKGEN :: AVD_LOCK_CNT :: COUNT [11:00] */
#define BCHP_CLKGEN_AVD_LOCK_CNT_COUNT_MASK                        0x00000fff
#define BCHP_CLKGEN_AVD_LOCK_CNT_COUNT_SHIFT                       0

/***************************************************************************
 *CPU_LOCK_CNT - CPU PLL Lock Counter
 ***************************************************************************/
/* CLKGEN :: CPU_LOCK_CNT :: reserved0 [31:12] */
#define BCHP_CLKGEN_CPU_LOCK_CNT_reserved0_MASK                    0xfffff000
#define BCHP_CLKGEN_CPU_LOCK_CNT_reserved0_SHIFT                   12

/* CLKGEN :: CPU_LOCK_CNT :: COUNT [11:00] */
#define BCHP_CLKGEN_CPU_LOCK_CNT_COUNT_MASK                        0x00000fff
#define BCHP_CLKGEN_CPU_LOCK_CNT_COUNT_SHIFT                       0

/***************************************************************************
 *MAIN_LOCK_CNT - MAIN PLL Lock Counter
 ***************************************************************************/
/* CLKGEN :: MAIN_LOCK_CNT :: reserved0 [31:12] */
#define BCHP_CLKGEN_MAIN_LOCK_CNT_reserved0_MASK                   0xfffff000
#define BCHP_CLKGEN_MAIN_LOCK_CNT_reserved0_SHIFT                  12

/* CLKGEN :: MAIN_LOCK_CNT :: COUNT [11:00] */
#define BCHP_CLKGEN_MAIN_LOCK_CNT_COUNT_MASK                       0x00000fff
#define BCHP_CLKGEN_MAIN_LOCK_CNT_COUNT_SHIFT                      0

/***************************************************************************
 *PLLMAIN_CH2_PM_CTRL - PLL_MAIN Powderdown FSKPHY Reference
 ***************************************************************************/
/* CLKGEN :: PLLMAIN_CH2_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLLMAIN_CH2_PM_CTRL_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLLMAIN_CH2_PM_CTRL_reserved0_SHIFT            1

/* CLKGEN :: PLLMAIN_CH2_PM_CTRL :: PWRDN_CH2_PLLMAIN [00:00] */
#define BCHP_CLKGEN_PLLMAIN_CH2_PM_CTRL_PWRDN_CH2_PLLMAIN_MASK     0x00000001
#define BCHP_CLKGEN_PLLMAIN_CH2_PM_CTRL_PWRDN_CH2_PLLMAIN_SHIFT    0

/***************************************************************************
 *PLLMAIN_CH3_PM_CTRL - PLL_MAIN Powerdown 81MHz Main clock
 ***************************************************************************/
/* CLKGEN :: PLLMAIN_CH3_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLLMAIN_CH3_PM_CTRL_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLLMAIN_CH3_PM_CTRL_reserved0_SHIFT            1

/* CLKGEN :: PLLMAIN_CH3_PM_CTRL :: PWRDN_CH3_PLLMAIN [00:00] */
#define BCHP_CLKGEN_PLLMAIN_CH3_PM_CTRL_PWRDN_CH3_PLLMAIN_MASK     0x00000001
#define BCHP_CLKGEN_PLLMAIN_CH3_PM_CTRL_PWRDN_CH3_PLLMAIN_SHIFT    0

/***************************************************************************
 *PLLMAIN_CH4_PM_CTRL - PLL_MAIN Powerdown 48MHz USB clock
 ***************************************************************************/
/* CLKGEN :: PLLMAIN_CH4_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLLMAIN_CH4_PM_CTRL_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLLMAIN_CH4_PM_CTRL_reserved0_SHIFT            1

/* CLKGEN :: PLLMAIN_CH4_PM_CTRL :: PWRDN_CH4_PLLMAIN [00:00] */
#define BCHP_CLKGEN_PLLMAIN_CH4_PM_CTRL_PWRDN_CH4_PLLMAIN_MASK     0x00000001
#define BCHP_CLKGEN_PLLMAIN_CH4_PM_CTRL_PWRDN_CH4_PLLMAIN_SHIFT    0

/***************************************************************************
 *PLLMAIN_CH5_PM_CTRL - PLL_MAIN Powerdown 33MHz PCI clock
 ***************************************************************************/
/* CLKGEN :: PLLMAIN_CH5_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLLMAIN_CH5_PM_CTRL_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLLMAIN_CH5_PM_CTRL_reserved0_SHIFT            1

/* CLKGEN :: PLLMAIN_CH5_PM_CTRL :: PWRDN_CH5_PLLMAIN [00:00] */
#define BCHP_CLKGEN_PLLMAIN_CH5_PM_CTRL_PWRDN_CH5_PLLMAIN_MASK     0x00000001
#define BCHP_CLKGEN_PLLMAIN_CH5_PM_CTRL_PWRDN_CH5_PLLMAIN_SHIFT    0

/***************************************************************************
 *PLLMAIN_CH6_PM_CTRL - PLL_MAIN Powerdown 32.4MHz Soft Modem clock
 ***************************************************************************/
/* CLKGEN :: PLLMAIN_CH6_PM_CTRL :: reserved0 [31:01] */
#define BCHP_CLKGEN_PLLMAIN_CH6_PM_CTRL_reserved0_MASK             0xfffffffe
#define BCHP_CLKGEN_PLLMAIN_CH6_PM_CTRL_reserved0_SHIFT            1

/* CLKGEN :: PLLMAIN_CH6_PM_CTRL :: PWRDN_CH6_PLLMAIN [00:00] */
#define BCHP_CLKGEN_PLLMAIN_CH6_PM_CTRL_PWRDN_CH6_PLLMAIN_MASK     0x00000001
#define BCHP_CLKGEN_PLLMAIN_CH6_PM_CTRL_PWRDN_CH6_PLLMAIN_SHIFT    0

/***************************************************************************
 *PLLMAIN_CTRL - PLL_MAIN Reset Status & DLY
 ***************************************************************************/
/* CLKGEN :: PLLMAIN_CTRL :: reserved0 [31:07] */
#define BCHP_CLKGEN_PLLMAIN_CTRL_reserved0_MASK                    0xffffff80
#define BCHP_CLKGEN_PLLMAIN_CTRL_reserved0_SHIFT                   7

/* CLKGEN :: PLLMAIN_CTRL :: PLL_MAIN_DLY_CH6 [06:06] */
#define BCHP_CLKGEN_PLLMAIN_CTRL_PLL_MAIN_DLY_CH6_MASK             0x00000040
#define BCHP_CLKGEN_PLLMAIN_CTRL_PLL_MAIN_DLY_CH6_SHIFT            6

/* CLKGEN :: PLLMAIN_CTRL :: PLL_MAIN_DLY_CH5 [05:05] */
#define BCHP_CLKGEN_PLLMAIN_CTRL_PLL_MAIN_DLY_CH5_MASK             0x00000020
#define BCHP_CLKGEN_PLLMAIN_CTRL_PLL_MAIN_DLY_CH5_SHIFT            5

/* CLKGEN :: PLLMAIN_CTRL :: PLL_MAIN_DLY_CH4 [04:04] */
#define BCHP_CLKGEN_PLLMAIN_CTRL_PLL_MAIN_DLY_CH4_MASK             0x00000010
#define BCHP_CLKGEN_PLLMAIN_CTRL_PLL_MAIN_DLY_CH4_SHIFT            4

/* CLKGEN :: PLLMAIN_CTRL :: PLL_MAIN_DLY_CH3 [03:03] */
#define BCHP_CLKGEN_PLLMAIN_CTRL_PLL_MAIN_DLY_CH3_MASK             0x00000008
#define BCHP_CLKGEN_PLLMAIN_CTRL_PLL_MAIN_DLY_CH3_SHIFT            3

/* CLKGEN :: PLLMAIN_CTRL :: PLL_MAIN_DLY_CH2 [02:02] */
#define BCHP_CLKGEN_PLLMAIN_CTRL_PLL_MAIN_DLY_CH2_MASK             0x00000004
#define BCHP_CLKGEN_PLLMAIN_CTRL_PLL_MAIN_DLY_CH2_SHIFT            2

/* CLKGEN :: PLLMAIN_CTRL :: DLY_CH1_PLLMAIN [01:01] */
#define BCHP_CLKGEN_PLLMAIN_CTRL_DLY_CH1_PLLMAIN_MASK              0x00000002
#define BCHP_CLKGEN_PLLMAIN_CTRL_DLY_CH1_PLLMAIN_SHIFT             1

/* CLKGEN :: PLLMAIN_CTRL :: RST_STATUS [00:00] */
#define BCHP_CLKGEN_PLLMAIN_CTRL_RST_STATUS_MASK                   0x00000001
#define BCHP_CLKGEN_PLLMAIN_CTRL_RST_STATUS_SHIFT                  0

/***************************************************************************
 *MIPS_PLL_CTRL - Mips PLL Control Register
 ***************************************************************************/
/* CLKGEN :: MIPS_PLL_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_MIPS_PLL_CTRL_reserved0_MASK                   0xfffffffc
#define BCHP_CLKGEN_MIPS_PLL_CTRL_reserved0_SHIFT                  2

/* CLKGEN :: MIPS_PLL_CTRL :: LDO_CTRL [01:00] */
#define BCHP_CLKGEN_MIPS_PLL_CTRL_LDO_CTRL_MASK                    0x00000003
#define BCHP_CLKGEN_MIPS_PLL_CTRL_LDO_CTRL_SHIFT                   0

/***************************************************************************
 *PLLAVD_RDSP_CTRL - PLLAVD_RDSP PLL Reset, Enable and Powerdown Control
 ***************************************************************************/
/* CLKGEN :: PLLAVD_RDSP_CTRL :: reserved0 [31:17] */
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_reserved0_MASK                0xfffe0000
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_reserved0_SHIFT               17

/* CLKGEN :: PLLAVD_RDSP_CTRL :: NDIV_INT [16:08] */
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_NDIV_INT_MASK                 0x0001ff00
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_NDIV_INT_SHIFT                8

/* CLKGEN :: PLLAVD_RDSP_CTRL :: reserved_for_eco1 [07:06] */
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_reserved_for_eco1_MASK        0x000000c0
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_reserved_for_eco1_SHIFT       6

/* CLKGEN :: PLLAVD_RDSP_CTRL :: VCO_RNG [05:04] */
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_VCO_RNG_MASK                  0x00000030
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_VCO_RNG_SHIFT                 4

/* CLKGEN :: PLLAVD_RDSP_CTRL :: ENB_CLOCKOUT [03:03] */
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_ENB_CLOCKOUT_MASK             0x00000008
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_ENB_CLOCKOUT_SHIFT            3

/* CLKGEN :: PLLAVD_RDSP_CTRL :: PWRDN [02:02] */
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_PWRDN_MASK                    0x00000004
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_PWRDN_SHIFT                   2

/* CLKGEN :: PLLAVD_RDSP_CTRL :: DRESET [01:01] */
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_DRESET_MASK                   0x00000002
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_DRESET_SHIFT                  1

/* CLKGEN :: PLLAVD_RDSP_CTRL :: ARESET [00:00] */
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_ARESET_MASK                   0x00000001
#define BCHP_CLKGEN_PLLAVD_RDSP_CTRL_ARESET_SHIFT                  0

/***************************************************************************
 *PLLAVD_RDSP_PM_CH1_CTRL - PLLAVD_RDSP Secondary 250.71MHz Satellite AFEC clock
 ***************************************************************************/
/* CLKGEN :: PLLAVD_RDSP_PM_CH1_CTRL :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH1_CTRL_reserved0_MASK         0xfffffffc
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH1_CTRL_reserved0_SHIFT        2

/* CLKGEN :: PLLAVD_RDSP_PM_CH1_CTRL :: PWRDN [01:01] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH1_CTRL_PWRDN_MASK             0x00000002
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH1_CTRL_PWRDN_SHIFT            1

/* CLKGEN :: PLLAVD_RDSP_PM_CH1_CTRL :: reserved_for_eco1 [00:00] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH1_CTRL_reserved_for_eco1_MASK 0x00000001
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH1_CTRL_reserved_for_eco1_SHIFT 0

/***************************************************************************
 *PLLAVD_RDSP_PM_CH2_CTRL - PLLAVD_RDSP 250.71MHz AVD/DSP Raptor clock
 ***************************************************************************/
/* CLKGEN :: PLLAVD_RDSP_PM_CH2_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL_reserved0_MASK         0xffff0000
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL_reserved0_SHIFT        16

/* CLKGEN :: PLLAVD_RDSP_PM_CH2_CTRL :: M2DIV [15:08] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL_M2DIV_MASK             0x0000ff00
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL_M2DIV_SHIFT            8

/* CLKGEN :: PLLAVD_RDSP_PM_CH2_CTRL :: reserved_for_eco1 [07:02] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL_reserved_for_eco1_MASK 0x000000fc
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL_reserved_for_eco1_SHIFT 2

/* CLKGEN :: PLLAVD_RDSP_PM_CH2_CTRL :: PWRDN [01:01] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL_PWRDN_MASK             0x00000002
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL_PWRDN_SHIFT            1

/* CLKGEN :: PLLAVD_RDSP_PM_CH2_CTRL :: EN_CMLBUF [00:00] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL_EN_CMLBUF_MASK         0x00000001
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH2_CTRL_EN_CMLBUF_SHIFT        0

/***************************************************************************
 *PLLAVD_RDSP_PM_CH3_CTRL - PLLAVD_RDSP 135MHz Satellite Analog clock
 ***************************************************************************/
/* CLKGEN :: PLLAVD_RDSP_PM_CH3_CTRL :: reserved0 [31:10] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH3_CTRL_reserved0_MASK         0xfffffc00
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH3_CTRL_reserved0_SHIFT        10

/* CLKGEN :: PLLAVD_RDSP_PM_CH3_CTRL :: M3DIV_BITS_1_0 [09:08] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH3_CTRL_M3DIV_BITS_1_0_MASK    0x00000300
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH3_CTRL_M3DIV_BITS_1_0_SHIFT   8

/* CLKGEN :: PLLAVD_RDSP_PM_CH3_CTRL :: reserved_for_eco1 [07:02] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH3_CTRL_reserved_for_eco1_MASK 0x000000fc
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH3_CTRL_reserved_for_eco1_SHIFT 2

/* CLKGEN :: PLLAVD_RDSP_PM_CH3_CTRL :: PWRDN [01:01] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH3_CTRL_PWRDN_MASK             0x00000002
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH3_CTRL_PWRDN_SHIFT            1

/* CLKGEN :: PLLAVD_RDSP_PM_CH3_CTRL :: EN_CMLBUF [00:00] */
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH3_CTRL_EN_CMLBUF_MASK         0x00000001
#define BCHP_CLKGEN_PLLAVD_RDSP_PM_CH3_CTRL_EN_CMLBUF_SHIFT        0

/***************************************************************************
 *PLLMOCA_CONTROL_HIGH_CTRL - Upper 14-bits of the 38-bit PLL control word
 ***************************************************************************/
/* CLKGEN :: PLLMOCA_CONTROL_HIGH_CTRL :: reserved0 [31:14] */
#define BCHP_CLKGEN_PLLMOCA_CONTROL_HIGH_CTRL_reserved0_MASK       0xffffc000
#define BCHP_CLKGEN_PLLMOCA_CONTROL_HIGH_CTRL_reserved0_SHIFT      14

/* CLKGEN :: PLLMOCA_CONTROL_HIGH_CTRL :: CONTROL_HIGH [13:00] */
#define BCHP_CLKGEN_PLLMOCA_CONTROL_HIGH_CTRL_CONTROL_HIGH_MASK    0x00003fff
#define BCHP_CLKGEN_PLLMOCA_CONTROL_HIGH_CTRL_CONTROL_HIGH_SHIFT   0

/***************************************************************************
 *PLLMOCA_CONTROL_LOW_CTRL - Lower 24-bits of the 38-bit PLL control word
 ***************************************************************************/
/* CLKGEN :: PLLMOCA_CONTROL_LOW_CTRL :: reserved0 [31:24] */
#define BCHP_CLKGEN_PLLMOCA_CONTROL_LOW_CTRL_reserved0_MASK        0xff000000
#define BCHP_CLKGEN_PLLMOCA_CONTROL_LOW_CTRL_reserved0_SHIFT       24

/* CLKGEN :: PLLMOCA_CONTROL_LOW_CTRL :: CONTROL_LOW [23:00] */
#define BCHP_CLKGEN_PLLMOCA_CONTROL_LOW_CTRL_CONTROL_LOW_MASK      0x00ffffff
#define BCHP_CLKGEN_PLLMOCA_CONTROL_LOW_CTRL_CONTROL_LOW_SHIFT     0

/***************************************************************************
 *PLLMOCA_CTRL - PLL_MOCA Reset, Powerdown and LDO controls
 ***************************************************************************/
/* CLKGEN :: PLLMOCA_CTRL :: reserved0 [31:06] */
#define BCHP_CLKGEN_PLLMOCA_CTRL_reserved0_MASK                    0xffffffc0
#define BCHP_CLKGEN_PLLMOCA_CTRL_reserved0_SHIFT                   6

/* CLKGEN :: PLLMOCA_CTRL :: LDO_CTRL [05:04] */
#define BCHP_CLKGEN_PLLMOCA_CTRL_LDO_CTRL_MASK                     0x00000030
#define BCHP_CLKGEN_PLLMOCA_CTRL_LDO_CTRL_SHIFT                    4

/* CLKGEN :: PLLMOCA_CTRL :: PWRDN_LDO [03:03] */
#define BCHP_CLKGEN_PLLMOCA_CTRL_PWRDN_LDO_MASK                    0x00000008
#define BCHP_CLKGEN_PLLMOCA_CTRL_PWRDN_LDO_SHIFT                   3

/* CLKGEN :: PLLMOCA_CTRL :: PWRDN [02:02] */
#define BCHP_CLKGEN_PLLMOCA_CTRL_PWRDN_MASK                        0x00000004
#define BCHP_CLKGEN_PLLMOCA_CTRL_PWRDN_SHIFT                       2

/* CLKGEN :: PLLMOCA_CTRL :: DRESET [01:01] */
#define BCHP_CLKGEN_PLLMOCA_CTRL_DRESET_MASK                       0x00000002
#define BCHP_CLKGEN_PLLMOCA_CTRL_DRESET_SHIFT                      1

/* CLKGEN :: PLLMOCA_CTRL :: ARESET [00:00] */
#define BCHP_CLKGEN_PLLMOCA_CTRL_ARESET_MASK                       0x00000001
#define BCHP_CLKGEN_PLLMOCA_CTRL_ARESET_SHIFT                      0

/***************************************************************************
 *PLLMOCA_CH1_PM_CTRL - PLL_MOCA 225MHz CPU clock channel control
 ***************************************************************************/
/* CLKGEN :: PLLMOCA_CH1_PM_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL_reserved0_MASK             0xffff0000
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL_reserved0_SHIFT            16

/* CLKGEN :: PLLMOCA_CH1_PM_CTRL :: M1DIV [15:08] */
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL_M1DIV_MASK                 0x0000ff00
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL_M1DIV_SHIFT                8

/* CLKGEN :: PLLMOCA_CH1_PM_CTRL :: reserved_for_eco1 [07:03] */
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL_reserved_for_eco1_MASK     0x000000f8
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL_reserved_for_eco1_SHIFT    3

/* CLKGEN :: PLLMOCA_CH1_PM_CTRL :: PWRDN_CH [02:02] */
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL_PWRDN_CH_MASK              0x00000004
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL_PWRDN_CH_SHIFT             2

/* CLKGEN :: PLLMOCA_CH1_PM_CTRL :: ENB_CLOCKOUT_CH [01:01] */
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL_ENB_CLOCKOUT_CH_MASK       0x00000002
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL_ENB_CLOCKOUT_CH_SHIFT      1

/* CLKGEN :: PLLMOCA_CH1_PM_CTRL :: EN_CMLBUF_CH [00:00] */
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL_EN_CMLBUF_CH_MASK          0x00000001
#define BCHP_CLKGEN_PLLMOCA_CH1_PM_CTRL_EN_CMLBUF_CH_SHIFT         0

/***************************************************************************
 *PLLMOCA_CH2_PM_CTRL - PLL_MOCA 225MHz PHY clock channel control
 ***************************************************************************/
/* CLKGEN :: PLLMOCA_CH2_PM_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL_reserved0_MASK             0xffff0000
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL_reserved0_SHIFT            16

/* CLKGEN :: PLLMOCA_CH2_PM_CTRL :: M2DIV [15:08] */
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL_M2DIV_MASK                 0x0000ff00
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL_M2DIV_SHIFT                8

/* CLKGEN :: PLLMOCA_CH2_PM_CTRL :: reserved_for_eco1 [07:03] */
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL_reserved_for_eco1_MASK     0x000000f8
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL_reserved_for_eco1_SHIFT    3

/* CLKGEN :: PLLMOCA_CH2_PM_CTRL :: PWRDN_CH [02:02] */
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL_PWRDN_CH_MASK              0x00000004
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL_PWRDN_CH_SHIFT             2

/* CLKGEN :: PLLMOCA_CH2_PM_CTRL :: ENB_CLOCKOUT_CH [01:01] */
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL_ENB_CLOCKOUT_CH_MASK       0x00000002
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL_ENB_CLOCKOUT_CH_SHIFT      1

/* CLKGEN :: PLLMOCA_CH2_PM_CTRL :: EN_CMLBUF_CH [00:00] */
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL_EN_CMLBUF_CH_MASK          0x00000001
#define BCHP_CLKGEN_PLLMOCA_CH2_PM_CTRL_EN_CMLBUF_CH_SHIFT         0

/***************************************************************************
 *PLLMOCA_CH3_PM_CTRL - PLL_MOCA 50MHz USDS clock channel control
 ***************************************************************************/
/* CLKGEN :: PLLMOCA_CH3_PM_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL_reserved0_MASK             0xffff0000
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL_reserved0_SHIFT            16

/* CLKGEN :: PLLMOCA_CH3_PM_CTRL :: M3DIV [15:08] */
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL_M3DIV_MASK                 0x0000ff00
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL_M3DIV_SHIFT                8

/* CLKGEN :: PLLMOCA_CH3_PM_CTRL :: reserved_for_eco1 [07:03] */
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL_reserved_for_eco1_MASK     0x000000f8
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL_reserved_for_eco1_SHIFT    3

/* CLKGEN :: PLLMOCA_CH3_PM_CTRL :: PWRDN_CH [02:02] */
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL_PWRDN_CH_MASK              0x00000004
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL_PWRDN_CH_SHIFT             2

/* CLKGEN :: PLLMOCA_CH3_PM_CTRL :: ENB_CLOCKOUT_CH [01:01] */
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL_ENB_CLOCKOUT_CH_MASK       0x00000002
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL_ENB_CLOCKOUT_CH_SHIFT      1

/* CLKGEN :: PLLMOCA_CH3_PM_CTRL :: EN_CMLBUF_CH [00:00] */
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL_EN_CMLBUF_CH_MASK          0x00000001
#define BCHP_CLKGEN_PLLMOCA_CH3_PM_CTRL_EN_CMLBUF_CH_SHIFT         0

/***************************************************************************
 *PLLMOCA_CH4_PM_CTRL - PLL_MOCA 25MHz GENET clock channel control
 ***************************************************************************/
/* CLKGEN :: PLLMOCA_CH4_PM_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL_reserved0_MASK             0xffff0000
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL_reserved0_SHIFT            16

/* CLKGEN :: PLLMOCA_CH4_PM_CTRL :: M4DIV [15:08] */
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL_M4DIV_MASK                 0x0000ff00
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL_M4DIV_SHIFT                8

/* CLKGEN :: PLLMOCA_CH4_PM_CTRL :: reserved_for_eco1 [07:03] */
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL_reserved_for_eco1_MASK     0x000000f8
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL_reserved_for_eco1_SHIFT    3

/* CLKGEN :: PLLMOCA_CH4_PM_CTRL :: PWRDN_CH [02:02] */
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL_PWRDN_CH_MASK              0x00000004
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL_PWRDN_CH_SHIFT             2

/* CLKGEN :: PLLMOCA_CH4_PM_CTRL :: ENB_CLOCKOUT_CH [01:01] */
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL_ENB_CLOCKOUT_CH_MASK       0x00000002
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL_ENB_CLOCKOUT_CH_SHIFT      1

/* CLKGEN :: PLLMOCA_CH4_PM_CTRL :: EN_CMLBUF_CH4 [00:00] */
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL_EN_CMLBUF_CH4_MASK         0x00000001
#define BCHP_CLKGEN_PLLMOCA_CH4_PM_CTRL_EN_CMLBUF_CH4_SHIFT        0

/***************************************************************************
 *PLLMOCA_CH5_PM_CTRL - PLL_MOCA Satellite Receiver Tuner 257MHz scan clock channel control
 ***************************************************************************/
/* CLKGEN :: PLLMOCA_CH5_PM_CTRL :: reserved0 [31:03] */
#define BCHP_CLKGEN_PLLMOCA_CH5_PM_CTRL_reserved0_MASK             0xfffffff8
#define BCHP_CLKGEN_PLLMOCA_CH5_PM_CTRL_reserved0_SHIFT            3

/* CLKGEN :: PLLMOCA_CH5_PM_CTRL :: PWRDN_CH [02:02] */
#define BCHP_CLKGEN_PLLMOCA_CH5_PM_CTRL_PWRDN_CH_MASK              0x00000004
#define BCHP_CLKGEN_PLLMOCA_CH5_PM_CTRL_PWRDN_CH_SHIFT             2

/* CLKGEN :: PLLMOCA_CH5_PM_CTRL :: ENB_CLOCKOUT_CH [01:01] */
#define BCHP_CLKGEN_PLLMOCA_CH5_PM_CTRL_ENB_CLOCKOUT_CH_MASK       0x00000002
#define BCHP_CLKGEN_PLLMOCA_CH5_PM_CTRL_ENB_CLOCKOUT_CH_SHIFT      1

/* CLKGEN :: PLLMOCA_CH5_PM_CTRL :: EN_CMLBUF_CH [00:00] */
#define BCHP_CLKGEN_PLLMOCA_CH5_PM_CTRL_EN_CMLBUF_CH_MASK          0x00000001
#define BCHP_CLKGEN_PLLMOCA_CH5_PM_CTRL_EN_CMLBUF_CH_SHIFT         0

/***************************************************************************
 *PLLMOCA_CH6_PM_CTRL - PLL_MOCA 100MHz MOCA clock channel control
 ***************************************************************************/
/* CLKGEN :: PLLMOCA_CH6_PM_CTRL :: reserved0 [31:16] */
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL_reserved0_MASK             0xffff0000
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL_reserved0_SHIFT            16

/* CLKGEN :: PLLMOCA_CH6_PM_CTRL :: M6DIV [15:08] */
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL_M6DIV_MASK                 0x0000ff00
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL_M6DIV_SHIFT                8

/* CLKGEN :: PLLMOCA_CH6_PM_CTRL :: reserved_for_eco1 [07:03] */
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL_reserved_for_eco1_MASK     0x000000f8
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL_reserved_for_eco1_SHIFT    3

/* CLKGEN :: PLLMOCA_CH6_PM_CTRL :: PWRDN_CH [02:02] */
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL_PWRDN_CH_MASK              0x00000004
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL_PWRDN_CH_SHIFT             2

/* CLKGEN :: PLLMOCA_CH6_PM_CTRL :: ENB_CLOCKOUT_CH [01:01] */
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL_ENB_CLOCKOUT_CH_MASK       0x00000002
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL_ENB_CLOCKOUT_CH_SHIFT      1

/* CLKGEN :: PLLMOCA_CH6_PM_CTRL :: EN_CMLBUF_CH6 [00:00] */
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL_EN_CMLBUF_CH6_MASK         0x00000001
#define BCHP_CLKGEN_PLLMOCA_CH6_PM_CTRL_EN_CMLBUF_CH6_SHIFT        0

/***************************************************************************
 *PLL_TIMER_SELECT - Select the delay after reset before using PLL
 ***************************************************************************/
/* CLKGEN :: PLL_TIMER_SELECT :: reserved0 [31:02] */
#define BCHP_CLKGEN_PLL_TIMER_SELECT_reserved0_MASK                0xfffffffc
#define BCHP_CLKGEN_PLL_TIMER_SELECT_reserved0_SHIFT               2

/* CLKGEN :: PLL_TIMER_SELECT :: TIMER [01:00] */
#define BCHP_CLKGEN_PLL_TIMER_SELECT_TIMER_MASK                    0x00000003
#define BCHP_CLKGEN_PLL_TIMER_SELECT_TIMER_SHIFT                   0

/***************************************************************************
 *PM_PLL_ALIVE_SEL - Program the PLLs to be alive in standby
 ***************************************************************************/
/* CLKGEN :: PM_PLL_ALIVE_SEL :: reserved0 [31:03] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_MASK                0xfffffff8
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_reserved0_SHIFT               3

/* CLKGEN :: PM_PLL_ALIVE_SEL :: DDR_PLL [02:02] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DDR_PLL_MASK                  0x00000004
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_DDR_PLL_SHIFT                 2

/* CLKGEN :: PM_PLL_ALIVE_SEL :: MIPS_PLL [01:01] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_MIPS_PLL_MASK                 0x00000002
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_MIPS_PLL_SHIFT                1

/* CLKGEN :: PM_PLL_ALIVE_SEL :: MAIN_PLL [00:00] */
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_MAIN_PLL_MASK                 0x00000001
#define BCHP_CLKGEN_PM_PLL_ALIVE_SEL_MAIN_PLL_SHIFT                0

/***************************************************************************
 *PM_CLOCK_216_108_ALIVE_SEL - Program the 216/108 clocks to be alive in standby
 ***************************************************************************/
/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: reserved0 [31:12] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_reserved0_MASK      0xfffff000
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_reserved0_SHIFT     12

/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_108_CG_FTM [11:11] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_FTM_MASK 0x00000800
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_FTM_SHIFT 11

/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_216_CG_FTM [10:10] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_FTM_MASK 0x00000400
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_FTM_SHIFT 10

/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_108_CG_QPSK [09:09] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_QPSK_MASK 0x00000200
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_QPSK_SHIFT 9

/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_216_CG_QPSK [08:08] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_QPSK_MASK 0x00000100
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_QPSK_SHIFT 8

/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_108_CG_STFEC [07:07] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_STFEC_MASK 0x00000080
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_STFEC_SHIFT 7

/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_216_CG_STFEC [06:06] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_STFEC_MASK 0x00000040
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_STFEC_SHIFT 6

/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_108_CG_SRCTN [05:05] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_SRCTN_MASK 0x00000020
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_SRCTN_SHIFT 5

/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_216_CG_SRCTN [04:04] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_SRCTN_MASK 0x00000010
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_SRCTN_SHIFT 4

/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_108_CG_SAFEC [03:03] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_SAFEC_MASK 0x00000008
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_SAFEC_SHIFT 3

/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_216_CG_SAFEC [02:02] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_SAFEC_MASK 0x00000004
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_SAFEC_SHIFT 2

/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_108_CG_XPT [01:01] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_XPT_MASK 0x00000002
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_108_CG_XPT_SHIFT 1

/* CLKGEN :: PM_CLOCK_216_108_ALIVE_SEL :: CLOCK_216_CG_XPT [00:00] */
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_XPT_MASK 0x00000001
#define BCHP_CLKGEN_PM_CLOCK_216_108_ALIVE_SEL_CLOCK_216_CG_XPT_SHIFT 0

/***************************************************************************
 *SMARTCARD_CLOCK_CTRL - SMARTCARD_CLOCK_CTRL Register
 ***************************************************************************/
/* CLKGEN :: SMARTCARD_CLOCK_CTRL :: reserved0 [31:05] */
#define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_reserved0_MASK            0xffffffe0
#define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_reserved0_SHIFT           5

/* CLKGEN :: SMARTCARD_CLOCK_CTRL :: SMARTCARD_PLL_REFERENCE_CLK_SEL [04:04] */
#define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_SMARTCARD_PLL_REFERENCE_CLK_SEL_MASK 0x00000010
#define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_SMARTCARD_PLL_REFERENCE_CLK_SEL_SHIFT 4

/* CLKGEN :: SMARTCARD_CLOCK_CTRL :: SMARTCARD_CLOCK_2_SOURCE_SEL [03:02] */
#define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_SMARTCARD_CLOCK_2_SOURCE_SEL_MASK 0x0000000c
#define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_SMARTCARD_CLOCK_2_SOURCE_SEL_SHIFT 2

/* CLKGEN :: SMARTCARD_CLOCK_CTRL :: SMARTCARD_CLOCK_1_SOURCE_SEL [01:00] */
#define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_SMARTCARD_CLOCK_1_SOURCE_SEL_MASK 0x00000003
#define BCHP_CLKGEN_SMARTCARD_CLOCK_CTRL_SMARTCARD_CLOCK_1_SOURCE_SEL_SHIFT 0

/***************************************************************************
 *SCRATCH_REG - Scratch Register
 ***************************************************************************/
/* CLKGEN :: SCRATCH_REG :: VALUE [31:00] */
#define BCHP_CLKGEN_SCRATCH_REG_VALUE_MASK                         0xffffffff
#define BCHP_CLKGEN_SCRATCH_REG_VALUE_SHIFT                        0

#endif /* #ifndef BCHP_CLKGEN_H__ */

/* End of File */