#ifndef _ASM_MIPS_PERF_REGS_H
#define _ASM_MIPS_PERF_REGS_H

enum perf_event_mips_regs {
       PERF_REG_MIPS_PC,
       PERF_REG_MIPS_R1,
       PERF_REG_MIPS_R2,
       PERF_REG_MIPS_R3,
       PERF_REG_MIPS_R4,
       PERF_REG_MIPS_R5,
       PERF_REG_MIPS_R6,
       PERF_REG_MIPS_R7,
       PERF_REG_MIPS_R8,
       PERF_REG_MIPS_R9,
       PERF_REG_MIPS_R10,
       PERF_REG_MIPS_R11,
       PERF_REG_MIPS_R12,
       PERF_REG_MIPS_R13,
       PERF_REG_MIPS_R14,
       PERF_REG_MIPS_R15,
       PERF_REG_MIPS_R16,
       PERF_REG_MIPS_R17,
       PERF_REG_MIPS_R18,
       PERF_REG_MIPS_R19,
       PERF_REG_MIPS_R20,
       PERF_REG_MIPS_R21,
       PERF_REG_MIPS_R22,
       PERF_REG_MIPS_R23,
       PERF_REG_MIPS_R24,
       PERF_REG_MIPS_R25,
       /*
        * 26 and 27 are k0 and k1, they are always clobbered thus not
        * stored.
        */
       PERF_REG_MIPS_R28,
       PERF_REG_MIPS_R29,
       PERF_REG_MIPS_R30,
       PERF_REG_MIPS_R31,
       PERF_REG_MIPS_MAX = PERF_REG_MIPS_R31 + 1,
};
#endif /* _ASM_MIPS_PERF_REGS_H */