blob: 554c15bf8df707a0f22b1595fca0827fca509281 [file] [log] [blame]
/*
* Device Tree file for Google Chimera board based on Marvell 88F6810
*
* derived from armada-385-db-ap.dts, which is:
*
* Copyright (C) 2014 Marvell
*
* Nadav Haklai <nadavh@marvell.com>
* Ed James <edjames@google.com>
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without
* any warranty of any kind, whether express or implied.
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include "armada-380.dtsi"
#include <dt-bindings/gpio/gpio.h>
/ {
model = "gfch100 - Marvell Armada 38x";
compatible = "google,gfch100", "marvell,armada380", "marvell,armada38x";
chosen {
bootargs = "console=ttyS0,115200";
};
memory {
device_type = "memory";
reg = <0x00000000 0x40000000>; /* 1GB */
};
soc {
ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
internal-regs {
spi0: spi@10600 {
compatible = "marvell,armada-370-spi", "marvell,orion-spi";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins>;
status = "okay";
spi-flash@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "st,m25p16";
reg = <0>; /* Chip select 0 */
spi-max-frequency = <50000000>;
partition@0 {
label = "loader";
reg = <0 0x100000>;
};
partition@100000 {
label = "env";
reg = <0x100000 0x10000>;
};
partition@110000 {
label = "reserved";
reg = <0x110000 0xf0000>;
};
};
k60@1 {
compatible = "broadcom,k60";
reg = <1>; /* Chip select 1 */
spi-max-frequency = <25000000>;
};
};
uart0: serial@12000 {
pinctrl-names = "default";
pinctrl-0 = <&uart0_pins>;
status = "okay";
};
uart1: serial@12100 {
pinctrl-names = "default";
pinctrl-0 = <&uart1_pins>;
status = "okay";
};
i2c0: i2c@11000 {
pinctrl-names = "default";
pinctrl-0 = <&i2c0_pins>;
status = "okay";
};
i2c1: i2c@11100 {
pinctrl-names = "default";
pinctrl-0 = <&i2c1_pins>;
status = "okay";
};
mdio@72004 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins>;
/* phy 3 is craft <-> SOC */
phy3: ethernet-phy@3 {
reg = <3>;
};
};
pinctrl@18000 {
status = "okay";
xhci0_vbus_pins: xhci0-vbus-pins {
marvell,pins = "mpp44";
marvell,function = "gpio";
};
i2c1_pins: i2c1-pins {
marvell,pins = "mpp26", "mpp27";
marvell,function = "i2c1";
};
};
/* craft port, serdes lane 1*/
ethernet@30000 {
status = "okay";
phy = <&phy3>;
phy-mode = "sgmii";
};
/* switch, serdes lane 0 */
ethernet@70000 {
status = "okay";
phy-mode = "sgmii";
fixed-link {
speed = <1000>;
full-duplex;
};
};
/* not used, but keeps uboot happy */
flash@d0000 {
status = "disabled";
};
sdhci@d8000 {
pinctrl-names = "default";
pinctrl-0 = <&sdhci_pins>;
broken-cd;
no-1-8-v;
wp-inverted;
bus-width = <8>;
status = "okay";
};
usb@58000 {
status = "okay";
};
usb3@f0000 {
status = "okay";
usb-phy = <&usb3_phy>;
};
};
pcie-controller {
status = "okay";
pcie@1,0 {
/* Port 0, Lane 0 */
status = "okay";
};
pcie@2,0 {
/* Port 1, Lane 0 */
status = "okay";
};
pcie@3,0 {
/* Port 2, Lane 0 */
status = "okay";
};
};
};
usb3_phy: usb3_phy {
compatible = "usb-nop-xceiv";
vcc-supply = <&reg_xhci0_vbus>;
};
reg_xhci0_vbus: xhci0-vbus {
compatible = "regulator-fixed";
pinctrl-names = "default";
pinctrl-0 = <&xhci0_vbus_pins>;
regulator-name = "xhci0-vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
enable-active-high;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
};
};