Merge Linux 4.4.40 to master

Change-Id: Ie8115c17a8caf7e069f6cacba722e309234c28d3
diff --git a/Documentation/hwmon/ltc2990 b/Documentation/hwmon/ltc2990
new file mode 100644
index 0000000..c25211e
--- /dev/null
+++ b/Documentation/hwmon/ltc2990
@@ -0,0 +1,43 @@
+Kernel driver ltc2990
+=====================
+
+Supported chips:
+  * Linear Technology LTC2990
+    Prefix: 'ltc2990'
+    Addresses scanned: -
+    Datasheet: http://www.linear.com/product/ltc2990
+
+Author: Mike Looijmans <mike.looijmans@topic.nl>
+
+
+Description
+-----------
+
+LTC2990 is a Quad I2C Voltage, Current and Temperature Monitor.
+The chip's inputs can measure 4 voltages, or two inputs together (1+2 and 3+4)
+can be combined to measure a differential voltage, which is typically used to
+measure current through a series resistor, or a temperature.
+
+This driver currently uses the 2x differential mode only. In order to support
+other modes, the driver will need to be expanded.
+
+
+Usage Notes
+-----------
+
+This driver does not probe for PMBus devices. You will have to instantiate
+devices explicitly.
+
+
+Sysfs attributes
+----------------
+
+The "curr*_input" measurements actually report the voltage drop across the
+input pins in microvolts. This is equivalent to the current through a 1mOhm
+sense resistor. Divide the reported value by the actual sense resistor value
+in mOhm to get the actual value.
+
+in0_input     Voltage at Vcc pin in millivolt (range 2.5V to 5V)
+temp1_input   Internal chip temperature in millidegrees Celcius
+curr1_input   Current in mA across v1-v2 assuming a 1mOhm sense resistor.
+curr2_input   Current in mA across v3-v4 assuming a 1mOhm sense resistor.
diff --git a/Makefile b/Makefile
index 5b59377..6bfb49b 100644
--- a/Makefile
+++ b/Makefile
@@ -1,7 +1,7 @@
 VERSION = 4
 PATCHLEVEL = 4
 SUBLEVEL = 40
-EXTRAVERSION =
+EXTRAVERSION = -gfiber0
 NAME = Blurry Fish Butt
 
 # *DOCUMENTATION*
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index 34e1569..5842ed1 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -782,6 +782,8 @@
 	bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
 	default y
 	select ARCH_MULTI_V6_V7
+	select ARCH_FLATMEM_ENABLE
+	select ARCH_SPARSEMEM_ENABLE
 	select CPU_V7
 	select HAVE_SMP
 
@@ -1643,11 +1645,11 @@
 config ARCH_HAS_HOLES_MEMORYMODEL
 	bool
 
-config ARCH_SPARSEMEM_ENABLE
+config ARCH_FLATMEM_ENABLE
 	bool
 
-config ARCH_SPARSEMEM_DEFAULT
-	def_bool ARCH_SPARSEMEM_ENABLE
+config ARCH_SPARSEMEM_ENABLE
+	bool
 
 config ARCH_SELECT_MEMORY_MODEL
 	def_bool ARCH_SPARSEMEM_ENABLE
diff --git a/arch/arm/Kconfig.debug b/arch/arm/Kconfig.debug
index ddbb361..84dd56c 100644
--- a/arch/arm/Kconfig.debug
+++ b/arch/arm/Kconfig.debug
@@ -1436,7 +1436,17 @@
 	default 0xe6e60000 if DEBUG_RCAR_GEN2_SCIF0
 	default 0xe8008000 if DEBUG_R7S72100_SCIF2
 	default 0xf0000be0 if ARCH_EBSA110
+	default 0xf040a900 if DEBUG_BRCMSTB_UART && BCM3390A0
+	default 0xf040a900 if DEBUG_BRCMSTB_UART && BCM7145B0
+	default 0xf040b400 if DEBUG_BRCMSTB_UART && BCM7250B0
+	default 0xf040b000 if DEBUG_BRCMSTB_UART && BCM7364A0
+	default 0xf040b000 if DEBUG_BRCMSTB_UART && BCM7366C0
+	default 0xf040a900 if DEBUG_BRCMSTB_UART && BCM7439B0
+	default 0xf040ab00 if DEBUG_BRCMSTB_UART && BCM7445D0
 	default 0xf040ab00 if DEBUG_BRCMSTB_UART
+# Note(jnewlin): The default in brcm's drop is below, but doesn't
+# match what is needed for 7428/7425, so keeping google's default.
+#	default 0xf0406b00 if DEBUG_BRCMSTB_UART
 	default 0xf1012000 if DEBUG_MVEBU_UART0_ALTERNATE
 	default 0xf1012100 if DEBUG_MVEBU_UART1_ALTERNATE
 	default 0xf1012000 if ARCH_DOVE || ARCH_MV78XX0 || \
@@ -1508,7 +1518,16 @@
 	default 0xfb002000 if DEBUG_CNS3XXX
 	default 0xfb009000 if DEBUG_REALVIEW_STD_PORT
 	default 0xfb10c000 if DEBUG_REALVIEW_PB1176_PORT
+	default 0xfc40a900 if DEBUG_BRCMSTB_UART && BCM3390A0
+	default 0xfc40a900 if DEBUG_BRCMSTB_UART && BCM7145B0
+	default 0xfc40b400 if DEBUG_BRCMSTB_UART && BCM7250B0
+	default 0xfc40b000 if DEBUG_BRCMSTB_UART && BCM7364A0
+	default 0xfc40b000 if DEBUG_BRCMSTB_UART && BCM7366C0
+	default 0xfc40a900 if DEBUG_BRCMSTB_UART && BCM7439B0
+	default 0xfc40ab00 if DEBUG_BRCMSTB_UART && BCM7445D0
 	default 0xfc40ab00 if DEBUG_BRCMSTB_UART
+# Keep google's default
+#	default 0xfc406b00 if DEBUG_BRCMSTB_UART
 	default 0xfc705000 if DEBUG_ZTE_ZX
 	default 0xfcfe8600 if DEBUG_BCM63XX_UART
 	default 0xfd000000 if ARCH_SPEAR3XX || ARCH_SPEAR6XX
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 2c2b28e..b7be932 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -252,11 +252,16 @@
 MACHINE  :=
 endif
 ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
+# hack for broadcom, don't clear MACHINE
+ifneq ($(machine-y),bcm)
 MACHINE  :=
 endif
+endif
 
 machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
 platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y)))
+$(shell echo machdirs=$(machdirs) >> /tmp/crap)
+$(shell echo platdirs=$(platdirs) >> /tmp/crap)
 
 ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
 ifeq ($(KBUILD_SRC),)
@@ -266,6 +271,16 @@
 endif
 endif
 
+# Hack for broadcom
+ifeq ($(machine-y),bcm)
+ifeq ($(KBUILD_SRC),)
+KBUILD_CPPFLAGS += $(patsubst %,-I%include,$(machdirs) $(platdirs))
+else
+KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
+endif
+endif
+# end hack for broadcom
+
 export	TEXT_OFFSET GZFLAGS MMUEXT
 
 # Do we have FASTFPE?
diff --git a/arch/arm/boot/dts/bcm7445a0.dts b/arch/arm/boot/dts/bcm7445a0.dts
new file mode 100644
index 0000000..4756c9f
--- /dev/null
+++ b/arch/arm/boot/dts/bcm7445a0.dts
@@ -0,0 +1,129 @@
+/dts-v1/;
+
+/ {
+	model = "Broadcom STB (7445a0)";
+	compatible = "brcm,brcmstb";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	interrupt-parent = <&gic>;
+
+	chosen {
+		bootargs = "console=ttyS0,115200 earlyprintk";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x10000000>; /* 256 MB */
+	};
+
+	// ARM GIC
+	gic: interrupt-controller@FFD00000 {
+		compatible = "arm,cortex-a15-gic";
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		reg = <0xFFD01000 0x1000>,
+		      <0xFFD02000 0x2000>;
+	};
+
+	//
+	// UARTS
+	//
+
+	// UART A (0)
+	uart0: serial@F0406B00 {
+		compatible = "ns16550a";
+		reg = <0xF0406B00 0x20>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <0 75 0x4>;
+		clock-frequency = <81000000>;
+	};
+
+	// UART B (1)
+	uart1: serial@F0406B40 {
+		compatible = "ns16550a";
+		reg = <0xF0406B40 0x20>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <0 76 0x4>;
+		clock-frequency = <81000000>;
+	};
+
+	// UART C (2)
+	uart2: serial@F0406B80 {
+		compatible = "ns16550a";
+		reg = <0xF0406B80 0x20>;
+		reg-shift = <2>;
+		reg-io-width = <4>;
+		interrupts = <0 77 0x4>;
+		clock-frequency = <81000000>;
+	};
+
+	usb0: usb@f0470000 {
+		compatible = "brcm,usb-instance";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xf0470200 0x100>;
+		ipp = <1>;
+		ioc = <1>;
+		ranges;
+
+		ehci0: ehci@f0470300 {
+			compatible = "brcm,ehci-brcm";
+			reg = <0xf0470300 0x100>;
+			interrupts = <0 79 0>;
+		};
+
+		ohci0: ehci@f0470400 {
+			compatible = "brcm,ohci-brcm";
+			reg = <0xf0470400 0x100>;
+			interrupts = <0 81 0>;
+		};
+
+		ehci1: ehci@f0470500 {
+			compatible = "brcm,ehci-brcm";
+			reg = <0xf0470500 0x100>;
+			interrupts = <0 80 0>;
+		};
+
+		ohci1: ehci@f0470600 {
+			compatible = "brcm,ohci-brcm";
+			reg = <0xf0470600 0x100>;
+			interrupts = <0 82 0>;
+		};
+	};
+
+	usb1: usb@f0480000 {
+		compatible = "brcm,usb-instance";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		reg = <0xf0480200 0x100>;
+		ipp = <1>;
+		ioc = <1>;
+		ranges;
+
+		ehci2: ehci@f0480300 {
+			compatible = "brcm,ehci-brcm";
+			reg = <0xf0480300 0x100>;
+			interrupts = <0 86 0>;
+		};
+
+		ohci2: ehci@f0480400 {
+			compatible = "brcm,ohci-brcm";
+			reg = <0xf0480400 0x100>;
+			interrupts = <0 88 0>;
+		};
+
+		ehci3: ehci@f0480500 {
+			compatible = "brcm,ehci-brcm";
+			reg = <0xf0480500 0x100>;
+			interrupts = <0 87 0>;
+		};
+
+		ohci3: ehci@f0480600 {
+			compatible = "brcm,ohci-brcm";
+			reg = <0xf0480600 0x100>;
+			interrupts = <0 89 0>;
+		};
+	};
+};
diff --git a/arch/arm/boot/dts/gfch100.dts b/arch/arm/boot/dts/gfch100.dts
new file mode 100644
index 0000000..554c15b
--- /dev/null
+++ b/arch/arm/boot/dts/gfch100.dts
@@ -0,0 +1,224 @@
+/*
+ * Device Tree file for Google Chimera board based on Marvell 88F6810
+ *
+ * derived from armada-385-db-ap.dts, which is:
+ *
+ *  Copyright (C) 2014 Marvell
+ *
+ * Nadav Haklai <nadavh@marvell.com>
+ * Ed James <edjames@google.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This file is licensed under the terms of the GNU General Public
+ *     License version 2.  This program is licensed "as is" without
+ *     any warranty of any kind, whether express or implied.
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+#include "armada-380.dtsi"
+
+#include <dt-bindings/gpio/gpio.h>
+
+/ {
+	model = "gfch100 - Marvell Armada 38x";
+	compatible = "google,gfch100", "marvell,armada380", "marvell,armada38x";
+
+	chosen {
+		bootargs = "console=ttyS0,115200";
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0x00000000 0x40000000>; /* 1GB */
+	};
+
+	soc {
+		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
+			  MBUS_ID(0x01, 0x1d) 0 0xfff00000 0x100000>;
+
+		internal-regs {
+			spi0: spi@10600 {
+				compatible = "marvell,armada-370-spi", "marvell,orion-spi";
+				pinctrl-names = "default";
+				pinctrl-0 = <&spi0_pins>;
+				status = "okay";
+
+				spi-flash@0 {
+					#address-cells = <1>;
+					#size-cells = <1>;
+					compatible = "st,m25p16";
+					reg = <0>; /* Chip select 0 */
+					spi-max-frequency = <50000000>;
+					partition@0 {
+						label = "loader";
+						reg = <0 0x100000>;
+					};
+					partition@100000 {
+						label = "env";
+						reg = <0x100000 0x10000>;
+					};
+					partition@110000 {
+						label = "reserved";
+						reg = <0x110000 0xf0000>;
+					};
+				};
+
+				k60@1 {
+					compatible = "broadcom,k60";
+					reg = <1>; /* Chip select 1 */
+					spi-max-frequency = <25000000>;
+				};
+			};
+
+			uart0: serial@12000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart0_pins>;
+				status = "okay";
+			};
+
+			uart1: serial@12100 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&uart1_pins>;
+				status = "okay";
+			};
+
+			i2c0: i2c@11000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c0_pins>;
+				status = "okay";
+			};
+
+			i2c1: i2c@11100 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&i2c1_pins>;
+				status = "okay";
+			};
+
+			mdio@72004 {
+				status = "okay";
+				pinctrl-names = "default";
+				pinctrl-0 = <&mdio_pins>;
+
+				/* phy 3 is craft <-> SOC */
+				phy3: ethernet-phy@3 {
+					reg = <3>;
+				};
+			};
+
+			pinctrl@18000 {
+				status = "okay";
+				xhci0_vbus_pins: xhci0-vbus-pins {
+					marvell,pins = "mpp44";
+					marvell,function = "gpio";
+				};
+				i2c1_pins: i2c1-pins {
+					marvell,pins = "mpp26",	 "mpp27";
+					marvell,function = "i2c1";
+				};
+			};
+
+			/* craft port, serdes lane 1*/
+			ethernet@30000 {
+				status = "okay";
+				phy = <&phy3>;
+				phy-mode = "sgmii";
+			};
+
+			/* switch, serdes lane 0 */
+			ethernet@70000 {
+				status = "okay";
+				phy-mode = "sgmii";
+				fixed-link {
+					speed = <1000>;
+					full-duplex;
+				};
+			};
+
+			/* not used, but keeps uboot happy */
+			flash@d0000 {
+				status = "disabled";
+			};
+
+			sdhci@d8000 {
+				pinctrl-names = "default";
+				pinctrl-0 = <&sdhci_pins>;
+				broken-cd;
+				no-1-8-v;
+				wp-inverted;
+				bus-width = <8>;
+				status = "okay";
+			};
+
+			usb@58000 {
+				status = "okay";
+			};
+
+			usb3@f0000 {
+				status = "okay";
+				usb-phy = <&usb3_phy>;
+			};
+		};
+
+		pcie-controller {
+			status = "okay";
+
+			pcie@1,0 {
+				/* Port 0, Lane 0 */
+				status = "okay";
+			};
+
+			pcie@2,0 {
+				/* Port 1, Lane 0 */
+				status = "okay";
+			};
+
+			pcie@3,0 {
+				/* Port 2, Lane 0 */
+				status = "okay";
+			};
+		};
+	};
+
+	usb3_phy: usb3_phy {
+		compatible = "usb-nop-xceiv";
+		vcc-supply = <&reg_xhci0_vbus>;
+	};
+
+	reg_xhci0_vbus: xhci0-vbus {
+		compatible = "regulator-fixed";
+		pinctrl-names = "default";
+		pinctrl-0 = <&xhci0_vbus_pins>;
+		regulator-name = "xhci0-vbus";
+		regulator-min-microvolt = <5000000>;
+		regulator-max-microvolt = <5000000>;
+		enable-active-high;
+		gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
+	};
+};
diff --git a/arch/arm/configs/bcm7445a0_defconfig b/arch/arm/configs/bcm7445a0_defconfig
new file mode 100644
index 0000000..907210c
--- /dev/null
+++ b/arch/arm/configs/bcm7445a0_defconfig
@@ -0,0 +1,125 @@
+CONFIG_EXPERIMENTAL=y
+CONFIG_CROSS_COMPILE="arm-linux-"
+CONFIG_KERNEL_LZMA=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_BRCMSTB=y
+# CONFIG_SWP_EMULATE is not set
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_SMP=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_CMDLINE="console=ttyS0,115200 earlyprintk"
+CONFIG_VFP=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_OF_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/arm/configs/brcmstb_defconfig b/arch/arm/configs/brcmstb_defconfig
new file mode 100644
index 0000000..7f0d16d
--- /dev/null
+++ b/arch/arm/configs/brcmstb_defconfig
@@ -0,0 +1,227 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BRCMSTB=y
+CONFIG_ARM_LPAE=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIEAER is not set
+CONFIG_SMP=y
+CONFIG_ARM_PSCI=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_CMA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+# CONFIG_KEXEC is not set
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_CRAMFS=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_UDP_DIAG=y
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_ALIGNMENT=12
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_EEPROM_93CX6=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_BRCMSTB=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HP is not set
+CONFIG_E1000E=y
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MPU3050=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_GPIOLIB=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_INTEL_POWERCLAMP=y
+CONFIG_BRCMSTB_THERMAL=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_GSPCA=y
+# CONFIG_VGA_ARB is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_BRCMSTB_BMEM=y
+CONFIG_BRCMSTB_CMA=y
+CONFIG_BRCMSTB_MEMORY_API=y
+CONFIG_BRCMSTB_SRPD=y
+CONFIG_BRCMSTB_WKTMR=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_GENERIC_PHY=y
+CONFIG_EXT4_FS=y
+CONFIG_JBD2_DEBUG=y
+CONFIG_FUSE_FS=y
+CONFIG_FHANDLE=y
+CONFIG_CGROUPS=y
+CONFIG_CUSE=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_BRCMSTB_UART=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/brcmstb_hardened_defconfig b/arch/arm/configs/brcmstb_hardened_defconfig
new file mode 100644
index 0000000..0fd8099
--- /dev/null
+++ b/arch/arm/configs/brcmstb_hardened_defconfig
@@ -0,0 +1,177 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+# CONFIG_SWAP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+# CONFIG_KALLSYMS is not set
+# CONFIG_PRINTK is not set
+# CONFIG_BUG is not set
+# CONFIG_ELF_CORE is not set
+# CONFIG_COMPAT_BRK is not set
+CONFIG_CC_STACKPROTECTOR_REGULAR=y
+CONFIG_MODULES=y
+CONFIG_MODVERSIONS=y
+# CONFIG_LBDAF is not set
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BRCMSTB=y
+# CONFIG_BRCM_MOCA is not set
+CONFIG_ARM_LPAE=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCIEPORTBUS=y
+# CONFIG_PCIEAER is not set
+CONFIG_SMP=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=32768
+CONFIG_CMA=y
+# CONFIG_ATAGS is not set
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_UDP_DIAG=y
+# CONFIG_IPV6 is not set
+CONFIG_NETFILTER=y
+CONFIG_IP_NF_IPTABLES=y
+CONFIG_BRIDGE=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_ALIGNMENT=12
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_3COM is not set
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HP is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+# CONFIG_INPUT is not set
+# CONFIG_SERIO is not set
+# CONFIG_VT is not set
+# CONFIG_LEGACY_PTYS is not set
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+# CONFIG_SERIAL_8250_PCI is not set
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_BRCMSTB_THERMAL=y
+CONFIG_SOUND=y
+CONFIG_SND=y
+# CONFIG_SND_VERBOSE_PROCFS is not set
+# CONFIG_SND_PCI is not set
+# CONFIG_SND_SPI is not set
+# CONFIG_SND_USB is not set
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_TMPFS=y
+# CONFIG_MISC_FILESYSTEMS is not set
+# CONFIG_NETWORK_FILESYSTEMS is not set
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_SCHED_DEBUG is not set
+# CONFIG_FTRACE is not set
+CONFIG_STRICT_DEVMEM=y
+# CONFIG_ARM_UNWIND is not set
+CONFIG_SECURITY_DMESG_RESTRICT=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
diff --git a/arch/arm/configs/bruno_gfhd254_defconfig b/arch/arm/configs/bruno_gfhd254_defconfig
new file mode 100644
index 0000000..8dba336
--- /dev/null
+++ b/arch/arm/configs/bruno_gfhd254_defconfig
@@ -0,0 +1,236 @@
+CONFIG_CROSS_COMPILE="arm-linux-gnueabihf-"
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_CGROUPS=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BRCMSTB=y
+CONFIG_BCM7439B0=y
+CONFIG_ARM_LPAE=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_SMP=y
+CONFIG_ARM_PSCI=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_CMA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_IPV6=y
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_BT=m
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_ALIGNMENT=12
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_EEPROM_93CX6=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_BRCMSTB=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HP is not set
+CONFIG_E1000E=y
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MPU3050=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_GPIOLIB=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_THERMAL_DEFAULT_GOV_USER_SPACE=y
+CONFIG_THERMAL_GOV_STEP_WISE=y
+CONFIG_CPU_THERMAL=y
+CONFIG_INTEL_POWERCLAMP=y
+CONFIG_BRCMSTB_THERMAL=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_GSPCA=y
+# CONFIG_VGA_ARB is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
+CONFIG_HID_GFRM=m
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_BRCMSTB_BMEM=y
+CONFIG_BRCMSTB_CMA=y
+CONFIG_BRCMSTB_MEMORY_API=y
+CONFIG_BRCMSTB_SRPD=y
+CONFIG_BRCMSTB_WKTMR=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_GENERIC_PHY=y
+CONFIG_EXT4_FS=y
+CONFIG_JBD2_DEBUG=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_CRAMFS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_DEBUG_FS=y
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_BRCMSTB_UART=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/bruno_gfhd300_defconfig b/arch/arm/configs/bruno_gfhd300_defconfig
new file mode 100644
index 0000000..53a9830
--- /dev/null
+++ b/arch/arm/configs/bruno_gfhd300_defconfig
@@ -0,0 +1,211 @@
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_IRQ_TIME_ACCOUNTING=y
+CONFIG_LOG_BUF_SHIFT=16
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_ARCH_BCM=y
+CONFIG_ARCH_BRCMSTB=y
+CONFIG_ARM_LPAE=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_SMP=y
+CONFIG_ARM_PSCI=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+CONFIG_HIGHPTE=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_CMA=y
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_KEXEC=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_CPU_IDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_INET_UDP_DIAG=y
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_DMA_CMA=y
+CONFIG_CMA_ALIGNMENT=12
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_PROC_DEVICETREE=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=8192
+CONFIG_EEPROM_93CX6=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_SATA_BRCMSTB=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ADAPTEC is not set
+# CONFIG_NET_VENDOR_ALTEON is not set
+# CONFIG_NET_VENDOR_AMD is not set
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_VENDOR_ATHEROS is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROCADE is not set
+# CONFIG_NET_VENDOR_CHELSIO is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_CISCO is not set
+# CONFIG_NET_VENDOR_DEC is not set
+# CONFIG_NET_VENDOR_DLINK is not set
+# CONFIG_NET_VENDOR_EMULEX is not set
+# CONFIG_NET_VENDOR_EXAR is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HP is not set
+CONFIG_E1000E=y
+# CONFIG_NET_VENDOR_MARVELL is not set
+# CONFIG_NET_VENDOR_MELLANOX is not set
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_MICROCHIP is not set
+# CONFIG_NET_VENDOR_MYRI is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_NVIDIA is not set
+# CONFIG_NET_VENDOR_OKI is not set
+# CONFIG_NET_PACKET_ENGINE is not set
+# CONFIG_NET_VENDOR_QLOGIC is not set
+# CONFIG_NET_VENDOR_REALTEK is not set
+# CONFIG_NET_VENDOR_RDC is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SILAN is not set
+# CONFIG_NET_VENDOR_SIS is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_SUN is not set
+# CONFIG_NET_VENDOR_TEHUTI is not set
+# CONFIG_NET_VENDOR_TI is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_USB_NET_NET1080 is not set
+# CONFIG_USB_NET_CDC_SUBSET is not set
+# CONFIG_USB_NET_ZAURUS is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_MOUSE_PS2_ELANTECH=y
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_MPU3050=y
+CONFIG_INPUT_UINPUT=y
+# CONFIG_SERIO_SERPORT is not set
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_SPI=y
+CONFIG_SPI_BITBANG=y
+CONFIG_POWER_SUPPLY=y
+CONFIG_POWER_RESET=y
+# CONFIG_HWMON is not set
+CONFIG_THERMAL=y
+CONFIG_CPU_THERMAL=y
+CONFIG_MEDIA_SUPPORT=y
+CONFIG_MEDIA_CAMERA_SUPPORT=y
+CONFIG_MEDIA_USB_SUPPORT=y
+CONFIG_USB_GSPCA=y
+# CONFIG_VGA_ARB is not set
+CONFIG_SOUND=y
+CONFIG_SND=y
+CONFIG_SND_SOC=y
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_OHCI_HCD=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RESET_CONTROLLER=y
+CONFIG_GENERIC_PHY=y
+CONFIG_EXT4_FS=y
+CONFIG_JBD2_DEBUG=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_INFO_REDUCED=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_BRCMSTB_UART=y
+CONFIG_EARLY_PRINTK=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
+# CONFIG_CRYPTO_HW is not set
+CONFIG_CRC_CCITT=y
diff --git a/arch/arm/configs/gfch100_defconfig b/arch/arm/configs/gfch100_defconfig
new file mode 100644
index 0000000..87bc262
--- /dev/null
+++ b/arch/arm/configs/gfch100_defconfig
@@ -0,0 +1,302 @@
+CONFIG_SYSVIPC=y
+CONFIG_FHANDLE=y
+CONFIG_IRQ_DOMAIN_DEBUG=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+CONFIG_PRINTK_PERSIST=y
+CONFIG_PERF_EVENTS=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_ARCH_MVEBU=y
+CONFIG_MACH_ARMADA_370=y
+CONFIG_MACH_ARMADA_375=y
+CONFIG_MACH_ARMADA_38X=y
+CONFIG_MACH_ARMADA_39X=y
+CONFIG_MACH_ARMADA_XP=y
+CONFIG_MACH_DOVE=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_MVEBU=y
+CONFIG_SMP=y
+CONFIG_AEABI=y
+CONFIG_HIGHMEM=y
+# CONFIG_COMPACTION is not set
+CONFIG_ZBOOT_ROM_TEXT=0x0
+CONFIG_ZBOOT_ROM_BSS=0x0
+CONFIG_ARM_APPENDED_DTB=y
+CONFIG_ARM_ATAG_DTB_COMPAT=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPUFREQ_DT=y
+CONFIG_CPU_IDLE=y
+CONFIG_ARM_MVEBU_V7_CPUIDLE=y
+CONFIG_VFP=y
+CONFIG_NEON=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_SYN_COOKIES=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET6_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET6_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET6_XFRM_MODE_BEET is not set
+# CONFIG_IPV6_SIT is not set
+CONFIG_NETFILTER=y
+CONFIG_BRIDGE_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HL=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_NETMAP=m
+CONFIG_NETFILTER_XT_TARGET_REDIRECT=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ECN=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_HL=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_NAT=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_RAW=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_IP6_NF_IPTABLES=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_NAT=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFB=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_MQPRIO=m
+CONFIG_NET_SCH_CHOKE=m
+CONFIG_NET_SCH_QFQ=m
+CONFIG_NET_SCH_CODEL=y
+CONFIG_NET_SCH_FQ_CODEL=y
+CONFIG_NET_SCH_FQ=m
+CONFIG_NET_SCH_HHF=m
+CONFIG_NET_SCH_PIE=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_PKTGEN=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_PHYSMAP_OF=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND_PXA3xx=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_EEPROM_AT24=m
+CONFIG_BLK_DEV_SD=y
+CONFIG_ATA=y
+CONFIG_AHCI_MVEBU=y
+CONFIG_SATA_MV=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_DEBUG=y
+CONFIG_DM_VERITY=y
+CONFIG_NETDEVICES=y
+# CONFIG_NET_VENDOR_ARC is not set
+# CONFIG_NET_CADENCE is not set
+# CONFIG_NET_VENDOR_BROADCOM is not set
+# CONFIG_NET_VENDOR_CIRRUS is not set
+# CONFIG_NET_VENDOR_FARADAY is not set
+# CONFIG_NET_VENDOR_HISILICON is not set
+# CONFIG_NET_VENDOR_INTEL is not set
+CONFIG_MV643XX_ETH=y
+CONFIG_MVNETA=y
+CONFIG_MVPP2=y
+# CONFIG_NET_VENDOR_MICREL is not set
+# CONFIG_NET_VENDOR_NATSEMI is not set
+# CONFIG_NET_VENDOR_QUALCOMM is not set
+# CONFIG_NET_VENDOR_ROCKER is not set
+# CONFIG_NET_VENDOR_SAMSUNG is not set
+# CONFIG_NET_VENDOR_SEEQ is not set
+# CONFIG_NET_VENDOR_SMSC is not set
+# CONFIG_NET_VENDOR_STMICRO is not set
+# CONFIG_NET_VENDOR_VIA is not set
+# CONFIG_NET_VENDOR_WIZNET is not set
+CONFIG_MARVELL_PHY=y
+# CONFIG_INPUT_MOUSEDEV is not set
+CONFIG_INPUT_EVDEV=y
+CONFIG_KEYBOARD_GPIO=y
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_OF_PLATFORM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_MUX=m
+CONFIG_I2C_MUX_PCA954x=m
+CONFIG_I2C_MV64XXX=y
+CONFIG_SPI=y
+CONFIG_SPI_GPIO=y
+CONFIG_SPI_ORION=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_PCA953X=m
+CONFIG_SENSORS_GPIO_FAN=y
+CONFIG_SENSORS_LTC2990=m
+CONFIG_SENSORS_TMP421=m
+CONFIG_THERMAL=y
+CONFIG_ARMADA_THERMAL=y
+CONFIG_WATCHDOG=y
+CONFIG_ORION_WATCHDOG=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_MVEBU=y
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+CONFIG_USB_ACM=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_SIMPLE=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_KEYSPAN=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=16
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_DOVE=y
+CONFIG_MMC_SDHCI_PXAV3=y
+CONFIG_MMC_MVSDIO=y
+CONFIG_RTC_CLASS=y
+CONFIG_RTC_DRV_S35390A=y
+CONFIG_RTC_DRV_MV=y
+CONFIG_RTC_DRV_ARMADA38X=y
+CONFIG_DMADEVICES=y
+CONFIG_MV_XOR=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_MEMORY=y
+CONFIG_EXT4_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=m
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_NFS_FS=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_850=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_NLS_ISO8859_2=y
+CONFIG_NLS_UTF8=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_FS=y
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=30
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_PANIC_TIMEOUT=3
+# CONFIG_SCHED_DEBUG is not set
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_USER=y
+CONFIG_DEBUG_LL=y
+CONFIG_DEBUG_UART_PHYS=0xf1012000
+CONFIG_EARLY_PRINTK=y
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_SHA256=y
diff --git a/arch/arm/include/asm/bug.h b/arch/arm/include/asm/bug.h
index e7335a9..196b0df 100644
--- a/arch/arm/include/asm/bug.h
+++ b/arch/arm/include/asm/bug.h
@@ -5,8 +5,6 @@
 #include <linux/types.h>
 #include <asm/opcodes.h>
 
-#ifdef CONFIG_BUG
-
 /*
  * Use a suitable undefined instruction to use for ARM/Thumb2 bug handling.
  * We need to be careful not to conflict with those used by other modules and
@@ -57,7 +55,6 @@
 #endif  /* CONFIG_DEBUG_BUGVERBOSE */
 
 #define HAVE_ARCH_BUG
-#endif  /* CONFIG_BUG */
 
 #include <asm-generic/bug.h>
 
diff --git a/arch/arm/include/asm/cacheflush.h b/arch/arm/include/asm/cacheflush.h
index d5525bf..63a59d1 100644
--- a/arch/arm/include/asm/cacheflush.h
+++ b/arch/arm/include/asm/cacheflush.h
@@ -195,7 +195,7 @@
  */
 #if (defined(CONFIG_CPU_V7) && \
      (defined(CONFIG_CPU_V6) || defined(CONFIG_CPU_V6K))) || \
-	defined(CONFIG_SMP_ON_UP)
+	defined(CONFIG_SMP_ON_UP) || defined(CONFIG_CACHE_B15_RAC)
 #define __flush_icache_preferred	__cpuc_flush_icache_all
 #elif __LINUX_ARM_ARCH__ >= 7 && defined(CONFIG_SMP)
 #define __flush_icache_preferred	__flush_icache_all_v7_smp
diff --git a/arch/arm/include/asm/glue-cache.h b/arch/arm/include/asm/glue-cache.h
index cab07f6..8fd8cf5 100644
--- a/arch/arm/include/asm/glue-cache.h
+++ b/arch/arm/include/asm/glue-cache.h
@@ -117,6 +117,10 @@
 # endif
 #endif
 
+#if defined(CONFIG_CACHE_B15_RAC)
+# define MULTI_CACHE 1
+#endif
+
 #if defined(CONFIG_CPU_V7M)
 # ifdef _CACHE
 #  define MULTI_CACHE 1
diff --git a/arch/arm/include/asm/hardware/cache-b15-rac.h b/arch/arm/include/asm/hardware/cache-b15-rac.h
new file mode 100644
index 0000000..76b888f
--- /dev/null
+++ b/arch/arm/include/asm/hardware/cache-b15-rac.h
@@ -0,0 +1,12 @@
+#ifndef __ASM_ARM_HARDWARE_CACHE_B15_RAC_H
+#define __ASM_ARM_HARDWARE_CACHE_B15_RAC_H
+
+#ifndef __ASSEMBLY__
+
+void b15_flush_kern_cache_all(void);
+void b15_flush_kern_cache_louis(void);
+void b15_flush_icache_all(void);
+
+#endif
+
+#endif
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 04286fd..48c07ad 100644
--- a/arch/arm/kernel/head.S
+++ b/arch/arm/kernel/head.S
@@ -248,6 +248,10 @@
 	ldr	r6, =(_end - 1)
 	orr	r3, r8, r7
 	add	r6, r4, r6, lsr #(SECTION_SHIFT - PMD_ORDER)
+#ifdef CONFIG_BRCMSTB
+	/* map a 1MB section after the kernel in case the DTB is copied there */
+	add	r6, #4
+#endif
 1:	str	r3, [r0], #1 << PMD_ORDER
 	add	r3, r3, #1 << SECTION_SHIFT
 	cmp	r0, r6
diff --git a/arch/arm/kernel/iwmmxt.S b/arch/arm/kernel/iwmmxt.S
index 49fadbd..fc050e7 100644
--- a/arch/arm/kernel/iwmmxt.S
+++ b/arch/arm/kernel/iwmmxt.S
@@ -145,6 +145,9 @@
 	wstrd	wR15, [r1, #MMX_WR15]
 
 2:	teq	r0, #0				@ anything to load?
+	/* TODO(jnewlin): brcm has here:
+	 * beq 3f
+	 */
 	reteq	lr				@ if not, return
 
 concan_load:
@@ -178,9 +181,19 @@
 	@ clear CUP/MUP (only if r1 != 0)
 	teq	r1, #0
 	mov 	r2, #0
+	/* TODO(jnewlin): brcm has here:
+	 * beq 3f
+	 */
 	reteq	lr
 
 	tmcr	wCon, r2
+	/* TODO(jnewlin): brcm has here:
++3:		
++#ifdef CONFIG_PREEMPT_COUNT
++	get_thread_info r10
++#endif
++4:	dec_preempt_count r10, r3
+		*/
 	ret	lr
 
 ENDPROC(iwmmxt_task_enable)
diff --git a/arch/arm/mach-bcm/Kconfig b/arch/arm/mach-bcm/Kconfig
index 8c53c55..d3c42e7 100644
--- a/arch/arm/mach-bcm/Kconfig
+++ b/arch/arm/mach-bcm/Kconfig
@@ -153,10 +153,21 @@
 
 config ARCH_BRCMSTB
 	bool "Broadcom BCM7XXX based boards" if ARCH_MULTI_V7
+	depends on MMU
 	select ARM_GIC
 	select ARM_ERRATA_798181 if SMP
+	select MIGHT_HAVE_PCI
+	select HAVE_SMP
 	select HAVE_ARM_ARCH_TIMER
+	select POWER_RESET_BRCMSTB
+	select BRCMSTB
+	select ARCH_HAS_OPP
+	select ARCH_HAS_CPUFREQ
+	select PM_OPP if PM
+	select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
+	select GENERIC_IRQ_CHIP
 	select BRCMSTB_GISB_ARB
+	select NEED_MACH_MEMORY_H
 	select BRCMSTB_L2_IRQ
 	select BCM7120_L2_IRQ
 	select ARCH_DMA_ADDR_T_64BIT if ARM_LPAE
@@ -170,3 +181,327 @@
 	  including the 7445 family of chips.
 
 endif
+
+choice
+	prompt "Chipset selection"
+	depends on BRCMSTB
+	help
+	  Select the Broadcom STB chipset you are building for.
+
+config BCM3390A0
+	bool "3390 Ax"
+	select BCM7145
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_MSPI_64B_WORDS
+
+config BCM7145B0
+	bool "7145 Bx"
+	select BCM7145
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_MSPI_64B_WORDS
+
+config BCM7250B0
+	bool "7250 Bx"
+	select BCM7250
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_MSPI_64B_WORDS
+	select BRCMSTB_XPT_HASH if PM
+
+config BCM7364A0
+	bool "7364 Ax"
+	select BCM7364
+	select BRCM_GENET_V4
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_MSPI_64B_WORDS
+	select BRCMSTB_XPT_HASH if PM
+
+config BCM7366C0
+	bool "7366 Cx"
+	select BCM7366
+	select BRCM_GENET_V4
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_MSPI_64B_WORDS
+	select BRCMSTB_XPT_HASH if PM
+
+config BCM74371A0
+	bool "74371 Ax"
+	select BCM74371
+	select BRCM_GENET_V4
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_0
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_MSPI_64B_WORDS
+
+config BCM7439B0
+	bool "7439 Bx"
+	select BCM7439
+	select BRCM_GENET_V4
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_MSPI_64B_WORDS
+	select BRCMSTB_XPT_HASH if PM
+
+config BCM7445D0
+	bool "7445 Dx"
+	select BCM7445
+	select BRCM_GENET_V4
+	select BRCM_HAS_MOCA_20_GEN23
+	select BRCM_HAS_NAND_MAJOR_7
+	select BRCM_HAS_NAND_MINOR_1
+	select BRCM_HAS_BSPI_V4
+	select BRCM_MSPI_64B_WORDS
+	select BRCMSTB_XPT_HASH if PM
+
+endchoice
+
+config SPI_BRCMSTB
+	tristate "Broadcom HIF SPI controller support"
+	default y
+	depends on BRCMSTB
+	help
+	  Say Y to enable support for SPI (serial) flash devices.
+
+config BCMGENET
+	tristate "Broadcom STB 10/100/1000 MAC/PHY support"
+	depends on ETHERNET && BRCMSTB
+	default y
+	select CRC32
+	select MII
+	select PHYLIB
+	select FIXED_PHY
+	select BCM7XXX_PHY
+	select BCM531XX_PHY
+	help
+	  Say Y to support the internal 10/100/1000 GENET MAC/PHY on
+	  Broadcom set-top chips.  This driver also supports the datapath
+	  for the onchip MoCA transceiver.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+config BRCM_MOCA
+	tristate "Broadcom MoCA character driver"
+	depends on BRCMSTB && (BRCM_HAS_GENET || BRCM_HAS_MOCA_20_GEN21 || \
+		BRCM_HAS_MOCA_20_GEN22 || BRCM_HAS_MOCA_20_GEN23) && !BRCM_IKOS
+	default y
+	help
+	  Say Y to build the MoCA control path driver.  This is a simple
+	  character driver that allows the MoCA daemon (mocad) to
+	  initialize and configure the MoCA interface.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+config BRCM_USB
+	tristate "Broadcom STB USB support"
+	depends on BRCMSTB && USB
+	select BRCM_USB_OHCI if USB_OHCI_HCD
+	select BRCM_USB_EHCI if USB_EHCI_HCD
+	select BRCM_USB_XHCI if USB_XHCI_HCD
+	default y
+	help
+	  Say Y to enable the drivers for the onchip USB controllers.
+
+	  If your chipset supports power management, disabling this driver
+	  will keep the device permanently powered down.
+
+
+config MTD_NAND_BRCMSTB
+	tristate "Broadcom NAND controller support"
+	default y
+	depends on OF && OF_MTD
+	select MTD_NAND
+	help
+	  Say Y to enable the onchip NAND controller.
+
+config BRCM_SDIO
+	tristate "Broadcom SDHCI (SDIO) support"
+	depends on BRCMSTB && MMC_SDHCI
+	default y
+	select MMC_SDHCI_IO_ACCESSORS
+	help
+	  Say Y to enable the driver for the onchip SDIO controller.
+
+	  If you do not plan on using this device, disabling CONFIG_MMC
+	  will save about 75KB.
+
+	  If unsure, say Y.
+
+#####################################################################
+# Hidden options
+#####################################################################
+
+config BRCMSTB
+	bool
+
+config BCM7145
+	bool
+
+config BCM7250
+	bool
+
+config BCM7364
+	bool
+
+config BCM7366
+	bool
+
+config BCM74371
+	bool
+
+config BCM7439
+	bool
+
+config BCM7445
+	bool
+
+config BRCM_GENET_V3
+	bool
+
+config BRCM_GENET_V4
+	bool
+
+config BRCM_GENET_VERSION
+	int
+	default 3 if BRCM_GENET_V3
+	default 4 if BRCM_GENET_V4
+
+# MoCA controller
+config BRCM_HAS_MOCA
+	bool
+
+# Original MoCA 1.1 (gen1 firmware)
+config BRCM_HAS_MOCA_11
+	bool
+	select BRCM_HAS_MOCA
+
+# Cost-reduced MoCA 1.1 with limited TX RAM (gen1 firmware)
+config BRCM_HAS_MOCA_11_LITE
+	bool
+	select BRCM_HAS_MOCA
+
+# MoCA 1.1 with selected 2.0 features (gen2 firmware)
+config BRCM_HAS_MOCA_11_PLUS
+	bool
+	select BRCM_HAS_MOCA
+
+# MoCA 2.0 (gen3 firmware for 1.1, gen2x firmware for 2.0)
+config BRCM_HAS_MOCA_20_GEN21
+	bool
+	select BRCM_HAS_MOCA
+
+config BRCM_HAS_MOCA_20_GEN22
+	bool
+	select BRCM_HAS_MOCA
+
+config BRCM_HAS_MOCA_20_GEN23
+	bool
+	select BRCM_HAS_MOCA
+
+config BRCM_MOCA_VERS
+	hex
+	default 0x1100 if BRCM_HAS_MOCA_11
+	default 0x1101 if BRCM_HAS_MOCA_11_LITE
+	default 0x1102 if BRCM_HAS_MOCA_11_PLUS
+	default 0x2001 if BRCM_HAS_MOCA_20_GEN21
+	default 0x2002 if BRCM_HAS_MOCA_20_GEN22
+	default 0x2003 if BRCM_HAS_MOCA_20_GEN23
+
+# select for MoCA on GENET_0
+config BRCM_MOCA_ON_GENET_0
+	bool
+	select BRCM_HAS_GENET_0
+
+# select for MoCA on GENET_1
+config BRCM_MOCA_ON_GENET_1
+	bool
+	select BRCM_HAS_GENET_1
+
+# MoCA is MidRF (default is HighRF)
+config BRCM_HAS_MOCA_MIDRF
+	bool
+
+config BRCM_HAS_NAND_MINOR_0
+	bool
+
+config BRCM_HAS_NAND_MINOR_1
+	bool
+
+config BRCM_HAS_NAND_MINOR_2
+	bool
+
+config BRCM_HAS_NAND_MINOR_3
+	bool
+
+config BRCM_HAS_NAND_MINOR_4
+	bool
+
+config BRCM_HAS_NAND_MAJOR_5
+	bool
+	select BRCM_HAS_NAND
+
+config BRCM_HAS_NAND_MAJOR_6
+	bool
+	select BRCM_HAS_NAND
+
+config BRCM_HAS_NAND_MAJOR_7
+	bool
+	select BRCM_HAS_NAND
+
+config BRCMNAND_MAJOR_VERS
+	int
+	default "7" if BRCM_HAS_NAND_MAJOR_7
+	default "6" if BRCM_HAS_NAND_MAJOR_6
+	default "5" if BRCM_HAS_NAND_MAJOR_5
+
+config BRCMNAND_MINOR_VERS
+	int
+	default "4" if BRCM_HAS_NAND_MINOR_4
+	default "3" if BRCM_HAS_NAND_MINOR_3
+	default "2" if BRCM_HAS_NAND_MINOR_2
+	default "1" if BRCM_HAS_NAND_MINOR_1
+	default "0" if BRCM_HAS_NAND_MINOR_0
+
+config BRCM_HAS_BSPI_V4
+	bool
+	select BRCM_HAS_SPI
+
+config BRCM_BSPI_MAJOR_VERS
+	int
+	default "4" if BRCM_HAS_BSPI_V4
+	default "3" if BRCM_HAS_BSPI_V3
+	default "2" if BRCM_HAS_BSPI_V2
+
+# For MSPI prior to v1.5 (first version with a revision register)
+config BRCM_MSPI_LEGACY
+	bool
+
+# MSPI can transfer either 64b or 8b per slot
+config BRCM_MSPI_64B_WORDS
+	bool
+
+config BRCM_USB_OHCI
+       tristate
+
+config BRCM_USB_EHCI
+       tristate
+
+config BRCM_USB_XHCI
+       tristate
diff --git a/arch/arm/mach-bcm/Makefile b/arch/arm/mach-bcm/Makefile
index 892261f..e1ce06b 100644
--- a/arch/arm/mach-bcm/Makefile
+++ b/arch/arm/mach-bcm/Makefile
@@ -49,5 +49,6 @@
 ifeq ($(CONFIG_ARCH_BRCMSTB),y)
 CFLAGS_platsmp-brcmstb.o	+= -march=armv7-a
 obj-y				+= brcmstb.o
-obj-$(CONFIG_SMP)		+= platsmp-brcmstb.o
+obj-$(CONFIG_SMP)		+= headsmp-brcmstb.o platsmp-brcmstb.o
+obj-$(CONFIG_PCI)		+= pci-brcmstb.o
 endif
diff --git a/arch/arm/mach-bcm/headsmp-brcmstb.h b/arch/arm/mach-bcm/headsmp-brcmstb.h
new file mode 100644
index 0000000..884a41a
--- /dev/null
+++ b/arch/arm/mach-bcm/headsmp-brcmstb.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation version 2.
+ *
+ * This program is distributed "as is" WITHOUT ANY WARRANTY of any
+ * kind, whether express or implied; without even the implied warranty
+ * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __HEADSMP_BRCMSTB_H__
+#define __HEADSMP_BRCMSTB_H__
+
+#if !defined(__ASSEMBLY__)
+
+extern void brcmstb_secondary_startup(void);
+
+#endif /* !defined(__ASSEMBLY__) */
+
+#endif /* __HEADSMP_BRCMSTB_H__ */
diff --git a/arch/arm/mach-bcm/include/mach/memory.h b/arch/arm/mach-bcm/include/mach/memory.h
new file mode 100644
index 0000000..9ca6c1f
--- /dev/null
+++ b/arch/arm/mach-bcm/include/mach/memory.h
@@ -0,0 +1,12 @@
+/*
+ * arch/arm/mach-bcm/include/mach/memory.h
+ */
+
+#ifndef __ASM_ARCH_MEMORY_H
+#define __ASM_ARCH_MEMORY_H
+
+/* google: Moved from arch/arm/include/asm/sparsemem.h */
+#define MAX_PHYSMEM_BITS        36
+#define SECTION_SIZE_BITS       28
+
+#endif
diff --git a/arch/arm/mach-bcm/pci-brcmstb.c b/arch/arm/mach-bcm/pci-brcmstb.c
new file mode 100644
index 0000000..df20c90
--- /dev/null
+++ b/arch/arm/mach-bcm/pci-brcmstb.c
@@ -0,0 +1,854 @@
+/*
+ * Copyright (C) 2009 - 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/slab.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/compiler.h>
+#include <linux/delay.h>
+#include <linux/io.h>
+#include <linux/clk.h>
+#include <linux/list.h>
+#include <linux/printk.h>
+#include <linux/syscore_ops.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/of_address.h>
+#include <linux/module.h>
+#include <linux/irqdomain.h>
+
+/* Broadcom PCIE Offsets */
+#define PCIE_RC_CFG_PCIE_LINK_CAPABILITY		0x00b8
+#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL		0x00bc
+#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL		0x00c8
+#define PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2		0x00dc
+#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1		0x0188
+#define PCIE_RC_CFG_PRIV1_ID_VAL3			0x043c
+#define PCIE_RC_DL_MDIO_ADDR				0x1100
+#define PCIE_RC_DL_MDIO_WR_DATA				0x1104
+#define PCIE_RC_DL_MDIO_RD_DATA				0x1108
+#define PCIE_MISC_MISC_CTRL				0x4008
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO		0x400c
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI		0x4010
+#define PCIE_MISC_RC_BAR1_CONFIG_LO			0x402c
+#define PCIE_MISC_RC_BAR1_CONFIG_HI			0x4030
+#define PCIE_MISC_RC_BAR2_CONFIG_LO			0x4034
+#define PCIE_MISC_RC_BAR2_CONFIG_HI			0x4038
+#define PCIE_MISC_RC_BAR3_CONFIG_LO			0x403c
+#define PCIE_MISC_RC_BAR3_CONFIG_HI			0x4040
+#define PCIE_MISC_MSI_BAR_CONFIG_LO			0x4044
+#define PCIE_MISC_MSI_BAR_CONFIG_HI			0x4048
+#define PCIE_MISC_PCIE_CTRL				0x4064
+#define PCIE_MISC_PCIE_STATUS				0x4068
+#define PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT	0x4070
+#define PCIE_MISC_HARD_PCIE_HARD_DEBUG			0x4204
+#define PCIE_INTR2_CPU_CLEAR				0x4308
+#define PCIE_INTR2_CPU_MASK_SET				0x4310
+#define PCIE_INTR2_CPU_MASK_CLEAR			0x4314
+#define PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX			0x9000
+#define PCIE_EXT_CFG_PCIE_EXT_CFG_DATA			0x9004
+#define PCIE_RGR1_SW_INIT_1				0x9210
+
+#define BRCM_NUM_PCI_OUT_WINS		0x4
+#define BRCM_MAX_SCB			0x4
+
+#define PCI_BUSNUM_SHIFT		20
+#define PCI_SLOT_SHIFT			15
+#define PCI_FUNC_SHIFT			12
+
+#define IDX_ADDR(base)		((base) + PCIE_EXT_CFG_PCIE_EXT_CFG_INDEX)
+#define DATA_ADDR(base)		((base) + PCIE_EXT_CFG_PCIE_EXT_CFG_DATA)
+
+static int brcm_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+				int where, int size, u32 *data);
+static int brcm_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+				 int where, int size, u32 data);
+
+static struct pci_ops brcm_pci_ops = {
+	.read = brcm_pci_read_config,
+	.write = brcm_pci_write_config,
+};
+
+static int brcm_setup_pcie_bridge(int nr, struct pci_sys_data *sys);
+static int __init brcm_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
+
+static struct hw_pci brcm_pcie_hw __initdata = {
+	.nr_controllers	= 0,
+	.setup		= brcm_setup_pcie_bridge,
+	.map_irq	= brcm_map_irq,
+	.ops		= &brcm_pci_ops,
+};
+
+struct brcm_window {
+	u64 pci_addr;
+	u64 size;
+	u64 cpu_addr;
+	u32 info;
+	struct resource pcie_iomem_res;
+};
+
+
+/* Internal Bus Controller Information.*/
+struct brcm_pcie {
+	struct list_head	list;
+	void __iomem		*base;
+	char			name[8];
+	bool			suspended;
+	struct clk		*clk;
+	struct device_node	*dn;
+	int			pcie_irq[4];
+	int			num_out_wins;
+	bool			ssc;
+	int			gen;
+	int			scb_size_vals[BRCM_MAX_SCB];
+	struct brcm_window	out_wins[BRCM_NUM_PCI_OUT_WINS];
+	struct pci_sys_data	*sys;
+	struct device		*dev;
+};
+
+static struct list_head brcm_pcie;
+static int brcm_num_pci_controllers;
+static int num_memc;
+static void turn_off(void __iomem *base);
+static void enter_l23(struct brcm_pcie *pcie);
+
+
+/***********************************************************************
+ * PCIe Bridge setup
+ ***********************************************************************/
+#if defined(__BIG_ENDIAN)
+#define	DATA_ENDIAN		2	/* PCI->DDR inbound accesses */
+#define MMIO_ENDIAN		2	/* CPU->PCI outbound accesses */
+#else
+#define	DATA_ENDIAN		0
+#define MMIO_ENDIAN		0
+#endif
+
+
+static void remove_pcie(struct brcm_pcie *pcie)
+{
+	struct list_head *pos, *q;
+	struct brcm_pcie *tmp;
+
+	list_for_each_safe(pos, q, &brcm_pcie) {
+		tmp = list_entry(pos, struct brcm_pcie, list);
+		if (tmp == pcie) {
+			list_del(pos);
+			break;
+		}
+	}
+}
+
+
+/* negative return value indicates error */
+static int mdio_read(void __iomem *base, u8 phyad, u8 regad)
+{
+	u32 data = ((phyad & 0xf) << 16)
+		| (regad & 0x1f)
+		| 0x100000;
+
+	__raw_writel(data, base + PCIE_RC_DL_MDIO_ADDR);
+	__raw_readl(base + PCIE_RC_DL_MDIO_ADDR);
+
+	data = __raw_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
+	if (!(data & 0x80000000)) {
+		mdelay(1);
+		data = __raw_readl(base + PCIE_RC_DL_MDIO_RD_DATA);
+	}
+	return (data & 0x80000000) ? (data & 0xffff) : -EIO;
+}
+
+
+/* negative return value indicates error */
+static int mdio_write(void __iomem *base, u8 phyad, u8 regad, u16 wrdata)
+{
+	u32 data = ((phyad & 0xf) << 16) | (regad & 0x1f);
+
+	__raw_writel(data, base + PCIE_RC_DL_MDIO_ADDR);
+	__raw_readl(base + PCIE_RC_DL_MDIO_ADDR);
+
+	__raw_writel(0x80000000 | wrdata, base + PCIE_RC_DL_MDIO_WR_DATA);
+	data = __raw_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
+	if (!(data & 0x80000000)) {
+		mdelay(1);
+		data = __raw_readl(base + PCIE_RC_DL_MDIO_WR_DATA);
+	}
+	return (data & 0x80000000) ? 0 : -EIO;
+}
+
+
+static void wr_fld(void __iomem *p, u32 mask, int shift, u32 val)
+{
+	u32 reg = __raw_readl(p);
+	reg = (reg & ~mask) | (val << shift);
+	__raw_writel(reg, p);
+}
+
+
+static void wr_fld_rb(void __iomem *p, u32 mask, int shift, u32 val)
+{
+	wr_fld(p, mask, shift, val);
+	(void) __raw_readl(p);
+}
+
+
+/* configures device for ssc mode; negative return value indicates error */
+static int set_ssc(void __iomem *base)
+{
+	int tmp;
+	u16 wrdata;
+
+	tmp = mdio_write(base, 0, 0x1f, 0x1100);
+	if (tmp < 0)
+		return tmp;
+
+	tmp = mdio_read(base, 0, 2);
+	if (tmp < 0)
+		return tmp;
+
+	wrdata = ((u16)tmp & 0x3fff) | 0xc000;
+	tmp = mdio_write(base, 0, 2, wrdata);
+	if (tmp < 0)
+		return tmp;
+
+	mdelay(1);
+	tmp = mdio_read(base, 0, 1);
+	if (tmp < 0)
+		return tmp;
+
+	return 0;
+}
+
+
+/* returns 0 if in ssc mode, 1 if not, <0 on error */
+static int is_ssc(void __iomem *base)
+{
+	int tmp = mdio_write(base, 0, 0x1f, 0x1100);
+	if (tmp < 0)
+		return tmp;
+	tmp = mdio_read(base, 0, 1);
+	if (tmp < 0)
+		return tmp;
+	return (tmp & 0xc00) == 0xc00 ? 0 : 1;
+}
+
+
+/* limits operation to a specific generation (1, 2, or 3) */
+static void set_gen(void __iomem *base, int gen)
+{
+	wr_fld(base + PCIE_RC_CFG_PCIE_LINK_CAPABILITY, 0xf, 0, gen);
+	wr_fld(base + PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL_2, 0xf, 0, gen);
+}
+
+
+static void set_pcie_outbound_win(void __iomem *base, unsigned win, u64 start,
+				  u64 len)
+{
+	u32 tmp;
+
+	__raw_writel((u32)(start) + MMIO_ENDIAN,
+		     base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_LO+(win*8));
+	__raw_writel((u32)(start >> 32),
+		     base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_HI+(win*8));
+	tmp = ((((u32)start) >> 20) << 4)
+		| (((((u32)start) + ((u32)len) - 1) >> 20) << 20);
+	__raw_writel(tmp,
+		     base + PCIE_MISC_CPU_2_PCIE_MEM_WIN0_BASE_LIMIT+(win*4));
+}
+
+
+static int is_pcie_link_up(struct brcm_pcie *pcie)
+{
+	void __iomem *base = pcie->base;
+	u32 val = __raw_readl(base + PCIE_MISC_PCIE_STATUS);
+	return  ((val & 0x30) == 0x30) ? 1 : 0;
+}
+
+
+static void brcm_pcie_setup_early(struct brcm_pcie *pcie)
+{
+	void __iomem *base = pcie->base;
+	unsigned int scb_size_val;
+	int i;
+
+	/* reset the bridge and the endpoint device */
+	/* field: PCIE_BRIDGE_SW_INIT = 1 */
+	wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000002, 1, 1);
+	/* field: PCIE_SW_PERST = 1 */
+	wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000001, 0, 1);
+
+	/* delay 100us */
+	udelay(100);
+
+	/* take the bridge out of reset */
+	/* field: PCIE_BRIDGE_SW_INIT = 0 */
+	wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000002, 1, 0);
+
+	/* enable SCB_MAX_BURST_SIZE | CSR_READ_UR_MODE | SCB_ACCESS_EN */
+	__raw_writel(0x81e03000, base + PCIE_MISC_MISC_CTRL);
+
+	for (i = 0; i < pcie->num_out_wins; i++) {
+		struct brcm_window *w = &pcie->out_wins[i];
+		set_pcie_outbound_win(base, i, w->cpu_addr, w->size);
+	}
+
+	/* set up 4GB PCIE->SCB memory window on BAR2 */
+	__raw_writel(0x00000011, base + PCIE_MISC_RC_BAR2_CONFIG_LO);
+	__raw_writel(0x00000000, base + PCIE_MISC_RC_BAR2_CONFIG_HI);
+
+	/* field: SCB0_SIZE, default = 0xf (1 GB) */
+	scb_size_val = pcie->scb_size_vals[0] ? pcie->scb_size_vals[0] : 0xf;
+	wr_fld(base + PCIE_MISC_MISC_CTRL, 0xf8000000, 27, scb_size_val);
+
+	/* field: SCB1_SIZE, default = 0xf (1 GB) */
+	if (num_memc > 1) {
+		scb_size_val = pcie->scb_size_vals[1]
+			? pcie->scb_size_vals[1] : 0xf;
+		wr_fld(base + PCIE_MISC_MISC_CTRL, 0x07c00000,
+		       22, scb_size_val);
+	}
+
+	/* field: SCB2_SIZE, default = 0xf (1 GB) */
+	if (num_memc > 2) {
+		scb_size_val = pcie->scb_size_vals[2]
+			? pcie->scb_size_vals[2] : 0xf;
+		wr_fld(base + PCIE_MISC_MISC_CTRL, 0x0000001f,
+		       0, scb_size_val);
+	}
+
+	/* disable the PCIE->GISB memory window */
+	__raw_writel(0x00000000, base + PCIE_MISC_RC_BAR1_CONFIG_LO);
+
+	/* disable the PCIE->SCB memory window */
+	__raw_writel(0x00000000, base + PCIE_MISC_RC_BAR3_CONFIG_LO);
+
+	/* disable MSI (for now...) */
+	__raw_writel(0x00000000, base + PCIE_MISC_MSI_BAR_CONFIG_LO);
+
+	/* set up L2 interrupt masks */
+	__raw_writel(0x00000000, base + PCIE_INTR2_CPU_CLEAR);
+	(void) __raw_readl(base + PCIE_INTR2_CPU_CLEAR);
+	__raw_writel(0x00000000, base + PCIE_INTR2_CPU_MASK_CLEAR);
+	(void) __raw_readl(base + PCIE_INTR2_CPU_MASK_CLEAR);
+	__raw_writel(0xffffffff, base + PCIE_INTR2_CPU_MASK_SET);
+	(void) __raw_readl(base + PCIE_INTR2_CPU_MASK_SET);
+
+	if (pcie->ssc)
+		if (set_ssc(base))
+			dev_err(pcie->dev, "error while configuring ssc mode\n");
+	if (pcie->gen)
+		set_gen(base, pcie->gen);
+
+	/* take the EP device out of reset */
+	/* field: PCIE_SW_PERST = 0 */
+	wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000001, 0, 0);
+}
+
+
+static int brcm_setup_pcie_bridge(int nr, struct pci_sys_data *sys)
+{
+	struct brcm_pcie *pcie = sys->private_data;
+	void __iomem *base = pcie->base;
+	const int limit = pcie->suspended ? 1000 : 100;
+	struct clk *clk;
+	unsigned status;
+	static const char *link_speed[4] = { "???", "2.5", "5.0", "8.0" };
+	int i, j;
+
+	pcie->sys = sys;
+
+	/* Give the RC/EP time to wake up, before trying to configure RC.
+	 * Intermittently check status for link-up, up to a total of 100ms
+	 * when we don't know if the device is there, and up to 1000ms if
+	 * we do know the device is there. */
+	for (i = 1, j = 0; j < limit && !is_pcie_link_up(pcie); j += i, i = i*2)
+		mdelay(i + j > limit ? limit - j : i);
+
+	if (!is_pcie_link_up(pcie)) {
+		dev_info(pcie->dev, "link down\n");
+		goto FAIL;
+	}
+
+	/* For config space accesses on the RC, show the right class for
+	 * a PCI-PCI bridge */
+	wr_fld_rb(base + PCIE_RC_CFG_PRIV1_ID_VAL3, 0x00ffffff, 0, 0x060400);
+
+	if (!pcie->suspended)
+		for (i = 0; i < pcie->num_out_wins; i++)
+			pci_add_resource_offset(&sys->resources,
+					&pcie->out_wins[i].pcie_iomem_res,
+					sys->mem_offset);
+
+	status = __raw_readl(base + PCIE_RC_CFG_PCIE_LINK_STATUS_CONTROL);
+	dev_info(pcie->dev, "link up, %s Gbps x%u\n",
+		 link_speed[((status & 0x000f0000) >> 16) & 0x3],
+		 (status & 0x03f00000) >> 20);
+
+	if (pcie->ssc && is_ssc(base) != 0)
+		dev_err(pcie->dev, "failed to enter ssc mode\n");
+
+	/* Enable configuration request retry (see pci_scan_device()) */
+	/* field RC_CRS_EN = 1 */
+	wr_fld(base + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL, 0x00000010, 4, 1);
+
+	/* PCIE->SCB endian mode for BAR */
+	/* field ENDIAN_MODE_BAR2 = DATA_ENDIAN */
+	wr_fld_rb(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1, 0x0000000c, 2,
+		  DATA_ENDIAN);
+
+	/* Refclk from RC should be gated with CLKREQ# input when ASPM L0s,L1
+	 * is enabled =>  setting the CLKREQ_DEBUG_ENABLE field to 1. */
+	wr_fld_rb(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, 0x00000002, 1, 1);
+
+	return 1;
+FAIL:
+	if (IS_ENABLED(CONFIG_PM))
+		turn_off(base);
+
+	clk = pcie->clk;
+	if (pcie->suspended)
+		clk_disable(clk);
+	else {
+		clk_disable_unprepare(clk);
+		clk_put(clk);
+		remove_pcie(pcie);
+	}
+	return 0;
+
+}
+
+
+/*
+ * syscore device to handle PCIe bus suspend and resume
+ */
+
+static void turn_off(void __iomem *base)
+{
+	/* Reset endpoint device */
+	wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000001, 0, 1);
+	/* deassert request for L23 in case it was asserted */
+	wr_fld_rb(base + PCIE_MISC_PCIE_CTRL, 0x1, 0, 0);
+	/* SERDES_IDDQ = 1 */
+	wr_fld_rb(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, 0x08000000,
+		  27, 1);
+	/* Shutdown PCIe bridge */
+	wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000002, 1, 1);
+}
+
+
+static void enter_l23(struct brcm_pcie *pcie)
+{
+	void __iomem *base = pcie->base;
+	int timeout = 1000;
+	int l23;
+
+	/* assert request for L23 */
+	wr_fld_rb(base + PCIE_MISC_PCIE_CTRL, 0x1, 0, 1);
+	do {
+		/* poll L23 status */
+		l23 = __raw_readl(base + PCIE_MISC_PCIE_STATUS) & (1 << 6);
+	} while (--timeout && !l23);
+
+	if (!timeout)
+		dev_err(pcie->dev, "failed to enter L23\n");
+}
+
+
+static int pcie_suspend(void)
+{
+	struct brcm_pcie *pcie;
+
+	list_for_each_entry(pcie, &brcm_pcie, list) {
+		enter_l23(pcie);
+		turn_off(pcie->base);
+		clk_disable(pcie->clk);
+		pcie->suspended = true;
+	}
+	return 0;
+}
+
+
+static void pcie_resume(void)
+{
+	int i = 0;
+	struct brcm_pcie *pcie;
+
+	list_for_each_entry(pcie, &brcm_pcie, list) {
+		void __iomem *base;
+
+		base = pcie->base;
+		clk_enable(pcie->clk);
+
+		/* Take bridge out of reset so we can access the SERDES reg */
+		wr_fld_rb(base + PCIE_RGR1_SW_INIT_1, 0x00000002, 1, 0);
+
+		/* SERDES_IDDQ = 0 */
+		wr_fld_rb(base + PCIE_MISC_HARD_PCIE_HARD_DEBUG, 0x08000000,
+			  27, 0);
+		/* wait for serdes to be stable */
+		udelay(100);
+
+		brcm_pcie_setup_early(pcie);
+	}
+
+	list_for_each_entry(pcie, &brcm_pcie, list) {
+		brcm_setup_pcie_bridge(i++, pcie->sys);
+		pcie->suspended = false;
+	}
+}
+
+static struct syscore_ops pcie_pm_ops = {
+	.suspend        = pcie_suspend,
+	.resume         = pcie_resume,
+};
+
+
+/***********************************************************************
+ * Read/write PCI configuration registers
+ ***********************************************************************/
+static int cfg_index(int busnr, int devfn, int reg)
+{
+	return ((PCI_SLOT(devfn) & 0x1f) << PCI_SLOT_SHIFT)
+		| ((PCI_FUNC(devfn) & 0x07) << PCI_FUNC_SHIFT)
+		| (busnr << PCI_BUSNUM_SHIFT)
+		| (reg & ~3);
+}
+
+static u32 read_config(void __iomem *base, int cfg_idx)
+{
+	__raw_writel(cfg_idx, IDX_ADDR(base));
+	__raw_readl(IDX_ADDR(base));
+	return __raw_readl(DATA_ADDR(base));
+}
+
+static void write_config(void __iomem *base, int cfg_idx, u32 val)
+{
+	__raw_writel(cfg_idx, IDX_ADDR(base));
+	__raw_readl(IDX_ADDR(base));
+	__raw_writel(val, DATA_ADDR(base));
+	__raw_readl(DATA_ADDR(base));
+}
+
+
+static int brcm_pci_write_config(struct pci_bus *bus, unsigned int devfn,
+				 int where, int size, u32 data)
+{
+	u32 val = 0, mask, shift;
+	struct pci_sys_data *sys = bus->sysdata;
+	struct brcm_pcie *pcie = sys->private_data;
+	void __iomem *base;
+	bool rc_access;
+	int idx;
+
+	if (!is_pcie_link_up(pcie))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	base = pcie->base;
+	rc_access = sys->busnr == bus->number;
+	idx = cfg_index(bus->number, devfn, where);
+	BUG_ON(((where & 3) + size) > 4);
+
+	if (rc_access && PCI_SLOT(devfn))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	if (size < 4) {
+		/* partial word - read, modify, write */
+		if (rc_access)
+			val = __raw_readl(base + (where & ~3));
+		else
+			val = read_config(base, idx);
+	}
+
+	shift = (where & 3) << 3;
+	mask = (0xffffffff >> ((4 - size) << 3)) << shift;
+	val = (val & ~mask) | ((data << shift) & mask);
+
+	if (rc_access) {
+		__raw_writel(val, base + (where & ~3));
+		__raw_readl(base + (where & ~3));
+	} else {
+		write_config(base, idx, val);
+	}
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+static int brcm_pci_read_config(struct pci_bus *bus, unsigned int devfn,
+				int where, int size, u32 *data)
+{
+	struct pci_sys_data *sys = bus->sysdata;
+	struct brcm_pcie *pcie = sys->private_data;
+	u32 val, mask, shift;
+	void __iomem *base;
+	bool rc_access;
+	int idx;
+
+	if (!is_pcie_link_up(pcie))
+		return PCIBIOS_DEVICE_NOT_FOUND;
+
+	base = pcie->base;
+	rc_access = sys->busnr == bus->number;
+	idx = cfg_index(bus->number, devfn, where);
+	BUG_ON(((where & 3) + size) > 4);
+
+	if (rc_access && PCI_SLOT(devfn)) {
+		*data = 0xffffffff;
+		return PCIBIOS_FUNC_NOT_SUPPORTED;
+	}
+
+	if (rc_access)
+		val = __raw_readl(base + (where & ~3));
+	else
+		val = read_config(base, idx);
+
+	shift = (where & 3) << 3;
+	mask = (0xffffffff >> ((4 - size) << 3)) << shift;
+	*data = (val & mask) >> shift;
+
+	return PCIBIOS_SUCCESSFUL;
+}
+
+
+
+
+/***********************************************************************
+ * PCI slot to IRQ mappings (aka "fixup")
+ ***********************************************************************/
+static int __init brcm_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
+{
+	struct pci_sys_data *sys = dev->bus->sysdata;
+	struct brcm_pcie *pcie = sys->private_data;
+
+	if (pcie) {
+		if ((pin - 1) > 3)
+			return 0;
+		return pcie->pcie_irq[pin - 1];
+	}
+	return 0;
+}
+
+
+/***********************************************************************
+ * Per-device initialization
+ ***********************************************************************/
+static void __attribute__((__section__("pci_fixup_early")))
+brcm_pcibios_fixup(struct pci_dev *dev)
+{
+	struct pci_sys_data *sys = dev->bus->sysdata;
+	struct brcm_pcie *pcie = sys->private_data;
+	int slot = PCI_SLOT(dev->devfn);
+
+	dev_info(pcie->dev,
+		 "found device %04x:%04x on bus %d (%s), slot %d (irq %d)\n",
+		 dev->vendor, dev->device, dev->bus->number, pcie->name,
+		 slot, brcm_map_irq(dev, slot, 1));
+}
+DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, brcm_pcibios_fixup);
+
+
+/***********************************************************************
+ * PCI Platform Driver
+ ***********************************************************************/
+static int __init brcm_pci_probe(struct platform_device *pdev)
+{
+	struct device_node *dn = pdev->dev.of_node, *mdn;
+	const u32 *imap_prop;
+	int len, i, irq_offset, rlen, pna, np, ret;
+	struct brcm_pcie *pcie;
+	struct resource *r;
+	const u32 *ranges, *log2_scb_sizes, *dma_ranges;
+	void __iomem *base;
+	u32 tmp;
+
+	pcie = devm_kzalloc(&pdev->dev, sizeof(struct brcm_pcie), GFP_KERNEL);
+	if (!pcie)
+		return -ENOMEM;
+
+	/* 'num_memc' will be set only by the first controller, and all
+	 * other controllers will use the value set by the first. */
+	if (num_memc == 0)
+		for_each_compatible_node(mdn, NULL, "brcm,brcmstb-memc")
+			if (of_device_is_available(mdn))
+				num_memc++;
+
+	r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (!r)
+		return -EINVAL;
+
+	base = devm_ioremap_resource(&pdev->dev, r);
+	if (!base)
+		return -ENOMEM;
+
+	imap_prop = of_get_property(dn, "interrupt-map", &len);
+	if (imap_prop == NULL) {
+		dev_err(&pdev->dev, "missing interrupt-map\n");
+		return -EINVAL;
+	}
+
+	irq_offset = irq_of_parse_and_map(dn, 0);
+	for (i = 0; i < 4 && i*4 < len; i++)
+		pcie->pcie_irq[i] = irq_offset
+			+ of_read_number(imap_prop + (i * 7 + 5), 1);
+
+	snprintf(pcie->name,
+		 sizeof(pcie->name)-1, "PCIe%d", brcm_num_pci_controllers);
+	pcie->suspended = false;
+	pcie->clk = of_clk_get_by_name(dn, "sw_pcie");
+	if (IS_ERR(pcie->clk)) {
+		dev_err(&pdev->dev, "could not get clock\n");
+		pcie->clk = NULL;
+	}
+	ret = clk_prepare_enable(pcie->clk);
+	if (ret) {
+		dev_err(&pdev->dev, "could not enable clock\n");
+		return ret;
+	}
+	pcie->dn = dn;
+	pcie->base = base;
+	pcie->dev = &pdev->dev;
+	pcie->gen = 0;
+
+	ret = of_property_read_u32(dn, "brcm,gen", &tmp);
+	if (ret == 0) {
+		if (tmp > 0 && tmp < 3)
+			pcie->gen = (int) tmp;
+		else
+			dev_warn(pcie->dev, "bad DT value for prop 'brcm,gen");
+	} else if (ret != -EINVAL) {
+		dev_warn(pcie->dev, "error reading DT prop 'brcm,gen");
+	}
+
+	pcie->ssc = of_property_read_bool(dn, "brcm,ssc");
+
+	/* Get the value for the log2 of the scb sizes.  Subtract 15 from
+	 * each because the target register field has 0==disabled and 1==64KB.
+	 */
+	log2_scb_sizes = of_get_property(dn, "brcm,log2-scb-sizes", &rlen);
+	if (log2_scb_sizes != NULL)
+		for (i = 0; i < rlen/4; i++)
+			pcie->scb_size_vals[i]
+				= (int) of_read_number(log2_scb_sizes + i, 1)
+					- 15;
+
+	/* Look for the dma-ranges property.  If it exists, issue a warning
+	 * as PCIe drivers may not work.  This is because the identity
+	 * mapping between system memory and PCIe space is not preserved,
+	 * and we need Linux to massage the dma_addr_t values it gets
+	 * from dma memory allocation.  This functionality will be added
+	 * in the near future.
+	 */
+	dma_ranges = of_get_property(dn, "dma-ranges", &rlen);
+	if (dma_ranges != NULL)
+		dev_warn(pcie->dev, "no identity map; PCI drivers may fail");
+
+	ranges = of_get_property(dn, "ranges", &rlen);
+	if (ranges == NULL) {
+		dev_err(pcie->dev, "no ranges property in dev tree.\n");
+		return -EINVAL;
+	}
+	/* set up CPU->PCIE memory windows (max of four) */
+	pna = of_n_addr_cells(dn);
+	np = pna + 5;
+
+	pcie->num_out_wins = rlen / (np * 4);
+
+	for (i = 0; i < pcie->num_out_wins; i++) {
+		struct brcm_window *w = &pcie->out_wins[i];
+		w->info = (u32) of_read_ulong(ranges + 0, 1);
+		w->pci_addr = of_read_number(ranges + 1, 2);
+		w->cpu_addr = of_translate_address(dn, ranges + 3);
+		w->size = of_read_number(ranges + pna + 3, 2);
+		ranges += np;
+
+		w->pcie_iomem_res.name	= "External PCIe MEM";
+		w->pcie_iomem_res.flags	= IORESOURCE_MEM;
+		w->pcie_iomem_res.start	= w->cpu_addr;
+		w->pcie_iomem_res.end	= w->cpu_addr + w->size - 1;
+
+		/* Request memory region resources. */
+		if (request_resource(&iomem_resource, &w->pcie_iomem_res)) {
+			dev_err(&pdev->dev,
+				"request PCIe memory resource failed\n");
+			return -EIO;
+		}
+	}
+
+	/*
+	 * Starts PCIe link negotiation immediately at kernel boot time.  The
+	 * RC is supposed to give the endpoint device 100ms to settle down
+	 * before attempting configuration accesses.  So we let the link
+	 * negotiation happen in the background instead of busy-waiting.
+	 */
+	brcm_pcie_setup_early(pcie);
+	list_add_tail(&pcie->list, &brcm_pcie);
+	brcm_num_pci_controllers++;
+
+	return 0;
+}
+
+
+static const struct of_device_id brcm_pci_match[] = {
+	{ .compatible = "brcm,pci-plat-dev" },
+	{},
+};
+MODULE_DEVICE_TABLE(of, brcm_pci_match);
+
+
+static struct platform_driver __refdata brcm_pci_driver = {
+	.probe = brcm_pci_probe,
+	.driver = {
+		.name = "brcm-pci",
+		.owner = THIS_MODULE,
+		.of_match_table = brcm_pci_match,
+	},
+};
+
+
+int __init brcm_pcibios_init(void)
+{
+	int ret;
+
+	INIT_LIST_HEAD(&brcm_pcie);
+	ret = platform_driver_probe(&brcm_pci_driver, brcm_pci_probe);
+	if (!ret && brcm_num_pci_controllers > 0) {
+		void **private_data;
+		struct brcm_pcie *pcie;
+		int i = 0;
+
+		brcm_pcie_hw.nr_controllers = brcm_num_pci_controllers;
+		if (IS_ENABLED(CONFIG_PM))
+			register_syscore_ops(&pcie_pm_ops);
+
+		private_data = kzalloc(brcm_num_pci_controllers
+				       * sizeof(void *), GFP_KERNEL);
+		if (!private_data)
+			return -ENOMEM;
+		list_for_each_entry(pcie, &brcm_pcie, list)
+			private_data[i++] = pcie;
+		BUG_ON(i != brcm_num_pci_controllers);
+		brcm_pcie_hw.private_data = private_data;
+		pci_common_init(&brcm_pcie_hw);
+		kfree(brcm_pcie_hw.private_data);
+		brcm_pcie_hw.private_data = NULL;
+	}
+	return ret;
+}
+
+
+arch_initcall(brcm_pcibios_init);
diff --git a/arch/arm/mach-brcmstb/Makefile b/arch/arm/mach-brcmstb/Makefile
new file mode 100644
index 0000000..157db0e
--- /dev/null
+++ b/arch/arm/mach-brcmstb/Makefile
@@ -0,0 +1 @@
+obj-y	+= common.o time.o platsmp.o headsmp.o
diff --git a/arch/arm/mach-brcmstb/Makefile.boot b/arch/arm/mach-brcmstb/Makefile.boot
new file mode 100644
index 0000000..5b9c54d
--- /dev/null
+++ b/arch/arm/mach-brcmstb/Makefile.boot
@@ -0,0 +1,3 @@
+zreladdr-y := 0x00008000
+
+dtb-$(CONFIG_BCM7445A0) += bcm7445a0.dtb
diff --git a/arch/arm/mach-brcmstb/common.c b/arch/arm/mach-brcmstb/common.c
new file mode 100644
index 0000000..377e79a
--- /dev/null
+++ b/arch/arm/mach-brcmstb/common.c
@@ -0,0 +1,105 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/delay.h>
+#include <linux/irq.h>
+#include <linux/irqdomain.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/clk.h>
+#include <linux/serial_8250.h>
+#include <linux/if_ether.h>
+#include <linux/platform_device.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#include <asm/mach/arch.h>
+#include <asm/mach/map.h>
+#include <asm/hardware/gic.h>
+
+#include <mach/irqs.h>
+#include <mach/hardware.h>
+
+#include "common.h"
+
+static struct map_desc io_map[] __initdata = {
+	{
+	.virtual = (unsigned long)BRCMSTB_PERIPH_VIRT,
+	.pfn     = __phys_to_pfn(BRCMSTB_PERIPH_PHYS),
+	.length  = BRCMSTB_PERIPH_LENGTH,
+	.type    = MT_DEVICE,
+	},
+};
+
+static const char *brcmstb_match[] __initdata = {
+	"brcm,brcmstb",
+	NULL
+};
+
+static const struct of_device_id brcmstb_dt_irq_match[] __initconst = {
+	{ .compatible = "arm,cortex-a15-gic", .data = gic_of_init },
+	{ }
+};
+
+static void __init brcmstb_map_io(void)
+{
+	iotable_init(io_map, ARRAY_SIZE(io_map));
+}
+
+static void __init brcmstb_machine_init(void)
+{
+	of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
+
+	/*
+	 * FIXME: In 3.8+ the bchip_* calls should go away; DT will tell us
+	 * which peripherals are enabled
+	 */
+	bchip_set_features();
+
+	printk(KERN_INFO "Options: moca=%d sata=%d pcie=%d usb=%d\n",
+		brcm_moca_enabled, brcm_sata_enabled,
+		brcm_pcie_enabled, brcm_usb_enabled);
+
+	bchip_early_setup();
+}
+
+static void brcmstb_restart(char mode, const char *cmd)
+{
+	brcm_machine_restart(cmd);
+}
+
+void __init brcmstb_dt_init_irq(void)
+{
+	BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK
+		| BCHP_IRQ0_IRQEN_uartb_irqen_MASK
+		| BCHP_IRQ0_IRQEN_uartc_irqen_MASK
+		);
+	of_irq_init(brcmstb_dt_irq_match);
+}
+
+extern asmlinkage void brcmstb_handle_irq(struct pt_regs *regs);
+
+DT_MACHINE_START(BRCMSTB, "Broadcom STB (Flattened Device Tree)")
+	.map_io		= brcmstb_map_io,
+	.init_irq	= brcmstb_dt_init_irq,
+	.handle_irq	= gic_handle_irq,
+	.timer		= &brcmstb_timer,
+	.init_machine	= brcmstb_machine_init,
+	.dt_compat	= brcmstb_match,
+	.restart	= brcmstb_restart,
+MACHINE_END
diff --git a/arch/arm/mach-brcmstb/common.h b/arch/arm/mach-brcmstb/common.h
new file mode 100644
index 0000000..b892125
--- /dev/null
+++ b/arch/arm/mach-brcmstb/common.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __BRCMSTB_COMMON_H__
+#define __BRCMSTB_COMMON_H__
+
+#include <asm/mach/time.h>
+
+extern struct sys_timer brcmstb_timer;
+extern void brcmstb_secondary_startup(void);
+
+#endif /* __BRCMSTB_COMMON_H__ */
diff --git a/arch/arm/mach-brcmstb/headsmp.S b/arch/arm/mach-brcmstb/headsmp.S
new file mode 100644
index 0000000..2cc8c27
--- /dev/null
+++ b/arch/arm/mach-brcmstb/headsmp.S
@@ -0,0 +1,75 @@
+/*
+ * SMP boot code for secondary CPUs
+ * Based on arch/arm/mach-tegra/headsmp.S
+ *
+ * Copyright (C) 2010 NVIDIA, Inc.
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/linkage.h>
+#include <linux/init.h>
+
+        .section ".text.head", "ax"
+	__CPUINIT
+
+/*
+ * Entry point for secondary CPUs.
+ *   The secondary kernel init calls v7_flush_dcache_all before it enables
+ *   the L1; however, the L1 comes out of reset in an undefined state, so
+ *   the clean + invalidate performed by v7_flush_dcache_all causes a bunch
+ *   of cache lines with uninitialized data and uninitialized tags to get
+ *   written out to memory, which does really unpleasant things to the main
+ *   processor.  We fix this by performing an invalidate, rather than a
+ *   clean + invalidate, before jumping into the kernel.
+ */
+ENTRY(v7_invalidate_l1)
+        mov     r0, #0
+        mcr     p15, 2, r0, c0, c0, 0
+        mrc     p15, 1, r0, c0, c0, 0
+
+        ldr     r1, =0x7fff
+        and     r2, r1, r0, lsr #13
+
+        ldr     r1, =0x3ff
+
+        and     r3, r1, r0, lsr #3  @ NumWays - 1
+        add     r2, r2, #1          @ NumSets
+
+        and     r0, r0, #0x7
+        add     r0, r0, #4          @ SetShift
+
+        clz     r1, r3              @ WayShift
+        add     r4, r3, #1          @ NumWays
+1:      sub     r2, r2, #1          @ NumSets--
+        mov     r3, r4              @ Temp = NumWays
+2:      subs    r3, r3, #1          @ Temp--
+        mov     r5, r3, lsl r1
+        mov     r6, r2, lsl r0
+        orr     r5, r5, r6          @ Reg = (Temp<<WayShift)|(NumSets<<SetShift)
+        mcr     p15, 0, r5, c7, c6, 2
+        bgt     2b
+        cmp     r2, #0
+        bgt     1b
+        dsb
+        isb
+        mov     pc, lr
+ENDPROC(v7_invalidate_l1)
+
+ENTRY(brcmstb_secondary_startup)
+        msr     cpsr_fsxc, #0xd3
+        bl      v7_invalidate_l1
+        b       secondary_startup
+ENDPROC(brcmstb_secondary_startup)
diff --git a/arch/arm/mach-brcmstb/include/mach/debug-macro.S b/arch/arm/mach-brcmstb/include/mach/debug-macro.S
new file mode 100644
index 0000000..a64e420
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/debug-macro.S
@@ -0,0 +1,36 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ * Copyright (c) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Derived from arch/arm/mach-davinci/include/mach/debug-macro.S to use 32-bit
+ * accesses to the 8250.
+ */
+
+#include <linux/serial_reg.h>
+#include <mach/hardware.h>
+
+#define UART_SHIFT 2
+
+		.macro	addruart, rp, rv, tmp
+		ldr	\rv, =PHYS_TO_IO(BRCMSTB_UARTA_BASE)
+		ldr	\rp, =BRCMSTB_UARTA_BASE
+		.endm
+
+		.macro	senduart,rd,rx
+		str	\rd, [\rx, #UART_TX << UART_SHIFT]
+		.endm
+
+		.macro	busyuart,rd,rx
+1002:		ldr	\rd, [\rx, #UART_LSR << UART_SHIFT]
+		and	\rd, \rd, #UART_LSR_TEMT | UART_LSR_THRE
+		teq	\rd, #UART_LSR_TEMT | UART_LSR_THRE
+		bne	1002b
+		.endm
+
+		/* The UART's don't have any flow control IO's wired up. */
+		.macro	waituart,rd,rx
+		.endm
diff --git a/arch/arm/mach-brcmstb/include/mach/entry-macro.S b/arch/arm/mach-brcmstb/include/mach/entry-macro.S
new file mode 100644
index 0000000..9b505ac
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/entry-macro.S
@@ -0,0 +1,16 @@
+/*
+ * entry-macro.S
+ *
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * Low-level IRQ helper macros for picoXcell platforms
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+	.macro  disable_fiq
+	.endm
+
+	.macro  arch_ret_to_user, tmp1, tmp2
+	.endm
diff --git a/arch/arm/mach-brcmstb/include/mach/gpio.h b/arch/arm/mach-brcmstb/include/mach/gpio.h
new file mode 100644
index 0000000..40a8c17
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/gpio.h
@@ -0,0 +1 @@
+/* empty */
diff --git a/arch/arm/mach-brcmstb/include/mach/hardware.h b/arch/arm/mach-brcmstb/include/mach/hardware.h
new file mode 100644
index 0000000..09c7fa8
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/hardware.h
@@ -0,0 +1,40 @@
+/*
+ * Copyright (C) 2013 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H
+#define __ASM_ARCH_HARDWARE_H
+
+#include <linux/brcmstb/brcmstb.h>
+#include <linux/compiler.h>
+
+/* FIXME: Read this from device tree */
+#define BRCMSTB_UARTA_BASE	BPHYSADDR(BCHP_UARTA_REG_START)
+
+#define __BRCMSTB_PERIPH_VIRT	0xfd000000
+#define BRCMSTB_PERIPH_VIRT	((void __iomem *)__BRCMSTB_PERIPH_VIRT)
+#define BRCMSTB_PERIPH_PHYS	BPHYSADDR(0)
+#define BRCMSTB_PERIPH_LENGTH	SZ_32M
+
+#define PHYS_TO_IO(x)		(((x) & 0x00ffffff) | __BRCMSTB_PERIPH_VIRT)
+
+#ifdef __ASSEMBLY__
+#define IO_ADDRESS(x)		PHYS_TO_IO((x))
+#else
+#define IO_ADDRESS(x)		(void __iomem __force *)(PHYS_TO_IO((x)))
+#endif
+
+#endif
diff --git a/arch/arm/mach-brcmstb/include/mach/io.h b/arch/arm/mach-brcmstb/include/mach/io.h
new file mode 100644
index 0000000..7573ec7
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/io.h
@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARM_ARCH_IO_H
+#define __ASM_ARM_ARCH_IO_H
+
+/* No ioports, but needed for driver compatibility. */
+#define __io(a)			__typesafe_io(a)
+/* No PCI possible on picoxcell. */
+#define __mem_pci(a)		(a)
+
+#endif /* __ASM_ARM_ARCH_IO_H */
diff --git a/arch/arm/mach-brcmstb/include/mach/irqs.h b/arch/arm/mach-brcmstb/include/mach/irqs.h
new file mode 100644
index 0000000..87be8d4
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/irqs.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __MACH_IRQS_H
+#define __MACH_IRQS_H
+
+/* We dynamically allocate our irq_desc's. */
+#define NR_IRQS				0
+
+#define IRQ_LOCALTIMER			29
+#define BRCMSTB_GIC_START		31
+
+#endif /* __MACH_IRQS_H */
diff --git a/arch/arm/mach-brcmstb/include/mach/system.h b/arch/arm/mach-brcmstb/include/mach/system.h
new file mode 100644
index 0000000..1a5d8cb
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/system.h
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __ASM_ARCH_SYSTEM_H
+#define __ASM_ARCH_SYSTEM_H
+
+static inline void arch_idle(void)
+{
+	/*
+	 * This should do all the clock switching and wait for interrupt
+	 * tricks.
+	 */
+	cpu_do_idle();
+}
+
+#endif /* __ASM_ARCH_SYSTEM_H */
diff --git a/arch/arm/mach-brcmstb/include/mach/timex.h b/arch/arm/mach-brcmstb/include/mach/timex.h
new file mode 100644
index 0000000..6c540a6
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/timex.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2011 Picochip Ltd., Jamie Iles
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+#ifndef __TIMEX_H__
+#define __TIMEX_H__
+
+/* Bogus value to allow the kernel to compile. */
+#define CLOCK_TICK_RATE		1000000
+
+#endif /* __TIMEX_H__ */
+
diff --git a/arch/arm/mach-brcmstb/include/mach/uncompress.h b/arch/arm/mach-brcmstb/include/mach/uncompress.h
new file mode 100644
index 0000000..b4d74ce
--- /dev/null
+++ b/arch/arm/mach-brcmstb/include/mach/uncompress.h
@@ -0,0 +1,49 @@
+/*
+ *  arch/arm/mach-brcmstb/include/mach/uncompress.h
+ *  Derived from: arch/arm/mach-ebsa110/include/mach/uncompress.h
+ *
+ *  Copyright (C) 1996,1997,1998 Russell King
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/serial_reg.h>
+#include <linux/types.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#define SERIAL_BASE	((void __iomem *)BPHYSADDR(BCHP_UARTA_REG_START))
+
+/*
+ * This does not append a newline
+ */
+static inline void putc(int c)
+{
+	u32 v;
+	u32 *base = SERIAL_BASE;
+
+	do {
+		v = base[UART_LSR];
+		barrier();
+	} while (!(v & UART_LSR_THRE));
+
+	base[UART_TX] = c;
+}
+
+static inline void flush(void)
+{
+	unsigned char v, *base = SERIAL_BASE;
+
+	do {
+		v = base[UART_LSR << 2];
+		barrier();
+	} while ((v & (UART_LSR_TEMT|UART_LSR_THRE)) !=
+		 (UART_LSR_TEMT|UART_LSR_THRE));
+}
+
+/*
+ * nothing to do
+ */
+#define arch_decomp_setup()
+#define arch_decomp_wdog()
diff --git a/arch/arm/mach-brcmstb/platsmp.c b/arch/arm/mach-brcmstb/platsmp.c
new file mode 100644
index 0000000..75e2528
--- /dev/null
+++ b/arch/arm/mach-brcmstb/platsmp.c
@@ -0,0 +1,133 @@
+/*
+ * Broadcom STB SMP support for ARM
+ * Based on arch/arm/mach-tegra/platsmp.c
+ *
+ *  Copyright (C) 2002 ARM Ltd.
+ *  All Rights Reserved
+ *
+ *  Copyright (C) 2009 Palm
+ *  All Rights Reserved
+ *
+ *  Copyright (C) 2013 Broadcom Corporation
+ *  All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/errno.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/jiffies.h>
+#include <linux/printk.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/gic.h>
+#include <asm/mach-types.h>
+
+#include <mach/hardware.h>
+#include "common.h"
+
+static DEFINE_SPINLOCK(boot_lock);
+
+/***********************************************************************
+ * SMP boot
+ ***********************************************************************/
+
+void __cpuinit platform_secondary_init(unsigned int cpu)
+{
+	/*
+	 * if any interrupts are already enabled for the primary
+	 * core (e.g. timer irq), then they will not have been enabled
+	 * for us: do so
+	 */
+	gic_secondary_init(0);
+
+	/*
+	 * Synchronise with the boot thread.
+	 */
+	spin_lock(&boot_lock);
+	spin_unlock(&boot_lock);
+}
+
+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
+{
+	unsigned long boot_vector;
+
+	pr_info("SMP: Booting CPU%d...\n", cpu);
+
+	/*
+	 * set synchronisation state between this boot processor
+	 * and the secondary one
+	 */
+	spin_lock(&boot_lock);
+
+	/* set the reset vector to point to the secondary_startup routine */
+	boot_vector = virt_to_phys(brcmstb_secondary_startup);
+	BDEV_WR(BCHP_HIF_CONTINUATION_STB_BOOT_ADDR0 + cpu * 8, boot_vector);
+
+	smp_wmb();
+
+	flush_cache_all();
+
+	/* unhalt the cpu */
+	BDEV_UNSET(BCHP_HIF_CPUBIUCTRL_CPU_RESET_CONFIG_REG, BIT(cpu));
+
+	/*
+	 * now the secondary core is starting up let it run its
+	 * calibrations, then wait for it to finish
+	 */
+	spin_unlock(&boot_lock);
+
+	return 0;
+}
+
+/*
+ * Initialise the CPU possible map early - this describes the CPUs
+ * which may be present or become present in the system.
+ */
+void __init smp_init_cpus(void)
+{
+	/* FIXME: ncores needs to come from DT */
+	unsigned int i, ncores = 4;
+
+	if (ncores > nr_cpu_ids) {
+		pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
+			ncores, nr_cpu_ids);
+		ncores = nr_cpu_ids;
+	}
+
+	for (i = 0; i < ncores; i++)
+		set_cpu_possible(i, true);
+
+	set_smp_cross_call(gic_raise_softirq);
+}
+
+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
+{
+}
+
+/***********************************************************************
+ * CPU Hotplug
+ ***********************************************************************/
+
+int platform_cpu_disable(unsigned int cpu)
+{
+	/* FIXME: not currently implemented */
+	return -EPERM;
+}
+
+void platform_cpu_die(unsigned int cpu)
+{
+	BUG();
+}
+
+int platform_cpu_kill(unsigned int cpu)
+{
+	return 0;
+}
diff --git a/arch/arm/mach-brcmstb/time.c b/arch/arm/mach-brcmstb/time.c
new file mode 100644
index 0000000..f9d759c
--- /dev/null
+++ b/arch/arm/mach-brcmstb/time.c
@@ -0,0 +1,364 @@
+/*
+ * Rudimentary ARM architected timer support
+ * Derived from arch/arm/kernel/arch_timer.c in mainline
+ *
+ * Copyright (C) 2011 ARM Ltd.
+ * All Rights Reserved
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/delay.h>
+#include <linux/device.h>
+#include <linux/smp.h>
+#include <linux/cpu.h>
+#include <linux/jiffies.h>
+#include <linux/clockchips.h>
+#include <linux/interrupt.h>
+#include <linux/of_irq.h>
+#include <linux/io.h>
+
+#include <asm/cputype.h>
+#include <asm/localtimer.h>
+#include <asm/sched_clock.h>
+#include <asm/mach/time.h>
+#include <asm/smp_plat.h>
+#include <mach/irqs.h>
+
+#include <linux/brcmstb/brcmstb.h>
+
+static unsigned long arch_timer_rate;
+static int arch_timer_ppi;
+static int arch_timer_ppi2;
+
+static struct clock_event_device __percpu **arch_timer_evt;
+
+/*
+ * Architected system timer support.
+ */
+
+#define ARCH_TIMER_CTRL_ENABLE		(1 << 0)
+#define ARCH_TIMER_CTRL_IT_MASK		(1 << 1)
+#define ARCH_TIMER_CTRL_IT_STAT		(1 << 2)
+
+#define ARCH_TIMER_REG_CTRL		0
+#define ARCH_TIMER_REG_FREQ		1
+#define ARCH_TIMER_REG_TVAL		2
+
+static void arch_timer_reg_write(int reg, u32 val)
+{
+	switch (reg) {
+	case ARCH_TIMER_REG_CTRL:
+		asm volatile("mcr p15, 0, %0, c14, c2, 1" : : "r" (val));
+		break;
+	case ARCH_TIMER_REG_TVAL:
+		asm volatile("mcr p15, 0, %0, c14, c2, 0" : : "r" (val));
+		break;
+	}
+
+	isb();
+}
+
+static u32 arch_timer_reg_read(int reg)
+{
+	u32 val;
+
+	switch (reg) {
+	case ARCH_TIMER_REG_CTRL:
+		asm volatile("mrc p15, 0, %0, c14, c2, 1" : "=r" (val));
+		break;
+	case ARCH_TIMER_REG_FREQ:
+		asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (val));
+		break;
+	case ARCH_TIMER_REG_TVAL:
+		asm volatile("mrc p15, 0, %0, c14, c2, 0" : "=r" (val));
+		break;
+	default:
+		BUG();
+	}
+
+	return val;
+}
+
+static irqreturn_t arch_timer_handler(int irq, void *dev_id)
+{
+	struct clock_event_device *evt = *(struct clock_event_device **)dev_id;
+	unsigned long ctrl;
+
+	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+	if (ctrl & ARCH_TIMER_CTRL_IT_STAT) {
+		ctrl |= ARCH_TIMER_CTRL_IT_MASK;
+		arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+		evt->event_handler(evt);
+		return IRQ_HANDLED;
+	}
+
+	return IRQ_NONE;
+}
+
+static void arch_timer_disable(void)
+{
+	unsigned long ctrl;
+
+	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+	ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
+	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+}
+
+static void arch_timer_set_mode(enum clock_event_mode mode,
+				struct clock_event_device *clk)
+{
+	switch (mode) {
+	case CLOCK_EVT_MODE_UNUSED:
+	case CLOCK_EVT_MODE_SHUTDOWN:
+		arch_timer_disable();
+		break;
+	default:
+		break;
+	}
+}
+
+static int arch_timer_set_next_event(unsigned long evt,
+				     struct clock_event_device *unused)
+{
+	unsigned long ctrl;
+
+	ctrl = arch_timer_reg_read(ARCH_TIMER_REG_CTRL);
+	ctrl |= ARCH_TIMER_CTRL_ENABLE;
+	ctrl &= ~ARCH_TIMER_CTRL_IT_MASK;
+
+	arch_timer_reg_write(ARCH_TIMER_REG_TVAL, evt);
+	arch_timer_reg_write(ARCH_TIMER_REG_CTRL, ctrl);
+
+	return 0;
+}
+
+int __cpuinit local_timer_setup(struct clock_event_device *clk)
+{
+	/* Be safe... */
+	arch_timer_disable();
+
+	clk->features = CLOCK_EVT_FEAT_ONESHOT;
+	clk->name = "arch_sys_timer";
+	clk->rating = 450;
+	clk->set_mode = arch_timer_set_mode;
+	clk->set_next_event = arch_timer_set_next_event;
+	clk->irq = arch_timer_ppi;
+
+	clockevents_config_and_register(clk, arch_timer_rate,
+					0xf, 0x7fffffff);
+
+	*__this_cpu_ptr(arch_timer_evt) = clk;
+
+	enable_percpu_irq(clk->irq, 0);
+	if (arch_timer_ppi2)
+		enable_percpu_irq(arch_timer_ppi2, 0);
+
+	return 0;
+}
+
+/* Is the optional system timer available? */
+static int local_timer_is_architected(void)
+{
+	return (cpu_architecture() >= CPU_ARCH_ARMv7) &&
+	       ((read_cpuid_ext(CPUID_EXT_PFR1) >> 16) & 0xf) == 1;
+}
+
+static int arch_timer_available(void)
+{
+	unsigned long freq;
+
+	if (!local_timer_is_architected())
+		return -ENXIO;
+
+	if (arch_timer_rate == 0) {
+		arch_timer_reg_write(ARCH_TIMER_REG_CTRL, 0);
+		freq = arch_timer_reg_read(ARCH_TIMER_REG_FREQ);
+
+		/* Check the timer frequency. */
+		if (freq == 0) {
+			pr_warn("Architected timer frequency not available\n");
+			return -EINVAL;
+		}
+
+		arch_timer_rate = freq;
+	}
+
+	pr_info_once("Architected local timer running at %lu.%02luMHz.\n",
+		     arch_timer_rate / 1000000,
+		     (arch_timer_rate / 10000) % 100);
+	return 0;
+}
+
+static inline cycle_t arch_counter_get_cntpct(void)
+{
+	u32 cvall, cvalh;
+
+	asm volatile("mrrc p15, 0, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+
+	return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static inline cycle_t arch_counter_get_cntvct(void)
+{
+	u32 cvall, cvalh;
+
+	asm volatile("mrrc p15, 1, %0, %1, c14" : "=r" (cvall), "=r" (cvalh));
+
+	return ((cycle_t) cvalh << 32) | cvall;
+}
+
+static u32 notrace arch_counter_get_cntvct32(void)
+{
+	cycle_t cntvct = arch_counter_get_cntvct();
+
+	/*
+	 * The sched_clock infrastructure only knows about counters
+	 * with at most 32bits. Forget about the upper 24 bits for the
+	 * time being...
+	 */
+	return (u32)(cntvct & (u32)~0);
+}
+
+static cycle_t arch_counter_read(struct clocksource *cs)
+{
+	return arch_counter_get_cntpct();
+}
+
+static struct clocksource clocksource_counter = {
+	.name	= "arch_sys_counter",
+	.rating	= 400,
+	.read	= arch_counter_read,
+	.mask	= CLOCKSOURCE_MASK(56),
+	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+void __cpuinit local_timer_stop(struct clock_event_device *clk)
+{
+	pr_debug("arch_timer_teardown disable IRQ%d cpu #%d\n",
+		 clk->irq, smp_processor_id());
+	disable_percpu_irq(clk->irq);
+	if (arch_timer_ppi2)
+		disable_percpu_irq(arch_timer_ppi2);
+	arch_timer_set_mode(CLOCK_EVT_MODE_UNUSED, clk);
+}
+
+static struct clock_event_device arch_timer_global_evt;
+
+static int __init arch_timer_register(void)
+{
+	int err;
+
+	err = arch_timer_available();
+	if (err)
+		return err;
+
+	arch_timer_evt = alloc_percpu(struct clock_event_device *);
+	if (!arch_timer_evt)
+		return -ENOMEM;
+
+	clocksource_register_hz(&clocksource_counter, arch_timer_rate);
+
+	err = request_percpu_irq(arch_timer_ppi, arch_timer_handler,
+				 "arch_timer", arch_timer_evt);
+	if (err) {
+		pr_err("arch_timer: can't register interrupt %d (%d)\n",
+		       arch_timer_ppi, err);
+		goto out_free;
+	}
+
+	if (arch_timer_ppi2) {
+		err = request_percpu_irq(arch_timer_ppi2, arch_timer_handler,
+					 "arch_timer", arch_timer_evt);
+		if (err) {
+			pr_err("arch_timer: can't register interrupt %d (%d)\n",
+			       arch_timer_ppi2, err);
+			arch_timer_ppi2 = 0;
+			goto out_free_irq;
+		}
+	}
+
+	/* Execute if 'nosmp' or UP configured */
+	if (setup_max_cpus <= 1) {
+		/*
+		 * We couldn't register as a local timer (could be
+		 * because we're on a UP platform, or because some
+		 * other local timer is already present...). Try as a
+		 * global timer instead.
+		 */
+		arch_timer_global_evt.cpumask = cpumask_of(0);
+		err = local_timer_setup(&arch_timer_global_evt);
+
+		if (err)
+			goto out_free_irq;
+	}
+
+	return 0;
+
+out_free_irq:
+	free_percpu_irq(arch_timer_ppi, arch_timer_evt);
+	if (arch_timer_ppi2)
+		free_percpu_irq(arch_timer_ppi2, arch_timer_evt);
+
+out_free:
+	free_percpu(arch_timer_evt);
+
+	return err;
+}
+
+static const struct of_device_id arch_timer_of_match[] __initconst = {
+	{.compatible	= "arm,armv7-timer",},
+	{},
+};
+
+int __init arch_timer_of_register(void)
+{
+	struct device_node *np;
+	u32 freq;
+
+	np = of_find_matching_node(NULL, arch_timer_of_match);
+	if (!np) {
+		pr_err("arch_timer: can't find DT node\n");
+		return -ENODEV;
+	}
+
+	/* Try to determine the frequency from the device tree or CNTFRQ */
+	if (!of_property_read_u32(np, "clock-frequency", &freq))
+		arch_timer_rate = freq;
+
+	arch_timer_ppi = irq_of_parse_and_map(np, 0);
+	arch_timer_ppi2 = irq_of_parse_and_map(np, 1);
+	pr_info("arch_timer: found %s irqs %d %d\n",
+		np->name, arch_timer_ppi, arch_timer_ppi2);
+
+	return arch_timer_register();
+}
+
+int __init arch_timer_sched_clock_init(void)
+{
+	int err;
+
+	err = arch_timer_available();
+	if (err)
+		return err;
+
+	setup_sched_clock(arch_counter_get_cntvct32, 32, arch_timer_rate);
+	return 0;
+}
+
+void __init brcmstb_timer_init(void)
+{
+	BUG_ON(arch_timer_of_register() != 0);
+	BUG_ON(arch_timer_sched_clock_init());
+
+	/* Calibrate the delay loop directly */
+	lpj_fine = arch_timer_rate / HZ;
+}
+
+struct sys_timer brcmstb_timer = {
+	.init = brcmstb_timer_init,
+};
diff --git a/arch/arm/mach-picoxcell/irq.c b/arch/arm/mach-picoxcell/irq.c
new file mode 100644
index 0000000..b9c97b9
--- /dev/null
+++ b/arch/arm/mach-picoxcell/irq.c
@@ -0,0 +1,93 @@
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/interrupt.h>
+#include <linux/syscore_ops.h>
+#include <linux/io.h>
+#include <linux/ioport.h>
+#include <linux/irq.h>
+#include <linux/bitops.h>
+
+#include <asm/exception.h>
+
+#include <mach/irqs.h>
+
+static const void __iomem *base = (void *)0xee41a400;
+
+#define IRQBIT(irq)		BIT((irq) & 0x1f)
+#define IRQWD(irq)		(base + (((irq) >> 5) << 2))
+
+void brcmstb_mask_irq(struct irq_data *d)
+{
+	__raw_writel(IRQBIT(d->irq), IRQWD(d->irq) + 0x18);
+}
+
+void brcmstb_unmask_irq(struct irq_data *d)
+{
+	__raw_writel(IRQBIT(d->irq), IRQWD(d->irq) + 0x24);
+}
+
+static struct irq_chip brcmstb_internal_irq_chip = {
+	.name		= "HIF_L1",
+	.irq_ack	= brcmstb_mask_irq,
+	.irq_mask	= brcmstb_mask_irq,
+	.irq_unmask	= brcmstb_unmask_irq,
+};
+
+#define do_IRQ(x)		handle_IRQ((x) - 1, regs)
+#define flip_tp(x)		do { } while (0)
+
+asmlinkage void __exception_irq_entry brcmstb_handle_irq(struct pt_regs *regs)
+{
+	u32 pend, shift;
+
+	pend = __raw_readl(IRQWD(0) + 0x00) & ~__raw_readl(IRQWD(0) + 0x0c);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+
+	pend = __raw_readl(IRQWD(32) + 0x00) & ~__raw_readl(IRQWD(32) + 0x0c);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 32;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+
+	pend = __raw_readl(IRQWD(64) + 0x00) & ~__raw_readl(IRQWD(64) + 0x0c);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 64;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+}
+
+#define BPHYSADDR(x)		((x) + 0xe0000000)
+
+static struct resource irq_resource = {
+	.name	= "HIF_L1",
+	.start	= BPHYSADDR(0x0041a400),
+	.end	= BPHYSADDR(0x0041a42f),
+};
+
+void __init brcmstb_init_irq(void)
+{
+	int i, n;
+
+	request_resource(&iomem_resource, &irq_resource);
+
+	for (n = 0; n < NR_IRQS; n += 32) {
+		__raw_writel(0xffffffff, IRQWD(n) + 0x18);
+
+		for (i = n; (i < (n + 32)) && (i < NR_IRQS); i++) {
+			irq_set_chip_and_handler(i, &brcmstb_internal_irq_chip,
+						 handle_level_irq);
+			//irq_set_chip_data(i, base);
+			set_irq_flags(i, IRQF_VALID);
+		}
+	}
+}
+
diff --git a/arch/arm/mm/Kconfig b/arch/arm/mm/Kconfig
index 4121886..cfc08d8 100644
--- a/arch/arm/mm/Kconfig
+++ b/arch/arm/mm/Kconfig
@@ -876,6 +876,14 @@
 	  The outer cache has a outer_cache_fns.sync function pointer
 	  that can be used to drain the write buffer of the outer cache.
 
+config CACHE_B15_RAC
+	bool "Enable the Broadcom Brahma-B15 read-ahead cache controller"
+	depends on ARCH_BRCMSTB
+	default y
+	help
+	  This option enables the Broadcom Brahma-B15 read-ahead cache
+	  controller. If disabled, the read-ahead cache remains off.
+
 config CACHE_FEROCEON_L2
 	bool "Enable the Feroceon L2 cache controller"
 	depends on ARCH_MV78XX0 || ARCH_MVEBU
diff --git a/arch/arm/mm/Makefile b/arch/arm/mm/Makefile
index 7f76d96..d6aad94 100644
--- a/arch/arm/mm/Makefile
+++ b/arch/arm/mm/Makefile
@@ -99,6 +99,7 @@
 AFLAGS_proc-v7.o	:=-Wa,-march=armv7-a
 
 obj-$(CONFIG_OUTER_CACHE)	+= l2c-common.o
+obj-$(CONFIG_CACHE_B15_RAC)	+= cache-b15-rac.o
 obj-$(CONFIG_CACHE_FEROCEON_L2)	+= cache-feroceon-l2.o
 obj-$(CONFIG_CACHE_L2X0)	+= cache-l2x0.o l2c-l2x0-resume.o
 obj-$(CONFIG_CACHE_XSC3L2)	+= cache-xsc3l2.o
diff --git a/arch/arm/mm/cache-b15-rac.c b/arch/arm/mm/cache-b15-rac.c
new file mode 100644
index 0000000..e43d688
--- /dev/null
+++ b/arch/arm/mm/cache-b15-rac.c
@@ -0,0 +1,368 @@
+/*
+ * Broadcom Brahma-B15 CPU read-ahead cache management functions
+ *
+ * Copyright (C) 2015, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/err.h>
+#include <linux/spinlock.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/of_address.h>
+#include <linux/notifier.h>
+#include <linux/cpu.h>
+#include <linux/syscore_ops.h>
+#include <linux/reboot.h>
+
+#include <asm/cacheflush.h>
+#include <asm/hardware/cache-b15-rac.h>
+
+extern void v7_flush_kern_cache_all(void);
+extern void v7_flush_kern_cache_louis(void);
+extern void v7_flush_icache_all(void);
+
+/* RAC register offsets, relative to the HIF_CPU_BIUCTRL register base */
+#define RAC_CONFIG0_REG			(0x78)
+#define  RACENPREF_MASK			(0x3)
+#define  RACPREFINST_SHIFT		(0)
+#define  RACENINST_SHIFT		(2)
+#define  RACPREFDATA_SHIFT		(4)
+#define  RACENDATA_SHIFT		(6)
+#define  RAC_CPU_SHIFT			(8)
+#define  RACCFG_MASK			(0xff)
+#define RAC_CONFIG1_REG			(0x7c)
+#define RAC_FLUSH_REG			(0x80)
+#define  FLUSH_RAC			(1 << 0)
+
+/* Bitmask to enable instruction and data prefetching with a 256-bytes stride */
+#define RAC_DATA_INST_EN_MASK		(1 << RACPREFINST_SHIFT | \
+					 RACENPREF_MASK << RACENINST_SHIFT | \
+					 1 << RACPREFDATA_SHIFT | \
+					 RACENPREF_MASK << RACENDATA_SHIFT)
+
+#define RAC_ENABLED			(1 << 0)
+/* Special state where we want to bypass the spinlock and call directly
+ * into the v7 cache maintenance operations during suspend/resume
+ */
+#define RAC_SUSPENDED			(1 << 1)
+
+static void __iomem *b15_rac_base;
+static DEFINE_SPINLOCK(rac_lock);
+static u32 rac_config0_reg;
+
+/* Initialization flag to avoid checking for b15_rac_base, and to prevent
+ * multi-platform kernels from crashing here as well.
+ */
+static unsigned long b15_rac_flags;
+
+static inline u32 __b15_rac_disable(void)
+{
+	u32 val = __raw_readl(b15_rac_base + RAC_CONFIG0_REG);
+	__raw_writel(0, b15_rac_base + RAC_CONFIG0_REG);
+	dmb();
+	return val;
+}
+
+static inline void __b15_rac_flush(void)
+{
+	u32 reg;
+
+	__raw_writel(FLUSH_RAC, b15_rac_base + RAC_FLUSH_REG);
+	do {
+		/* This dmb() is required to force the Bus Interface Unit
+		 * to clean oustanding writes, and forces an idle cycle
+		 * to be inserted.
+		 */
+		dmb();
+		reg = __raw_readl(b15_rac_base + RAC_FLUSH_REG);
+	} while (reg & RAC_FLUSH_REG);
+}
+
+static inline u32 b15_rac_disable_and_flush(void)
+{
+	u32 reg;
+
+	reg = __b15_rac_disable();
+	__b15_rac_flush();
+	return reg;
+}
+
+static inline void __b15_rac_enable(u32 val)
+{
+	__raw_writel(val, b15_rac_base + RAC_CONFIG0_REG);
+	/* dsb() is required here to be consistent with __flush_icache_all() */
+	dsb();
+}
+
+#define BUILD_RAC_CACHE_OP(name, bar)				\
+void b15_flush_##name(void)					\
+{								\
+	unsigned int do_flush;					\
+	u32 val = 0;						\
+								\
+	if (test_bit(RAC_SUSPENDED, &b15_rac_flags)) {		\
+		v7_flush_##name();				\
+		bar;						\
+		return;						\
+	}							\
+								\
+	spin_lock(&rac_lock);					\
+	do_flush = test_bit(RAC_ENABLED, &b15_rac_flags);	\
+	if (do_flush)						\
+		val = b15_rac_disable_and_flush();		\
+	v7_flush_##name();					\
+	if (!do_flush)						\
+		bar;						\
+	else							\
+		__b15_rac_enable(val);				\
+	spin_unlock(&rac_lock);					\
+}
+
+#define nobarrier
+
+/* The readahead cache present in the Brahma-B15 CPU is a special piece of
+ * hardware after the integrated L2 cache of the B15 CPU complex whose purpose
+ * is to prefetch instruction and/or data with a line size of either 64 bytes
+ * or 256 bytes. The rationale is that the data-bus of the CPU interface is
+ * optimized for 256-bytes transactions, and enabling the readahead cache
+ * provides a significant performance boost we want it enabled (typically
+ * twice the performance for a memcpy benchmark application).
+ *
+ * The readahead cache is transparent for Modified Virtual Addresses
+ * cache maintenance operations: ICIMVAU, DCIMVAC, DCCMVAC, DCCMVAU and
+ * DCCIMVAC.
+ *
+ * It is however not transparent for the following cache maintenance
+ * operations: DCISW, DCCSW, DCCISW, ICIALLUIS and ICIALLU which is precisely
+ * what we are patching here with our BUILD_RAC_CACHE_OP here.
+ */
+
+BUILD_RAC_CACHE_OP(kern_cache_all, nobarrier);
+BUILD_RAC_CACHE_OP(kern_cache_louis, nobarrier);
+BUILD_RAC_CACHE_OP(icache_all, dsb());
+
+static void b15_rac_enable(void)
+{
+	unsigned int cpu;
+	u32 enable = 0;
+
+	for_each_possible_cpu(cpu)
+		enable |= (RAC_DATA_INST_EN_MASK << (cpu * RAC_CPU_SHIFT));
+
+	b15_rac_disable_and_flush();
+	__b15_rac_enable(enable);
+}
+
+static int b15_rac_reboot_notifier(struct notifier_block *nb,
+				   unsigned long action,
+				   void *data)
+{
+	/* During kexec, we are not yet migrated on the boot CPU, so we need to
+	 * make sure we are SMP safe here. Once the RAC is disabled, flag it as
+	 * suspended such that the hotplug notifier returns early.
+	 */
+	if (action == SYS_RESTART) {
+		spin_lock(&rac_lock);
+		b15_rac_disable_and_flush();
+		clear_bit(RAC_ENABLED, &b15_rac_flags);
+		set_bit(RAC_SUSPENDED, &b15_rac_flags);
+		spin_unlock(&rac_lock);
+	}
+
+	return NOTIFY_DONE;
+}
+
+static struct notifier_block b15_rac_reboot_nb = {
+	.notifier_call	= b15_rac_reboot_notifier,
+};
+
+#ifdef CONFIG_HOTPLUG_CPU
+static void b15_rac_hotplug_start(void)
+{
+	/* Indicate that we are starting a hotplug procedure */
+	clear_bit(RAC_ENABLED, &b15_rac_flags);
+
+	/* Disable the readahead cache and save its value to a global */
+	rac_config0_reg = b15_rac_disable_and_flush();
+}
+
+static void b15_rac_hotplug_end(void)
+{
+	/* And enable it */
+	__b15_rac_enable(rac_config0_reg);
+	set_bit(RAC_ENABLED, &b15_rac_flags);
+}
+
+/* The CPU hotplug case is the most interesting one, we basically need to make
+ * sure that the RAC is disabled for the entire system prior to having a CPU
+ * die, in particular prior to this dying CPU having exited the coherency
+ * domain.
+ *
+ * Once this CPU is marked dead, we can safely re-enable the RAC for the
+ * remaining CPUs in the system which are still online.
+ *
+ * Offlining a CPU is the problematic case, onlining a CPU is not much of an
+ * issue since the CPU and its cache-level hierarchy will start filling with
+ * the RAC disabled, so L1 and L2 only.
+ *
+ * In this function, we should NOT have to verify any unsafe setting/condition
+ * b15_rac_base:
+ *
+ *   It is protected by the RAC_ENABLED flag which is cleared by default, and
+ *   being cleared when initial procedure is done. b15_rac_base had been set at
+ *   that time.
+ *
+ * RAC_ENABLED:
+ *   There is a small timing windows, in b15_rac_init(), between
+ *      register_cpu_notifier(&b15_rac_cpu_nb);
+ *      ...
+ *      set RAC_ENABLED
+ *   However, there is no hotplug activity based on the Linux booting procedure.
+ *
+ * Regarding the notification actions, we will receive CPU_DOWN_PREPARE,
+ * CPU_DOWN_FAILED, CPU_DYING, CPU_DEAD, and CPU_POST_DEAD notification (see
+ * _cpu_down() for detail).
+ *
+ * Since we have to disable RAC for all cores, we keep RAC on as long as as
+ * possible (disable it as late as possible) to gain the cache benefit.
+ *
+ * Thus, CPU_DYING/CPU_DEAD pair are chosen.
+ *
+ * We are choosing not do disable the RAC on a per-CPU basis, here, if we did
+ * we would want to consider disabling it as early as possible to benefit the
+ * other active CPUs.
+ */
+static int b15_rac_cpu_notify(struct notifier_block *self,
+			      unsigned long action, void *hcpu)
+{
+	action &= ~CPU_TASKS_FROZEN;
+
+	if (action != CPU_DYING && action != CPU_DOWN_FAILED &&
+	    action != CPU_DEAD)
+		return NOTIFY_OK;
+
+	/* During kexec/reboot, the RAC is disabled via the reboot notifier
+	 * return early here.
+	 */
+	if (test_bit(RAC_SUSPENDED, &b15_rac_flags))
+		return NOTIFY_DONE;
+
+	spin_lock(&rac_lock);
+	switch (action) {
+	/* called on the dying CPU, exactly what we want */
+	case CPU_DYING:
+		b15_rac_hotplug_start();
+		break;
+
+	/* called on a non-dying CPU, what we want too */
+	case CPU_DOWN_FAILED:
+	case CPU_DEAD:
+		b15_rac_hotplug_end();
+		break;
+	}
+	spin_unlock(&rac_lock);
+
+	return NOTIFY_OK;
+}
+
+static struct notifier_block b15_rac_cpu_nb = {
+	.notifier_call	= b15_rac_cpu_notify,
+};
+#endif /* CONFIG_HOTPLUG_CPU */
+
+#ifdef CONFIG_PM_SLEEP
+static int b15_rac_suspend(void)
+{
+	/* Suspend the read-ahead cache oeprations, forcing our cache
+	 * implementation to fallback to the regular ARMv7 calls.
+	 *
+	 * We are guaranteed to be running on the boot CPU at this point and
+	 * with every other CPU quiesced, so setting RAC_SUSPENDED is not racy
+	 * here.
+	 */
+	rac_config0_reg = b15_rac_disable_and_flush();
+	set_bit(RAC_SUSPENDED, &b15_rac_flags);
+
+	return 0;
+}
+
+static void b15_rac_resume(void)
+{
+	/* Coming out of a S3 suspend/resume cycle, the read-ahead cache
+	 * register RAC_CONFIG0_REG will be restored to its default value, make
+	 * sure we re-enable it and set the enable flag, we are also guaranteed
+	 * to run on the boot CPU, so not racy again.
+	 */
+	__b15_rac_enable(rac_config0_reg);
+	clear_bit(RAC_SUSPENDED, &b15_rac_flags);
+}
+
+static struct syscore_ops b15_rac_syscore_ops = {
+	.suspend	= b15_rac_suspend,
+	.resume		= b15_rac_resume,
+};
+#endif
+
+static int __init b15_rac_init(void)
+{
+	struct device_node *dn;
+	int ret = 0, cpu;
+	u32 reg, en_mask = 0;
+
+	dn = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl");
+	if (!dn)
+		return -ENODEV;
+
+	if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n"))
+		goto out;
+
+	b15_rac_base = of_iomap(dn, 0);
+	if (!b15_rac_base) {
+		pr_err("failed to remap BIU control base\n");
+		ret = -ENOMEM;
+		goto out;
+	}
+
+	ret = register_reboot_notifier(&b15_rac_reboot_nb);
+	if (ret) {
+		pr_err("failed to register reboot notifier\n");
+		iounmap(b15_rac_base);
+		goto out;
+	}
+
+#ifdef CONFIG_HOTPLUG_CPU
+	ret = register_cpu_notifier(&b15_rac_cpu_nb);
+	if (ret) {
+		pr_err("failed to register notifier block\n");
+		iounmap(b15_rac_base);
+		unregister_reboot_notifier(&b15_rac_reboot_nb);
+		goto out;
+	}
+#endif
+
+#ifdef CONFIG_PM_SLEEP
+	register_syscore_ops(&b15_rac_syscore_ops);
+#endif
+
+	spin_lock(&rac_lock);
+	reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG);
+	for_each_possible_cpu(cpu)
+		en_mask |= ((1 << RACPREFDATA_SHIFT) << (cpu * RAC_CPU_SHIFT));
+	WARN(reg & en_mask, "Read-ahead cache not previously disabled\n");
+
+	b15_rac_enable();
+	set_bit(RAC_ENABLED, &b15_rac_flags);
+	spin_unlock(&rac_lock);
+
+	pr_info("Broadcom Brahma-B15 readahead cache at: 0x%p\n",
+		b15_rac_base + RAC_CONFIG0_REG);
+
+out:
+	of_node_put(dn);
+	return ret;
+}
+arch_initcall(b15_rac_init);
diff --git a/arch/arm/mm/cache-v7.S b/arch/arm/mm/cache-v7.S
index a134d8a..a0197a0 100644
--- a/arch/arm/mm/cache-v7.S
+++ b/arch/arm/mm/cache-v7.S
@@ -15,6 +15,7 @@
 #include <asm/assembler.h>
 #include <asm/errno.h>
 #include <asm/unwind.h>
+#include <asm/hardware/cache-b15-rac.h>
 
 #include "proc-macros.S"
 
@@ -446,3 +447,23 @@
 
 	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
 	define_cache_functions v7
+
+	/* The Broadcom Brahma-B15 read-ahead cache requires some modifications
+	 * to the v7_cache_fns, we only override the ones we need
+	 */
+#ifndef CONFIG_CACHE_B15_RAC
+	globl_equ	b15_flush_icache_all,		v7_flush_icache_all
+	globl_equ	b15_flush_kern_cache_all,	v7_flush_kern_cache_all
+	globl_equ	b15_flush_kern_cache_louis,	v7_flush_kern_cache_louis
+#endif
+	globl_equ	b15_flush_user_cache_all,	v7_flush_user_cache_all
+	globl_equ	b15_flush_user_cache_range,	v7_flush_user_cache_range
+	globl_equ	b15_coherent_kern_range,	v7_coherent_kern_range
+	globl_equ	b15_coherent_user_range,	v7_coherent_user_range
+	globl_equ	b15_flush_kern_dcache_area,	v7_flush_kern_dcache_area
+
+	globl_equ	b15_dma_map_area,		v7_dma_map_area
+	globl_equ	b15_dma_unmap_area,		v7_dma_unmap_area
+	globl_equ	b15_dma_flush_range,		v7_dma_flush_range
+
+	define_cache_functions b15
diff --git a/arch/arm/mm/init.c b/arch/arm/mm/init.c
index 7f8cd1b..befcdb4 100644
--- a/arch/arm/mm/init.c
+++ b/arch/arm/mm/init.c
@@ -265,12 +265,26 @@
 
 	arm_mm_memblock_reserve();
 
+#ifdef CONFIG_BRCMSTB
+	/*
+	 * Moved before platform reserve so that we can find all the
+	 * non-cma, non-bmem reserved areas without implementing interval
+	 * subtraction
+	 */
+	early_init_fdt_reserve_self();
+	early_init_fdt_scan_reserved_mem();
+
+	/* reserve any platform specific memblock areas */
+	if (mdesc->reserve)
+		mdesc->reserve();
+#else
 	/* reserve any platform specific memblock areas */
 	if (mdesc->reserve)
 		mdesc->reserve();
 
 	early_init_fdt_reserve_self();
 	early_init_fdt_scan_reserved_mem();
+#endif
 
 	/* reserve memory for DMA contiguous allocations */
 	dma_contiguous_reserve(arm_dma_limit);
diff --git a/arch/arm/mm/mmu.c b/arch/arm/mm/mmu.c
index 4867f5d..2856344 100644
--- a/arch/arm/mm/mmu.c
+++ b/arch/arm/mm/mmu.c
@@ -1080,10 +1080,15 @@
 static void * __initdata vmalloc_min =
 	(void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET);
 
+static bool __initdata brcmstb_did_override_vmalloc;
+
 /*
  * vmalloc=size forces the vmalloc area to be exactly 'size'
  * bytes. This can be used to increase (or decrease) the vmalloc
  * area - the default is 240m.
+ *
+ * NOTE: different default for BRCMSTB with >= 1GiB RAM, see
+ * brcmstb_maybe_increase_vmalloc() below.
  */
 static int __init early_vmalloc(char *arg)
 {
@@ -1102,20 +1107,43 @@
 	}
 
 	vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve);
+	brcmstb_did_override_vmalloc = true;
 	return 0;
 }
 early_param("vmalloc", early_vmalloc);
 
+static void __init brcmstb_maybe_increase_vmalloc(void)
+{
+#if 0
+#ifdef CONFIG_BRCMSTB
+	if (brcmstb_did_override_vmalloc)
+		return;
+	if (meminfo.bank[0].size >= SZ_1G || meminfo.nr_banks > 1) {
+		vmalloc_min = (void *)(VMALLOC_END - (744 << 20) -
+				VMALLOC_OFFSET);
+	}
+#else
+	return;
+#endif
+#endif
+        // TODO(jnewlin):  meminfo is gone baby gone in the 4.1kernel, figure
+        // out an alternative.
+        return;
+}
+
 phys_addr_t arm_lowmem_limit __initdata = 0;
 
 void __init sanity_check_meminfo(void)
 {
 	phys_addr_t memblock_limit = 0;
 	int highmem = 0;
-	phys_addr_t vmalloc_limit = __pa(vmalloc_min - 1) + 1;
+	phys_addr_t vmalloc_limit;
 	struct memblock_region *reg;
 	bool should_use_highmem = false;
 
+	brcmstb_maybe_increase_vmalloc();
+	vmalloc_limit = __pa(vmalloc_min - 1) + 1;
+
 	for_each_memblock(memory, reg) {
 		phys_addr_t block_start = reg->base;
 		phys_addr_t block_end = reg->base + reg->size;
diff --git a/arch/arm/mm/proc-v7-2level.S b/arch/arm/mm/proc-v7-2level.S
index c6141a5..febf530 100644
--- a/arch/arm/mm/proc-v7-2level.S
+++ b/arch/arm/mm/proc-v7-2level.S
@@ -7,7 +7,6 @@
  * it under the terms of the GNU General Public License version 2 as
  * published by the Free Software Foundation.
  */
-
 #define TTB_S		(1 << 1)
 #define TTB_RGN_NC	(0 << 3)
 #define TTB_RGN_OC_WBWA	(1 << 3)
diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 8e1ea43..8130303 100644
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -509,7 +509,7 @@
 	/*
 	 * Standard v7 proc info content
 	 */
-.macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions
+.macro __v7_proc name, initfunc, mm_mmuflags = 0, io_mmuflags = 0, hwcaps = 0, proc_fns = v7_processor_functions, cache_fns = v7_cache_fns
 	ALT_SMP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
 			PMD_SECT_AF | PMD_FLAGS_SMP | \mm_mmuflags)
 	ALT_UP(.long	PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_AP_READ | \
@@ -525,7 +525,7 @@
 	.long	\proc_fns
 	.long	v7wbi_tlb_fns
 	.long	v6_user_fns
-	.long	v7_cache_fns
+	.long	\cache_fns
 .endm
 
 #ifndef CONFIG_ARM_LPAE
diff --git a/arch/mips/Kbuild.platforms b/arch/mips/Kbuild.platforms
index a96c81d..b7a4408 100644
--- a/arch/mips/Kbuild.platforms
+++ b/arch/mips/Kbuild.platforms
@@ -7,6 +7,7 @@
 platforms += bcm47xx
 platforms += bcm63xx
 platforms += bmips
+platforms += brcmstb
 platforms += cavium-octeon
 platforms += cobalt
 platforms += dec
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index db45961..e761ccc 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -11,6 +11,8 @@
 	select HAVE_IDE
 	select HAVE_OPROFILE
 	select HAVE_PERF_EVENTS
+	select HAVE_PERF_REGS
+	select HAVE_PERF_USER_STACK_DUMP
 	select PERF_USE_VMALLOC
 	select HAVE_ARCH_KGDB
 	select HAVE_ARCH_SECCOMP_FILTER
@@ -37,6 +39,7 @@
 	select GENERIC_IRQ_PROBE
 	select GENERIC_IRQ_SHOW
 	select GENERIC_PCI_IOMAP
+	select GENERIC_SCHED_CLOCK
 	select HAVE_ARCH_JUMP_LABEL
 	select ARCH_WANT_IPC_PARSE_VERSION
 	select IRQ_FORCED_THREADING
@@ -216,6 +219,11 @@
 	help
 	 Support for BCM63XX based boards
 
+config BRCMSTB
+	bool "Broadcom BCM7XXX based boards"
+	help
+	  Support for BCM7XXX based boards
+
 config MIPS_COBALT
 	bool "Cobalt Server"
 	select CEVT_R4K
@@ -996,6 +1004,9 @@
 
 endmenu
 
+source "drivers/brcmstb/Kconfig"
+source "arch/mips/bruno/Kconfig"
+
 config RWSEM_GENERIC_SPINLOCK
 	bool
 	default y
@@ -1793,6 +1804,7 @@
 	select MIPS_L1_CACHE_SHIFT_7
 	select SYS_SUPPORTS_SMP
 	select SYS_SUPPORTS_HOTPLUG_CPU
+	select MIPS_PERF_SHARED_TC_COUNTERS
 
 config SYS_HAS_CPU_LOONGSON3
 	bool
diff --git a/arch/mips/brcmstb/Makefile b/arch/mips/brcmstb/Makefile
new file mode 100644
index 0000000..15180da
--- /dev/null
+++ b/arch/mips/brcmstb/Makefile
@@ -0,0 +1,4 @@
+obj-y			+= prom.o bmips.o memory.o irq.o time.o
+obj-$(CONFIG_BRCM_HAS_STANDBY)	+= standby.o
+obj-$(CONFIG_BRCM_HAS_AON) += s3_standby.o
+obj-$(CONFIG_BCM7435) += bmips_5xxx_init.o
diff --git a/arch/mips/brcmstb/Platform b/arch/mips/brcmstb/Platform
new file mode 100644
index 0000000..eac8773
--- /dev/null
+++ b/arch/mips/brcmstb/Platform
@@ -0,0 +1,8 @@
+#
+# Broadcom set-top platforms
+#
+platform-$(CONFIG_BRCMSTB)	+= brcmstb/
+cflags-$(CONFIG_BRCMSTB)	+= -I$(srctree)/arch/mips/include/asm/mach-brcmstb
+load-$(CONFIG_BRCMSTB)		+= 0x80001000
+
+cflags-$(CONFIG_NO_INLINE)	+= -fno-inline
diff --git a/arch/mips/brcmstb/bmips.c b/arch/mips/brcmstb/bmips.c
new file mode 100644
index 0000000..0e7fd41
--- /dev/null
+++ b/arch/mips/brcmstb/bmips.c
@@ -0,0 +1,614 @@
+/*
+ * Copyright (C) 2012 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/types.h>
+#include <linux/dma-mapping.h>
+#include <linux/mm.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/version.h>
+#include <linux/compiler.h>
+
+#include <asm/cpu-info.h>
+#include <asm/mipsregs.h>
+#include <asm/barrier.h>
+#include <asm/cacheflush.h>
+#include <asm/r4kcache.h>
+#include <asm/asm-offsets.h>
+#include <asm/inst.h>
+#include <asm/fpu.h>
+#include <asm/hazards.h>
+#include <asm/cpu-features.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <dma-coherence.h>
+
+/***********************************************************************
+ * MIPS features, caches, and bus interface
+ ***********************************************************************/
+
+void brcmstb_cpu_setup(void)
+{
+#if   defined(CONFIG_CPU_BMIPS3300)
+
+	unsigned long cbr = __BMIPS_GET_CBR();
+
+	/* Set BIU to async mode */
+	set_c0_brcm_bus_pll(BIT(22));
+	__sync();
+
+#ifdef BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT
+	/* Enable write gathering */
+	BDEV_WR_RB(BCHP_MISB_BRIDGE_WG_MODE_N_TIMEOUT, 0x264);
+
+	/* Enable split mode */
+	BDEV_WR_RB(BCHP_MISB_BRIDGE_MISB_SPLIT_MODE, 0x1);
+	__sync();
+#endif
+
+	/* put the BIU back in sync mode */
+	clear_c0_brcm_bus_pll(BIT(22));
+
+	/* clear BHTD to enable branch history table */
+	clear_c0_brcm_reset(BIT(16));
+
+	/* Flush and enable RAC */
+	DEV_WR_RB(cbr + BMIPS_RAC_CONFIG, 0x100);
+	DEV_WR_RB(cbr + BMIPS_RAC_CONFIG, 0xf);
+	DEV_WR_RB(cbr + BMIPS_RAC_ADDRESS_RANGE, 0x0fff0000);
+
+#elif defined(CONFIG_CPU_BMIPS4380)
+
+	unsigned long cbr = __BMIPS_GET_CBR();
+
+	/* CRBMIPS438X-164: CBG workaround */
+	switch (read_c0_prid()) {
+	case 0x2a040:
+	case 0x2a042:
+	case 0x2a044:
+	case 0x2a060:
+		DEV_UNSET(cbr + BMIPS_L2_CONFIG, 0x07000000);
+	}
+
+	/* clear BHTD to enable branch history table */
+	clear_c0_brcm_config_0(BIT(21));
+
+	/* XI/ROTR enable */
+	if (kernel_uses_smartmips_rixi) {
+		set_c0_brcm_config_0(BIT(23));
+		set_c0_brcm_cmt_ctrl(BIT(15));
+	}
+
+#elif defined(CONFIG_CPU_BMIPS5000)
+
+	/* enable RDHWR, BRDHWR */
+	set_c0_brcm_config(BIT(17) | BIT(21));
+
+	if (kernel_uses_smartmips_rixi) {
+		/* XI enable */
+		set_c0_brcm_config(BIT(27));
+
+		/* enable MIPS32R2 ROR instruction for XI TLB handlers */
+		__asm__ __volatile__(
+		"	li	$8, 0x5a455048\n"
+		"	.word	0x4088b00f\n"	/* mtc0 $8, $22, 15 */
+		"	nop; nop; nop\n"
+		"	.word	0x4008b008\n"	/* mfc0 $8, $22, 8 */
+		"	lui	$9, 0x0100\n"
+		"	or	$8, $9\n"
+		"	.word	0x4088b008\n"	/* mtc0 $8, $22, 8 */
+		"	sync\n"
+		"	li	$8, 0x0\n"
+		"	.word	0x4088b00f\n"
+		"	nop; nop; nop\n"
+		: : : "$8", "$9");
+	}
+
+#if defined(CONFIG_BCM7425)
+	/* Disable PREF 30 */
+	__asm__ __volatile__(
+	"	li	$8, 0x5a455048\n"
+	"	.word	0x4088b00f\n"
+	"	nop; nop; nop\n"
+	"	.word	0x4008b008\n"
+	"	lui	$9, 0x0800\n"
+	"	or	$8, $8, $9\n"
+	"	.word	0x4088b008\n"
+	"	sync\n"
+	"	li	$8, 0x0\n"
+	"	.word	0x4088b00f\n"
+	"	nop; nop; nop\n"
+	: : : "$8", "$9");
+#endif
+
+#if defined(CONFIG_BCM7425) || defined(CONFIG_BCM7429)
+	/* Disable JTB and CRS */
+	__asm__ __volatile__(
+	"	li	$8, 0x5a455048\n"
+	"	.word	0x4088b00f\n"
+	"	nop; nop; nop\n"
+	"	.word	0x4008b008\n"
+	"	li	$9, 0xfbffffff\n"
+	"	and	$8, $8, $9\n"
+	"	li	$9, 0x0400c000\n"
+	"	or	$8, $8, $9\n"
+	"	.word	0x4088b008\n"
+	"	sync\n"
+	"	li	$8, 0x0\n"
+	"	.word	0x4088b00f\n"
+	"	nop; nop; nop\n"
+	: : : "$8", "$9");
+#endif
+#endif
+}
+
+/***********************************************************************
+ * Simulate privileged instructions (RDHWR, MFC0) and unaligned accesses
+ ***********************************************************************/
+
+#define OPCODE 0xfc000000
+#define BASE   0x03e00000
+#define RT     0x001f0000
+#define OFFSET 0x0000ffff
+#define LL     0xc0000000
+#define SC     0xe0000000
+#define SPEC0  0x00000000
+#define SPEC3  0x7c000000
+#define RD     0x0000f800
+#define FUNC   0x0000003f
+#define SYNC   0x0000000f
+#define RDHWR  0x0000003b
+
+#define BRDHWR 0xec000000
+#define OP_MFC0 0x40000000
+
+int brcm_simulate_opcode(struct pt_regs *regs, unsigned int opcode)
+{
+	struct thread_info *ti = task_thread_info(current);
+	int rd = (opcode & RD) >> 11;
+	int rt = (opcode & RT) >> 16;
+
+	/* PR34054: use alternate RDHWR instruction encoding */
+	if (((opcode & OPCODE) == BRDHWR && (opcode & FUNC) == RDHWR)
+	    || ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR)) {
+
+		if (rd == 29) {
+			regs->regs[rt] = ti->tp_value;
+			atomic_inc(&brcm_rdhwr_count);
+			return 0;
+		}
+	}
+
+	/* emulate MFC0 $15 for optimized memcpy() CPU detection */
+	if ((opcode & OPCODE) == OP_MFC0 &&
+	    (opcode & OFFSET) == (15 << 11)) {
+		regs->regs[rt] = read_c0_prid();
+		return 0;
+	}
+
+	return -1;	/* unhandled */
+}
+
+int brcm_unaligned_fp(void __user *addr, union mips_instruction *insn,
+	struct pt_regs *regs)
+{
+	unsigned int op = insn->i_format.opcode;
+	unsigned int rt = insn->i_format.rt;
+	unsigned int res;
+	int wordlen = 8;
+
+	/* on r4k, only the even slots ($f0, $f2, ...) are used */
+	u8 *fprptr = (u8 *)current + THREAD_FPR0 + (rt >> 1) *
+		(THREAD_FPR2 - THREAD_FPR0);
+
+	if (op == lwc1_op || op == swc1_op) {
+		wordlen = 4;
+#ifdef __LITTLE_ENDIAN
+		/* LE: LSW ($f0) precedes MSW ($f1) */
+		fprptr += (rt & 1) ? 4 : 0;
+#else
+		/* BE: MSW ($f1) precedes LSW ($f0) */
+		fprptr += (rt & 1) ? 0 : 4;
+#endif
+	}
+
+	preempt_disable();
+	if (is_fpu_owner())
+		save_fp(current);
+	else
+		own_fpu(1);
+
+	if (op == lwc1_op || op == ldc1_op) {
+		if (!access_ok(VERIFY_READ, addr, wordlen))
+			goto sigbus;
+		/*
+		 * FPR load: copy from user struct to kernel saved
+		 * register struct, then restore all FPRs
+		 */
+		__asm__ __volatile__ (
+		"1:	lb	%0, 0(%3)\n"
+		"	sb	%0, 0(%2)\n"
+		"	addiu	%2, 1\n"
+		"	addiu	%3, 1\n"
+		"	addiu	%1, -1\n"
+		"	bnez	%1, 1b\n"
+		"	li	%0, 0\n"
+		"3:\n"
+		"	.section .fixup,\"ax\"\n"
+		"4:	li	%0, %4\n"
+		"	j	3b\n"
+		"	.previous\n"
+		"	.section __ex_table,\"a\"\n"
+		STR(PTR)" 1b,4b\n"
+		"	.previous\n"
+			: "=&r" (res), "+r" (wordlen),
+			  "+r" (fprptr), "+r" (addr)
+			: "i" (-EFAULT));
+		if (res)
+			goto fault;
+
+		restore_fp(current);
+	} else {
+		if (!access_ok(VERIFY_WRITE, addr, wordlen))
+			goto sigbus;
+		/*
+		 * FPR store: copy from kernel saved register struct
+		 * to user struct
+		 */
+		__asm__ __volatile__ (
+		"2:	lb	%0, 0(%2)\n"
+		"1:	sb	%0, 0(%3)\n"
+		"	addiu	%2, 1\n"
+		"	addiu	%3, 1\n"
+		"	addiu	%1, -1\n"
+		"	bnez	%1, 2b\n"
+		"	li	%0, 0\n"
+		"3:\n"
+		"	.section .fixup,\"ax\"\n"
+		"4:	li	%0, %4\n"
+		"	j	3b\n"
+		"	.previous\n"
+		"	.section __ex_table,\"a\"\n"
+		STR(PTR)" 1b,4b\n"
+		"	.previous\n"
+			: "=&r" (res), "+r" (wordlen),
+			  "+r" (fprptr), "+r" (addr)
+			: "i" (-EFAULT));
+		if (res)
+			goto fault;
+	}
+	preempt_enable();
+
+	atomic_inc(&brcm_unaligned_fp_count);
+	return 0;
+
+sigbus:
+	preempt_enable();
+	return -EINVAL;
+
+fault:
+	preempt_enable();
+	return -EFAULT;
+}
+
+/***********************************************************************
+ * CPU divisor / PLL manipulation
+ ***********************************************************************/
+/*
+ * 0: CP0 COUNT/COMPARE frequency depends on divisor
+ * 1: CP0 COUNT/COMPARE frequency does not depend on divisor
+ */
+static int fixed_counter_freq;
+
+#if defined(CONFIG_BCM7425B0) || defined(CONFIG_BCM7344B0) || \
+	defined(CONFIG_BCM7346B0)
+/* SWLINUX-2063: MIPS cannot enter divide-by-N mode */
+#define	BROKEN_MIPS_DIVIDER
+#endif
+
+/* MIPS active standby on 7550 */
+#define CPU_PLL_MODE1		216000
+
+/*
+ * current ADJUSTED base frequency (reflects the current PLL settings)
+ * brcm_cpu_khz (in time.c) always has the ORIGINAL clock frequency and
+ *   is never changed after bootup
+ */
+unsigned long brcm_adj_cpu_khz;
+
+/* multiplier used in brcm_fixup_ticks to scale the # of ticks
+ * 0               - no fixup needed
+ * any other value - factor * 2^16 */
+static unsigned long fixup_ticks_ratio;
+
+/* current CPU divisor, as set by the user */
+static __maybe_unused int cpu_div = 1;
+
+/*
+ * MIPS clockevent code always assumes the original boot-time CP0 clock rate.
+ * This function scales the number of ticks according to the current HW
+ * settings.
+ */
+unsigned long brcm_fixup_ticks(unsigned long delta)
+{
+	unsigned long long tmp = delta;
+
+	if (unlikely(!brcm_adj_cpu_khz))
+		brcm_adj_cpu_khz = brcm_cpu_khz;
+
+	if (likely(!fixup_ticks_ratio))
+		return delta;
+
+	tmp *= fixup_ticks_ratio;
+	tmp >>= 16;
+
+	return (unsigned long)tmp;
+}
+
+static unsigned int orig_udelay_val[NR_CPUS];
+
+struct spd_change {
+	int			old_div;
+	int			new_div;
+	int			old_base;
+	int			new_base;
+};
+
+void brcm_set_cpu_speed(void *arg)
+{
+	struct spd_change *c = arg;
+	uint32_t new_div = (uint32_t)c->new_div;
+	unsigned long __maybe_unused count, compare, delta;
+	signed long sdelta;
+	int cpu = smp_processor_id();
+	uint32_t __maybe_unused tmp0, tmp1, tmp2, tmp3;
+
+	/* scale udelay_val */
+	if (!orig_udelay_val[cpu])
+		orig_udelay_val[cpu] = current_cpu_data.udelay_val;
+
+	if (c->new_base == brcm_cpu_khz)
+		current_cpu_data.udelay_val = orig_udelay_val[cpu] / new_div;
+	else
+		current_cpu_data.udelay_val =
+			(unsigned long long)orig_udelay_val[cpu] *
+			c->new_base / (new_div * c->old_base);
+
+	/* scale any pending timer events */
+	compare = read_c0_compare();
+	count = read_c0_count();
+
+	sdelta = (long)compare - (long)count;
+	if (sdelta > 0) {
+		if (!fixed_counter_freq)
+			delta = ((unsigned long long)sdelta *
+				c->old_div * c->new_base) /
+				(new_div * c->old_base);
+		else
+			delta = ((unsigned long long)sdelta *
+				c->new_base) / c->old_base;
+	write_c0_compare(read_c0_count() + delta);
+	}
+
+	if (cpu != 0)
+		return;
+
+#if defined(CONFIG_BRCM_CPU_PLL)
+	brcm_adj_cpu_khz = c->new_base;
+#if defined(CONFIG_BCM7550)
+	if (brcm_adj_cpu_khz == CPU_PLL_MODE1) {
+		/* 216Mhz */
+		BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_NEXT_CFG_3A,
+			0x801b2806);
+		BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_NEXT_CFG_3B,
+			0x00300618);
+	} else {
+		/* 324Mhz */
+		BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_NEXT_CFG_3A,
+			0x801b2806);
+		BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_NEXT_CFG_3B,
+			0x00300418);
+	}
+	BDEV_WR_RB(BCHP_VCXO_CTL_CONFIG_FSM_PLL_UPDATE, 1);
+#else
+#error CPU PLL adjustment not supported on this chip
+#endif
+#endif
+
+	if ((brcm_adj_cpu_khz == brcm_cpu_khz) &&
+	    (fixed_counter_freq || new_div == 1)) {
+		fixup_ticks_ratio = 0;
+	} else {
+		fixup_ticks_ratio =
+			((unsigned long long)brcm_adj_cpu_khz << 16) /
+			 (unsigned long long)brcm_cpu_khz;
+		if (!fixed_counter_freq)
+			fixup_ticks_ratio /= new_div;
+	}
+
+	printk(KERN_DEBUG "ratio=%lu adj=%lu freq=%lu new_div=%d\n",
+	       fixup_ticks_ratio, brcm_adj_cpu_khz, brcm_cpu_khz, new_div);
+	new_div = ffs(new_div) - 1;
+
+	/* see BMIPS datasheet, CP0 register $22 */
+
+#if defined(CONFIG_CPU_BMIPS3300)
+	change_c0_brcm_bus_pll(0x07 << 22, (new_div << 23) | (0 << 22));
+#elif defined(CONFIG_CPU_BMIPS5000)
+	change_c0_brcm_mode(0x0f << 4, (1 << 7) | (new_div << 4));
+#elif defined(CONFIG_CPU_BMIPS4380)
+	__asm__ __volatile__(
+	"	.set	push\n"
+	"	.set	noreorder\n"
+	"	.set	nomacro\n"
+	"	.set	mips32\n"
+	/* get kseg1 address for CBA into %3 */
+	"	mfc0	%3, $22, 6\n"
+	"	li	%2, 0xfffc0000\n"
+	"	and	%3, %2\n"
+	"	li	%2, 0xa0000000\n"
+	"	add	%3, %2\n"
+	/* %1 = async bit, %2 = mask out everything but 30:28 */
+	"	lui	%1, 0x1000\n"
+	"	lui	%2, 0x8fff\n"
+	"	beqz	%0, 1f\n"
+	"	ori	%2, 0xffff\n"
+	/* handle SYNC to ASYNC */
+	"	sync\n"
+	"	mfc0	%4, $22, 5\n"
+	"	and	%4, %2\n"
+	"	or	%4, %1\n"
+	"	mtc0	%4, $22, 5\n"
+	"	nop\n"
+	"	nop\n"
+	"	lw	%2, 4(%3)\n"
+	"	sw	%2, 4(%3)\n"
+	"	sync\n"
+	"	sll	%0, 29\n"
+	"	or	%4, %0\n"
+	"	mtc0	%4, $22, 5\n"
+	"	nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop\n"
+	"	b	2f\n"
+	"	nop\n"
+	/* handle ASYNC to SYNC */
+	"1:\n"
+	"	mfc0	%4, $22, 5\n"
+	"	and	%4, %2\n"
+	"	or	%4, %1\n"
+	"	mtc0	%4, $22, 5\n"
+	"	nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop\n"
+	"	sync\n"
+	"	and	%4, %2\n"
+	"	mtc0	%4, $22, 5\n"
+	"	nop\n"
+	"	nop\n"
+	"	lw	%2, 4(%3)\n"
+	"	sw	%2, 4(%3)\n"
+	"	sync\n"
+	"2:\n"
+	"	.set	pop\n"
+	: "+r" (new_div),
+	  "=&r" (tmp0), "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3));
+#endif
+}
+
+#ifdef CONFIG_BRCM_CPU_DIV
+
+ssize_t brcm_pm_show_cpu_div(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n", cpu_div);
+}
+
+ssize_t brcm_pm_store_cpu_div(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	struct spd_change chg;
+
+	if (sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	if (val != 1 && val != 2 && val != 4 && val != 8
+#if defined(CONFIG_CPU_BMIPS5000)
+		&& val != 16
+#endif
+			)
+		return -EINVAL;
+
+#if defined(BROKEN_MIPS_DIVIDER)
+	return val == 1 ? count : -EINVAL;
+#endif
+
+	chg.old_div = cpu_div;
+	chg.new_div = val;
+	chg.old_base = brcm_adj_cpu_khz;
+	chg.new_base = brcm_adj_cpu_khz;
+
+	on_each_cpu(brcm_set_cpu_speed, &chg, 1);
+	cpu_div = val;
+	return count;
+}
+
+#endif /* CONFIG_BRCM_CPU_DIV */
+
+#ifdef CONFIG_BRCM_CPU_PLL
+
+static int cpu_pll_mode;
+
+ssize_t brcm_pm_show_cpu_pll(struct device *dev,
+	struct device_attribute *attr, char *buf)
+{
+	return snprintf(buf, PAGE_SIZE, "%d\n", cpu_pll_mode);
+}
+
+ssize_t brcm_pm_store_cpu_pll(struct device *dev,
+	struct device_attribute *attr, const char *buf, size_t count)
+{
+	int val;
+	struct spd_change chg;
+
+	if (sscanf(buf, "%d", &val) != 1)
+		return -EINVAL;
+
+	if (cpu_pll_mode == val)
+		return count;
+
+	switch (val) {
+	case 0:
+		chg.new_base = brcm_cpu_khz;
+		break;
+	case 1:
+		chg.new_base = CPU_PLL_MODE1;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	chg.old_div = cpu_div;
+	chg.new_div = cpu_div;
+	chg.old_base = brcm_adj_cpu_khz;
+	on_each_cpu(brcm_set_cpu_speed, &chg, 1);
+
+	cpu_pll_mode = val;
+	return count;
+}
+
+#endif /* CONFIG_BRCM_CPU_PLL */
+
+static int bmips_check_caps(void)
+{
+	unsigned long __maybe_unused config;
+#ifdef CONFIG_CPU_BMIPS5000
+	fixed_counter_freq = 1;
+#elif defined(CONFIG_CPU_BMIPS4380)
+	config = read_c0_brcm_config();
+	fixed_counter_freq = !!(config & 0x40);
+#else
+	fixed_counter_freq = 0;
+#endif
+	printk(KERN_INFO "PM: CP0 COUNT/COMPARE frequency %s on divisor\n",
+	       fixed_counter_freq ? "does not depend" : "depends");
+	return 0;
+}
+late_initcall(bmips_check_caps);
diff --git a/arch/mips/brcmstb/bmips_5xxx_init.S b/arch/mips/brcmstb/bmips_5xxx_init.S
new file mode 100644
index 0000000..48c40ae
--- /dev/null
+++ b/arch/mips/brcmstb/bmips_5xxx_init.S
@@ -0,0 +1,753 @@
+
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2011-2012 by Broadcom Corporation
+ *
+ * Init for bmips 5000.
+ * Used to init second core in dual core 5000's.
+ */
+
+#include <linux/init.h>
+
+#include <asm/asm.h>
+#include <asm/asmmacro.h>
+#include <asm/cacheops.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/stackframe.h>
+#include <asm/addrspace.h>
+#include <asm/hazards.h>
+#include <asm/bmips.h>
+
+#ifdef CONFIG_CPU_BMIPS5000
+
+
+#define cacheop(kva, size, linesize, op) 	\
+	.set noreorder			;	\
+	addu		t1, kva, size   ;	\
+        subu		t2, linesize, 1 ;	\
+        not		t2		;	\
+        and		t0, kva, t2     ;	\
+        addiu		t1, t1, -1      ;    	\
+        and		t1, t2          ;	\
+9:	cache		op, 0(t0)       ;	\
+        bne		t0, t1, 9b	;	\
+        addu		t0, linesize    ;	\
+        .set reorder			;
+
+
+
+#define	IS_SHIFT	22
+#define	IL_SHIFT	19
+#define	IA_SHIFT	16
+#define	DS_SHIFT	13
+#define	DL_SHIFT	10
+#define	DA_SHIFT	 7
+#define	IS_MASK		 7
+#define	IL_MASK		 7
+#define	IA_MASK		 7
+#define	DS_MASK		 7
+#define	DL_MASK		 7
+#define	DA_MASK		 7
+#define	ICE_MASK	0x80000000
+#define	DCE_MASK	0x40000000
+
+#define CP0_BRCM_CONFIG0	$22, 0
+#define CP0_BRCM_MODE		$22, 1
+#define	CP0_CONFIG_K0_MASK	7
+
+#define CP0_ICACHE_TAG_LO       $28
+#define CP0_ICACHE_DATA_LO      $28, 1
+#define CP0_DCACHE_TAG_LO       $28, 2
+#define CP0_D_SEC_CACHE_DATA_LO	$28, 3
+#define CP0_ICACHE_TAG_HI       $29
+#define CP0_ICACHE_DATA_HI      $29, 1
+#define CP0_DCACHE_TAG_HI       $29, 2
+
+#define CP0_BRCM_MODE_Luc_MASK		(1 << 11)
+#define	CP0_BRCM_CONFIG0_CWF_MASK	(1 << 20)
+#define	CP0_BRCM_CONFIG0_TSE_MASK	(1 << 19)
+#define CP0_BRCM_MODE_SET_MASK		(1 << 7)
+#define CP0_BRCM_MODE_ClkRATIO_MASK	(7 << 4)
+#define CP0_BRCM_MODE_BrPRED_MASK 	(3 << 24)
+#define CP0_BRCM_MODE_BrPRED_SHIFT	24
+#define CP0_BRCM_MODE_BrHIST_MASK 	(0x1f << 20)
+#define CP0_BRCM_MODE_BrHIST_SHIFT	20
+
+/* ZSC L2 Cache Register Access Register Definitions */
+#define BRCM_ZSC_ALL_REGS_SELECT                0x7 << 24
+
+#define BRCM_ZSC_CONFIG_REG			0 << 3
+#define BRCM_ZSC_REQ_BUFFER_REG			2 << 3
+#define BRCM_ZSC_RBUS_ADDR_MAPPING_REG0		4 << 3
+#define BRCM_ZSC_RBUS_ADDR_MAPPING_REG1		6 << 3
+#define BRCM_ZSC_RBUS_ADDR_MAPPING_REG2		8 << 3
+
+#define BRCM_ZSC_SCB0_ADDR_MAPPING_REG0		0xa << 3
+#define BRCM_ZSC_SCB0_ADDR_MAPPING_REG1		0xc << 3
+
+#define BRCM_ZSC_SCB1_ADDR_MAPPING_REG0		0xe << 3
+#define BRCM_ZSC_SCB1_ADDR_MAPPING_REG1		0x10 << 3
+
+#define BRCM_ZSC_CONFIG_LMB1En			1 << (15)
+#define BRCM_ZSC_CONFIG_LMB0En			1 << (14)
+
+/* branch predition values */
+
+#define BRCM_BrPRED_ALL_TAKEN		(0x0)
+#define BRCM_BrPRED_ALL_NOT_TAKEN	(0x1)
+#define BRCM_BrPRED_BHT_ENABLE		(0x2)
+#define BRCM_BrPRED_PREDICT_BACKWARD	(0x3)
+
+
+
+.align 2
+/*
+ * Function: 	size_i_cache
+ * Arguments: 	None
+ * Returns:	v0 = i cache size, v1 = I cache line size
+ * Description: compute the I-cache size and I-cache line size
+ * Trashes:	v0, v1, a0, t0
+ *
+ *	pseudo code:
+ *
+ */
+
+LEAF(size_i_cache)
+	.set    noreorder
+
+	mfc0    a0, CP0_CONFIG, 1
+	move	t0, a0
+
+	/*
+	 * Determine sets per way: IS
+	 *
+	 * This field contains the number of sets (i.e., indices) per way of
+	 * the instruction cache:
+	 * i) 0x0: 64, ii) 0x1: 128, iii) 0x2: 256, iv) 0x3: 512, v) 0x4: 1k
+	 * vi) 0x5 - 0x7: Reserved.
+	 */
+
+	srl     a0, a0, IS_SHIFT
+	and     a0, a0, IS_MASK
+
+	/* sets per way = (64<<IS) */
+
+	li	v0, 0x40
+	sllv    v0, v0, a0
+
+	/*
+	 * Determine line size
+	 *
+	 * This field contains the line size of the instruction cache:
+	 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
+	 * 0x5: 64 bytes, iv) the rest: Reserved.
+	 */
+
+	move	a0, t0
+
+	srl	a0, a0, IL_SHIFT
+	and	a0, a0, IL_MASK
+
+	beqz	a0, no_i_cache
+	nop
+
+	/* line size = 2 ^ (IL+1) */
+
+	addi	a0, a0, 1
+	li	v1, 1
+	sll	v1, v1, a0
+
+	/* v0 now have sets per way, multiply it by line size now
+	 * that will give the set size
+	 */
+
+	sll	v0, v0, a0
+
+	/*
+	 * Determine set associativity
+	 *
+	 * This field contains the set associativity of the instruction cache.
+	 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
+	 * 4-way, v) 0x4 - 0x7: Reserved.
+	 */
+
+	move	a0, t0
+
+	srl	a0, a0, IA_SHIFT
+	and	a0, a0, IA_MASK
+	addi	a0, a0, 0x1
+
+	/* v0 has the set size, multiply it by
+	 * set associativiy, to get the cache size
+	 */
+
+	multu	v0, a0	/*multu is interlocked, so no need to insert nops */
+	mflo    v0
+	b	1f
+	nop
+
+no_i_cache:
+	move    v0, zero
+	move	v1, zero
+1:
+	jr       ra
+	nop
+	.set    reorder
+
+END(size_i_cache)
+
+/*
+ * Function: 	size_d_cache
+ * Arguments: 	None
+ * Returns:	v0 = d cache size, v1 = d cache line size
+ * Description: compute the D-cache size and D-cache line size.
+ * Trashes:	v0, v1, a0, t0
+ *
+ */
+
+LEAF(size_d_cache)
+	.set    noreorder
+
+	mfc0    a0, CP0_CONFIG, 1
+	move	t0, a0
+
+	/*
+	 * Determine sets per way: IS
+	 *
+	 * This field contains the number of sets (i.e., indices) per way of
+	 * the instruction cache:
+	 * i) 0x0: 64, ii) 0x1: 128, iii) 0x2: 256, iv) 0x3: 512, v) 0x4: 1k
+	 * vi) 0x5 - 0x7: Reserved.
+	 */
+
+	srl     a0, a0, DS_SHIFT
+	and     a0, a0, DS_MASK
+
+	/* sets per way = (64<<IS) */
+
+	li	v0, 0x40
+	sllv    v0, v0, a0
+
+	/*
+	 * Determine line size
+	 *
+	 * This field contains the line size of the instruction cache:
+	 * i) 0x0: No I-cache present, i) 0x3: 16 bytes, ii) 0x4: 32 bytes, iii)
+	 * 0x5: 64 bytes, iv) the rest: Reserved.
+	 */
+	move	a0, t0
+
+	srl	a0, a0, DL_SHIFT
+	and	a0, a0, DL_MASK
+
+	beqz	a0, no_d_cache
+	nop
+
+	/* line size = 2 ^ (IL+1) */
+
+	addi	a0, a0, 1
+	li	v1, 1
+	sll	v1, v1, a0
+
+	/* v0 now have sets per way, multiply it by line size now
+	 * that will give the set size
+	 */
+
+	sll	v0, v0, a0
+
+	/* determine set associativity
+	 *
+	 * This field contains the set associativity of the instruction cache.
+	 * i) 0x0: Direct mapped, ii) 0x1: 2-way, iii) 0x2: 3-way, iv) 0x3:
+	 * 4-way, v) 0x4 - 0x7: Reserved.
+	 */
+
+	move	a0, t0
+
+	srl	a0, a0, DA_SHIFT
+	and	a0, a0, DA_MASK
+	addi	a0, a0, 0x1
+
+	/* v0 has the set size, multiply it by
+	 * set associativiy, to get the cache size
+	 */
+
+	multu	v0, a0	/*multu is interlocked, so no need to insert nops */
+	mflo    v0
+
+	b	1f
+	nop
+
+no_d_cache:
+	move    v0, zero
+	move	v1, zero
+1:
+	jr	ra
+	nop
+	.set    reorder
+
+END(size_d_cache)
+
+
+/*
+ * Function: enable_ID
+ * Arguments: 	None
+ * Returns:	None
+ * Description: Enable I and D caches, initialize I and D-caches, also set
+ *                 hardware delay for d-cache (TP0).
+ * Trashes:	t0
+ *
+ */
+	.global	enable_ID
+	.ent	enable_ID
+	.set    noreorder
+enable_ID:
+	mfc0    t0, CP0_BRCM_CONFIG0
+	or	t0, t0, (ICE_MASK | DCE_MASK)
+	mtc0    t0, CP0_BRCM_CONFIG0
+	jr	ra
+	nop
+
+	.end	enable_ID
+	.set    reorder
+
+
+/*
+ * Function: l1_init
+ * Arguments: 	None
+ * Returns:	None
+ * Description: Enable I and D caches, and initialize I and D-caches
+ * Trashes:	a0, v0, v1, t0, t1, t2, t8
+ *
+ */
+	.globl	l1_init
+	.ent	l1_init
+	.set    noreorder
+l1_init:
+
+	/* save return address */
+	move    t8, ra
+
+
+	/* initialize I and D cache Data and Tag registers.  */
+	mtc0    zero, CP0_ICACHE_TAG_LO
+	mtc0    zero, CP0_ICACHE_TAG_HI
+	mtc0	zero, CP0_ICACHE_DATA_LO
+	mtc0	zero, CP0_ICACHE_DATA_HI
+	mtc0	zero, CP0_DCACHE_TAG_LO
+	mtc0	zero, CP0_DCACHE_TAG_HI
+
+	/* Enable Caches before Clearing. If the caches are disabled
+	 * then the cache operations to clear the cache will be ignored
+	 */
+
+	jal	enable_ID
+	nop
+
+	jal	size_i_cache	/* v0 = i-cache size, v1 = i-cache line size */
+	nop
+
+	/* run uncached in kseg 1 */
+	la	k0, 1f
+	lui	k1, 0x2000
+	or	k0, k1, k0
+	jr	k0
+	nop
+1:
+
+	/*
+	 * set K0 cache mode
+	 */
+
+	mfc0    t0, CP0_CONFIG
+	and     t0, t0, ~CP0_CONFIG_K0_MASK
+	or      t0, t0, 3	/* Write Back mode */
+	mtc0    t0, CP0_CONFIG
+
+	/*
+	 * Initialize  instruction cache.
+	 */
+
+	li	a0, KSEG0
+	cacheop(a0, v0, v1, Index_Store_Tag_I)
+
+	/*
+	 * Now we can run from I-$, kseg 0
+	 */
+	la	k0, 1f
+	lui	k1, 0x2000
+	or	k0, k1, k0
+	xor	k0, k1, k0
+	jr	k0
+	nop
+1:
+	/*
+	 * Initialize  data cache.
+	 */
+
+	jal	size_d_cache	/* v0 = d-cache size, v1 = d-cache line size */
+	nop
+
+
+	li      a0, KSEG0
+	cacheop(a0, v0, v1, Index_Store_Tag_D)
+
+	jr	t8
+	nop
+
+	.end 	l1_init
+	.set    reorder
+
+
+/*
+ * Function: 	set_other_config
+ * Arguments:	none
+ * Returns:	None
+ * Description: initialize other remainder configuration to defaults.
+ * Trashes:	t0, t1
+ *
+ *	pseudo code:
+ *
+ */
+LEAF(set_other_config)
+	.set noreorder
+
+        /* enable Bus error for I-fetch */
+        mfc0	t0, CP0_CACHEERR, 0
+        li	t1, 0x4
+        or	t0, t1
+	mtc0	t0, CP0_CACHEERR, 0
+
+        /* enable Bus error for Load */
+        mfc0	t0, CP0_CACHEERR, 1
+        li	t1, 0x4
+        or	t0, t1
+	mtc0	t0, CP0_CACHEERR, 1
+
+	/* enable Bus Error for Store */
+        mfc0	t0, CP0_CACHEERR, 2
+	li	t1, 0x4
+	or	t0, t1
+        mtc0	t0, CP0_CACHEERR, 2
+
+	jr	ra
+	nop
+	.set reorder
+END(set_other_config)
+
+/*
+ * Function: 	set_branch_pred
+ * Arguments:	none
+ * Returns:	None
+ * Description:
+ * Trashes:	t0, t1
+ *
+ *	pseudo code:
+ *
+ */
+
+LEAF(set_branch_pred)
+	.set noreorder
+	mfc0    t0, CP0_BRCM_MODE
+	li	t1, ~(CP0_BRCM_MODE_BrPRED_MASK | CP0_BRCM_MODE_BrHIST_MASK )
+	and	t0, t0, t1
+
+	/* enable Branch prediction */
+	li	t1, BRCM_BrPRED_BHT_ENABLE
+	sll	t1, CP0_BRCM_MODE_BrPRED_SHIFT
+	or	t0, t0, t1
+
+	/* set history count to 8 */
+	li	t1, 8
+	sll	t1, CP0_BRCM_MODE_BrHIST_SHIFT
+	or	t0, t0, t1
+
+	mtc0    t0, CP0_BRCM_MODE
+	jr	ra
+	nop
+	.set    reorder
+END(set_branch_pred)
+
+
+/*
+ * Function: 	set_luc
+ * Arguments:	set link uncached.
+ * Returns:	None
+ * Description:
+ * Trashes:	t0, t1
+ *
+ */
+LEAF(set_luc)
+	.set noreorder
+	mfc0    t0, CP0_BRCM_MODE
+	li	t1, ~(CP0_BRCM_MODE_Luc_MASK)
+	and	t0, t0, t1
+
+	/* set Luc */
+        ori	t0, t0, CP0_BRCM_MODE_Luc_MASK
+
+	mtc0    t0, CP0_BRCM_MODE
+	jr	ra
+	nop
+	.set    reorder
+END(set_luc)
+
+/*
+ * Function: 	set_cwf_tse
+ * Arguments:	set CWF and TSE bits
+ * Returns:	None
+ * Description:
+ * Trashes:	t0, t1
+ *
+ */
+LEAF(set_cwf_tse)
+	.set noreorder
+	mfc0    t0, CP0_BRCM_CONFIG0
+	li	t1, (CP0_BRCM_CONFIG0_CWF_MASK | CP0_BRCM_CONFIG0_TSE_MASK)
+	or	t0, t0, t1
+
+	mtc0    t0, CP0_BRCM_CONFIG0
+	jr	ra
+	nop
+	.set    reorder
+END(set_cwf_tse)
+
+/*
+ * Function: 	set_clock_ratio
+ * Arguments:   set clock ratio specified by a0
+ * Returns:	None
+ * Description:
+ * Trashes:	v0, v1, a0, a1
+ *
+ *	pseudo code:
+ *
+ */
+LEAF(set_clock_ratio)
+	.set noreorder
+
+	mfc0    t0, CP0_BRCM_MODE
+	li	t1, ~(CP0_BRCM_MODE_SET_MASK | CP0_BRCM_MODE_ClkRATIO_MASK)
+	and	t0, t0, t1
+	li	t1, CP0_BRCM_MODE_SET_MASK
+	or	t0, t0, t1
+	or	t0, t0, a0
+	mtc0    t0, CP0_BRCM_MODE
+	jr	ra
+	nop
+	.set    reorder
+END(set_clock_ratio)
+/*
+ * Function: set_zephyr
+ * Arguments:   None
+ * Returns:     None
+ * Description: Set any zephyr bits
+ * Trashes:     t0 & t1
+ *
+ */
+LEAF(set_zephyr)
+        .set    noreorder
+
+        /* enable read/write of CP0 #22 sel. 8 */
+        li      t0, 0x5a455048
+	.word	0x4088b00f      /* mtc0    t0, $22, 15 */
+
+	.word	0x4008b008      /* mfc0    t0, $22, 8 */
+        li      t1, 0x09000000	/* turn off pref */
+        or      t0, t0, t1
+	.word	0x4088b008      /* mtc0    t0, $22, 8 */
+        sync
+
+	/* disable read/write of CP0 #22 sel 8 */
+        li      t0, 0x0
+	.word	0x4088b00f      /* mtc0    t0, $22, 15 */
+
+
+        jr      ra
+        nop
+	.set reorder
+
+END(set_zephyr)
+
+
+/*
+ * Function:    set_llmb
+ * Arguments:   a0=0 disable llmb, a0=1 enables llmb
+ * Returns:     None
+ * Description:
+ * Trashes:     t0, t1, t2
+ *
+ *      pseudo code:
+ *
+ */
+LEAF(set_llmb)
+	.set noreorder
+
+	li	t2, 0x90000000 | BRCM_ZSC_ALL_REGS_SELECT | BRCM_ZSC_CONFIG_REG
+	sync
+	cache	0x7, 0x0(t2)
+	sync
+	mfc0	t0, CP0_D_SEC_CACHE_DATA_LO
+	li	t1, ~(BRCM_ZSC_CONFIG_LMB1En | BRCM_ZSC_CONFIG_LMB0En)
+	and	t0, t0, t1
+
+	beqz	a0, svlmb
+	nop
+
+enable_lmb:
+	li	t1, (BRCM_ZSC_CONFIG_LMB1En | BRCM_ZSC_CONFIG_LMB0En)
+	or	t0, t0, t1
+
+svlmb:
+	mtc0	t0, CP0_D_SEC_CACHE_DATA_LO
+	sync
+	cache	0xb, 0x0(t2)
+	sync
+
+	jr      ra
+	nop
+	.set reorder
+
+END(set_llmb)
+/*
+ * Function: 	core_init
+ * Arguments:	none
+ * Returns:	None
+ * Description: initialize core related configuration
+ * Trashes:	v0,v1,a0,a1,t8
+ *
+ *	pseudo code:
+ *
+ */
+	.globl	core_init
+	.ent    core_init
+	.set	noreorder
+core_init:
+	move	t8, ra
+
+	/* set Zephyr bits. */
+	bal	set_zephyr
+	nop
+
+#if ENABLE_FPU==1
+	/* initialize the Floating point unit (both TPs) */
+	bal	init_fpu
+	nop
+#endif
+
+	/* set low latency memory bus */
+	li      a0, 1
+	bal     set_llmb
+	nop
+
+	/* set branch prediction (TP0 only) */
+	bal	set_branch_pred
+	nop
+
+	/* set link uncached */
+	bal	set_luc
+	nop
+
+	/* set CWF and TSE */
+	bal     set_cwf_tse
+	nop
+
+	/*
+	 *set clock ratio by setting 1 to 'set'
+	 * and 0 to ClkRatio, (TP0 only)
+	 */
+	li	a0, 0
+	bal	set_clock_ratio
+	nop
+
+	/* set other configuration to defaults */
+	bal	set_other_config
+	nop
+
+	move	ra, t8
+	jr	ra
+	nop
+
+	.set reorder
+	.end	core_init
+
+/*
+ * Function: 	clear_jump_target_buffer
+ * Arguments:   None
+ * Returns:     None
+ * Description:
+ * Trashes:     t0, t1, t2
+ *
+ */
+#define RESET_CALL_RETURN_STACK_THIS_THREAD             (0x06<<16)
+#define RESET_JUMP_TARGET_BUFFER_THIS_THREAD    	(0x04<<16)
+#define JTB_CS_CNTL_MASK				(0xFF<<16)
+
+	.globl  clear_jump_target_buffer
+	.ent    clear_jump_target_buffer
+	.set    noreorder
+clear_jump_target_buffer:
+
+        mfc0    t0, $22, 2
+        nop
+        nop
+
+        li	t1, ~JTB_CS_CNTL_MASK
+        and	t0, t0, t1
+        li	t2, RESET_CALL_RETURN_STACK_THIS_THREAD
+        or	t0, t0, t2
+        mtc0    t0, $22, 2
+        nop
+        nop
+
+        and	t0, t0, t1
+        li	t2, RESET_JUMP_TARGET_BUFFER_THIS_THREAD
+        or	t0, t0, t2
+        mtc0	t0, $22, 2
+        nop
+        nop
+        jr      ra
+        nop
+
+	.end    clear_jump_target_buffer
+	.set    reorder
+/*
+ * Function: 	bmips_cache_init
+ * Arguments: 	None
+ * Returns:	None
+ * Description: Enable I and D caches, and initialize I and D-caches
+ * Trashes:	v0, v1, t0, t1, t2, t5, t7, t8
+ *
+ */
+	.globl	bmips_5xxx_init
+	.ent	bmips_5xxx_init
+	.set    noreorder
+bmips_5xxx_init:
+
+	/* save return address  and A0 */
+	move    t7, ra
+	move	t5, a0
+
+	jal	l1_init
+	nop
+
+	jal	core_init
+	nop
+
+	jal	clear_jump_target_buffer
+	nop
+
+        mtc0    zero, CP0_CAUSE
+
+	move 	a0, t5
+	jr	t7
+	nop
+
+	.end 	bmips_5xxx_init
+	.set    reorder
+
+
+#endif
diff --git a/arch/mips/brcmstb/irq.c b/arch/mips/brcmstb/irq.c
new file mode 100644
index 0000000..1661028
--- /dev/null
+++ b/arch/mips/brcmstb/irq.c
@@ -0,0 +1,442 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/irq.h>
+#include <linux/cpumask.h>
+#include <linux/smp.h>
+#include <linux/io.h>
+#include <linux/bitops.h>
+#include <linux/version.h>
+
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/irq_cpu.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#ifdef CONFIG_SMP
+static int next_cpu[NR_IRQS + 1] = { [0 ... NR_IRQS] = 0 };
+#define NEXT_CPU(irq) next_cpu[irq]
+
+#define TP0_BASE BCHP_HIF_CPU_INTR1_REG_START
+#define TP1_BASE BCHP_HIF_CPU_TP1_INTR1_REG_START
+#define L1_WR_ALL(word, reg, val) do { \
+	L1_WR_##word(TP0_BASE, reg, val); \
+	if (cpu_online(1)) \
+		L1_WR_##word(TP1_BASE, reg, val); \
+	} while (0)
+
+#else
+
+#define TP0_BASE BCHP_HIF_CPU_INTR1_REG_START
+#define TP1_BASE TP0_BASE
+#define L1_WR_ALL(word, reg, val) do { \
+	L1_WR_##word(TP0_BASE, reg, val); \
+	} while (0)
+
+#define NEXT_CPU(irq) 0
+#endif
+
+#define L1_REG(base, off) ((base) + (off) - BCHP_HIF_CPU_INTR1_REG_START)
+
+#define L1_RD_W0(base, reg) \
+	BDEV_RD(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W0_##reg))
+#define L1_RD_W1(base, reg) \
+	BDEV_RD(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W1_##reg))
+
+#define L1_WR_W0(base, reg, val) \
+	BDEV_WR_RB(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W0_##reg), val)
+#define L1_WR_W1(base, reg, val) \
+	BDEV_WR_RB(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W1_##reg), val)
+
+#if defined(BCHP_HIF_CPU_INTR1_INTR_W2_STATUS)
+
+#define L1_RD_W2(base, reg) \
+	BDEV_RD(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W2_##reg))
+#define L1_WR_W2(base, reg, val) \
+	BDEV_WR_RB(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W2_##reg), val)
+
+#else
+/* nop on chips with only 64 L1 interrupts */
+#define L1_RD_W2(base, reg)	0
+#define L1_WR_W2(base, reg, val) do { } while (0)
+#endif
+
+#if defined(BCHP_HIF_CPU_INTR1_INTR_W3_STATUS)
+
+#define L1_RD_W3(base, reg) \
+	BDEV_RD(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W3_##reg))
+#define L1_WR_W3(base, reg, val) \
+	BDEV_WR_RB(L1_REG(base, BCHP_HIF_CPU_INTR1_INTR_W3_##reg), val)
+
+#else
+/* nop on chips with only 96 L1 interrupts */
+#define L1_RD_W3(base, reg)	0
+#define L1_WR_W3(base, reg, val) do { } while (0)
+#endif
+
+/*
+ * For interrupt map, see include/asm-mips/brcmstb/<plat>/bcmintrnum.h
+ */
+
+/***********************************************************************
+ * INTC (aka L1 interrupt) functions
+ ***********************************************************************/
+
+static void brcm_intc_enable(struct irq_data *d)
+{
+	unsigned int irq = d->irq;
+	unsigned int shift;
+	unsigned long base = NEXT_CPU(irq) ? TP1_BASE : TP0_BASE;
+
+	if (irq > 0 && irq <= 32) {
+		shift = irq - 1;
+		L1_WR_W0(base, MASK_CLEAR, (1UL << shift));
+	} else if (irq > 32 && irq <= 32+32) {
+		shift = irq - 32 - 1;
+		L1_WR_W1(base, MASK_CLEAR, (1UL << shift));
+	} else if (irq > 64 && irq <= 32+32+32) {
+		shift = irq - 64 - 1;
+		L1_WR_W2(base, MASK_CLEAR, (1UL << shift));
+	} else if (irq > 96 && irq <= 32+32+32+32) {
+		shift = irq - 96 - 1;
+		L1_WR_W3(base, MASK_CLEAR, (1UL << shift));
+	} else
+		BUG();
+}
+
+static void brcm_intc_disable(struct irq_data *d)
+{
+	unsigned int irq = d->irq;
+	unsigned int shift;
+
+	if (irq > 0 && irq <= 32) {
+		shift = irq - 1;
+		L1_WR_ALL(W0, MASK_SET, (1UL << shift));
+	} else if (irq > 32 && irq <= 32+32) {
+		shift = irq - 32 - 1;
+		L1_WR_ALL(W1, MASK_SET, (1UL << shift));
+	} else if (irq > 64 && irq <= 32+32+32) {
+		shift = irq - 64 - 1;
+		L1_WR_ALL(W2, MASK_SET, (1UL << shift));
+	} else if (irq > 96 && irq <= 32+32+32+32) {
+		shift = irq - 96 - 1;
+		L1_WR_ALL(W3, MASK_SET, (1UL << shift));
+	} else
+		BUG();
+}
+
+#ifdef CONFIG_SMP
+static int brcm_intc_set_affinity(struct irq_data *d,
+	const struct cpumask *dest, bool force)
+{
+	unsigned int irq = d->irq;
+	unsigned int shift;
+	unsigned long flags;
+
+	local_irq_save(flags);
+	if (irq > 0 && irq <= 32) {
+		shift = irq - 1;
+
+		if (cpumask_test_cpu(0, dest)) {
+			L1_WR_W0(TP1_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W0(TP0_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 0;
+		} else {
+			L1_WR_W0(TP0_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W0(TP1_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 1;
+		}
+	} else if (irq > 32 && irq <= 64) {
+		shift = irq - 32 - 1;
+		next_cpu[irq] = 0;
+
+		if (cpumask_test_cpu(0, dest)) {
+			L1_WR_W1(TP1_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W1(TP0_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 0;
+		} else {
+			L1_WR_W1(TP0_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W1(TP1_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 1;
+		}
+	} else if (irq > 64 && irq <= 96) {
+		shift = irq - 64 - 1;
+		next_cpu[irq] = 0;
+
+		if (cpumask_test_cpu(0, dest)) {
+			L1_WR_W2(TP1_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W2(TP0_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 0;
+		} else {
+			L1_WR_W2(TP0_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W2(TP1_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 1;
+		}
+	} else if (irq > 96 && irq <= 128) {
+		shift = irq - 96 - 1;
+		next_cpu[irq] = 0;
+
+		if (cpumask_test_cpu(0, dest)) {
+			L1_WR_W3(TP1_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W3(TP0_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 0;
+		} else {
+			L1_WR_W3(TP0_BASE, MASK_SET, (1UL << shift));
+			L1_WR_W3(TP1_BASE, MASK_CLEAR, (1UL << shift));
+			next_cpu[irq] = 1;
+		}
+	}
+	local_irq_restore(flags);
+	return 0;
+}
+#endif /* CONFIG_SMP */
+
+/*
+ * THT: These INTC disable the interrupt before calling the IRQ handle_irq
+ */
+static struct irq_chip brcm_intc_type = {
+	.name			= "BRCM L1",
+	.irq_ack		= brcm_intc_disable,
+	.irq_mask		= brcm_intc_disable,
+	.irq_mask_ack		= brcm_intc_disable,
+	.irq_unmask		= brcm_intc_enable,
+#ifdef CONFIG_SMP
+	.irq_set_affinity	= brcm_intc_set_affinity,
+#endif /* CONFIG_SMP */
+	NULL
+};
+
+/*
+ * Move the interrupt to the other TP, to balance load (if affinity permits)
+ */
+static void flip_tp(int irq)
+{
+#ifndef CONFIG_BRUNO
+#ifdef CONFIG_SMP
+	int tp = smp_processor_id();
+	unsigned long local_lev1, remote_lev1;
+	unsigned long mask = 1 << ((irq - 1) & 0x1f);
+
+	if (tp == 0) {
+		local_lev1 = TP0_BASE;
+		remote_lev1 = TP1_BASE;
+	} else {
+		local_lev1 = TP1_BASE;
+		remote_lev1 = TP0_BASE;
+	}
+
+	if (cpumask_test_cpu(tp ^ 1, irq_desc[irq].irq_data.affinity)) {
+		next_cpu[irq] = tp ^ 1;
+		if (irq > 0 && irq <= 32) {
+			L1_WR_W0(local_lev1, MASK_SET, mask);
+			L1_WR_W0(remote_lev1, MASK_CLEAR, mask);
+		}
+		if (irq > 32 && irq <= 64) {
+			L1_WR_W1(local_lev1, MASK_SET, mask);
+			L1_WR_W1(remote_lev1, MASK_CLEAR, mask);
+		}
+		if (irq > 64 && irq <= 96) {
+			L1_WR_W2(local_lev1, MASK_SET, mask);
+			L1_WR_W2(remote_lev1, MASK_CLEAR, mask);
+		}
+		if (irq > 96 && irq <= 128) {
+			L1_WR_W3(local_lev1, MASK_SET, mask);
+			L1_WR_W3(remote_lev1, MASK_CLEAR, mask);
+		}
+	}
+#endif /* CONFIG_SMP */
+#endif
+}
+
+static void brcm_intc_dispatch(unsigned long base)
+{
+	u32 pend, shift;
+
+	pend = L1_RD_W0(base, STATUS) & ~L1_RD_W0(base, MASK_STATUS);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+
+	pend = L1_RD_W1(base, STATUS) & ~L1_RD_W1(base, MASK_STATUS);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 32;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+	pend = L1_RD_W2(base, STATUS) & ~L1_RD_W2(base, MASK_STATUS);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 64;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+	pend = L1_RD_W3(base, STATUS) & ~L1_RD_W3(base, MASK_STATUS);
+	while ((shift = ffs(pend)) != 0) {
+		pend ^= (1 << (shift - 1));
+		shift += 96;
+		do_IRQ(shift);
+		flip_tp(shift);
+	}
+}
+
+/* IRQ2 = L1 interrupt for TP0 */
+static void brcm_mips_int2_dispatch(void)
+{
+	clear_c0_status(STATUSF_IP2);
+	brcm_intc_dispatch(TP0_BASE);
+	set_c0_status(STATUSF_IP2);
+}
+
+#ifdef CONFIG_SMP
+/* IRQ3 = L1 interrupt for TP1 */
+static void brcm_mips_int3_dispatch(void)
+{
+	clear_c0_status(STATUSF_IP3);
+	brcm_intc_dispatch(TP1_BASE);
+	set_c0_status(STATUSF_IP3);
+}
+#endif
+
+/***********************************************************************
+ * IRQ setup / dispatch
+ ***********************************************************************/
+
+void __init arch_init_irq(void)
+{
+	int irq;
+
+	mips_cpu_irq_init();
+
+	L1_WR_ALL(W0, MASK_SET, 0xffffffff);
+	L1_WR_ALL(W1, MASK_SET, 0xffffffff);
+	L1_WR_ALL(W2, MASK_SET, 0xffffffff);
+	L1_WR_ALL(W3, MASK_SET, 0xffffffff);
+
+	clear_c0_status(ST0_IE | ST0_IM);
+
+	/* Set up all L1 IRQs */
+	for (irq = 1; irq < BRCM_VIRTIRQ_BASE; irq++)
+#if LINUX_VERSION_CODE >= KERNEL_VERSION(2, 6, 39)
+		irq_set_chip_and_handler(irq, &brcm_intc_type,
+			handle_level_irq);
+#else
+		set_irq_chip_and_handler(irq, &brcm_intc_type,
+			handle_level_irq);
+#endif
+
+#if defined(CONFIG_SMP)
+	/* default affinity: 1 (TP0 only) */
+	cpumask_clear(irq_default_affinity);
+	cpumask_set_cpu(0, irq_default_affinity);
+#endif
+
+	/* enable IRQ2 (this runs on TP0).  IRQ3 enabled during TP1 boot. */
+	set_c0_status(STATUSF_IP2);
+
+	/* enable non-shared UART interrupts in the L2 */
+
+#if defined(BCHP_IRQ0_UART_IRQEN_uarta_MASK)
+	/* 3548 style - separate register */
+	BDEV_WR(BCHP_IRQ0_UART_IRQEN, BCHP_IRQ0_UART_IRQEN_uarta_MASK |
+		BCHP_IRQ0_UART_IRQEN_uartb_MASK |
+		BCHP_IRQ0_UART_IRQEN_uartc_MASK);
+	BDEV_WR(BCHP_IRQ0_IRQEN, 0);
+#elif defined(BCHP_IRQ0_IRQEN_uarta_irqen_MASK)
+	/* 7405 style - shared with L2 */
+	BDEV_WR(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_MASK
+		| BCHP_IRQ0_IRQEN_uartb_irqen_MASK
+#if defined(BCHP_IRQ0_IRQEN_uartc_irqen_MASK)
+		| BCHP_IRQ0_IRQEN_uartc_irqen_MASK
+#endif
+		);
+#endif
+
+#if defined(BCHP_HIF_INTR2_CPU_MASK_SET)
+	/* mask and clear all HIF L2 interrupts */
+	BDEV_WR_RB(BCHP_HIF_INTR2_CPU_MASK_SET, 0xffffffff);
+	BDEV_WR_RB(BCHP_HIF_INTR2_CPU_CLEAR, 0xffffffff);
+#endif
+}
+
+asmlinkage void plat_irq_dispatch(void)
+{
+	unsigned int pend = ((read_c0_cause() & read_c0_status()) >> 8) & 0xff;
+	unsigned int shift;
+
+	while ((shift = ffs(pend)) != 0) {
+		shift--;
+		pend ^= 1 << shift;
+		if (shift == 2)
+			brcm_mips_int2_dispatch();
+#ifdef CONFIG_SMP
+		else if (unlikely(shift == 3))
+			brcm_mips_int3_dispatch();
+#endif
+		else
+			do_IRQ(MIPS_CPU_IRQ_BASE + shift);
+	}
+}
+
+/***********************************************************************
+ * Power management
+ ***********************************************************************/
+
+static unsigned long brcm_irq_state[NR_IRQS / 32];
+
+void brcm_irq_standby_enter(int wake_irq)
+{
+	/* save the current state, then mask everything */
+	brcm_irq_state[0] = L1_RD_W0(TP0_BASE, MASK_STATUS);
+	L1_WR_W0(TP0_BASE, MASK_SET, 0xffffffff);
+	brcm_irq_state[1] = L1_RD_W1(TP0_BASE, MASK_STATUS);
+	L1_WR_W1(TP0_BASE, MASK_SET, 0xffffffff);
+	brcm_irq_state[2] = L1_RD_W2(TP0_BASE, MASK_STATUS);
+	L1_WR_W2(TP0_BASE, MASK_SET, 0xffffffff);
+	brcm_irq_state[3] = L1_RD_W3(TP0_BASE, MASK_STATUS);
+	L1_WR_W3(TP0_BASE, MASK_SET, 0xffffffff);
+
+	/* unmask the wakeup IRQ */
+	if (wake_irq > 0 && wake_irq <= 32)
+		L1_WR_W0(TP0_BASE, MASK_CLEAR, 1 << (wake_irq - 1));
+	else if (wake_irq > 32 && wake_irq <= 64)
+		L1_WR_W1(TP0_BASE, MASK_CLEAR, 1 << (wake_irq - 33));
+	else if (wake_irq > 64 && wake_irq <= 96)
+		L1_WR_W2(TP0_BASE, MASK_CLEAR, 1 << (wake_irq - 65));
+	else if (wake_irq > 96 && wake_irq <= 128)
+		L1_WR_W3(TP0_BASE, MASK_CLEAR, 1 << (wake_irq - 97));
+}
+
+void brcm_irq_standby_exit(void)
+{
+	/* restore the saved L1 state */
+	L1_WR_W0(TP0_BASE, MASK_SET, 0xffffffff);
+	L1_WR_W0(TP0_BASE, MASK_CLEAR, ~brcm_irq_state[0]);
+	L1_WR_W1(TP0_BASE, MASK_SET, 0xffffffff);
+	L1_WR_W1(TP0_BASE, MASK_CLEAR, ~brcm_irq_state[1]);
+	L1_WR_W2(TP0_BASE, MASK_SET, 0xffffffff);
+	L1_WR_W2(TP0_BASE, MASK_CLEAR, ~brcm_irq_state[2]);
+	L1_WR_W3(TP0_BASE, MASK_SET, 0xffffffff);
+	L1_WR_W3(TP0_BASE, MASK_CLEAR, ~brcm_irq_state[3]);
+}
diff --git a/arch/mips/brcmstb/memory.c b/arch/mips/brcmstb/memory.c
new file mode 100644
index 0000000..c3ff4d3
--- /dev/null
+++ b/arch/mips/brcmstb/memory.c
@@ -0,0 +1,565 @@
+/*
+ * Copyright (C) 2000-2004 Russell King
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/bootmem.h>
+#include <linux/spinlock.h>
+#include <linux/mm.h>
+#include <linux/kernel.h>
+#include <linux/pci.h>
+#include <linux/ioport.h>
+#include <linux/list.h>
+#include <linux/vmalloc.h>
+#include <linux/compiler.h>
+#include <linux/atomic.h>
+#include <linux/printk.h>
+#include <linux/module.h>
+
+#include <asm/page.h>
+#include <asm/pgtable-32.h>
+#include <asm/pgtable-bits.h>
+#include <asm/addrspace.h>
+#include <asm/tlbflush.h>
+#include <asm/r4kcache.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#include <spaces.h>
+
+/*
+ * Override default behavior to allow cached access to all valid DRAM ranges
+ */
+int __uncached_access(struct file *file, unsigned long addr)
+{
+	if (file->f_flags & O_SYNC)
+		return 1;
+	if (addr >= BCHP_PHYSICAL_OFFSET && addr < UPPERMEM_START)
+		return 1;
+	if (addr >= PCIE_MEM_START)
+		return 1;
+	return 0;
+}
+
+/***********************************************************************
+ * Wired TLB mappings for upper memory support
+ ***********************************************************************/
+
+#define UNIQUE_ENTRYHI(idx) (CKSEG0 + ((idx) << (PAGE_SHIFT + 1)))
+
+/* (PFN << 6) | GLOBAL | VALID | DIRTY | cacheability */
+#define ENTRYLO_CACHED(paddr)	(((paddr) >> 6) | (0x07) | (0x03 << 3))
+#define ENTRYLO_UNCACHED(paddr)	(((paddr) >> 6) | (0x07) | (0x02 << 3))
+
+/* GLOBAL | !VALID */
+#define ENTRYLO_INVALID()	(0x01)
+
+struct tlb_entry {
+	unsigned long entrylo0;
+	unsigned long entrylo1;
+	unsigned long entryhi;
+	unsigned long pagemask;
+};
+
+static struct tlb_entry __maybe_unused uppermem_mappings[] = {
+{
+#if defined(CONFIG_BRCM_UPPER_768MB)
+	.entrylo0		= ENTRYLO_CACHED(TLB_UPPERMEM_PA),
+	.entrylo1		= ENTRYLO_INVALID(),
+	.entryhi		= TLB_UPPERMEM_VA,
+	.pagemask		= PM_256M,
+#endif
+},
+};
+
+static inline void brcm_write_tlb_entry(int idx,
+	unsigned long entrylo0, unsigned long entrylo1, unsigned long entryhi,
+	unsigned long pagemask)
+{
+	write_c0_entrylo0(entrylo0);
+	write_c0_entrylo1(entrylo1);
+	write_c0_entryhi(entryhi);
+	write_c0_pagemask(pagemask);
+	write_c0_index(idx);
+	mtc0_tlbw_hazard();
+	tlb_write_indexed();
+	tlbw_use_hazard();
+}
+
+/*
+ * This function is used instead of add_wired_entry(), because it does not
+ * have any external dependencies and is not marked __init
+ */
+static inline void brcm_add_wired_entry(unsigned long entrylo0,
+	unsigned long entrylo1, unsigned long entryhi, unsigned long pagemask)
+{
+	int i = read_c0_wired();
+	write_c0_wired(i + 1);
+	brcm_write_tlb_entry(i, entrylo0, entrylo1, entryhi, pagemask);
+}
+
+extern void tlb_init(void);
+extern void build_tlb_refill_handler(void);
+
+void brcm_tlb_init(void)
+{
+#ifdef CONFIG_BRCM_UPPER_MEMORY
+	if (smp_processor_id() == 0) {
+		int i;
+		struct tlb_entry *e = uppermem_mappings;
+
+		tlb_init();
+		for (i = 0; i < ARRAY_SIZE(uppermem_mappings); i++, e++)
+			brcm_add_wired_entry(e->entrylo0, e->entrylo1,
+				e->entryhi, e->pagemask);
+		write_c0_pagemask(PM_DEFAULT_MASK);
+	} else {
+		/* bypass tlb_init() / probe_tlb() for secondary CPU */
+		cpu_data[smp_processor_id()].tlbsize = cpu_data[0].tlbsize;
+		build_tlb_refill_handler();
+	}
+#else
+	tlb_init();
+#endif
+}
+
+/*
+ * Initialize upper memory TLB entries
+ *
+ * On TP1 this must happen before we set up $sp/$gp .  It is always
+ * possible for stacks, task_structs, thread_info's, and other
+ * important structures to be allocated out of upper memory so
+ * this happens early on.
+ */
+asmlinkage void plat_wired_tlb_setup(void)
+{
+#ifdef CONFIG_BRCM_UPPER_MEMORY
+	int i, tlbsz;
+
+	/* Flush TLB.  local_flush_tlb_all() is not available yet. */
+	write_c0_entrylo0(0);
+	write_c0_entrylo1(0);
+	write_c0_pagemask(PM_DEFAULT_MASK);
+	write_c0_wired(0);
+
+	tlbsz = (read_c0_config1() >> 25) & 0x3f;
+	for (i = 0; i <= tlbsz; i++) {
+		write_c0_entryhi(UNIQUE_ENTRYHI(i));
+		write_c0_index(i);
+		mtc0_tlbw_hazard();
+		tlb_write_indexed();
+		tlbw_use_hazard();
+	}
+
+	write_c0_wired(0);
+	mtc0_tlbw_hazard();
+
+	for (i = 0; i < ARRAY_SIZE(uppermem_mappings); i++) {
+		struct tlb_entry *e = &uppermem_mappings[i];
+		brcm_add_wired_entry(e->entrylo0, e->entrylo1, e->entryhi,
+			e->pagemask);
+	}
+
+	write_c0_pagemask(PM_DEFAULT_MASK);
+#endif
+}
+
+#ifdef CONFIG_BRCM_UPPER_768MB
+
+/***********************************************************************
+ * Special allocator for coherent (uncached) memory
+ * (Required for >256MB upper memory)
+ ***********************************************************************/
+
+#define CONSISTENT_DMA_SIZE	(CONSISTENT_END - CONSISTENT_BASE)
+#define CONSISTENT_OFFSET(x)	(((unsigned long)(x) - CONSISTENT_BASE) >> \
+	PAGE_SHIFT)
+#define CONSISTENT_PTE_INDEX(x) (((unsigned long)(x) - CONSISTENT_BASE) >> \
+	PGDIR_SHIFT)
+#define NUM_CONSISTENT_PTES	(CONSISTENT_DMA_SIZE >> PGDIR_SHIFT)
+
+/*
+ * These are the page tables (4MB each) covering uncached, DMA consistent
+ * allocations
+ */
+static pte_t *consistent_pte[NUM_CONSISTENT_PTES];
+static DEFINE_SPINLOCK(consistent_lock);
+
+struct arm_vm_region {
+	struct list_head	vm_list;
+	unsigned long		vm_start;
+	unsigned long		vm_end;
+	void			*vm_cac_va;
+	int			vm_active;
+};
+
+static struct arm_vm_region consistent_head = {
+	.vm_list	= LIST_HEAD_INIT(consistent_head.vm_list),
+	.vm_start	= CONSISTENT_BASE,
+	.vm_end		= CONSISTENT_END,
+};
+
+static struct arm_vm_region *
+arm_vm_region_alloc(struct arm_vm_region *head, size_t size, gfp_t gfp)
+{
+	unsigned long addr = head->vm_start, end = head->vm_end - size;
+	unsigned long flags;
+	struct arm_vm_region *c, *new;
+
+	new = kmalloc(sizeof(struct arm_vm_region), gfp);
+	if (!new)
+		goto out;
+
+	spin_lock_irqsave(&consistent_lock, flags);
+
+	list_for_each_entry(c, &head->vm_list, vm_list) {
+		if ((addr + size) < addr)
+			goto nospc;
+		if ((addr + size) <= c->vm_start)
+			goto found;
+		addr = c->vm_end;
+		if (addr > end)
+			goto nospc;
+	}
+
+found:
+	/*
+	 * Insert this entry _before_ the one we found.
+	 */
+	list_add_tail(&new->vm_list, &c->vm_list);
+	new->vm_start = addr;
+	new->vm_end = addr + size;
+	new->vm_active = 1;
+
+	spin_unlock_irqrestore(&consistent_lock, flags);
+	return new;
+
+nospc:
+	spin_unlock_irqrestore(&consistent_lock, flags);
+	kfree(new);
+out:
+	return NULL;
+}
+
+static struct arm_vm_region *arm_vm_region_find(struct arm_vm_region *head,
+	unsigned long addr)
+{
+	struct arm_vm_region *c;
+
+	list_for_each_entry(c, &head->vm_list, vm_list) {
+		if (c->vm_active && c->vm_start == addr)
+			goto out;
+	}
+	c = NULL;
+out:
+	return c;
+}
+
+static int __init consistent_init(void)
+{
+	pgd_t *pgd;
+	pud_t *pud;
+	pmd_t *pmd;
+	pte_t *pte;
+	int ret = 0, i = 0;
+	u32 base = CONSISTENT_BASE;
+
+	do {
+		pgd = pgd_offset(&init_mm, base);
+		pud = pud_alloc(&init_mm, pgd, base);
+		if (!pud) {
+			pr_err("%s: no pud tables\n", __func__);
+			ret = -ENOMEM;
+			break;
+		}
+		pmd = pmd_alloc(&init_mm, pud, base);
+		if (!pmd) {
+			pr_err("%s: no pmd tables\n", __func__);
+			ret = -ENOMEM;
+			break;
+		}
+
+		pte = pte_alloc_kernel(pmd, base);
+		if (!pte) {
+			pr_err("%s: no pte tables\n", __func__);
+			ret = -ENOMEM;
+			break;
+		}
+
+		consistent_pte[i++] = pte;
+		base += (1 << PGDIR_SHIFT);
+	} while (base < CONSISTENT_END);
+
+	return ret;
+}
+
+core_initcall(consistent_init);
+
+int brcm_map_coherent(dma_addr_t dma_handle, void *cac_va, size_t size,
+	void **uncac_va, gfp_t gfp)
+{
+	struct arm_vm_region *c;
+	struct page *page;
+	pte_t *pte;
+	int idx;
+	u32 off;
+
+	c = arm_vm_region_alloc(&consistent_head, size, gfp);
+	if (!c)
+		return -EINVAL;
+
+	c->vm_cac_va = cac_va;
+
+	page = virt_to_page(cac_va);
+	idx = CONSISTENT_PTE_INDEX(c->vm_start);
+	off = CONSISTENT_OFFSET(c->vm_start) & (PTRS_PER_PTE-1);
+	pte = consistent_pte[idx] + off;
+
+	pr_debug("map addr %08lx idx %x off %x pte %p\n",
+		c->vm_start, idx, off, pte);
+
+	do {
+		BUG_ON(!pte_none(*pte));
+		set_pte(pte, mk_pte(page, PAGE_KERNEL_UNCACHED));
+		page++;
+		pte++;
+		off++;
+		if (off >= PTRS_PER_PTE) {
+			off = 0;
+			idx++;
+			BUG_ON(idx < 0 || idx >= ARRAY_SIZE(consistent_pte));
+			pte = consistent_pte[idx];
+		}
+	} while (size -= PAGE_SIZE);
+
+	*uncac_va = (void *)c->vm_start;
+	return 0;
+}
+
+void *brcm_unmap_coherent(void *vaddr)
+{
+	struct arm_vm_region *c;
+	unsigned long flags, addr;
+	void *ret = NULL;
+	pte_t *pte;
+	int idx;
+	u32 off;
+
+	spin_lock_irqsave(&consistent_lock, flags);
+	c = arm_vm_region_find(&consistent_head, (unsigned long)vaddr);
+	if (!c) {
+		spin_unlock_irqrestore(&consistent_lock, flags);
+		pr_err("%s: invalid VA %p\n", __func__, vaddr);
+		return NULL;
+	}
+	c->vm_active = 0;
+	spin_unlock_irqrestore(&consistent_lock, flags);
+
+	ret = c->vm_cac_va;
+	addr = c->vm_start;
+
+	idx = CONSISTENT_PTE_INDEX(addr);
+	off = CONSISTENT_OFFSET(addr) & (PTRS_PER_PTE-1);
+	pte = consistent_pte[idx] + off;
+
+	pr_debug("unmap addr %08lx idx %x off %x pte %p\n",
+		addr, idx, off, pte);
+
+	do {
+		pte_clear(&init_mm, addr, pte);
+		pte++;
+		off++;
+		if (off >= PTRS_PER_PTE) {
+			off = 0;
+			idx++;
+			BUG_ON(idx < 0 || idx >= ARRAY_SIZE(consistent_pte));
+			pte = consistent_pte[idx];
+		}
+		addr += PAGE_SIZE;
+	} while (addr < c->vm_end);
+	flush_tlb_kernel_range(c->vm_start, c->vm_end);
+
+	spin_lock_irqsave(&consistent_lock, flags);
+	list_del(&c->vm_list);
+	spin_unlock_irqrestore(&consistent_lock, flags);
+
+	kfree(c);
+
+	return ret;
+}
+
+#endif /* CONFIG_BRCM_UPPER_768MB */
+
+void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+	unsigned long flags)
+{
+	/* sanity check */
+	if ((offset + size - 1) < offset ||
+	    !size ||
+	    offset > max(KSEG0_SIZE, KSEG1_SIZE))
+		return NULL;
+
+	/* !XKS01, XKS01: uncached access to EBI/registers @ PA 1000_0000 */
+	if (offset >= 0x10000000 &&
+	    (offset + size) <= 0x20000000 &&
+	    flags == _CACHE_UNCACHED)
+		return (void *)(KSEG1 + offset);
+
+	/* !XKS01, XKS01: easy cached access to some DRAM */
+	if ((offset + size) <= KSEG0_SIZE &&
+	    flags == _CACHE_CACHABLE_NONCOHERENT)
+		return (void *)(KSEG0 + offset);
+
+	/* !XKS01 only: easy uncached access to some DRAM */
+	if ((offset + size) <= KSEG1_SIZE &&
+	    flags == _CACHE_UNCACHED)
+		return (void *)(KSEG1 + offset);
+
+	/* anything else gets mapped using page tables */
+	return NULL;
+}
+EXPORT_SYMBOL(plat_ioremap);
+
+int plat_iounmap(const volatile void __iomem *addr)
+{
+	phys_addr_t va = (unsigned long)addr;
+
+	if (va >= KSEG0 && va < (KSEG0 + KSEG0_SIZE))
+		return 1;
+	if (va >= KSEG1 && va < (KSEG1 + KSEG1_SIZE))
+		return 1;
+	return 0;
+}
+EXPORT_SYMBOL(plat_iounmap);
+
+/***********************************************************************
+ * RAM configuration
+ ***********************************************************************/
+
+#define MAGIC0		0xdeadbeef
+#define MAGIC1		0xfeedcafe
+
+static inline unsigned int __init probe_ram_size(void)
+{
+	unsigned long addr = KSEG1, taddr;
+	uint32_t olddata;
+	unsigned long flags;
+	unsigned int i, memsize = 256;
+
+	pr_info("Probing system memory size... ");
+
+	local_irq_save(flags);
+	cache_op(Hit_Writeback_Inv_D, KSEG0);
+	olddata = DEV_RD(addr);
+
+	/*
+	 * Try to figure out where memory wraps around.  If it does not
+	 * wrap, assume 256MB
+	*/
+	for (i = 4; i <= 128; i <<= 1) {
+		taddr = KSEG1 + i * 1048576;
+		DEV_WR(addr, MAGIC0);
+		if (DEV_RD(taddr) == MAGIC0) {
+			DEV_WR(addr, MAGIC1);
+			if (DEV_RD(taddr) == MAGIC1) {
+				memsize = i;
+				break;
+			}
+		}
+	}
+
+	DEV_WR(addr, olddata);
+	cache_op(Hit_Writeback_Inv_D, KSEG0);
+	local_irq_restore(flags);
+
+	pr_cont("found %u MB\n", memsize);
+
+	return memsize;
+}
+
+void __init board_get_ram_size(unsigned long *dram0_mb, unsigned long *dram1_mb)
+{
+#if defined(CONFIG_BRCM_OVERRIDE_RAM_SIZE)
+	*dram0_mb = CONFIG_BRCM_FORCED_DRAM0_SIZE;
+#if defined(CONFIG_BRCM_FORCED_DRAM1_SIZE)
+	*dram1_mb = CONFIG_BRCM_FORCED_DRAM1_SIZE;
+#endif
+	pr_info("Using %lu MB + %lu MB RAM (from kernel configuration)\n",
+		*dram0_mb, *dram1_mb);
+#else
+	/* DRAM0_SIZE variable from CFE */
+	if (*dram0_mb) {
+		pr_info("Using %lu MB + %lu MB RAM (from CFE)\n",
+			*dram0_mb, *dram1_mb);
+		return;
+	}
+	*dram0_mb = probe_ram_size();
+#endif
+}
+
+static void __init __brcm_wraparound_check(unsigned long start,
+	unsigned long midpoint, int memc_no)
+{
+	int found = 0, idx = read_c0_wired();
+	unsigned long *a, *b, old_a, va = FIXADDR_TOP - 0x2000;
+
+	brcm_write_tlb_entry(idx, ENTRYLO_UNCACHED(start),
+		ENTRYLO_UNCACHED(midpoint), va, PM_4K);
+
+	a = (unsigned long *)(va);
+	b = (unsigned long *)(va + 0x1000);
+
+	old_a = *a;
+	mb();
+
+	*b ^= 0x55555555;
+	mb();
+
+	if (*a != old_a)
+		found = 1;
+	mb();
+
+	*b ^= 0x55555555;
+	mb();
+
+	/* this should always match, but check anyway */
+	if (*a != old_a)
+		found = 1;
+
+	brcm_write_tlb_entry(idx, ENTRYLO_INVALID(), ENTRYLO_INVALID(),
+		UNIQUE_ENTRYHI(idx), PM_4K);
+
+	if (found)
+		panic("DRAM%d wraparound detected at 0x%lx\n",
+			memc_no, midpoint);
+}
+
+void __init brcm_wraparound_check(void)
+{
+	/*
+	 * Find the middle of the DRAM region, compensating for the memory
+	 * hole at the 256MB mark if necessary.  If there is no wraparound
+	 * at the middle address, everything else should be OK.
+	 */
+	if (brcm_dram0_size_mb >= 512)
+		__brcm_wraparound_check(0,
+			(brcm_dram0_size_mb << 19) + 0x10000000, 0);
+	else
+		__brcm_wraparound_check(0, brcm_dram0_size_mb << 19, 0);
+
+	if (brcm_dram1_size_mb)
+		__brcm_wraparound_check(MEMC1_START,
+			brcm_dram1_size_mb << 19, 1);
+}
diff --git a/arch/mips/brcmstb/prom.c b/arch/mips/brcmstb/prom.c
new file mode 100644
index 0000000..f0126ea
--- /dev/null
+++ b/arch/mips/brcmstb/prom.c
@@ -0,0 +1,509 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/ctype.h>
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/fs.h>
+#include <linux/root_dev.h>
+#include <linux/types.h>
+#include <linux/smp.h>
+#include <linux/bmoca-compat.h>
+#include <linux/version.h>
+#include <linux/serial_reg.h>
+#include <linux/io.h>
+#include <linux/string.h>
+#include <linux/compiler.h>
+#include <linux/pci.h>
+#include <linux/console.h>
+#include <linux/mtd/mtd.h>
+
+#include <asm/bootinfo.h>
+#include <asm/r4kcache.h>
+#include <asm/traps.h>
+#include <asm/cacheflush.h>
+#include <asm/mipsregs.h>
+#include <asm/hazards.h>
+#include <asm/smp-ops.h>
+#include <asm/reboot.h>
+#include <asm/fw/cfe/cfe_api.h>
+#include <asm/fw/cfe/cfe_error.h>
+
+#include <linux/brcmstb/brcmstb.h>
+#include <spaces.h>
+
+int cfe_lock_console_in = 1;
+
+unsigned long __initdata cfe_seal;
+unsigned long __initdata cfe_entry;
+unsigned long __initdata cfe_handle;
+
+#ifdef CONFIG_CMDLINE_BOOL
+static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE;
+#endif
+
+/***********************************************************************
+ * CFE bootloader queries
+ ***********************************************************************/
+
+static int __init hex(char ch)
+{
+	if (ch >= 'a' && ch <= 'f')
+		return ch-'a'+10;
+	if (ch >= '0' && ch <= '9')
+		return ch-'0';
+	if (ch >= 'A' && ch <= 'F')
+		return ch-'A'+10;
+	return -1;
+}
+
+static int __init hex16(const char *b)
+{
+	int d0, d1;
+
+	d0 = hex(b[0]);
+	d1 = hex(b[1]);
+	if ((d0 == -1) || (d1 == -1))
+		return -1;
+	return (d0 << 4) | d1;
+}
+
+void __init cfe_die(char *fmt, ...)
+{
+	char msg[128];
+	va_list ap;
+	int handle;
+	unsigned int count;
+
+	va_start(ap, fmt);
+	vsprintf(msg, fmt, ap);
+	strcat(msg, "\r\n");
+
+	if (cfe_seal != CFE_EPTSEAL)
+		goto no_cfe;
+
+	/* disable XKS01 so that CFE can access the registers */
+
+#if defined(CONFIG_CPU_BMIPS4380)
+	__write_32bit_c0_register($22, 3,
+		__read_32bit_c0_register($22, 3) & ~BIT(12));
+#elif defined(CONFIG_CPU_BMIPS5000)
+	__write_32bit_c0_register($22, 5,
+		__read_32bit_c0_register($22, 5) & ~BIT(8));
+#endif
+
+	handle = cfe_getstdhandle(CFE_STDHANDLE_CONSOLE);
+	if (handle < 0)
+		goto no_cfe;
+
+	cfe_write(handle, msg, strlen(msg));
+
+	for (count = 0; count < 0x7fffffff; count++)
+		mb();
+	cfe_exit(0, 1);
+	while (1)
+		;
+
+no_cfe:
+	/* probably won't print anywhere useful */
+	printk(KERN_ERR "%s", msg);
+	BUG();
+
+	va_end(ap);
+}
+
+static inline int __init parse_eth0_hwaddr(const char *buf, u8 *out)
+{
+	int i, t;
+	u8 addr[6];
+
+	for (i = 0; i < 6; i++) {
+		t = hex16(buf);
+		if (t == -1)
+			return -1;
+		addr[i] = t;
+		buf += 3;
+	}
+	memcpy(out, addr, 6);
+
+	return 0;
+}
+
+static inline int __init parse_eth0_mdio_mode(const char *buf,
+	unsigned long *val)
+{
+	if (strcmp(buf, "boot") == 0 || strcmp(buf, "0") == 0)
+		*val = 1;
+	return 0;
+}
+
+static inline int __init parse_ulong(const char *buf, unsigned long *val)
+{
+	char *endp;
+	unsigned long tmp;
+
+	tmp = simple_strtoul(buf, &endp, 0);
+	if (*endp == 0) {
+		*val = tmp;
+		return 0;
+	}
+	return -1;
+}
+
+static inline int __init parse_hex(const char *buf, unsigned long *val)
+{
+	char *endp;
+	unsigned long tmp;
+
+	tmp = simple_strtoul(buf, &endp, 16);
+	if (*endp == 0) {
+		*val = tmp;
+		return 0;
+	}
+	return -1;
+}
+
+static inline int __init parse_cmdline(const char *buf, char *dst)
+{
+	strlcpy(dst, buf, COMMAND_LINE_SIZE);
+	return 0;
+}
+
+static inline int __init parse_string(const char *buf, char *dst)
+{
+	strlcpy(dst, buf, CFE_STRING_SIZE);
+	return 0;
+}
+
+static char __initdata cfe_buf[COMMAND_LINE_SIZE];
+
+static void __init __maybe_unused cfe_read_configuration(void)
+{
+	int fetched = 0;
+
+	printk(KERN_INFO "Fetching vars from bootloader... ");
+	if (cfe_seal != CFE_EPTSEAL) {
+		printk(KERN_CONT "none present, using defaults.\n");
+		return;
+	}
+
+#define DPRINTK(...) do { } while (0)
+/* #define DPRINTK(...) printk(__VA_ARGS__) */
+
+#define FETCH(name, fn, arg) do { \
+	if (cfe_getenv(name, cfe_buf, COMMAND_LINE_SIZE) == CFE_OK) { \
+		DPRINTK("Fetch var '%s' = '%s'\n", name, cfe_buf); \
+		fn(cfe_buf, arg); \
+		fetched++; \
+	} else { \
+		DPRINTK("Could not fetch var '%s'\n", name); \
+	} \
+	} while (0)
+
+	FETCH("ETH0_HWADDR", parse_eth0_hwaddr, brcm_eth0_macaddr);
+	FETCH("ETH0_MDIO_MODE", parse_eth0_mdio_mode, &brcm_eth0_no_mdio);
+	FETCH("ETH0_PHY", parse_string, brcm_eth0_phy);
+	FETCH("ETH0_PHYADDR", parse_string, brcm_eth0_phyaddr);
+	FETCH("ETH0_SPEED", parse_ulong, &brcm_eth0_speed);
+
+	memcpy(brcm_moca0_macaddr, brcm_eth0_macaddr, ETH_ALEN);
+	macaddr_increment(brcm_moca0_macaddr, ETH_ALEN, 1);
+	FETCH("MOCA0_HWADDR", parse_eth0_hwaddr, brcm_moca0_macaddr);
+
+	FETCH("DRAM0_SIZE", parse_ulong, &brcm_dram0_size_mb);
+	FETCH("DRAM1_SIZE", parse_ulong, &brcm_dram1_size_mb);
+	FETCH("CFE_BOARDNAME", parse_string, brcm_cfe_boardname);
+	FETCH("BOOT_FLAGS", parse_cmdline, arcs_cmdline);
+
+	FETCH("LINUX_FFS_STARTAD", parse_hex, &brcm_mtd_rootfs_start);
+	FETCH("LINUX_FFS_SIZE", parse_hex, &brcm_mtd_rootfs_len);
+	FETCH("LINUX_PART_STARTAD", parse_hex, &brcm_mtd_kernel_start);
+	FETCH("LINUX_PART_SIZE", parse_hex, &brcm_mtd_kernel_len);
+	FETCH("OCAP_PART_STARTAD", parse_hex, &brcm_mtd_ocap_start);
+	FETCH("OCAP_PART_SIZE", parse_hex, &brcm_mtd_ocap_len);
+	FETCH("FLASH_SIZE", parse_ulong, &brcm_mtd_flash_size_mb);
+	FETCH("FLASH_TYPE", parse_string, brcm_mtd_flash_type);
+
+	printk(KERN_CONT "found %d vars.\n", fetched);
+}
+
+/***********************************************************************
+ * Early printk
+ ***********************************************************************/
+
+static unsigned long brcm_early_uart;
+
+#define UART_REG(x)		(brcm_early_uart + ((x) << 2))
+#define BAUD			115200
+
+static void __init init_port(void)
+{
+	unsigned int divisor;
+
+	BDEV_WR(UART_REG(UART_LCR), 0x3);	/* 8n1 */
+	BDEV_WR(UART_REG(UART_IER), 0);		/* no interrupt */
+	BDEV_WR(UART_REG(UART_FCR), 0);		/* no fifo */
+	BDEV_WR(UART_REG(UART_MCR), 0x3);	/* DTR + RTS */
+
+	BDEV_SET(UART_REG(UART_LCR), UART_LCR_DLAB);
+#if defined(CONFIG_BRCM_IKOS)
+	/* Reverse-engineer brcm_base_baud0 from the bootloader's setting */
+
+	divisor = (BDEV_RD(UART_REG(UART_DLM)) << 8) |
+		BDEV_RD(UART_REG(UART_DLL));
+	brcm_base_baud0 = divisor * BAUD;
+#endif
+	divisor = (brcm_base_baud0 + BAUD/2) / BAUD;
+	BDEV_WR(UART_REG(UART_DLL), divisor & 0xff);
+	BDEV_WR(UART_REG(UART_DLM), (divisor >> 8) & 0xff);
+	BDEV_UNSET(UART_REG(UART_LCR), UART_LCR_DLAB);
+}
+
+void prom_putchar(char x)
+{
+	while (!(BDEV_RD(UART_REG(UART_LSR)) & UART_LSR_THRE))
+		;
+	BDEV_WR(UART_REG(UART_TX), x);
+}
+
+int lock_console_in(void) {
+	return cfe_lock_console_in;
+}
+
+static void __init brcm_setup_early_printk(void)
+{
+	char *arg = strstr(arcs_cmdline, "console=");
+	int dev = CONFIG_BRCM_CONSOLE_DEVICE;
+	const unsigned long base[] = {
+		BCHP_UARTA_REG_START, BCHP_UARTB_REG_START,
+#ifdef CONFIG_BRCM_HAS_UARTC
+		BCHP_UARTC_REG_START,
+#endif
+		0, 0,
+	};
+
+	if (strstr(arcs_cmdline, "login=") || strstr(arcs_cmdline, "debug=")) {
+		cfe_lock_console_in = 0;
+	}
+
+	/*
+	 * quick command line parse to pick the early printk console
+	 * valid formats:
+	 *   console=ttyS0,115200
+	 *   console=0,115200
+	 */
+	while (arg && *arg != '\0' && *arg != ' ') {
+		if ((*arg >= '0') && (*arg <= '3')) {
+			dev = *arg - '0';
+			if (base[dev] == 0)
+				dev = 0;
+			break;
+		}
+		arg++;
+	}
+	brcm_early_uart = base[dev];
+	init_port();
+}
+
+/***********************************************************************
+ * Main entry point
+ ***********************************************************************/
+
+void __init prom_init(void)
+{
+	char *ptr;
+
+	cfe_init(cfe_handle, cfe_entry);
+
+	bchip_check_compat();
+	brcmstb_cpu_setup();
+
+	/* default to SATA (where available) or MTD rootfs */
+#ifdef CONFIG_BRCM_HAS_SATA
+	ROOT_DEV = Root_SDA1;
+#else
+	ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 0);
+#endif
+	root_mountflags &= ~MS_RDONLY;
+
+	bchip_set_features();
+
+#if defined(CONFIG_BRCM_IKOS_DEBUG)
+	strcpy(arcs_cmdline, "debug initcall_debug");
+#elif !defined(CONFIG_BRCM_IKOS)
+	cfe_read_configuration();
+#endif
+	brcm_setup_early_printk();
+
+#ifdef CONFIG_CMDLINE_BOOL
+#ifdef CONFIG_CMDLINE_OVERRIDE
+	strlcpy(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
+#else
+	if (builtin_cmdline[0]) {
+		strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
+		strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
+	}
+#endif
+#endif
+	/* provide "ubiroot" alias to reduce typing */
+	if (strstr(arcs_cmdline, "ubiroot"))
+		strcat(arcs_cmdline, " ubi.mtd=rootfs rootfstype=ubifs "
+			"root=ubi0:rootfs");
+
+	ptr = strstr(arcs_cmdline, "memc1=");
+	if (ptr)
+		brcm_dram1_linux_mb = memparse(ptr + 6, &ptr) >> 20;
+
+	printk(KERN_INFO "Options: moca=%d sata=%d pcie=%d usb=%d\n",
+		brcm_moca_enabled, brcm_sata_enabled,
+		brcm_pcie_enabled, brcm_usb_enabled);
+
+	bchip_early_setup();
+	board_pinmux_setup();
+
+	board_get_ram_size(&brcm_dram0_size_mb, &brcm_dram1_size_mb);
+
+	do {
+		unsigned long dram0_mb = brcm_dram0_size_mb, mb;
+
+		mb = min(dram0_mb, BRCM_MAX_LOWER_MB);
+		dram0_mb -= mb;
+
+		add_memory_region(0, mb << 20, BOOT_MEM_RAM);
+		if (!dram0_mb)
+			break;
+
+#ifdef CONFIG_BRCM_UPPER_MEMORY
+		mb = min(dram0_mb, BRCM_MAX_UPPER_MB);
+		dram0_mb -= mb;
+
+		plat_wired_tlb_setup();
+		add_memory_region(UPPERMEM_START, mb << 20, BOOT_MEM_RAM);
+		if (!dram0_mb)
+			break;
+#endif
+
+#if defined(CONFIG_HIGHMEM)
+		add_memory_region(HIGHMEM_START, dram0_mb << 20, BOOT_MEM_RAM);
+		break;
+#endif
+		/*
+		 * We wound up here because the chip's architecture cannot
+		 * make use of all MEMC0 RAM in Linux.  i.e. no suitable
+		 * HIGHMEM or upper memory options are supported by the CPU.
+		 *
+		 * But we can still report the excess memory as a "bonus"
+		 * reserved (bmem) region, so the application can manage it.
+		 */
+		mb = brcm_dram0_size_mb - dram0_mb;	/* Linux memory */
+		if (!brcm_dram1_size_mb) {
+			printk(KERN_INFO "MEMC0 split: %lu MB -> Linux; "
+				"%lu MB -> extra bmem\n", mb, dram0_mb);
+			brcm_dram1_size_mb = dram0_mb;
+			brcm_dram1_start = UPPERMEM_START;
+		}
+	} while (0);
+
+#if defined(CONFIG_HIGHMEM) && defined(CONFIG_BRCM_HAS_1GB_MEMC1)
+	if (brcm_dram1_linux_mb > brcm_dram1_size_mb) {
+		printk(KERN_WARNING "warning: 'memc1=%luM' exceeds "
+			"available memory (%lu MB); ignoring\n",
+			brcm_dram1_linux_mb, brcm_dram1_size_mb);
+		brcm_dram1_linux_mb = 0;
+	} else if (brcm_dram1_linux_mb)
+		add_memory_region(MEMC1_START, brcm_dram1_linux_mb << 20,
+			BOOT_MEM_RAM);
+#else
+	if (brcm_dram1_linux_mb) {
+		printk(KERN_WARNING "warning: MEMC1 is not available on this "
+			"system; ignoring\n");
+		brcm_dram1_linux_mb = 0;
+	}
+#endif
+
+	board_ebase_setup = &bmips_ebase_setup;
+	register_bmips_smp_ops();
+}
+
+/***********************************************************************
+ * NMI hook
+ ***********************************************************************/
+
+static void (*nmi_fn)(struct pt_regs *);
+
+static int brcm_nmi_notifier(struct notifier_block *nb,
+	unsigned long val, void *v)
+{
+	nmi_fn(NULL);
+	return 0;
+}
+
+void brcm_set_nmi_handler(void (*fn)(struct pt_regs *))
+{
+	nmi_notifier(brcm_nmi_notifier, 0);
+}
+EXPORT_SYMBOL(brcm_set_nmi_handler);
+
+/***********************************************************************
+ * Miscellaneous utility functions
+ ***********************************************************************/
+
+static char brcm_system_type[64];
+
+const char *get_system_type(void)
+{
+	u32 class = BRCM_CHIP_ID();
+
+	if (class >> 16 == 0)
+		class >>= 8;
+	else
+		class >>= 12;
+
+	snprintf(brcm_system_type, 64, "BCM%04x%02X %s platform",
+		BRCM_CHIP_ID(), BRCM_CHIP_REV() + 0xa0,
+		class == 0x35 ? "DTV" :
+		(class == 0x76 ? "DVD" : "STB"));
+
+	return (const char *)brcm_system_type;
+}
+
+void __init prom_free_prom_memory(void) {}
+
+static void brcm_machine_restart_mips(char *command)
+{
+	dma_cache_wback_inv(0, ~0);
+
+	/* On ARM the argument needs to be const */
+	brcm_machine_restart(command);
+}
+
+void __init plat_mem_setup(void)
+{
+	_machine_restart = brcm_machine_restart_mips;
+	_machine_halt = brcm_machine_halt;
+	pm_power_off = brcm_machine_halt;
+
+	brcm_wraparound_check();
+	panic_timeout = 10;
+
+#ifdef CONFIG_PCI
+	pcibios_plat_setup = brcmstb_pcibios_setup;
+#endif
+
+	add_preferred_console("ttyS", CONFIG_BRCM_CONSOLE_DEVICE, "115200");
+}
diff --git a/arch/mips/brcmstb/s3_standby.S b/arch/mips/brcmstb/s3_standby.S
new file mode 100644
index 0000000..1273f91
--- /dev/null
+++ b/arch/mips/brcmstb/s3_standby.S
@@ -0,0 +1,279 @@
+/*
+ * Copyright (C) 2011 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/addrspace.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#define REG_OFFSET		(KSEG1 | BCHP_PHYSICAL_OFFSET)
+#define REG(x)			(REG_OFFSET + (x))
+
+/*
+ * Bootloader parameters for warm boot:
+ *	byte offset	value
+ *	0-3:		magic word
+ *	4-7:		reentry address
+ *	8-11:		m2m descriptors PA
+ *	12-15:		encryption slot
+ *	16-19:		address of hash
+ *	20-35:		hash
+ */
+	.text
+	.set		noreorder
+	.align		5
+	.global		s3_reentry
+
+#if defined(CONFIG_CPU_BMIPS5000)
+#define CACHE_WRITEBACK_CMD	Hit_Writeback_Inv_SD
+#else
+#define CACHE_WRITEBACK_CMD	Hit_Writeback_Inv_D
+#endif
+
+/*
+ * We do not need stack frame, the entire context gets saved
+ * in a dedicated structure brcm_pm_s3_context
+ * Upon warm reboot the context gets restored from this structure
+ * Parameters:
+ *	a0: options
+ *	a1: dram encoder start function or NULL if not installed
+ *	a2: d-cache line size
+ */
+	LEAF(brcm_pm_s3_standby_asm)
+
+	la	t0, s3_context
+	/* general purpose registers */
+	sw	ra, 0(t0)
+	sw	s0, 4(t0)
+	sw	s1, 8(t0)
+	sw	s2, 12(t0)
+	sw	s3, 16(t0)
+	sw	s4, 20(t0)
+	sw	s5, 24(t0)
+	sw	s6, 28(t0)
+	sw	s7, 32(t0)
+	sw	gp, 36(t0)
+	sw	sp, 40(t0)
+	sw	fp, 44(t0)
+
+	mfc0	t1, CP0_STATUS
+# save cp0 sr
+	sw	t1, 48(t0)
+
+# Write-back gp registers - cache will be gone after wakeup
+# align context area address to the cache line
+	addiu	t1, a2, -1
+	not	t1
+	and	t0, t1
+
+# flush at least 64 bytes
+	addiu	t2, t0, 64
+	and	t2, t1
+
+1:	cache	CACHE_WRITEBACK_CMD, 0(t0)
+	bne	t0, t2, 1b
+	addu	t0, a2
+
+	beqz	a1, skip_dram_encode
+	nop
+
+	/*
+	 * Call DRAM encoder start method if it was installed
+	 * Nobody can modify DRAM content by now.
+	 */
+	jal	a1
+	nop
+
+/* NOTE: Uncommenting this block will force hash mismatch
+ * if .data segment is in the authentication region.
+ * Use for CFE secure warm boot testing.
+ */
+#	la	t0, secure_s3_dummy_data
+#	lw	t1, 0(t0)
+#	addi	t1, 1
+#	sw	t1, 0(t0)
+#	cache	CACHE_WRITEBACK_CMD, 0(t0)
+#	nop
+
+skip_dram_encode:
+
+	li	t0, REG(BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT)
+	li	t1, 0xffff
+	sw	t1, 0(t0)
+	lw	zero, 0(t0)
+
+# deep power down request
+pd_request:
+	li	t0, REG(BCHP_AON_CTRL_PM_CTRL)
+# SET: pm_deep_standby, pm_warm_boot, pm_enable_pll_pwrdn
+	li	t1, 0x32
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+	sw	t1, 0(t0)
+	lw	zero, 0(t0)
+
+# SET: pm_start_pwrdn
+	li	t1, 0x33
+	sw	t1, 0(t0)
+	lw	zero, 0(t0)
+
+/***********************************************************************
+ * Wait for interrupt
+ ***********************************************************************/
+wait_loop:
+# enable int2 and then wait for an interrupt
+	mfc0	t0, CP0_STATUS
+
+	li	t1, ~(ST0_IM | ST0_IE)
+	and	t0, t1
+	ori	t0, STATUSF_IP2
+	mtc0	t0, CP0_STATUS
+	nop
+	nop
+	nop
+	ori	t0, ST0_IE
+	mtc0	t0, CP0_STATUS
+	wait
+	nop
+
+s3_reentry:
+
+#ifdef CONFIG_CPU_BMIPS5000
+# clear CRS and JTB
+	li	t0, (0x06 << 16)
+	mtc0	t0, $22, 2
+	ssnop
+	ssnop
+	ssnop
+
+	li	t0, (0x04 << 16)
+	mtc0	t0, $22, 2
+	ssnop
+	ssnop
+	ssnop
+#endif
+
+#ifdef CONFIG_CPU_BMIPS4380
+# flush 4-entry call/return stack
+	jal	1f
+	nop
+1:	jal	1f
+	nop
+1:	jal	1f
+	nop
+1:	jal	1f
+	nop
+1:
+#endif
+
+# restore sr
+	sync
+	nop
+
+s3_standby_exit:
+#ifdef CONFIG_BRCM_UPPER_768MB
+#if defined(CONFIG_CPU_BMIPS4380)
+	mfc0	t0, $22, 3
+	li	t1, 0x1ff0
+	li	t2, (1 << 12) | (1 << 9)
+	or	t0, t1
+	xor	t0, t1
+	or	t0, t2
+	mtc0	t0, $22, 3
+#elif defined(CONFIG_CPU_BMIPS5000)
+	mfc0	t0, $22, 5
+	li	t1, 0x01ff
+	li	t2, (1 << 8) | (1 << 5)
+	or	t0, t1
+	xor	t0, t1
+	or	t0, t2
+	mtc0	t0, $22, 5
+#endif
+#endif
+	sync
+	nop
+
+	/* setup mmu defaults */
+	mtc0	zero, CP0_WIRED
+	mtc0	zero, CP0_ENTRYHI
+	li	k0, PM_DEFAULT_MASK
+	mtc0	k0, CP0_PAGEMASK
+
+#ifdef CONFIG_BRCM_UPPER_MEMORY
+	li	sp, BRCM_WARM_RESTART_VEC
+	la	k0, plat_wired_tlb_setup
+	jalr	k0
+	nop
+#endif
+
+# return to caller
+	/* general purpose registers */
+	la	t0, s3_context
+	lw	ra, 0(t0)
+	lw	s0, 4(t0)
+	lw	s1, 8(t0)
+	lw	s2, 12(t0)
+	lw	s3, 16(t0)
+	lw	s4, 20(t0)
+	lw	s5, 24(t0)
+	lw	s6, 28(t0)
+	lw	s7, 32(t0)
+	lw	gp, 36(t0)
+	lw	sp, 40(t0)
+	lw	fp, 44(t0)
+
+# restore cp0 sr
+	lw	t1, 48(t0)
+	mtc0	t1, CP0_STATUS
+
+	li	v0, 1
+	jr	ra
+	nop
+
+
+	END(brcm_pm_s3_standby_asm)
+
+	.align 4
+	.data
+secure_s3_dummy_data:	.word 0
+
+#define UART_LSR_OFFSET		0x14
+#define UART_LSR_MASK		BCHP_UARTA_LSR_THRE_MASK
+#define UART_TX_OFFSET		0x00
+
+__dputc:
+
+	li	t1, REG(BCHP_UARTA_REG_START)
+1:
+	lw	t2, UART_LSR_OFFSET(t1)
+	andi	t2, UART_LSR_MASK
+	beqz	t2, 1b
+	nop
+
+	sw	a0, UART_TX_OFFSET(t1)
+
+1:	lw	t2, UART_LSR_OFFSET(t1)
+	andi	t2, UART_LSR_MASK
+	beqz	t2, 1b
+	nop
+	jr	ra
+	nop
+
+s3_standby_section_end:
+	nop
diff --git a/arch/mips/brcmstb/standby.S b/arch/mips/brcmstb/standby.S
new file mode 100644
index 0000000..38b53f9
--- /dev/null
+++ b/arch/mips/brcmstb/standby.S
@@ -0,0 +1,1195 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <asm/asm.h>
+#include <asm/regdef.h>
+#include <asm/mipsregs.h>
+#include <asm/cacheops.h>
+#include <asm/addrspace.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#define REG_OFFSET		(KSEG1 | BCHP_PHYSICAL_OFFSET)
+#define REG(x)			(REG_OFFSET + (x))
+#define UPG_USEC_TICKS		(UPGTMR_FREQ / 1000000)
+
+/* debug output - BRCM_STANDBY_VERBOSE */
+#define UART_BASE		BCHP_UARTA_REG_START
+#define UART_LSR_OFFSET		0x14
+#define UART_LSR_MASK		BCHP_UARTA_LSR_THRE_MASK
+#define UART_TX_OFFSET		0x00
+
+#define USE_WATCHDOG		0
+
+#if defined(BCHP_AON_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK) || \
+ defined(BCHP_SUN_TOP_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK)
+#define PM_CMD_BASE		0x0b
+#else
+#define PM_CMD_BASE		0x03
+#endif
+
+#if defined(CONFIG_CPU_BMIPS5000)
+#define PM_USE_MIPS_READY	0x04
+#else
+#define PM_USE_MIPS_READY	0x00
+#endif
+
+#define PM_STANDBY_COMMAND	(PM_CMD_BASE|PM_USE_MIPS_READY)
+
+#ifdef BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL
+#define VCDL_SAVE_REG		BCHP_MEMC_DDR23_APHY_WL1_0_SPARE0_RW
+#define RELOAD_VCDL		1
+#else
+#define RELOAD_VCDL		0
+#endif
+
+#if defined(CONFIG_BRCM_HAS_AON)
+#define PM_WAIT_COUNT		BCHP_AON_CTRL_PM_MIPS_WAIT_COUNT
+#define PM_CONTROL		BCHP_AON_CTRL_PM_CTRL
+#define PM_STATUS		BCHP_AON_CTRL_PM_STATUS
+#define PM_STATUS_bsp_ready	BCHP_AON_CTRL_PM_STATUS_pm_bsp_ready_for_pwrdn_MASK
+#else
+#define PM_WAIT_COUNT		BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT
+#define PM_CONTROL		BCHP_SUN_TOP_CTRL_PM_CTRL
+#define PM_STATUS		PM_CONTROL
+#define PM_STATUS_bsp_ready	BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_MASK
+#endif
+
+#define FLAGREG			s5
+
+	.text
+	.set	noreorder
+	.align	5
+
+# a0 is icache line size
+# a1 is the interrupt vector (or general exception base)
+# a2 is the interrupt vector size
+# a3 is brcm_pm_standby_flags
+
+	LEAF(brcm_pm_standby_asm)
+	subu	sp, 64
+	sw	ra, 0(sp)
+	sw	s0, 4(sp)
+	sw	s1, 8(sp)
+	sw	s2, 12(sp)
+	sw	s3, 16(sp)
+	sw	s4, 20(sp)
+	sw	s5, 24(sp)
+	sw	s6, 28(sp)
+	sw	s7, 32(sp)
+
+	move	FLAGREG, a3
+
+	bal	memc_settings_valid
+	nop
+	bnez	v0, standby_exit
+	nop
+
+#ifdef BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL
+	/*
+	 * Save VCDL values:
+	 * WL0_0_BYTE0 -> bits 07:00
+	 * WL0_0_BYTE1 -> bits 15:08
+	 * WL1_0_BYTE0 -> bits 23:16
+	 * WL1_0_BYTE1 -> bits 31:24
+	 */
+	li	t0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL)
+	lw	t1, 0(t0)
+	andi	t2, t1, 0x1f
+	lw	t1, 4(t0)
+	andi	t1, t1, 0x1f
+	sll	t1, 8
+	or	t2, t1
+
+	li	t0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_BYTE0_VCDL_PHASE_CNTL)
+	lw	t1, 0(t0)
+	andi	t1, t1, 0x1f
+	sll	t1, 16
+	or	t2, t1
+	lw	t1, 4(t0)
+	andi	t1, t1, 0x1f
+	sll	t1, 24
+	or	t2, t1
+
+	li	t0, REG(VCDL_SAVE_REG)
+	sw	t2, 0(t0)
+	lw	zero, 0(t0)
+#endif
+
+#ifdef CONFIG_CPU_BMIPS5000
+	/*
+	 * reset jump target buffer and call/return stack, to avoid
+	 * unexpected accesses to DRAM
+	 */
+	li	t0, 0x00040000
+	mtc0	t0, $22, 2
+	mfc0	t0, $22, 2
+
+	li	t0, 0x00060000
+	mtc0	t0, $22, 2
+	mfc0	t0, $22, 2
+
+	ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ;
+	ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ;
+	ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ;
+	ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop ; ssnop
+#endif
+
+# lock the asm section into the I-cache
+	move	s0, a0
+	addiu	t1, s0, -1
+	not	t1
+
+	la	t0, brcm_pm_standby_asm
+	and	t0, t1
+
+	la	t2, passiveIRQ_end
+	and	t2, t1
+
+1:	cache	0x1c, 0(t0)
+	bne	t0, t2, 1b
+	addu	t0, s0
+
+# now lock the interrupt vector
+	move	t0, zero
+2:
+	cache	0x1c, 0(a1)
+	addu	a1, s0
+	addu	t0, s0
+	ble	t0, a2, 2b
+	nop
+
+	bal	dputc
+	li	a0, 's'
+
+/***********************************************************************
+ * Flush memory transactions and put MEMC into standby
+ ***********************************************************************/
+	sync
+
+#ifdef CONFIG_BRCM_HAS_ANALOG_DDR_PHY
+	li	t0, BRCM_STANDBY_DDR_PLL_ON
+	and	t0, FLAGREG
+	beqz	t0, 2f
+	nop
+
+	bal	set_pll_frequency
+	li	a0, 0x3d43
+
+	bal	set_pll_frequency
+	li	a0, 0x2d43
+2:
+#endif
+
+#if !defined(CONFIG_BRCM_PWR_HANDSHAKE)
+	li	t0, REG(BCHP_MEMC_DDR_0_SSPD_CMD)
+	li	t1, BCHP_MEMC_DDR_0_SSPD_CMD_SSPD_MASK
+	sw	t1, 0(t0)
+
+	li	t0, REG(BCHP_MEMC_DDR_0_POWER_DOWN_STATUS)
+1:	lw	t1, 0(t0)
+	andi	t1, BCHP_MEMC_DDR_0_POWER_DOWN_STATUS_SSPD_MASK
+	beqz	t1, 1b
+	nop
+
+	bal	dputc
+	li	a0, 'd'
+
+#endif
+
+/*
+ * enable power down of MEMSYS PLL
+ * 7436 and 7425 only
+ */
+#if defined(CONFIG_BCM7346)
+	li	t0, REG(BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT)
+	li	t1, BCHP_CLKGEN_MEMSYS_32_INST_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK
+	sw	t1, 0(t0)
+#endif
+
+#if defined(CONFIG_BCM7425)
+	li	t0, REG(BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT)
+	li	t1, BCHP_CLKGEN_MEMSYS_0_32_POWER_MANAGEMENT_MEMSYS_PLL_PWRDN_POWER_MANAGEMENT_MASK
+	sw	t1, 0(t0)
+#endif
+
+# power down request
+2:
+	/* delay if requested by the user: 4 * 30s */
+	li	t0, BRCM_STANDBY_DELAY
+	and	t0, FLAGREG
+	beqz	t0, 2f
+	nop
+
+	bal	dputc
+	li	a0, 'w'
+
+	li	v1, 4
+1:	li	a0, (UPGTMR_FREQ * 30)
+	bal	delay
+	addiu	v1, -1
+	bnez	v1, 1b
+	nop
+
+	bal	dputc
+	li	a0, 'W'
+
+# power down request
+2:
+	/* set wait count */
+	li	t0, REG(PM_WAIT_COUNT)
+	li	t1, 0xffff
+	sw	t1, 0(t0)
+	lw	zero, 0(t0)
+
+	li	t0, REG(PM_CONTROL)
+	li	t1, PM_STANDBY_COMMAND
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+
+/***********************************************************************
+ * Wait for interrupt
+ ***********************************************************************/
+
+wait_loop:
+# enable int2 and then wait for an interrupt
+	mfc0	t0, CP0_STATUS
+# save cp0 sr
+	move	s2, t0
+
+	li	t1, ~(ST0_IM | ST0_IE)
+	and	t0, t1
+	ori	t0, STATUSF_IP2
+	mtc0	t0, CP0_STATUS
+	nop
+	nop
+	nop
+	ori	t0, ST0_IE
+	mtc0	t0, CP0_STATUS
+	wait
+	nop
+
+/***********************************************************************
+ * Save wakeup timestamp in AON
+ ***********************************************************************/
+#ifdef CONFIG_BRCM_HAS_AON
+	li	t0, REG(BCHP_WKTMR_COUNTER)
+	lw	a0, 0(t0)	/* WKTMR_COUNTER */
+	lw	a1, 12(t0)	/* WKTMR_PRESCALER_VAL */
+	li	t0, REG(AON_RAM_BASE)
+	sw	a0, 0(t0)
+	sw	a1, 4(t0)
+#endif
+
+/***********************************************************************
+ * Bring MEMC back up
+ ***********************************************************************/
+	bal	dputc
+	li	a0, 'M'
+
+#if USE_WATCHDOG
+# arm the watchdog timer
+	li	t0, REG(BCHP_TIMER_WDTIMEOUT)
+	li	t1, 3 * UPGTMR_FREQ
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+
+	li	t0, REG(BCHP_TIMER_WDCMD)
+	li	t1, 0xff00
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+	li	t1, 0x00ff
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+#endif
+
+	/*
+	 * Bypass MEMC wakeup if DDR PLL is on
+	 */
+	li	t0, BRCM_STANDBY_DDR_PLL_ON
+	and	t0, FLAGREG
+	bnez	t0, 2f
+	nop
+
+	bal	wake_up_memc_0
+	nop
+
+2:
+	bal	dputc
+	li	a0, 'm'
+
+#if defined(CONFIG_BRCM_PWR_HANDSHAKE_V0)
+# disarm the BSP
+	li	t0, REG(BCHP_BSP_GLB_CONTROL_REG_START + 0x38)
+	lw	t1, 0(t0)
+	ori	t1, 0xff00
+	xori	t1, 0xfe00
+	sw	t1, 0(t0)
+
+	bal	dputc
+	li	a0, 'B'
+
+	li	t0, REG(PM_STATUS)
+	li	t2, PM_STATUS_bsp_ready
+1:
+	lw	t1, 0(t0)
+	and	t1, t2
+	bnez	t1, 1b
+	nop
+
+	bal	dputc
+	li	a0, 'b'
+#elif defined(CONFIG_BRCM_PWR_HANDSHAKE_V1)
+	li	t0, REG(BCHP_AON_CTRL_HOST_MISC_CMDS)
+	li	t1, BCHP_AON_CTRL_HOST_MISC_CMDS_pm_restore_MASK
+	sw	t1, 0(t0)
+	lw	t1, 0(t0)
+#endif /* CONFIG_BRCM_PWR_HANDSHAKE_V0/V1 */
+
+	li	t0, REG(PM_CONTROL)
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+
+#ifdef CONFIG_BRCM_HAS_ANALOG_DDR_PHY
+	li	t0, BRCM_STANDBY_DDR_PLL_ON
+	and	t0, FLAGREG
+	beqz	t0, 2f
+	nop
+
+	bal	set_pll_frequency
+	li	a0, 0x3d43
+
+	bal	set_pll_frequency
+	li	a0, 0x4a43
+2:
+#endif
+
+/***********************************************************************
+ * Unlock I$ lines and resume execution
+ ***********************************************************************/
+	sync
+
+rtn_from_wait:
+	bal	dputc
+	li	a0, 'S'
+
+# unlock I$ lines
+	addiu	t1, s0, -1
+	not	t1
+
+	la	t0, brcm_pm_standby_asm
+	and	t0, t1
+
+	la	t2, passiveIRQ_end
+	and	t2, t1
+
+1:	cache	Hit_Invalidate_I, 0(t0)
+	bne	t0, t2, 1b
+	addu	t0, s0
+
+	bal	dputc
+	li	a0, 'L'
+
+# restore sr
+	sync
+	nop
+
+	bal	dputc
+	li	a0, 'l'
+	bal	dputc
+	li	a0, 0x0d
+	bal	dputc
+	li	a0, 0x0a
+
+	mtc0	s2, CP0_STATUS
+	nop
+
+	li	v0, 0
+
+standby_exit:
+
+# return to caller
+	lw	s7, 32(sp)
+	lw	s6, 28(sp)
+	lw	s5, 24(sp)
+	lw	s4, 20(sp)
+	lw	s3, 16(sp)
+	lw	s2, 12(sp)
+	lw	s1, 8(sp)
+	lw	s0, 4(sp)
+	lw	ra, 0(sp)
+	addiu	sp, 64
+
+	jr	ra
+	nop
+	END(brcm_pm_standby_asm)
+
+# debug character output
+
+dputc:
+	/* INPUT: char in a0 */
+	/* USES: t1, t2 */
+
+	li	t1, BRCM_STANDBY_VERBOSE
+	and	t1, FLAGREG
+	bnez	t1, 1f
+	nop
+	jr	ra
+	nop
+
+1:
+	li	t1, REG(UART_BASE)
+1:
+	lw	t2, UART_LSR_OFFSET(t1)
+	andi	t2, UART_LSR_MASK
+	beqz	t2, 1b
+	nop
+
+	sw	a0, UART_TX_OFFSET(t1)
+
+1:	lw	t2, UART_LSR_OFFSET(t1)
+	andi	t2, UART_LSR_MASK
+	beqz	t2, 1b
+	nop
+	jr	ra
+	nop
+
+/***********************************************************************
+ * Delay loop
+ ***********************************************************************/
+
+delay:
+# need to reset TIMER1 since it is not normally used
+	li	t2, 0x0
+	li	t1, REG(BCHP_TIMER_TIMER1_CTRL)
+	sw	t2, 0(t1)
+	lw	t2, 0(t1)
+
+	li	t2, 0xbfffffff
+	sw	t2, 0(t1)
+	lw	t2, 0(t1)
+
+	li	t2, 0x3fffffff
+	li	t1, REG(BCHP_TIMER_TIMER1_STAT)
+	lw	t0, 0(t1)
+	and	t0, t2
+	add	t0, a0
+	not	t2
+	and	t2, t0
+	bnez	t2, delay_overflow
+	nop
+
+# wait for timer value (t2) to exceed expiry time (t0)
+1:	lw	t2, 0(t1)
+	sltu	t2, t2, t0
+	bnez	t2, 1b
+	nop
+
+	jr	ra
+	nop
+
+# timer1 overflow (this should never happen)
+delay_overflow:
+	move	t4, ra
+	bal	dputc
+	li	a0, 'O'
+
+	jr	t4
+	nop
+
+/***********************************************************************
+ * PM IRQ handler
+ ***********************************************************************/
+
+LEAF(brcm_pm_irq)
+
+# Block interrupts and then return to the wait loop
+	mfc0	k0, CP0_STATUS
+	li	k1, ~ST0_IE
+	and	k0, k1
+	mtc0	k0, CP0_STATUS
+	eret
+	nop
+
+END(brcm_pm_irq)
+
+/***********************************************************************
+ * MEMC wakeup
+ ***********************************************************************/
+
+#ifdef CONFIG_BRCM_HAS_ANALOG_DDR_PHY
+
+#define SLEEP_1_MILLI_SEC		27000
+
+/***********************************************************************
+ * Delay routine
+ ***********************************************************************/
+LEAF(upg_sleep)
+
+	li	t0, REG(BCHP_TIMER_TIMER0_CTRL)
+	lw	t1, 0(t0)
+
+	/* TIMER_TIMER0_CTRL.MODE  = 1 => count down mode */
+	li	t2, BCHP_TIMER_TIMER0_CTRL_MODE_MASK
+	or	t1, t1, t2
+
+	/* TIMER_TIMER0_CTRL.TIMEOUT_VAL = a0 */
+
+	li	t2, BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK
+	li	t3, BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT
+
+	not	t2, t2
+	and	t1, t1, t2
+	sll	a0, a0, t3
+	or	t1, t1, a0
+
+	sw	t1, 0(t0)
+
+	li	t0, REG(BCHP_TIMER_TIMER_IS)
+	lw	t1, 0(t0)
+
+	/* TIMER_TIMER_IS.TMR0TO = 1 => clears this bit, resets time count */
+
+	#li	t2, ~BCHP_TIMER_TIMER_IS_TMR0TO_MASK
+	#and	t1, t1, t2
+	sw	t1, 0(t0)
+
+	/* TIMER_TIMER0_CTRL.ENA = 1 => start counting */
+
+	li	t0, REG(BCHP_TIMER_TIMER0_CTRL)
+	lw	t1, 0(t0)
+
+	li	t2, BCHP_TIMER_TIMER0_CTRL_ENA_MASK
+	or	t1, t1, t2
+	sw	t1, 0(t0)
+
+	li	t0, REG(BCHP_TIMER_TIMER_IS)
+	li	t2, BCHP_TIMER_TIMER_IS_TMR0TO_MASK
+
+1:	lw	t1, 0(t0)
+	and	t1, t1, t2
+	beq	zero, t1, 1b
+	nop
+
+	/* TIMER_TIMER0_CTRL.ENA = 0 => stop counting */
+
+	li	t0, REG(BCHP_TIMER_TIMER0_CTRL)
+	lw	t1, 0(t0)
+	li	t2, ~BCHP_TIMER_TIMER0_CTRL_ENA_MASK
+	and	t1, t1, t2
+	sw	t1, 0(t0)
+
+	jr	ra
+	nop
+
+END(upg_sleep)
+
+/***********************************************************************
+ * Main MEMC0 recovery function
+ ***********************************************************************/
+LEAF(wake_up_memc_0)
+
+	move	s7, ra
+
+	li	a0, 0
+	bal	set_memc_0_write_dqs_phase_cntl_direct
+	nop
+
+	li	a0, 0
+	bal	set_memc_0_write_dq_phase_cntl_direct
+	nop
+
+	li	a0, 0
+	bal	set_memc_0_pll_ch2_clk_phase_cntrl
+	nop
+
+	li	a0, 0
+	bal	set_memc_0_deskew_bypass_phase
+	nop
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_DDR_PAD_CNTRL)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_WL0_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_DDR_PAD_CNTRL)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_WL1_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_WORDSLICE_CNTRL_1)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_WL0_0_WORDSLICE_CNTRL_1_PWRDN_DLL_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_WORDSLICE_CNTRL_1)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_WL1_0_WORDSLICE_CNTRL_1_PWRDN_DLL_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_AC_0_POWERDOWN)
+	lw	a1, 0(a0)
+	li	a2, ~(BCHP_MEMC_DDR23_APHY_AC_0_POWERDOWN_PLLCLKS_OFF_ON_SELFREF_MASK)
+	and	a1, a1, a2
+	sw	a1, 0(a0)
+
+	bal	reprogram_ddr_pll
+	nop
+
+	jr	s7
+	nop
+
+END(wake_up_memc_0)
+
+/***********************************************************************
+ * VCDL incremental reload
+ * a0 - VCDL register
+ * a1 - maximum value
+ ***********************************************************************/
+reload_vcdl:
+	sll	v0, a1, 8
+	or	a1, v0		# max value to load
+
+	move	v1, zero
+vcdl_loop:
+	addi	v1, 0x0101
+	sw	v1, 0(a0)
+	lw	zero, 0(a0)
+	bne	v1, a1, vcdl_loop
+	nop
+
+	jr	ra
+	nop
+
+/***********************************************************************
+ * Set new DDR PLL frequency divider
+ * Used when suspending with DDR PLL on
+ * a0 - Frequency divider value
+ ***********************************************************************/
+LEAF(set_pll_frequency)
+
+	move	s3, ra
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_FREQ_CNTL)
+	sw	a0, 0(v0)
+	lw	zero, 0(v0)
+
+	li	a0, (27000)
+	bal	upg_sleep
+	nop
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_DDR_PLL_LOCK_STATUS)
+	li	a0, BCHP_MEMC_DDR23_APHY_AC_0_DDR_PLL_LOCK_STATUS_LOCK_STATUS_MASK
+1:
+	lw	v1, 0(v0)
+	and	v1, v1, a0
+
+	beqz	v1, 1b
+	nop
+
+	jr	s3
+	nop
+END(set_pll_frequency)
+
+/***********************************************************************
+ * DDR PLL reset and reconfiguration
+ ***********************************************************************/
+LEAF(reprogram_ddr_pll)
+
+	move	s6, ra
+
+	/* reset the freq divider */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, BCHP_MEMC_DDR23_APHY_AC_0_RESET_FREQ_DIV_RESET_MASK
+	lw	a0, 0(v0)
+	or	a0, a0, v1
+	sw	a0, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* reset the vcxo */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, BCHP_MEMC_DDR23_APHY_AC_0_RESET_VCXO_RESET_MASK
+	lw	a0, 0(v0)
+	or	a0, a0, v1
+	sw	a0, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* reset DATAPATH_216, RD_DATAPATH_RESET, RESET_DATAPATH_DDR  */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, (BCHP_MEMC_DDR23_APHY_AC_0_RESET_DATAPATH_216_RESET_MASK | \
+		     BCHP_MEMC_DDR23_APHY_AC_0_RESET_RD_DATAPATH_RESET_MASK | \
+		     BCHP_MEMC_DDR23_APHY_AC_0_RESET_DATAPATH_DDR_RESET_MASK)
+	lw	a0, 0(v0)
+	or	a0, a0, v1
+	sw	a0, 0(v0)
+
+	/* de-assert reset from vcxo */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, ~BCHP_MEMC_DDR23_APHY_AC_0_RESET_VCXO_RESET_MASK
+	lw	a0, 0(v0)
+	and	a0, a0, v1
+	sw	a0, 0(v0)
+
+	/* de-assert reset from freq divider */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	li	v1, ~BCHP_MEMC_DDR23_APHY_AC_0_RESET_FREQ_DIV_RESET_MASK
+	lw	a0, 0(v0)
+	and	a0, a0, v1
+	sw	a0, 0(v0)
+
+	/* wait for 1ms for stable clock */
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* check for pll lock */
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_DDR_PLL_LOCK_STATUS)
+	li	a0, BCHP_MEMC_DDR23_APHY_AC_0_DDR_PLL_LOCK_STATUS_LOCK_STATUS_MASK
+1:
+	lw	v1, 0(v0)
+	and	v1, v1, a0
+
+	beqz	v1, 1b
+	nop
+
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA4)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_wl0_dq_phase
+	nop
+
+	/* set wl1_dq phase */
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA5)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_wl1_dq_phase
+	nop
+
+	/* set ch2 phase */
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA6)
+	lw	a0, 0(a1)
+
+	move	a1, a0
+	and	a0, a0, zero
+1:
+	bal	set_memc_0_pll_ch2_clk_phase_cntrl
+	nop
+	add	a0, a0, 1
+
+	bne	a0, a1, 1b
+	nop
+
+	/* set ch6 phase */
+	li	a1, REG(BCHP_MEMC_MISC_0_SCRATCH_0)
+	lw	a0, 0(a1)
+
+	move	a1, a0
+	and	a0, a0, zero
+1:
+	bal	set_memc_0_deskew_bypass_phase
+	nop
+
+	add	a0, a0, 1
+
+	bne	a0, a1, 1b
+	nop
+
+	/* set wl0_dqs0 phases */
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA0)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_dqs0_phase
+	nop
+
+	/* set wl0_dqs1 phases */
+
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA1)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_dqs1_phase
+	nop
+
+	/* set wl1_dqs0 phases */
+
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA2)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_dqs2_phase
+	nop
+	/* set wl1_dqs1 phases */
+
+	li	a1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA3)
+	lw	a0, 0(a1)
+
+	bal	set_memc_0_dqs3_phase
+	nop
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL)
+	lw	v1, 0(v0)
+	ori     v1, (BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_MASK | BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK)
+	xori	v1, (BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL_DEVCLK_OFF_ON_SELFREF_MASK | BCHP_MEMC_DDR23_APHY_AC_0_DDR_PAD_CNTRL_IDDQ_MODE_ON_SELFREF_MASK)
+	sw	v1, 0(v0)
+	lw	zero, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* reset the word slice dll */
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_WORD_SLICE_DLL_RESET)
+	li	v1, 1
+	sw	v1, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_WORD_SLICE_DLL_RESET)
+	sw	v1, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* reset VCDL values */
+	li	t0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL)
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+	sw	zero, 4(t0)
+	lw	zero, 4(t0)
+
+	li	t0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_BYTE0_VCDL_PHASE_CNTL)
+	sw	zero, 0(t0)
+	lw	zero, 0(t0)
+	sw	zero, 4(t0)
+	lw	zero, 4(t0)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_WORD_SLICE_DLL_RESET)
+	li	v1, 0
+	sw	v1, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_WORD_SLICE_DLL_RESET)
+	sw	v1, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/* de-assert reset from DATAPATH_216 and DATAPATH_DDR */
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_RESET)
+	lw	v1, 0(v0)
+
+	/* de-assert reset from DATAPATH_216_RESET */
+	li	a0, ~(BCHP_MEMC_DDR23_APHY_AC_0_RESET_DATAPATH_216_RESET_MASK)
+	and	v1, v1, a0
+	sw	v1, 0(v0)
+
+	/* de-assert reset from RD_DATAPATH_RESET */
+	li	a0, ~(BCHP_MEMC_DDR23_APHY_AC_0_RESET_RD_DATAPATH_RESET_MASK)
+	and	v1, v1, a0
+	sw	v1, 0(v0)
+
+	/* de-assert reset from DATAPATH_DDR_RESET */
+	li	a0, ~(BCHP_MEMC_DDR23_APHY_AC_0_RESET_DATAPATH_DDR_RESET_MASK)
+	and	v1, v1, a0
+	sw	v1, 0(v0)
+
+	li	a0, (SLEEP_1_MILLI_SEC)
+	bal	upg_sleep
+	nop
+
+	/*
+	 * Reload VCDL values:
+	 * WL0_0_BYTE0 <- bits 07:00
+	 * WL0_0_BYTE1 <- bits 15:08
+	 * WL1_0_BYTE0 <- bits 23:16
+	 * WL1_0_BYTE1 <- bits 31:24
+	 */
+
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_BYTE0_VCDL_PHASE_CNTL)
+	li	t0, REG(VCDL_SAVE_REG)
+	lw	t0, 0(t0)
+	bal	reload_vcdl
+	andi	a1, t0, 0x1f
+
+	srl	a1, t0, 8
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL0_0_BYTE1_VCDL_PHASE_CNTL)
+	bal	reload_vcdl
+	andi	a1, 0x1f
+
+	srl	a1, t0, 16
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_BYTE0_VCDL_PHASE_CNTL)
+	bal	reload_vcdl
+	andi	a1, 0x1f
+
+	srl	a1, t0, 24
+	li	a0, REG(BCHP_MEMC_DDR23_APHY_WL1_0_BYTE1_VCDL_PHASE_CNTL)
+	bal	reload_vcdl
+	andi	a1, 0x1f
+
+	jr	s6
+	nop
+
+END(reprogram_ddr_pll)
+
+LEAF(set_memc_0_write_dqs_phase_cntl_direct)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH4_WL0_DQS0_PHASE_CNTRL)
+	sw	a0, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH5_WL0_DQS1_PHASE_CNTRL)
+	sw	a0, 0(v0)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH8_WL1_DQS0_PHASE_CNTRL)
+	sw	a0, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH9_WL1_DQS1_PHASE_CNTRL)
+	sw	a0, 0(v0)
+
+	jr	ra
+	nop
+
+END(set_memc_0_write_dqs_phase_cntl_direct)
+
+LEAF(set_memc_0_write_dq_phase_cntl_direct)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH3_WL0_DQ_PHASE_CNTRL)
+	sw	a0, 0(v0)
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH7_WL1_DQ_PHASE_CNTRL)
+	sw	a0, 0(v0)
+
+	jr	ra
+	nop
+
+END(set_memc_0_write_dq_phase_cntl_direct)
+
+LEAF(set_memc_0_pll_ch2_clk_phase_cntrl)
+
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH2_CLOCK_PHASE_CNTRL)
+	sw	a0, 0(v0)
+
+	jr	ra
+	nop
+END(set_memc_0_pll_ch2_clk_phase_cntrl)
+
+LEAF(set_memc_0_deskew_bypass_phase)
+
+	li	t8, REG(BCHP_MEMC_DDR23_APHY_AC_0_DESKEW_DLL_CNTRL)
+	lw	t7, 0(t8)
+
+	li	t6, ~BCHP_MEMC_DDR23_APHY_AC_0_DESKEW_DLL_CNTRL_BYPASS_PHASE_MASK
+	and	t7, t7, t6
+
+	li	t6, BCHP_MEMC_DDR23_APHY_AC_0_DESKEW_DLL_CNTRL_BYPASS_PHASE_SHIFT
+	sll	t5, a0, t6
+	or	t7, t7, t5
+	sw	t7, 0(t8)
+
+	jr	ra
+	nop
+END(set_memc_0_deskew_bypass_phase)
+
+LEAF(set_memc_0_wl0_dq_phase)
+
+	addi	a0, a0, 1
+	and	a1, a1, zero
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH3_WL0_DQ_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	addi	a1, a1, 1
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+END(set_memc_0_wl0_dq_phase)
+
+LEAF(set_memc_0_wl1_dq_phase)
+
+	addi	a0, a0, 1
+	and	a1, a1, zero
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH7_WL1_DQ_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	addi	a1, a1, 1
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+END(set_memc_0_wl1_dq_phase)
+
+
+LEAF(set_memc_0_dqs0_phase)
+
+	li	a2, -1
+	blt	a0, zero, 1f
+	nop
+
+	li	a2, 1
+1:
+	and	a1, a1, zero
+	add	a0, a0, a2
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH4_WL0_DQS0_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	add	a1, a1, a2
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+
+END(set_memc_0_dqs0_phase)
+
+LEAF(set_memc_0_dqs1_phase)
+
+	li	a2, -1
+	blt	a0, zero, 1f
+	nop
+
+	li	a2, 1
+1:
+	and	a1, a1, zero
+	add	a0, a0, a2
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH5_WL0_DQS1_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	add	a1, a1, a2
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+
+
+END(set_memc_0_dqs1_phase)
+
+LEAF(set_memc_0_dqs2_phase)
+
+	li	a2, -1
+	blt	a0, zero, 1f
+	nop
+
+	li	a2, 1
+1:
+	and	a1, a1, zero
+	add	a0, a0, a2
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH8_WL1_DQS0_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	add	a1, a1, a2
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+
+END(set_memc_0_dqs2_phase)
+
+LEAF(set_memc_0_dqs3_phase)
+
+	li	a2, -1
+	blt	a0, zero, 1f
+	nop
+
+	li	a2, 1
+1:
+	and	a1, a1, zero
+	add	a0, a0, a2
+	li	v0, REG(BCHP_MEMC_DDR23_APHY_AC_0_PLL_CH9_WL1_DQS1_PHASE_CNTRL)
+2:
+	sw	a1, 0(v0)
+	add	a1, a1, a2
+	bne	a1, a0, 2b
+	nop
+
+	jr	ra
+	nop
+
+END(set_memc_0_dqs3_phase)
+
+LEAF(memc_settings_valid)
+
+	li	t2, 0xdeadbeef
+	li	t1, REG(BCHP_MEMC_GEN_0_MSA_WR_DATA7)
+	lw	t0, 0(t1)
+	li	v0, 0
+	beq	t0, t2, 1f
+	nop
+	li	v0, -1
+
+1:	jr	ra
+	nop
+
+END(memc_settings_valid)
+
+#endif /* CONFIG_BRCM_HAS_ANALOG_DDR_PHY */
+
+#ifdef CONFIG_BRCM_HAS_DIGITAL_DDR_PHY
+
+LEAF(memc_settings_valid)
+
+1:	jr	ra
+	li	v0, 0
+
+END(memc_settings_valid)
+
+LEAF(wake_up_memc_0)
+
+	move	s7, ra
+
+#if !defined(CONFIG_BRCM_PWR_HANDSHAKE)
+	li	t0, REG(BCHP_MEMC_DDR_0_SSPD_CMD)
+	li	t1, 0
+	sw	t1, 0(t0)
+#endif
+
+#ifdef BCHP_DDR23_PHY_CONTROL_REGS_0_PLL_STATUS
+	li	t0, REG(BCHP_DDR23_PHY_CONTROL_REGS_0_PLL_STATUS)
+#elif defined(BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS)
+	li	t0, REG(BCHP_DDR40_PHY_CONTROL_REGS_0_PLL_STATUS)
+#else
+#error No MEMC phy control register defined
+#endif
+
+1:	lw	t1, 0(t0)
+	andi	t1, 1
+	beqz	t1, 1b
+	nop
+
+# 1 ms delay - needed on 7552/7358 for stable recovery
+	li	a0, (27000)
+	bal	delay
+	nop
+
+	jr	s7
+	nop
+
+END(wake_up_memc_0)
+
+#endif /* CONFIG_BRCM_HAS_DIGITAL_DDR_PHY */
+
+	.globl passiveIRQ_end
+passiveIRQ_end:
+	nop
diff --git a/arch/mips/brcmstb/time.c b/arch/mips/brcmstb/time.c
new file mode 100644
index 0000000..197a2c4
--- /dev/null
+++ b/arch/mips/brcmstb/time.c
@@ -0,0 +1,175 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/clocksource.h>
+#include <linux/printk.h>
+#include <linux/spinlock.h>
+
+#include <asm/time.h>
+#include <linux/brcmstb/brcmstb.h>
+
+/* MIPS clock measured at boot time.  Value is not changed by PM. */
+unsigned long brcm_cpu_khz;
+
+/* Sampling period for MIPS calibration.  50 = 1/50 of a second. */
+#define SAMPLE_PERIOD		50
+
+/***********************************************************************
+ * UPG clocksource
+ ***********************************************************************/
+
+static cycle_t upg_cs_read(struct clocksource *cs)
+{
+	return BDEV_RD_F(TIMER_TIMER3_STAT, COUNTER_VAL);
+}
+
+static struct clocksource clocksource_upg = {
+	.name		= "upg",
+	.read		= upg_cs_read,
+	.mask		= CLOCKSOURCE_MASK(30),
+	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static inline void __init init_upg_clocksource(void)
+{
+	BDEV_WR_RB(BCHP_TIMER_TIMER3_CTRL, 0);
+	BDEV_WR_F_RB(TIMER_TIMER_IS, TMR3TO, 1);
+	BDEV_WR_RB(BCHP_TIMER_TIMER3_CTRL, 0xbfffffff);
+
+	clocksource_upg.rating = 250;
+	clocksource_register_hz(&clocksource_upg, UPGTMR_FREQ);
+}
+
+#ifdef CONFIG_BRCM_HAS_WKTMR
+
+/***********************************************************************
+ * WKTMR clocksource
+ ***********************************************************************/
+
+static DEFINE_SPINLOCK(wktmr_lock);
+
+static cycle_t wktmr_cs_read(struct clocksource *cs)
+{
+	struct wktmr_time t;
+	unsigned long flags;
+
+	spin_lock_irqsave(&wktmr_lock, flags);
+	wktmr_read(&t);
+	spin_unlock_irqrestore(&wktmr_lock, flags);
+
+	return (t.sec * (cycle_t)WKTMR_FREQ) + t.pre;
+}
+
+static struct clocksource clocksource_wktmr = {
+	.name		= "wktmr",
+	.read		= wktmr_cs_read,
+	.mask		= CLOCKSOURCE_MASK(64),
+	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
+};
+
+static inline void __init init_wktmr_clocksource(void)
+{
+	clocksource_wktmr.rating = 250;
+	clocksource_register_hz(&clocksource_wktmr, WKTMR_FREQ);
+}
+
+/*
+ * MIPS frequency calibration (WKTMR)
+ */
+
+static __init unsigned long brcm_mips_freq(void)
+{
+	struct wktmr_time start;
+
+	wktmr_read(&start);
+	write_c0_count(0);
+
+	while (wktmr_elapsed(&start) < (WKTMR_FREQ / SAMPLE_PERIOD))
+		;
+
+	return read_c0_count() * SAMPLE_PERIOD;
+}
+
+void read_persistent_clock(struct timespec *ts)
+{
+	struct wktmr_time now;
+
+	wktmr_read(&now);
+
+	ts->tv_sec = now.sec;
+	ts->tv_nsec = now.pre * (1000000000/WKTMR_FREQ);
+}
+
+
+#else /* CONFIG_BRCM_HAS_WKTMR */
+
+/*
+ * MIPS frequency calibration (UPG TIMER3)
+ */
+
+static __init unsigned long brcm_mips_freq(void)
+{
+	unsigned long ret;
+
+	/* reset countdown timer */
+	BDEV_WR_RB(BCHP_TIMER_TIMER3_CTRL, 0);
+	BDEV_WR_F_RB(TIMER_TIMER_IS, TMR3TO, 1);
+
+	/* set up for countdown */
+	BDEV_WR(BCHP_TIMER_TIMER0_CTRL, 0xc0000000 |
+		(UPGTMR_FREQ / SAMPLE_PERIOD));
+	write_c0_count(0);
+
+	while ((BDEV_RD(BCHP_TIMER_TIMER_IS) & 1) == 0)
+		;
+
+	ret = read_c0_count();
+	BDEV_WR(BCHP_TIMER_TIMER0_CTRL, 0);
+
+	return ret * SAMPLE_PERIOD;
+}
+
+#endif /* CONFIG_BRCM_HAS_WKTMR */
+
+/***********************************************************************
+ * Timer setup
+ ***********************************************************************/
+
+void __init plat_time_init(void)
+{
+	unsigned int khz;
+
+	pr_info("Measuring MIPS counter frequency...\n");
+	mips_hpt_frequency = brcm_mips_freq();
+	khz = mips_hpt_frequency / 1000;
+#ifdef CONFIG_CPU_BMIPS5000
+	brcm_cpu_khz = mips_hpt_frequency * 8 / 1000;
+#else
+	brcm_cpu_khz = mips_hpt_frequency * 2 / 1000;
+#endif
+
+	pr_info("Detected MIPS clock frequency: %lu MHz (%u.%03u MHz counter)\n",
+		brcm_cpu_khz / 1000, khz / 1000, khz % 1000);
+
+#ifdef CONFIG_CSRC_WKTMR
+	init_wktmr_clocksource();
+#endif
+#ifdef CONFIG_CSRC_UPG
+	init_upg_clocksource();
+#endif
+}
diff --git a/arch/mips/bruno/Kconfig b/arch/mips/bruno/Kconfig
new file mode 100644
index 0000000..8a0f8a5
--- /dev/null
+++ b/arch/mips/bruno/Kconfig
@@ -0,0 +1,40 @@
+config BRUNO
+	bool "BRUNO Platform"
+	default y
+	help
+	  This enables support for BRUNO platform.
+	select BCMGENET_0_GPHY
+	select BRCM_OVERRIDE_USB
+	select BRCM_FORCE_USB_PWR_HI
+	select BRCM_FORCE_USB_OC_LO
+	select MEDIA_SUPPORT
+	select SND
+	select SND_DRIVERS
+	select SND_HWDEP
+	select SND_MIPS
+	select SND_PCM
+	select SND_RAWMIDI
+	select SND_SPI
+	select SND_TIMER
+	select SND_VERBOSE_PROCFS
+#	select SND_USB
+#	select SND_USB_AUDIO
+	select SOUND
+#	select USB_VIDEO_CLASS
+#	select USB_VIDEO_CLASS_INPUT_EVDEV
+#	select V4L_USB_DRIVERS
+#	select VIDEO_CAPTURE_DRIVERS
+#	select VIDEO_DEV
+#	select VIDEO_MEDIA
+##	select VIDEO_USB_DRIVERS
+#	select VIDEO_V4L2
+#	select VIDEO_V4L2_COMMON
+	select REPARTITION
+	# select ARCH_SUSPEND_POSSIBLE
+
+config REPARTITION
+	tristate "Repartition Support"
+	default y
+	depends on BRUNO
+	help
+	  This module enables support for repartition.
diff --git a/arch/mips/configs/bcm7231b0_defconfig b/arch/mips/configs/bcm7231b0_defconfig
new file mode 100644
index 0000000..83d5fb3
--- /dev/null
+++ b/arch/mips/configs/bcm7231b0_defconfig
@@ -0,0 +1,116 @@
+CONFIG_BRCMSTB=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7344b0_defconfig b/arch/mips/configs/bcm7344b0_defconfig
new file mode 100644
index 0000000..756c0fe
--- /dev/null
+++ b/arch/mips/configs/bcm7344b0_defconfig
@@ -0,0 +1,115 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7344B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7346b0_defconfig b/arch/mips/configs/bcm7346b0_defconfig
new file mode 100644
index 0000000..e11da1c
--- /dev/null
+++ b/arch/mips/configs/bcm7346b0_defconfig
@@ -0,0 +1,117 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7346B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7358a0_defconfig b/arch/mips/configs/bcm7358a0_defconfig
new file mode 100644
index 0000000..8f37492
--- /dev/null
+++ b/arch/mips/configs/bcm7358a0_defconfig
@@ -0,0 +1,112 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7358A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7360a0_defconfig b/arch/mips/configs/bcm7360a0_defconfig
new file mode 100644
index 0000000..255edea
--- /dev/null
+++ b/arch/mips/configs/bcm7360a0_defconfig
@@ -0,0 +1,113 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7360A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7362a0_defconfig b/arch/mips/configs/bcm7362a0_defconfig
new file mode 100644
index 0000000..2753452
--- /dev/null
+++ b/arch/mips/configs/bcm7362a0_defconfig
@@ -0,0 +1,115 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7362A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7425b0_defconfig b/arch/mips/configs/bcm7425b0_defconfig
new file mode 100644
index 0000000..3c452a6
--- /dev/null
+++ b/arch/mips/configs/bcm7425b0_defconfig
@@ -0,0 +1,114 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7425B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_HIGHMEM=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_PCI=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_FUNCTION_TRACER=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7429b0_defconfig b/arch/mips/configs/bcm7429b0_defconfig
new file mode 100644
index 0000000..b2a8465
--- /dev/null
+++ b/arch/mips/configs/bcm7429b0_defconfig
@@ -0,0 +1,116 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7429B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7435b0_defconfig b/arch/mips/configs/bcm7435b0_defconfig
new file mode 100644
index 0000000..df5c75c
--- /dev/null
+++ b/arch/mips/configs/bcm7435b0_defconfig
@@ -0,0 +1,119 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7435B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_HIGHMEM=y
+CONFIG_SPARSEMEM_MANUAL=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=4
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_PCI=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7543a0_defconfig b/arch/mips/configs/bcm7543a0_defconfig
new file mode 100644
index 0000000..4291719
--- /dev/null
+++ b/arch/mips/configs/bcm7543a0_defconfig
@@ -0,0 +1,115 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7543A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7552b0_defconfig b/arch/mips/configs/bcm7552b0_defconfig
new file mode 100644
index 0000000..1ed9703
--- /dev/null
+++ b/arch/mips/configs/bcm7552b0_defconfig
@@ -0,0 +1,115 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7552B0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7563a0_defconfig b/arch/mips/configs/bcm7563a0_defconfig
new file mode 100644
index 0000000..df562f7
--- /dev/null
+++ b/arch/mips/configs/bcm7563a0_defconfig
@@ -0,0 +1,118 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7563A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI_PLATFORM=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bcm7584a0_defconfig b/arch/mips/configs/bcm7584a0_defconfig
new file mode 100644
index 0000000..b75d11f
--- /dev/null
+++ b/arch/mips/configs/bcm7584a0_defconfig
@@ -0,0 +1,117 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7584A0=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_HZ_1000=y
+# CONFIG_SECCOMP is not set
+CONFIG_EXPERIMENTAL=y
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EMBEDDED=y
+CONFIG_SLAB=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_EFI_PARTITION=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_PM_RUNTIME=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_IP_PNP_BOOTP=y
+CONFIG_IP_PNP_RARP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+# CONFIG_IPV6 is not set
+CONFIG_BRIDGE=y
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_CHAR=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_USB=y
+CONFIG_USB_DEVICEFS=y
+CONFIG_USB_SUSPEND=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+# CONFIG_EXT4_FS_XATTR is not set
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_FS=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_CRYPTO_ANSI_CPRNG is not set
diff --git a/arch/mips/configs/bruno_gfhd100b2_defconfig b/arch/mips/configs/bruno_gfhd100b2_defconfig
new file mode 100644
index 0000000..00ce13b
--- /dev/null
+++ b/arch/mips/configs/bruno_gfhd100b2_defconfig
@@ -0,0 +1,193 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7425B0=y
+CONFIG_BRCM_FIXED_MTD_PARTITIONS=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_HIGHMEM=y
+CONFIG_LOW_MEM_NOTIFY=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_HZ_1000=y
+CONFIG_PREEMPT=y
+# CONFIG_SECCOMP is not set
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AR_CLOCK=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_PRINTK_PERSIST=y
+CONFIG_BOOTLOG_COPY=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_PCI=y
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_WESTWOOD=y
+CONFIG_TCP_CONG_HTCP=y
+CONFIG_TCP_CONG_HSTCP=y
+CONFIG_TCP_CONG_HYBLA=y
+CONFIG_TCP_CONG_SCALABLE=y
+CONFIG_TCP_CONG_LP=y
+CONFIG_TCP_CONG_VENO=y
+CONFIG_TCP_CONG_YEAH=y
+CONFIG_TCP_CONG_ILLINOIS=y
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFB=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_MQPRIO=m
+CONFIG_NET_SCH_CHOKE=m
+CONFIG_NET_SCH_QFQ=m
+CONFIG_NET_SCH_CODEL=m
+CONFIG_NET_SCH_FQ_CODEL=m
+CONFIG_NET_SCH_FQ=m
+CONFIG_NET_SCH_HHF=m
+CONFIG_NET_SCH_PIE=m
+CONFIG_NET_PKTGEN=m
+CONFIG_BT=m
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=256
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_SATA_AHCI=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_DEBUG=y
+CONFIG_DM_VERITY=y
+CONFIG_NETDEVICES=y
+CONFIG_TUN=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
+CONFIG_HID_GFRM=m
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_KEYSPAN=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=64
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_DEBUG_STACK_USAGE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_HIGHMEM=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=30
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_FUNCTION_TRACER=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="bmem=192m@64m bmem=80m@512m memc1=256m log_buf_len=8388608 slub_debug=F softlockup_all_cpu_backtrace=1"
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_ARC4=y
diff --git a/arch/mips/configs/bruno_gfhd200_defconfig b/arch/mips/configs/bruno_gfhd200_defconfig
new file mode 100644
index 0000000..c25721e
--- /dev/null
+++ b/arch/mips/configs/bruno_gfhd200_defconfig
@@ -0,0 +1,190 @@
+CONFIG_BRCMSTB=y
+CONFIG_BCM7429B0=y
+CONFIG_BRCM_FIXED_MTD_PARTITIONS=y
+CONFIG_CPU_LITTLE_ENDIAN=y
+CONFIG_HIGHMEM=y
+CONFIG_LOW_MEM_NOTIFY=y
+CONFIG_SMP=y
+CONFIG_NR_CPUS=2
+CONFIG_HZ_1000=y
+CONFIG_PREEMPT=y
+# CONFIG_SECCOMP is not set
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_AR_CLOCK=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_LOG_BUF_SHIFT=14
+CONFIG_SYSFS_DEPRECATED=y
+CONFIG_SYSFS_DEPRECATED_V2=y
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_PRINTK_PERSIST=y
+CONFIG_BOOTLOG_COPY=y
+CONFIG_EMBEDDED=y
+CONFIG_PERF_EVENTS=y
+CONFIG_MODULES=y
+CONFIG_MODULE_FORCE_LOAD=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_IOSCHED_DEADLINE is not set
+# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
+# CONFIG_INET_XFRM_MODE_TUNNEL is not set
+# CONFIG_INET_XFRM_MODE_BEET is not set
+# CONFIG_INET_LRO is not set
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_WESTWOOD=y
+CONFIG_TCP_CONG_HTCP=y
+CONFIG_TCP_CONG_HSTCP=y
+CONFIG_TCP_CONG_HYBLA=y
+CONFIG_TCP_CONG_SCALABLE=y
+CONFIG_TCP_CONG_LP=y
+CONFIG_TCP_CONG_VENO=y
+CONFIG_TCP_CONG_YEAH=y
+CONFIG_TCP_CONG_ILLINOIS=y
+CONFIG_BRIDGE=y
+CONFIG_VLAN_8021Q=y
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFB=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_MQPRIO=m
+CONFIG_NET_SCH_CHOKE=m
+CONFIG_NET_SCH_QFQ=m
+CONFIG_NET_SCH_CODEL=m
+CONFIG_NET_SCH_FQ_CODEL=m
+CONFIG_NET_SCH_FQ=m
+CONFIG_NET_SCH_HHF=m
+CONFIG_NET_SCH_PIE=m
+CONFIG_NET_PKTGEN=m
+CONFIG_BT=m
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_MRVL_SDIO=m
+CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_CMDLINE_PARTS=y
+CONFIG_MTD_BLOCK=y
+CONFIG_MTD_CFI=y
+CONFIG_MTD_JEDECPROBE=y
+CONFIG_MTD_CFI_INTELEXT=y
+CONFIG_MTD_CFI_AMDSTD=y
+CONFIG_MTD_CFI_STAA=y
+CONFIG_MTD_ROM=y
+CONFIG_MTD_ABSENT=y
+CONFIG_MTD_PHYSMAP=y
+CONFIG_MTD_M25P80=y
+CONFIG_MTD_NAND=y
+CONFIG_MTD_SPI_NOR=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_WL_THRESHOLD=256
+CONFIG_MTD_UBI_GLUEBI=y
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_SD=y
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_ATA=y
+CONFIG_MD=y
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_DEBUG=y
+CONFIG_DM_VERITY=y
+CONFIG_NETDEVICES=y
+CONFIG_USB_PEGASUS=y
+CONFIG_USB_USBNET=y
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+# CONFIG_SERIO is not set
+# CONFIG_CONSOLE_TRANSLATIONS is not set
+# CONFIG_VT_CONSOLE is not set
+# CONFIG_LEGACY_PTYS is not set
+CONFIG_HW_RANDOM=y
+CONFIG_SPI=y
+# CONFIG_HWMON is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_HIDRAW=y
+CONFIG_UHID=m
+# CONFIG_HID_GENERIC is not set
+CONFIG_HID_GFRM=m
+CONFIG_USB=y
+CONFIG_USB_MON=y
+CONFIG_USB_STORAGE=y
+CONFIG_USB_SERIAL=y
+CONFIG_USB_SERIAL_FTDI_SIO=y
+CONFIG_USB_SERIAL_KEYSPAN=y
+CONFIG_USB_SERIAL_PL2303=y
+CONFIG_MMC=y
+CONFIG_MMC_BLOCK_MINORS=64
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_EXT4_FS=y
+CONFIG_JBD2_DEBUG=y
+# CONFIG_DNOTIFY is not set
+CONFIG_FUSE_FS=y
+CONFIG_ISO9660_FS=y
+CONFIG_JOLIET=y
+CONFIG_UDF_FS=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_TMPFS=y
+CONFIG_JFFS2_FS=y
+CONFIG_UBIFS_FS=y
+CONFIG_SQUASHFS=y
+CONFIG_SQUASHFS_LZO=y
+CONFIG_SQUASHFS_XZ=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V4=y
+CONFIG_ROOT_NFS=y
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_ISO8859_1=y
+CONFIG_PRINTK_TIME=y
+CONFIG_DYNAMIC_DEBUG=y
+# CONFIG_ENABLE_WARN_DEPRECATED is not set
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_DEBUG_SECTION_MISMATCH=y
+CONFIG_DEBUG_STACK_USAGE=y
+CONFIG_DEBUG_MEMORY_INIT=y
+CONFIG_DEBUG_HIGHMEM=y
+CONFIG_LOCKUP_DETECTOR=y
+CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y
+CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=30
+CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y
+CONFIG_PANIC_ON_OOPS=y
+CONFIG_FUNCTION_TRACER=y
+CONFIG_CMDLINE_BOOL=y
+CONFIG_CMDLINE="bmem=96m@160m bmem=352m@512m log_buf_len=8388608 slub_debug=F softlockup_all_cpu_backtrace=1"
+CONFIG_CRYPTO_ECB=y
+CONFIG_CRYPTO_CMAC=y
+CONFIG_CRYPTO_SHA256=y
+CONFIG_CRYPTO_ARC4=y
diff --git a/arch/mips/include/asm/addrspace.h b/arch/mips/include/asm/addrspace.h
index 3b0e51d..2479a94 100644
--- a/arch/mips/include/asm/addrspace.h
+++ b/arch/mips/include/asm/addrspace.h
@@ -96,13 +96,21 @@
  */
 #define KUSEG			0x00000000
 #define KSEG0			0x80000000
+#if defined(CONFIG_BRCM_UPPER_768MB)
+#define KSEG1			KSEG0
+#else
 #define KSEG1			0xa0000000
+#endif
 #define KSEG2			0xc0000000
 #define KSEG3			0xe0000000
 
 #define CKUSEG			0x00000000
 #define CKSEG0			0x80000000
+#if defined(CONFIG_BRCM_UPPER_768MB)
+#define CKSEG1			CKSEG0
+#else
 #define CKSEG1			0xa0000000
+#endif
 #define CKSEG2			0xc0000000
 #define CKSEG3			0xe0000000
 
diff --git a/arch/mips/include/asm/io.h b/arch/mips/include/asm/io.h
index d10fd80..16edf59 100644
--- a/arch/mips/include/asm/io.h
+++ b/arch/mips/include/asm/io.h
@@ -206,6 +206,7 @@
 		if (!size || last_addr < phys_addr)
 			return NULL;
 
+#if !defined(CONFIG_BRCM_UPPER_768MB)
 		/*
 		 * Map uncached objects in the low 512MB of address
 		 * space using KSEG1.
@@ -214,6 +215,7 @@
 		    flags == _CACHE_UNCACHED)
 			return (void __iomem *)
 				(unsigned long)CKSEG1ADDR(phys_addr);
+#endif
 	}
 
 	return __ioremap(offset, size, flags);
diff --git a/arch/mips/include/asm/mach-brcmstb/cpu-feature-overrides.h b/arch/mips/include/asm/mach-brcmstb/cpu-feature-overrides.h
new file mode 100644
index 0000000..96253be
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/cpu-feature-overrides.h
@@ -0,0 +1,63 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003 Ralf Baechle
+ * Copyright (C) 2009 Broadcom Corporation
+ */
+#ifndef __ASM_MACH_BRCMSTB_CPU_FEATURE_OVERRIDES_H
+#define __ASM_MACH_BRCMSTB_CPU_FEATURE_OVERRIDES_H
+
+#if defined(CONFIG_CPU_BMIPS4380)
+
+#define cpu_has_dc_aliases		1
+#define cpu_has_ic_fills_f_dc		0
+#define cpu_has_vtag_icache		0
+#define cpu_has_inclusive_pcaches	0
+#define cpu_icache_snoops_remote_store	1
+#define cpu_has_mips32r1		1
+#define cpu_has_mips32r2		0
+#define cpu_has_mips64r1		0
+#define cpu_has_mips64r2		0
+#define cpu_dcache_line_size()		64
+#define cpu_icache_line_size()		64
+#define cpu_scache_line_size()		0
+
+#elif defined(CONFIG_CPU_BMIPS3300)
+
+#define cpu_has_dc_aliases		1
+#define cpu_has_ic_fills_f_dc		0
+#define cpu_has_vtag_icache		0
+#define cpu_has_inclusive_pcaches	0
+#define cpu_icache_snoops_remote_store	1
+#define cpu_has_mips32r1		1
+#define cpu_has_mips32r2		0
+#define cpu_has_mips64r1		0
+#define cpu_has_mips64r2		0
+#define cpu_dcache_line_size()		16
+#define cpu_icache_line_size()		16
+#define cpu_scache_line_size()		0
+
+#elif defined(CONFIG_CPU_BMIPS5000)
+
+#define cpu_has_dc_aliases		0
+#define cpu_has_ic_fills_f_dc		1
+#define cpu_has_vtag_icache		0
+#define cpu_has_inclusive_pcaches	1
+#define cpu_icache_snoops_remote_store	1
+#define cpu_has_mips32r1		1
+#define cpu_has_mips32r2		0
+#define cpu_has_mips64r1		0
+#define cpu_has_mips64r2		0
+#define cpu_dcache_line_size()		32
+#define cpu_icache_line_size()		64
+#define cpu_scache_line_size()		128
+
+#endif
+
+#if defined(CONFIG_BRCM_HAS_XI)
+#define kernel_uses_smartmips_rixi	1
+#endif
+
+#endif /* __ASM_MACH_BRCMSTB_CPU_FEATURE_OVERRIDES_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/dma-coherence.h b/arch/mips/include/asm/mach-brcmstb/dma-coherence.h
new file mode 100644
index 0000000..cff0da7
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/dma-coherence.h
@@ -0,0 +1,89 @@
+/*
+ * Copyright (C) 2006 Ralf Baechle <ralf@linux-mips.org>
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __ASM_MACH_BRCMSTB_DMA_COHERENCE_H
+#define __ASM_MACH_BRCMSTB_DMA_COHERENCE_H
+
+struct device;
+
+#if defined(CONFIG_PCI)
+
+extern dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size);
+extern dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page);
+extern unsigned long plat_dma_addr_to_phys(struct device *dev,
+	dma_addr_t dma_addr);
+
+#else
+
+static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
+	size_t size)
+{
+	return virt_to_phys(addr);
+}
+
+static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
+	struct page *page)
+{
+	return page_to_phys(page);
+}
+
+static inline unsigned long plat_dma_addr_to_phys(struct device *dev,
+	dma_addr_t dma_addr)
+{
+	return dma_addr;
+}
+
+#endif
+
+extern void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+	size_t size, int dir);
+
+static inline int plat_dma_supported(struct device *dev, u64 mask)
+{
+	/*
+	 * we fall back to GFP_DMA when the mask isn't all 1s,
+	 * so we can't guarantee allocations that must be
+	 * within a tighter range than GFP_DMA..
+	 */
+	if (mask < DMA_BIT_MASK(24))
+		return 0;
+
+	return 1;
+}
+
+static inline void plat_extra_sync_for_device(struct device *dev)
+{
+	return;
+}
+
+static inline int plat_dma_mapping_error(struct device *dev,
+					 dma_addr_t dma_addr)
+{
+	return 0;
+}
+
+static inline int plat_device_is_coherent(struct device *dev)
+{
+	return 0;
+}
+
+static inline void plat_post_dma_flush(struct device *dev)
+{
+}
+
+#endif /* __ASM_MACH_BRCMSTB_DMA_COHERENCE_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/ioremap.h b/arch/mips/include/asm/mach-brcmstb/ioremap.h
new file mode 100644
index 0000000..e356825
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/ioremap.h
@@ -0,0 +1,27 @@
+/*
+ *	include/asm-mips/mach-brcmstb/ioremap.h
+ *
+ *	This program is free software; you can redistribute it and/or
+ *	modify it under the terms of the GNU General Public License
+ *	as published by the Free Software Foundation; either version
+ *	2 of the License, or (at your option) any later version.
+ */
+#ifndef __ASM_MACH_BRCMSTB_IOREMAP_H
+#define __ASM_MACH_BRCMSTB_IOREMAP_H
+
+#include <linux/types.h>
+
+/*
+ * Allow physical addresses to be fixed up to help peripherals located
+ * outside the low 32-bit range -- generic pass-through version.
+ */
+static inline phys_addr_t fixup_bigphys_addr(phys_addr_t phys_addr, phys_addr_t size)
+{
+	return phys_addr;
+}
+
+extern void __iomem *plat_ioremap(phys_addr_t offset, unsigned long size,
+	unsigned long flags);
+extern int plat_iounmap(const volatile void __iomem *addr);
+
+#endif /* __ASM_MACH_BRCMSTB_IOREMAP_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/irq.h b/arch/mips/include/asm/mach-brcmstb/irq.h
new file mode 100644
index 0000000..8d44f84
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/irq.h
@@ -0,0 +1,56 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef __ASM_MACH_BRCMSTB_IRQ_H
+#define __ASM_MACH_BRCMSTB_IRQ_H
+
+/*
+ * This file has IRQ definitions that DO NOT depend on the BCHP headers
+ * See also: linux/brcmstb/brcmstb.h
+ */
+
+/* IRQs 1-128 are used for HIF L1 */
+#define BRCM_VIRTIRQ_BASE	(1 + 128)
+
+/* virtual (non-L1) IRQs */
+
+#define BRCM_CPUIRQ_BASE	(BRCM_VIRTIRQ_BASE + 0)
+#define BRCM_OTHERIRQ_BASE	(BRCM_VIRTIRQ_BASE + 8)
+
+/* MIPS interrupts 0-7 */
+#define BRCM_IRQ_CPU0		(BRCM_CPUIRQ_BASE + 0)
+#define BRCM_IRQ_CPU1		(BRCM_CPUIRQ_BASE + 1)
+#define BRCM_IRQ_CPU2		(BRCM_CPUIRQ_BASE + 2)
+#define BRCM_IRQ_CPU3		(BRCM_CPUIRQ_BASE + 3)
+#define BRCM_IRQ_CPU4		(BRCM_CPUIRQ_BASE + 4)
+#define BRCM_IRQ_CPU5		(BRCM_CPUIRQ_BASE + 5)
+#define BRCM_IRQ_CPU6		(BRCM_CPUIRQ_BASE + 6)
+#define BRCM_IRQ_CPU7		(BRCM_CPUIRQ_BASE + 7)
+
+#define BRCM_IRQ_IPI0		BRCM_IRQ_CPU0
+#define BRCM_IRQ_IPI1		BRCM_IRQ_CPU1
+#define BRCM_IRQ_HW0		BRCM_IRQ_CPU2
+#define BRCM_IRQ_HW1		BRCM_IRQ_CPU3
+
+/* performance counter */
+
+#define BRCM_IRQ_PERF		(BRCM_OTHERIRQ_BASE + 0)
+
+#define NR_IRQS			160
+#define MIPS_CPU_IRQ_BASE	BRCM_CPUIRQ_BASE
+
+#endif /* __ASM_MACH_BRCMSTB_IRQ_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/kernel-entry-init.h b/arch/mips/include/asm/mach-brcmstb/kernel-entry-init.h
new file mode 100644
index 0000000..3133784
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/kernel-entry-init.h
@@ -0,0 +1,36 @@
+/***************************************************************************
+ *     Copyright (c) 2008, Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ *
+ ***************************************************************************/
+
+#ifndef __ASM_MACH_BRCMSTB_KERNEL_ENTRY_H
+#define __ASM_MACH_BRCMSTB_KERNEL_ENTRY_H
+
+	.macro kernel_entry_setup
+
+	# save arguments for CFE callback
+	sw	a0, cfe_handle
+	sw	a2, cfe_entry
+	sw	a3, cfe_seal
+
+	jal	bmips_enable_xks01
+
+	.endm
+
+        .macro  smp_slave_setup
+        .endm
+
+#endif /* __ASM_MACH_BRCMSTB_KERNEL_ENTRY_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/mangle-port.h b/arch/mips/include/asm/mach-brcmstb/mangle-port.h
new file mode 100644
index 0000000..8440103
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/mangle-port.h
@@ -0,0 +1,53 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2003, 2004 Ralf Baechle
+ * Copyright (C) 2009 Broadcom Corporation
+ */
+#ifndef __ASM_MACH_BRCMSTB_MANGLE_PORT_H
+#define __ASM_MACH_BRCMSTB_MANGLE_PORT_H
+
+#define __swizzle_addr_b(port)	(port)
+#define __swizzle_addr_w(port)	(port)
+#define __swizzle_addr_l(port)	(port)
+#define __swizzle_addr_q(port)	(port)
+
+/*
+ * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
+ * less sane hardware forces software to fiddle with this...
+ *
+ * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
+ * you can't have the numerical value of data and byte addresses within
+ * multibyte quantities both preserved at the same time.  Hence two
+ * variations of functions: non-prefixed ones that preserve the value
+ * and prefixed ones that preserve byte addresses.  The latters are
+ * typically used for moving raw data between a peripheral and memory (cf.
+ * string I/O functions), hence the "__mem_" prefix.
+ */
+#if defined(CONFIG_SWAP_IO_SPACE)
+
+# define ioswabb(a, x)		(x)
+# define __mem_ioswabb(a, x)	(x)
+# define ioswabw(a, x)		le16_to_cpu(x)
+# define __mem_ioswabw(a, x)	(x)
+# define ioswabl(a, x)		le32_to_cpu(x)
+# define __mem_ioswabl(a, x)	(x)
+# define ioswabq(a, x)		le64_to_cpu(x)
+# define __mem_ioswabq(a, x)	(x)
+
+#else
+
+# define ioswabb(a, x)		(x)
+# define __mem_ioswabb(a, x)	(x)
+# define ioswabw(a, x)		(x)
+# define __mem_ioswabw(a, x)	cpu_to_le16(x)
+# define ioswabl(a, x)		(x)
+# define __mem_ioswabl(a, x)	cpu_to_le32(x)
+# define ioswabq(a, x)		(x)
+# define __mem_ioswabq(a, x)	cpu_to_le32(x)
+
+#endif
+
+#endif /* __ASM_MACH_BRCMSTB_MANGLE_PORT_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/spaces.h b/arch/mips/include/asm/mach-brcmstb/spaces.h
new file mode 100644
index 0000000..23a1bd7
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/spaces.h
@@ -0,0 +1,151 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2009 Broadcom Corporation
+ */
+
+#ifndef _ASM_MACH_BRCMSTB_SPACES_H
+#define _ASM_MACH_BRCMSTB_SPACES_H
+
+#include <linux/const.h>
+
+/***********************************************************************
+ * Kernel virtual address space
+ ***********************************************************************/
+
+#if !defined(CONFIG_BRCM_UPPER_MEMORY)
+
+/*
+ * 256MB standard MIPS32 virtual address map
+ *
+ * 8000_0000 - 8fff_ffff: lower 256MB, cached mapping
+ * 9000_0000 - 9fff_ffff: EBI/registers, cached mapping (unused)
+ * a000_0000 - afff_ffff: lower 256MB, uncached mapping
+ * b000_0000 - bfff_ffff: EBI/registers, uncached mapping
+ * c000_0000 - ff1f_7fff: vmalloc region
+ * ff1f_8000 - ff1f_ffff: FIXMAP
+ */
+
+#define KSEG0_SIZE		_AC(0x20000000, UL)
+#define KSEG1_SIZE		_AC(0x20000000, UL)
+#define MAP_BASE		_AC(0xc0000000, UL)
+#define FIXADDR_TOP		_AC(0xff200000, UL)
+#define BRCM_MAX_UPPER_MB	_AC(0, UL)
+
+#elif defined(CONFIG_BRCM_UPPER_768MB)
+
+/*
+ * 1024MB Broadcom 256+768 virtual address map
+ *
+ * 8000_0000 - 8fff_ffff: 256MB RAM @ 0000_0000, cached
+ * 9000_0000 - 9fff_ffff: 256MB EBI/Registers @ 1000_0000, uncached
+ * a000_0000 - cfff_ffff: 768MB RAM @ 2000_0000, cached
+ * d000_0000 - dfff_ffff: TBD
+ * e000_0000 - ff1f_7fff: vmalloc region
+ * ff1f_8000 - ff1f_ffff: FIXMAP
+ * ff40_0000 - ff7f_ffff: CONSISTENT region
+ *
+ * PA 5000_0000 and above are accessed through HIGHMEM (BMIPS5000 only).
+ */
+
+#define TLB_UPPERMEM_VA		_AC(0xc0000000, UL)
+#define TLB_UPPERMEM_PA		_AC(0x40000000, UL)
+#define KSEG0_SIZE		_AC(0x40000000, UL)
+#define KSEG1_SIZE		_AC(0x00000000, UL)
+#define MAP_BASE		_AC(0xe0000000, UL)
+#define FIXADDR_TOP		_AC(0xff200000, UL)
+/* BASE and END must be 4MB-aligned (PGDIR_SIZE) */
+#define CONSISTENT_BASE		_AC(0xff400000, UL)
+#define CONSISTENT_END		_AC(0xff800000, UL)
+#define BRCM_MAX_UPPER_MB	_AC(768, UL)
+
+#endif /* CONFIG_BRCM_UPPER_MEMORY */
+
+/***********************************************************************
+ * Physical / PCI address space
+ ***********************************************************************/
+
+#ifdef CONFIG_BRCM_HAS_2GB_MEMC0
+
+/*
+ * Physical address map for 2GB MEMC0
+ *
+ * 0000_0000 - 0fff_ffff: MEMC0 (256MB)
+ * 1000_0000 - 1fff_ffff: EBI/Registers (256MB)
+ * 2000_0000 - 8fff_ffff: MEMC0 (1792MB)
+ * 9000_0000 - cfff_ffff: MEMC1 (1024MB)
+ * d000_0000 - efff_ffff: PCIe MEM BARs (512MB)
+ *
+ * PCIe inbound BAR:
+ *
+ * 0000_0000 - 0fff_ffff: MEMC0 (256MB  @ 0000_0000)
+ * 1000_0000 - 7fff_ffff: MEMC0 (1792MB @ 2000_0000)
+ * 8000_0000 - bfff_ffff: MEMC1 (1024MB @ 9000_0000)
+ */
+
+#define PCI_MEM_START		_AC(0xdeadbeef, UL)
+#define PCI_MEM_SIZE		_AC(0xdeadbeef, UL)
+
+#define PCI_IO_START		_AC(0xffff0000, UL)
+#define PCI_IO_SIZE		_AC(0x00001000, UL)
+
+#define PCIE_MEM_START		_AC(0xd0000000, UL)
+#define PCIE_MEM_SIZE		_AC(0x20000000, UL)
+
+#define MEMC1_START		_AC(0x90000000, UL)
+#define MEMC1_PCI_OFFSET	_AC(0x10000000, UL)
+
+#else /* CONFIG_BRCM_HAS_2GB_MEMC0 */
+
+/*
+ * Physical address map for <= 1GB MEMC0
+ *
+ * 0000_0000 - 0fff_ffff: MEMC0 (256MB)
+ * 1000_0000 - 1fff_ffff: EBI/Registers (256MB)
+ * 2000_0000 - 4fff_ffff: MEMC0 (768MB)
+ * 6000_0000 - 7fff_ffff: MEMC1 (512MB)
+ * a000_0000 - bfff_ffff: PCIe MEM BARs (512MB)
+ * d000_0000 - efff_ffff: PCI2.3 MEM BARs (512MB)
+ * f000_0000 - f05f_ffff: PCI2.3 IO BARs (6MB)
+ * f000_0000 - f060_000b: PCI2.3 Configuration access (12B)
+ * f100_0000 - f100_001f: PCIe Configuration access - 7420 only (32B)
+ *
+ * PCI2.3/PCIe inbound BAR:
+ *
+ * 0000_0000 - 0fff_ffff: MEMC0 (256MB  @ 0000_0000)
+ * 1000_0000 - 3fff_ffff: MEMC0 (768MB  @ 2000_0000)
+ * 4000_0000 - 7fff_ffff: MEMC1 (1024MB @ 6000_0000) (not currently implemented)
+ */
+
+#define PCI_MEM_START		_AC(0xd0000000, UL)
+#define PCI_MEM_SIZE		_AC(0x20000000, UL)
+
+/* this is really 6MB long, but 32k ought to be enough for anyone */
+#define PCI_IO_START		_AC(0xf0000000, UL)
+#define PCI_IO_SIZE		_AC(0x00008000, UL)
+#define PCI_IO_ACTUAL_SIZE	_AC(0x00600000, UL)
+
+#define PCI_IO_REG_START	_AC(0xf0600000, UL)
+#define PCI_IO_REG_SIZE		_AC(0x0000000c, UL)
+
+#define PCIE_MEM_START		_AC(0xa0000000, UL)
+#define PCIE_MEM_SIZE		_AC(0x20000000, UL)
+
+#define MEMC1_START		_AC(0x60000000, UL)
+#define MEMC1_PCI_OFFSET	_AC(0x20000000, UL)
+
+#endif /* CONFIG_BRCM_HAS_2GB_MEMC0 */
+
+#define UPPERMEM_START		_AC(0x20000000, UL)
+#define HIGHMEM_START		(UPPERMEM_START + (BRCM_MAX_UPPER_MB << 20))
+
+#define BRCM_PCI_HOLE_START	_AC(0x10000000, UL)
+#define BRCM_PCI_HOLE_SIZE	_AC(0x10000000, UL)
+
+#define BRCM_MAX_LOWER_MB	_AC(256, UL)
+
+#include <asm/mach-generic/spaces.h>
+
+#endif /* _ASM_MACH_BRCMSTB_SPACES_H */
diff --git a/arch/mips/include/asm/mach-brcmstb/war.h b/arch/mips/include/asm/mach-brcmstb/war.h
new file mode 100644
index 0000000..ebb8f2b
--- /dev/null
+++ b/arch/mips/include/asm/mach-brcmstb/war.h
@@ -0,0 +1,25 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
+ */
+#ifndef __ASM_MIPS_MACH_BRCMSTB_WAR_H
+#define __ASM_MIPS_MACH_BRCMSTB_WAR_H
+
+#define R4600_V1_INDEX_ICACHEOP_WAR	0
+#define R4600_V1_HIT_CACHEOP_WAR	0
+#define R4600_V2_HIT_CACHEOP_WAR	0
+#define R5432_CP0_INTERRUPT_WAR		0
+#define BCM1250_M3_WAR			0
+#define SIBYTE_1956_WAR			0
+#define MIPS4K_ICACHE_REFILL_WAR	0
+#define MIPS_CACHE_SYNC_WAR		0
+#define TX49XX_ICACHE_INDEX_INV_WAR	0
+#define RM9000_CDEX_SMP_WAR		0
+#define ICACHE_REFILLS_WORKAROUND_WAR	0
+#define R10000_LLSC_WAR			0
+#define MIPS34K_MISSED_ITLB_WAR		0
+
+#endif /* __ASM_MIPS_MACH_BRCMSTB_WAR_H */
diff --git a/arch/mips/include/asm/page.h b/arch/mips/include/asm/page.h
index 21ed715..aed433b 100644
--- a/arch/mips/include/asm/page.h
+++ b/arch/mips/include/asm/page.h
@@ -232,8 +232,16 @@
 #define VM_DATA_DEFAULT_FLAGS	(VM_READ | VM_WRITE | VM_EXEC | \
 				 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
 
+#if defined(CONFIG_BRCM_UPPER_768MB)
+
+/* uncached kseg1 does not exist in this configuration */
+
+#define CAC_ADDR(addr)		({ BUG(); 0; })
+
+#else
 #define UNCAC_ADDR(addr)	((addr) - PAGE_OFFSET + UNCAC_BASE)
 #define CAC_ADDR(addr)		((addr) - UNCAC_BASE + PAGE_OFFSET)
+#endif
 
 #include <asm-generic/memory_model.h>
 #include <asm-generic/getorder.h>
diff --git a/arch/mips/include/asm/sparsemem.h b/arch/mips/include/asm/sparsemem.h
index b1071c1..b6dd216 100644
--- a/arch/mips/include/asm/sparsemem.h
+++ b/arch/mips/include/asm/sparsemem.h
@@ -11,7 +11,9 @@
 #else
 # define SECTION_SIZE_BITS	28
 #endif
-#define MAX_PHYSMEM_BITS	48
+
+/* TODO(edjames): This is 48 in 3.19+ upstream */
+#define MAX_PHYSMEM_BITS	35
 
 #endif /* CONFIG_SPARSEMEM */
 #endif /* _MIPS_SPARSEMEM_H */
diff --git a/arch/mips/include/uapi/asm/perf_regs.h b/arch/mips/include/uapi/asm/perf_regs.h
new file mode 100644
index 0000000..412d6e1
--- /dev/null
+++ b/arch/mips/include/uapi/asm/perf_regs.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_MIPS_PERF_REGS_H
+#define _ASM_MIPS_PERF_REGS_H
+
+enum perf_event_mips_regs {
+       PERF_REG_MIPS_PC,
+       PERF_REG_MIPS_R1,
+       PERF_REG_MIPS_R2,
+       PERF_REG_MIPS_R3,
+       PERF_REG_MIPS_R4,
+       PERF_REG_MIPS_R5,
+       PERF_REG_MIPS_R6,
+       PERF_REG_MIPS_R7,
+       PERF_REG_MIPS_R8,
+       PERF_REG_MIPS_R9,
+       PERF_REG_MIPS_R10,
+       PERF_REG_MIPS_R11,
+       PERF_REG_MIPS_R12,
+       PERF_REG_MIPS_R13,
+       PERF_REG_MIPS_R14,
+       PERF_REG_MIPS_R15,
+       PERF_REG_MIPS_R16,
+       PERF_REG_MIPS_R17,
+       PERF_REG_MIPS_R18,
+       PERF_REG_MIPS_R19,
+       PERF_REG_MIPS_R20,
+       PERF_REG_MIPS_R21,
+       PERF_REG_MIPS_R22,
+       PERF_REG_MIPS_R23,
+       PERF_REG_MIPS_R24,
+       PERF_REG_MIPS_R25,
+       /*
+        * 26 and 27 are k0 and k1, they are always clobbered thus not
+        * stored.
+        */
+       PERF_REG_MIPS_R28,
+       PERF_REG_MIPS_R29,
+       PERF_REG_MIPS_R30,
+       PERF_REG_MIPS_R31,
+       PERF_REG_MIPS_MAX = PERF_REG_MIPS_R31 + 1,
+};
+#endif /* _ASM_MIPS_PERF_REGS_H */
diff --git a/arch/mips/include/uapi/asm/socket.h b/arch/mips/include/uapi/asm/socket.h
index dec3c85..541385a 100644
--- a/arch/mips/include/uapi/asm/socket.h
+++ b/arch/mips/include/uapi/asm/socket.h
@@ -80,6 +80,7 @@
 #define SCM_TIMESTAMPING	SO_TIMESTAMPING
 
 #define SO_RXQ_OVFL		40
+#define SO_RXQ_ALLOC		101  /* non-upstreamed sockopt */
 
 #define SO_WIFI_STATUS		41
 #define SCM_WIFI_STATUS		SO_WIFI_STATUS
diff --git a/arch/mips/kernel/Makefile b/arch/mips/kernel/Makefile
index 68e2b7d..a1b7166 100644
--- a/arch/mips/kernel/Makefile
+++ b/arch/mips/kernel/Makefile
@@ -96,7 +96,7 @@
 
 obj-$(CONFIG_HAVE_STD_PC_SERIAL_PORT)	+= 8250-platform.o
 
-obj-$(CONFIG_PERF_EVENTS)	+= perf_event.o
+obj-$(CONFIG_PERF_EVENTS)	+= perf_event.o perf_regs.o
 obj-$(CONFIG_HW_PERF_EVENTS)	+= perf_event_mipsxx.o
 
 obj-$(CONFIG_JUMP_LABEL)	+= jump_label.o
diff --git a/arch/mips/kernel/bmips_vec.S b/arch/mips/kernel/bmips_vec.S
index 8649507..9d227ef 100644
--- a/arch/mips/kernel/bmips_vec.S
+++ b/arch/mips/kernel/bmips_vec.S
@@ -84,11 +84,11 @@
 	.align	4
 
 #ifdef CONFIG_SMP
-	/* if the NMI bit is clear, assume this is a CPU1 reset instead */
+	/* if the NMI bit is clear, assume this is a soft reset */
 	li	k1, (1 << 19)
 	mfc0	k0, CP0_STATUS
 	and	k0, k1
-	beqz	k0, bmips_smp_entry
+	beqz	k0, soft_reset
 
 #if defined(CONFIG_CPU_BMIPS5000)
 	mfc0	k0, CP0_PRID
@@ -126,12 +126,52 @@
 	eret
 
 /***********************************************************************
- * CPU1 reset vector (used for the initial boot only)
+ * CPU1 reset vector (used for the initial and warm boot only)
  * This is still part of bmips_reset_nmi_vec().
  ***********************************************************************/
 
 #ifdef CONFIG_SMP
 
+soft_reset:
+
+#if defined(CONFIG_CPU_BMIPS5000) && defined(CONFIG_BCM7435)
+	/* if running on TP 1, jump  to  bmips_smp_entry */
+	mfc0	k0, $22
+	li	k1, (1 << 24)
+	and	k1, k0
+	bnez	k1, bmips_smp_entry
+	nop
+
+	/*
+	 * running on TP0, can not be core 0 (the boot core).
+	 * Check for soft reset.  Indicates a warm boot
+	 */
+	mfc0	k0, $12
+	li	k1, (1 << 20)
+	and	k0, k1
+	beqz	k0, bmips_smp_entry
+
+	/*
+	 * Warm boot.
+	 * Cache init is only done on TP0
+	 */
+	la	k0, bmips_5xxx_init
+	jalr	k0
+	nop
+
+#if !defined(CONFIG_BCM7435A0)
+	b	bmips_smp_entry
+	nop
+#else
+	/* wait for nmi interrupt from start_secondary */
+1:
+	wait
+	b	1b
+	nop
+#endif
+#endif
+
+
 bmips_smp_entry:
 
 	/* set up CP0 STATUS; enable FPU */
diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
index 8dfe6a6..2731c68 100644
--- a/arch/mips/kernel/cevt-r4k.c
+++ b/arch/mips/kernel/cevt-r4k.c
@@ -15,6 +15,10 @@
 #include <asm/time.h>
 #include <asm/cevt-r4k.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 static int mips_next_event(unsigned long delta,
 			   struct clock_event_device *evt)
 {
@@ -22,7 +26,11 @@
 	int res;
 
 	cnt = read_c0_count();
+#ifdef CONFIG_BRCMSTB
+	cnt += brcm_fixup_ticks(delta);
+#else
 	cnt += delta;
+#endif
 	write_c0_compare(cnt);
 	res = ((int)(read_c0_count() - cnt) >= 0) ? -ETIME : 0;
 	return res;
diff --git a/arch/mips/kernel/perf_regs.c b/arch/mips/kernel/perf_regs.c
new file mode 100644
index 0000000..b5eea4b
--- /dev/null
+++ b/arch/mips/kernel/perf_regs.c
@@ -0,0 +1,67 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Some parts derived from x86 version of this file.
+ *
+ * Copyright (C) 2013 Cavium, Inc.
+ */
+
+#include <linux/perf_event.h>
+
+#include <asm/ptrace.h>
+
+#ifdef CONFIG_32BIT
+u64 perf_reg_abi(struct task_struct *tsk)
+{
+       return PERF_SAMPLE_REGS_ABI_32;
+}
+#else /* Must be CONFIG_64BIT */
+u64 perf_reg_abi(struct task_struct *tsk)
+{
+       if (test_tsk_thread_flag(tsk, TIF_32BIT_REGS))
+               return PERF_SAMPLE_REGS_ABI_32;
+       else
+               return PERF_SAMPLE_REGS_ABI_64;
+}
+#endif /* CONFIG_32BIT */
+
+int perf_reg_validate(u64 mask)
+{
+       if (!mask)
+               return -EINVAL;
+       if (mask & ~((1ull << PERF_REG_MIPS_MAX) - 1))
+               return -EINVAL;
+       return 0;
+}
+
+u64 perf_reg_value(struct pt_regs *regs, int idx)
+{
+       long v;
+
+       switch (idx) {
+       case PERF_REG_MIPS_PC:
+               v = regs->cp0_epc;
+               break;
+       case PERF_REG_MIPS_R1 ... PERF_REG_MIPS_R25:
+               v = regs->regs[idx - PERF_REG_MIPS_R1 + 1];
+               break;
+       case PERF_REG_MIPS_R28 ... PERF_REG_MIPS_R31:
+               v = regs->regs[idx - PERF_REG_MIPS_R28 + 28];
+               break;
+
+       default:
+               WARN_ON_ONCE(1);
+               return 0;
+       }
+
+       return (s64)v; /* Sign extend if 32-bit. */
+}
+
+void perf_get_regs_user(struct perf_regs *regs_user,
+       struct pt_regs *regs, struct pt_regs *regs_user_copy)
+{
+       regs_user->regs = task_pt_regs(current);
+       regs_user->abi = perf_reg_abi(current);
+}
diff --git a/arch/mips/kernel/proc.c b/arch/mips/kernel/proc.c
index 298b2b7..aac03af 100644
--- a/arch/mips/kernel/proc.c
+++ b/arch/mips/kernel/proc.c
@@ -15,6 +15,10 @@
 #include <asm/processor.h>
 #include <asm/prom.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 unsigned int vced_count, vcei_count;
 
 /*
@@ -65,6 +69,11 @@
 	seq_printf(m, "BogoMIPS\t\t: %u.%02u\n",
 		      cpu_data[n].udelay_val / (500000/HZ),
 		      (cpu_data[n].udelay_val / (5000/HZ)) % 100);
+#ifdef CONFIG_BRCMSTB
+	/* for Oprofile opreport */
+	seq_printf(m, "cpu MHz\t\t\t: %lu.%03lu\n", brcm_adj_cpu_khz / 1000,
+		   brcm_adj_cpu_khz % 1000);
+#endif
 	seq_printf(m, "wait instruction\t: %s\n", cpu_wait ? "yes" : "no");
 	seq_printf(m, "microsecond timers\t: %s\n",
 		      cpu_has_counter ? "yes" : "no");
diff --git a/arch/mips/kernel/setup.c b/arch/mips/kernel/setup.c
index 8acae31..e4bbf01 100644
--- a/arch/mips/kernel/setup.c
+++ b/arch/mips/kernel/setup.c
@@ -39,6 +39,10 @@
 #include <asm/smp-ops.h>
 #include <asm/prom.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 #ifdef CONFIG_MIPS_ELF_APPENDED_DTB
 const char __section(.appended_dtb) __appended_dtb[0x100000];
 #endif /* CONFIG_MIPS_ELF_APPENDED_DTB */
@@ -72,10 +76,6 @@
 static char __initdata command_line[COMMAND_LINE_SIZE];
 char __initdata arcs_cmdline[COMMAND_LINE_SIZE];
 
-#ifdef CONFIG_CMDLINE_BOOL
-static char __initdata builtin_cmdline[COMMAND_LINE_SIZE] = CONFIG_CMDLINE;
-#endif
-
 /*
  * mips_io_port_base is the begin of the address space to which x86 style
  * I/O ports are mapped.
@@ -460,8 +460,12 @@
 		size = end - start;
 
 		/* Register lowmem ranges */
+#ifdef CONFIG_BRCMSTB
+		/* carve out space for bmem */
+		brcm_free_bootmem(PFN_PHYS(start), size << PAGE_SHIFT);
+#else
 		free_bootmem(PFN_PHYS(start), size << PAGE_SHIFT);
-		memory_present(0, start, end);
+#endif
 	}
 
 	/*
@@ -473,6 +477,23 @@
 	 * Reserve initrd memory if needed.
 	 */
 	finalize_initrd();
+
+	/*
+	 * Call memory_present() on all valid ranges, for SPARSEMEM.
+	 * This must be done after setting up bootmem, since memory_present()
+	 * may allocate bootmem.
+	 */
+	for (i = 0; i < boot_mem_map.nr_map; i++) {
+		unsigned long start, end;
+
+		if (boot_mem_map.map[i].type != BOOT_MEM_RAM)
+			continue;
+
+		start = PFN_UP(boot_mem_map.map[i].addr);
+		end   = PFN_DOWN(boot_mem_map.map[i].addr
+				    + boot_mem_map.map[i].size);
+		memory_present(0, start, end);
+	}
 }
 
 #endif	/* CONFIG_SGI_IP27 */
@@ -649,25 +670,7 @@
 	pr_info("Determined physical RAM map:\n");
 	print_memory_map();
 
-#if defined(CONFIG_CMDLINE_BOOL) && defined(CONFIG_CMDLINE_OVERRIDE)
-	strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
-#else
-	if ((USE_PROM_CMDLINE && arcs_cmdline[0]) ||
-	    (USE_DTB_CMDLINE && !boot_command_line[0]))
-		strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
-
-	if (EXTEND_WITH_PROM && arcs_cmdline[0]) {
-		strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
-		strlcat(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
-	}
-
-#if defined(CONFIG_CMDLINE_BOOL)
-	if (builtin_cmdline[0]) {
-		strlcat(boot_command_line, " ", COMMAND_LINE_SIZE);
-		strlcat(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
-	}
-#endif
-#endif
+	strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
 	strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
 
 	*cmdline_p = command_line;
diff --git a/arch/mips/kernel/smp-bmips.c b/arch/mips/kernel/smp-bmips.c
index 78cf8c2..de0ad52 100644
--- a/arch/mips/kernel/smp-bmips.c
+++ b/arch/mips/kernel/smp-bmips.c
@@ -254,6 +254,19 @@
 {
 	pr_info("SMP: CPU%d is running\n", smp_processor_id());
 
+	if (current_cpu_type() == CPU_BMIPS5000) {
+		u32 tp_id = ((read_c0_brcm_config() >> 24) & 0x1);
+		u32 xks_en = !!(read_c0_brcm_config_1() & BIT(8));
+
+		/* If XKS is enabled, need to move bootvec to KSEG0 */
+		if (xks_en)
+			write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
+					      ~(0x2000 << (16 * tp_id)));
+
+		/* Enable NMI interrupt delivery to this thread */
+		write_c0_brcm_mode(read_c0_brcm_mode() | BIT(tp_id));
+	}
+
 	/* make sure there won't be a timer interrupt for a little while */
 	write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
 
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 99a4022..2085feb 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -65,6 +65,10 @@
 #include <asm/stacktrace.h>
 #include <asm/uasm.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 extern void check_wait(void);
 extern asmlinkage void rollback_handle_int(void);
 extern asmlinkage void handle_int(void);
@@ -332,6 +336,17 @@
 	if (1 <= exccode && exccode <= 5)
 		printk("BadVA : %0*lx\n", field, regs->cp0_badvaddr);
 
+#ifdef CONFIG_CPU_BMIPS5000
+	if (exccode == 6) {
+		printk("SCER: %08x\n", __read_32bit_c0_register($27, 2));
+		printk("ICER: %08x\n", __read_32bit_c0_register($27, 0));
+	}
+	if (exccode == 7) {
+		printk("SCER: %08x\n", __read_32bit_c0_register($27, 2));
+		printk("DCER: %08x\n", __read_32bit_c0_register($27, 1));
+	}
+#endif
+
 	printk("PrId  : %08x (%s)\n", read_c0_prid(),
 	       cpu_name_string());
 }
@@ -651,6 +666,10 @@
 
 static int simulate_rdhwr_normal(struct pt_regs *regs, unsigned int opcode)
 {
+#ifdef CONFIG_BRCMSTB
+	if (((opcode & FUNC) == RDHWR) && !brcm_simulate_opcode(regs, opcode))
+		return 0;
+#endif
 	if ((opcode & OPCODE) == SPEC3 && (opcode & FUNC) == RDHWR) {
 		int rd = (opcode & RD) >> 11;
 		int rt = (opcode & RT) >> 16;
@@ -2149,7 +2168,11 @@
 	/* Boot CPU's cache setup in setup_arch(). */
 	if (!is_boot_cpu)
 		cpu_cache_init();
+#ifdef CONFIG_BRCMSTB
+	brcm_tlb_init();
+#else
 	tlb_init();
+#endif
 	TLBMISS_HANDLER_SETUP();
 }
 
diff --git a/arch/mips/kernel/unaligned.c b/arch/mips/kernel/unaligned.c
index 5c62065..019d16f 100644
--- a/arch/mips/kernel/unaligned.c
+++ b/arch/mips/kernel/unaligned.c
@@ -91,6 +91,10 @@
 #include <asm/inst.h>
 #include <asm/uaccess.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 #define STR(x)	__STR(x)
 #define __STR(x)  #x
 
@@ -1191,6 +1195,16 @@
 	case ldc1_op:
 	case swc1_op:
 	case sdc1_op:
+#ifdef CONFIG_BRCMSTB
+		switch (brcm_unaligned_fp(addr, &insn, regs)) {
+		case -EINVAL:
+			goto sigbus;
+		case -EFAULT:
+			goto fault;
+		}
+		compute_return_epc(regs);
+		break;
+#endif
 		die_if_kernel("Unaligned FP access in kernel code", regs);
 		BUG_ON(!used_math());
 
diff --git a/arch/mips/lib/Makefile b/arch/mips/lib/Makefile
index 0344e57..d693af6 100644
--- a/arch/mips/lib/Makefile
+++ b/arch/mips/lib/Makefile
@@ -15,4 +15,4 @@
 obj-$(CONFIG_CPU_TX39XX)	+= r3k_dump_tlb.o
 
 # libgcc-style stuff needed in the kernel
-obj-y += ashldi3.o ashrdi3.o bswapsi.o bswapdi.o cmpdi2.o lshrdi3.o ucmpdi2.o
+obj-y += ashldi3.o ashrdi3.o bswapsi.o bswapdi.o cmpdi2.o lshrdi3.o ucmpdi2.o udivdi3.o
diff --git a/arch/mips/lib/longlong.h b/arch/mips/lib/longlong.h
new file mode 100644
index 0000000..d7d7398
--- /dev/null
+++ b/arch/mips/lib/longlong.h
@@ -0,0 +1,1350 @@
+/* longlong.h -- definitions for mixed size 32/64 bit arithmetic.
+   Copyright (C) 1991, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000
+   Free Software Foundation, Inc.
+
+   This definition file is free software; you can redistribute it
+   and/or modify it under the terms of the GNU General Public
+   License as published by the Free Software Foundation; either
+   version 2, or (at your option) any later version.
+
+   This definition file is distributed in the hope that it will be
+   useful, but WITHOUT ANY WARRANTY; without even the implied
+   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+   See the GNU General Public License for more details.
+
+   You should have received a copy of the GNU General Public License
+   along with this program; if not, write to the Free Software
+   Foundation, Inc., 59 Temple Place - Suite 330,
+   Boston, MA 02111-1307, USA.  */
+
+/* You have to define the following before including this file:
+
+   UWtype -- An unsigned type, default type for operations (typically a "word")
+   UHWtype -- An unsigned type, at least half the size of UWtype.
+   UDWtype -- An unsigned type, at least twice as large a UWtype
+   W_TYPE_SIZE -- size in bits of UWtype
+
+   UQItype -- Unsigned 8 bit type.
+   SItype, USItype -- Signed and unsigned 32 bit types.
+   DItype, UDItype -- Signed and unsigned 64 bit types.
+
+   On a 32 bit machine UWtype should typically be USItype;
+   on a 64 bit machine, UWtype should typically be UDItype.
+*/
+
+#define __BITS4 (W_TYPE_SIZE / 4)
+#define __ll_B ((UWtype) 1 << (W_TYPE_SIZE / 2))
+#define __ll_lowpart(t) ((UWtype) (t) & (__ll_B - 1))
+#define __ll_highpart(t) ((UWtype) (t) >> (W_TYPE_SIZE / 2))
+
+#ifndef W_TYPE_SIZE
+#define W_TYPE_SIZE	32
+#define UWtype		USItype
+#define UHWtype		USItype
+#define UDWtype		UDItype
+#endif
+
+/* Define auxiliary asm macros.
+
+   1) umul_ppmm(high_prod, low_prod, multipler, multiplicand) multiplies two
+   UWtype integers MULTIPLER and MULTIPLICAND, and generates a two UWtype
+   word product in HIGH_PROD and LOW_PROD.
+
+   2) __umulsidi3(a,b) multiplies two UWtype integers A and B, and returns a
+   UDWtype product.  This is just a variant of umul_ppmm.
+
+   3) udiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
+   denominator) divides a UDWtype, composed by the UWtype integers
+   HIGH_NUMERATOR and LOW_NUMERATOR, by DENOMINATOR and places the quotient
+   in QUOTIENT and the remainder in REMAINDER.  HIGH_NUMERATOR must be less
+   than DENOMINATOR for correct operation.  If, in addition, the most
+   significant bit of DENOMINATOR must be 1, then the pre-processor symbol
+   UDIV_NEEDS_NORMALIZATION is defined to 1.
+
+   4) sdiv_qrnnd(quotient, remainder, high_numerator, low_numerator,
+   denominator).  Like udiv_qrnnd but the numbers are signed.  The quotient
+   is rounded towards 0.
+
+   5) count_leading_zeros(count, x) counts the number of zero-bits from the
+   msb to the first nonzero bit in the UWtype X.  This is the number of
+   steps X needs to be shifted left to set the msb.  Undefined for X == 0,
+   unless the symbol COUNT_LEADING_ZEROS_0 is defined to some value.
+
+   6) count_trailing_zeros(count, x) like count_leading_zeros, but counts
+   from the least significant end.
+
+   7) add_ssaaaa(high_sum, low_sum, high_addend_1, low_addend_1,
+   high_addend_2, low_addend_2) adds two UWtype integers, composed by
+   HIGH_ADDEND_1 and LOW_ADDEND_1, and HIGH_ADDEND_2 and LOW_ADDEND_2
+   respectively.  The result is placed in HIGH_SUM and LOW_SUM.  Overflow
+   (i.e. carry out) is not stored anywhere, and is lost.
+
+   8) sub_ddmmss(high_difference, low_difference, high_minuend, low_minuend,
+   high_subtrahend, low_subtrahend) subtracts two two-word UWtype integers,
+   composed by HIGH_MINUEND_1 and LOW_MINUEND_1, and HIGH_SUBTRAHEND_2 and
+   LOW_SUBTRAHEND_2 respectively.  The result is placed in HIGH_DIFFERENCE
+   and LOW_DIFFERENCE.  Overflow (i.e. carry out) is not stored anywhere,
+   and is lost.
+
+   If any of these macros are left undefined for a particular CPU,
+   C macros are used.  */
+
+/* The CPUs come in alphabetical order below.
+
+   Please add support for more CPUs here, or improve the current support
+   for the CPUs below!
+   (E.g. WE32100, IBM360.)  */
+
+#if defined (__GNUC__) && !defined (NO_ASM)
+
+/* We sometimes need to clobber "cc" with gcc2, but that would not be
+   understood by gcc1.  Use cpp to avoid major code duplication.  */
+#if __GNUC__ < 2
+#define __CLOBBER_CC
+#define __AND_CLOBBER_CC
+#else /* __GNUC__ >= 2 */
+#define __CLOBBER_CC : "cc"
+#define __AND_CLOBBER_CC , "cc"
+#endif /* __GNUC__ < 2 */
+
+#if defined (__alpha) && W_TYPE_SIZE == 64
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    UDItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("umulh %r1,%2,%0"						\
+	     : "=r" ((UDItype) ph)					\
+	     : "%rJ" (__m0),						\
+	       "rI" (__m1));						\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define UMUL_TIME 46
+#ifndef LONGLONG_STANDALONE
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  do { UDItype __r;							\
+    (q) = __udiv_qrnnd (&__r, (n1), (n0), (d));				\
+    (r) = __r;								\
+  } while (0)
+extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
+#define UDIV_TIME 220
+#endif /* LONGLONG_STANDALONE */
+#ifdef __alpha_cix__
+#define count_leading_zeros(COUNT,X) \
+  __asm__("ctlz %1,%0" : "=r"(COUNT) : "r"(X))
+#define count_trailing_zeros(COUNT,X) \
+  __asm__("cttz %1,%0" : "=r"(COUNT) : "r"(X))
+#define COUNT_LEADING_ZEROS_0 64
+#else
+extern const UQItype __clz_tab[];
+#define count_leading_zeros(COUNT,X) \
+  do {									\
+    UDItype __xr = (X), __t, __a;					\
+    __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr));		\
+    __a = __clz_tab[__t ^ 0xff] - 1;					\
+    __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a));	\
+    (COUNT) = 64 - (__clz_tab[__t] + __a*8);				\
+  } while (0)
+#define count_trailing_zeros(COUNT,X) \
+  do {									\
+    UDItype __xr = (X), __t, __a;					\
+    __asm__("cmpbge $31,%1,%0" : "=r"(__t) : "r"(__xr));		\
+    __t = ~__t & -~__t;							\
+    __a = ((__t & 0xCC) != 0) * 2;					\
+    __a += ((__t & 0xF0) != 0) * 4;					\
+    __a += ((__t & 0xAA) != 0);						\
+    __asm__("extbl %1,%2,%0" : "=r"(__t) : "r"(__xr), "r"(__a));	\
+    __a <<= 3;								\
+    __t &= -__t;							\
+    __a += ((__t & 0xCC) != 0) * 2;					\
+    __a += ((__t & 0xF0) != 0) * 4;					\
+    __a += ((__t & 0xAA) != 0);						\
+    (COUNT) = __a;							\
+  } while (0)
+#endif /* __alpha_cix__ */
+#endif /* __alpha */
+
+#if defined (__arc__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add.f	%1, %4, %5\n\tadc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%r" ((USItype) (ah)),					\
+	     "rIJ" ((USItype) (bh)),					\
+	     "%r" ((USItype) (al)),					\
+	     "rIJ" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub.f	%1, %4, %5\n\tsbc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "r" ((USItype) (ah)),					\
+	     "rIJ" ((USItype) (bh)),					\
+	     "r" ((USItype) (al)),					\
+	     "rIJ" ((USItype) (bl)))
+/* Call libgcc routine.  */
+#define umul_ppmm(w1, w0, u, v) \
+do {									\
+  DWunion __w;								\
+  __w.ll = __umulsidi3 (u, v);						\
+  w1 = __w.s.high;							\
+  w0 = __w.s.low;							\
+} while (0)
+#define __umulsidi3 __umulsidi3
+UDItype __umulsidi3 (USItype, USItype);
+#endif
+
+#if defined (__arm__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("adds	%1, %4, %5\n\tadc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%r" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "%r" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subs	%1, %4, %5\n\tsbc	%0, %2, %3"		\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "r" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "r" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl)))
+#define umul_ppmm(xh, xl, a, b) \
+{register USItype __t0, __t1, __t2;					\
+  __asm__ ("%@ Inlined umul_ppmm\n"					\
+	   "	mov	%2, %5, lsr #16\n"				\
+	   "	mov	%0, %6, lsr #16\n"				\
+	   "	bic	%3, %5, %2, lsl #16\n"				\
+	   "	bic	%4, %6, %0, lsl #16\n"				\
+	   "	mul	%1, %3, %4\n"					\
+	   "	mul	%4, %2, %4\n"					\
+	   "	mul	%3, %0, %3\n"					\
+	   "	mul	%0, %2, %0\n"					\
+	   "	adds	%3, %4, %3\n"					\
+	   "	addcs	%0, %0, #65536\n"				\
+	   "	adds	%1, %1, %3, lsl #16\n"				\
+	   "	adc	%0, %0, %3, lsr #16"				\
+	   : "=&r" ((USItype) (xh)),					\
+	     "=r" ((USItype) (xl)),					\
+	     "=&r" (__t0), "=&r" (__t1), "=r" (__t2)			\
+	   : "r" ((USItype) (a)),					\
+	     "r" ((USItype) (b)));}
+#define UMUL_TIME 20
+#define UDIV_TIME 100
+#endif /* __arm__ */
+
+#if defined (__hppa) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add %4,%5,%1\n\taddc %2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%rM" ((USItype) (ah)),					\
+	     "rM" ((USItype) (bh)),					\
+	     "%rM" ((USItype) (al)),					\
+	     "rM" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub %4,%5,%1\n\tsubb %2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "rM" ((USItype) (ah)),					\
+	     "rM" ((USItype) (bh)),					\
+	     "rM" ((USItype) (al)),					\
+	     "rM" ((USItype) (bl)))
+#if defined (_PA_RISC1_1)
+#define umul_ppmm(w1, w0, u, v) \
+  do {									\
+    union								\
+      {									\
+	UDItype __f;							\
+	struct {USItype __w1, __w0;} __w1w0;				\
+      } __t;								\
+    __asm__ ("xmpyu %1,%2,%0"						\
+	     : "=x" (__t.__f)						\
+	     : "x" ((USItype) (u)),					\
+	       "x" ((USItype) (v)));					\
+    (w1) = __t.__w1w0.__w1;						\
+    (w0) = __t.__w1w0.__w0;						\
+     } while (0)
+#define UMUL_TIME 8
+#else
+#define UMUL_TIME 30
+#endif
+#define UDIV_TIME 40
+#define count_leading_zeros(count, x) \
+  do {									\
+    USItype __tmp;							\
+    __asm__ (								\
+       "ldi		1,%0\n"						\
+"	extru,=		%1,15,16,%%r0		; Bits 31..16 zero?\n"	\
+"	extru,tr	%1,15,16,%1		; No.  Shift down, skip add.\n"\
+"	ldo		16(%0),%0		; Yes.  Perform add.\n"	\
+"	extru,=		%1,23,8,%%r0		; Bits 15..8 zero?\n"	\
+"	extru,tr	%1,23,8,%1		; No.  Shift down, skip add.\n"\
+"	ldo		8(%0),%0		; Yes.  Perform add.\n"	\
+"	extru,=		%1,27,4,%%r0		; Bits 7..4 zero?\n"	\
+"	extru,tr	%1,27,4,%1		; No.  Shift down, skip add.\n"\
+"	ldo		4(%0),%0		; Yes.  Perform add.\n"	\
+"	extru,=		%1,29,2,%%r0		; Bits 3..2 zero?\n"	\
+"	extru,tr	%1,29,2,%1		; No.  Shift down, skip add.\n"\
+"	ldo		2(%0),%0		; Yes.  Perform add.\n"	\
+"	extru		%1,30,1,%1		; Extract bit 1.\n"	\
+"	sub		%0,%1,%0		; Subtract it.\n"	\
+	: "=r" (count), "=r" (__tmp) : "1" (x));			\
+  } while (0)
+#endif
+
+#if (defined (__i370__) || defined (__s390__) || defined (__mvs__)) && W_TYPE_SIZE == 32
+#define smul_ppmm(xh, xl, m0, m1) \
+  do {									\
+    union {DItype __ll;							\
+	   struct {USItype __h, __l;} __i;				\
+	  } __x;							\
+    __asm__ ("lr %N0,%1\n\tmr %0,%2"					\
+	     : "=&r" (__x.__ll)						\
+	     : "r" (m0), "r" (m1));					\
+    (xh) = __x.__i.__h; (xl) = __x.__i.__l;				\
+  } while (0)
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  do {									\
+    union {DItype __ll;							\
+	   struct {USItype __h, __l;} __i;				\
+	  } __x;							\
+    __x.__i.__h = n1; __x.__i.__l = n0;					\
+    __asm__ ("dr %0,%2"							\
+	     : "=r" (__x.__ll)						\
+	     : "0" (__x.__ll), "r" (d));				\
+    (q) = __x.__i.__l; (r) = __x.__i.__h;				\
+  } while (0)
+#endif
+
+#if (defined (__i386__) || defined (__i486__)) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addl %5,%1\n\tadcl %3,%0"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subl %5,%1\n\tsbbl %3,%0"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("mull %3"							\
+	   : "=a" ((USItype) (w0)),					\
+	     "=d" ((USItype) (w1))					\
+	   : "%0" ((USItype) (u)),					\
+	     "rm" ((USItype) (v)))
+#define udiv_qrnnd(q, r, n1, n0, dv) \
+  __asm__ ("divl %4"							\
+	   : "=a" ((USItype) (q)),					\
+	     "=d" ((USItype) (r))					\
+	   : "0" ((USItype) (n0)),					\
+	     "1" ((USItype) (n1)),					\
+	     "rm" ((USItype) (dv)))
+#define count_leading_zeros(count, x) \
+  do {									\
+    USItype __cbtmp;							\
+    __asm__ ("bsrl %1,%0"						\
+	     : "=r" (__cbtmp) : "rm" ((USItype) (x)));			\
+    (count) = __cbtmp ^ 31;						\
+  } while (0)
+#define count_trailing_zeros(count, x) \
+  __asm__ ("bsfl %1,%0" : "=r" (count) : "rm" ((USItype)(x)))
+#define UMUL_TIME 40
+#define UDIV_TIME 40
+#endif /* 80x86 */
+
+#if defined (__i960__) && W_TYPE_SIZE == 32
+#define umul_ppmm(w1, w0, u, v) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __l, __h;} __i;				\
+	  } __xx;							\
+  __asm__ ("emul	%2,%1,%0"					\
+	   : "=d" (__xx.__ll)						\
+	   : "%dI" ((USItype) (u)),					\
+	     "dI" ((USItype) (v)));					\
+  (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
+#define __umulsidi3(u, v) \
+  ({UDItype __w;							\
+    __asm__ ("emul	%2,%1,%0"					\
+	     : "=d" (__w)						\
+	     : "%dI" ((USItype) (u)),					\
+	       "dI" ((USItype) (v)));					\
+    __w; })
+#endif /* __i960__ */
+
+#if defined (__M32R__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  /* The cmp clears the condition bit.  */ \
+  __asm__ ("cmp %0,%0\n\taddx %%5,%1\n\taddx %%3,%0"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl))					\
+	   : "cbit")
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  /* The cmp clears the condition bit.  */ \
+  __asm__ ("cmp %0,%0\n\tsubx %5,%1\n\tsubx %3,%0"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl))					\
+	   : "cbit")
+#endif /* __M32R__ */
+
+#if defined (__mc68000__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add%.l %5,%1\n\taddx%.l %3,%0"				\
+	   : "=d" ((USItype) (sh)),					\
+	     "=&d" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "d" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub%.l %5,%1\n\tsubx%.l %3,%0"				\
+	   : "=d" ((USItype) (sh)),					\
+	     "=&d" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "d" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+
+/* The '020, '030, '040 and CPU32 have 32x32->64 and 64/32->32q-32r.  */
+#if defined (__mc68020__) || defined(mc68020) \
+	|| defined(__mc68030__) || defined(mc68030) \
+	|| defined(__mc68040__) || defined(mc68040) \
+	|| defined(__mcpu32__) || defined(mcpu32)
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("mulu%.l %3,%1:%0"						\
+	   : "=d" ((USItype) (w0)),					\
+	     "=d" ((USItype) (w1))					\
+	   : "%0" ((USItype) (u)),					\
+	     "dmi" ((USItype) (v)))
+#define UMUL_TIME 45
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("divu%.l %4,%1:%0"						\
+	   : "=d" ((USItype) (q)),					\
+	     "=d" ((USItype) (r))					\
+	   : "0" ((USItype) (n0)),					\
+	     "1" ((USItype) (n1)),					\
+	     "dmi" ((USItype) (d)))
+#define UDIV_TIME 90
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("divs%.l %4,%1:%0"						\
+	   : "=d" ((USItype) (q)),					\
+	     "=d" ((USItype) (r))					\
+	   : "0" ((USItype) (n0)),					\
+	     "1" ((USItype) (n1)),					\
+	     "dmi" ((USItype) (d)))
+
+#else /* not mc68020 */
+#if !defined(__mcf5200__)
+/* %/ inserts REGISTER_PREFIX, %# inserts IMMEDIATE_PREFIX.  */
+#define umul_ppmm(xh, xl, a, b) \
+  __asm__ ("| Inlined umul_ppmm\n"					\
+	   "	move%.l	%2,%/d0\n"					\
+	   "	move%.l	%3,%/d1\n"					\
+	   "	move%.l	%/d0,%/d2\n"					\
+	   "	swap	%/d0\n"						\
+	   "	move%.l	%/d1,%/d3\n"					\
+	   "	swap	%/d1\n"						\
+	   "	move%.w	%/d2,%/d4\n"					\
+	   "	mulu	%/d3,%/d4\n"					\
+	   "	mulu	%/d1,%/d2\n"					\
+	   "	mulu	%/d0,%/d3\n"					\
+	   "	mulu	%/d0,%/d1\n"					\
+	   "	move%.l	%/d4,%/d0\n"					\
+	   "	eor%.w	%/d0,%/d0\n"					\
+	   "	swap	%/d0\n"						\
+	   "	add%.l	%/d0,%/d2\n"					\
+	   "	add%.l	%/d3,%/d2\n"					\
+	   "	jcc	1f\n"						\
+	   "	add%.l	%#65536,%/d1\n"					\
+	   "1:	swap	%/d2\n"						\
+	   "	moveq	%#0,%/d0\n"					\
+	   "	move%.w	%/d2,%/d0\n"					\
+	   "	move%.w	%/d4,%/d2\n"					\
+	   "	move%.l	%/d2,%1\n"					\
+	   "	add%.l	%/d1,%/d0\n"					\
+	   "	move%.l	%/d0,%0"					\
+	   : "=g" ((USItype) (xh)),					\
+	     "=g" ((USItype) (xl))					\
+	   : "g" ((USItype) (a)),					\
+	     "g" ((USItype) (b))					\
+	   : "d0", "d1", "d2", "d3", "d4")
+#define UMUL_TIME 100
+#define UDIV_TIME 400
+#endif /* not mcf5200 */
+#endif /* not mc68020 */
+
+/* The '020, '030, '040 and '060 have bitfield insns.  */
+#if defined (__mc68020__) || defined(mc68020) \
+	|| defined(__mc68030__) || defined(mc68030) \
+	|| defined(__mc68040__) || defined(mc68040) \
+	|| defined(__mc68060__) || defined(mc68060)
+#define count_leading_zeros(count, x) \
+  __asm__ ("bfffo %1{%b2:%b2},%0"					\
+	   : "=d" ((USItype) (count))					\
+	   : "od" ((USItype) (x)), "n" (0))
+#endif
+#endif /* mc68000 */
+
+#if defined (__m88000__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addu.co %1,%r4,%r5\n\taddu.ci %0,%r2,%r3"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%rJ" ((USItype) (ah)),					\
+	     "rJ" ((USItype) (bh)),					\
+	     "%rJ" ((USItype) (al)),					\
+	     "rJ" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subu.co %1,%r4,%r5\n\tsubu.ci %0,%r2,%r3"			\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "rJ" ((USItype) (ah)),					\
+	     "rJ" ((USItype) (bh)),					\
+	     "rJ" ((USItype) (al)),					\
+	     "rJ" ((USItype) (bl)))
+#define count_leading_zeros(count, x) \
+  do {									\
+    USItype __cbtmp;							\
+    __asm__ ("ff1 %0,%1"						\
+	     : "=r" (__cbtmp)						\
+	     : "r" ((USItype) (x)));					\
+    (count) = __cbtmp ^ 31;						\
+  } while (0)
+#define COUNT_LEADING_ZEROS_0 63 /* sic */
+#if defined (__mc88110__)
+#define umul_ppmm(wh, wl, u, v) \
+  do {									\
+    union {UDItype __ll;						\
+	   struct {USItype __h, __l;} __i;				\
+	  } __xx;							\
+    __asm__ ("mulu.d	%0,%1,%2"					\
+	     : "=r" (__xx.__ll)						\
+	     : "r" ((USItype) (u)),					\
+	       "r" ((USItype) (v)));					\
+    (wh) = __xx.__i.__h;						\
+    (wl) = __xx.__i.__l;						\
+  } while (0)
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __h, __l;} __i;				\
+	  } __xx;							\
+  USItype __q;								\
+  __xx.__i.__h = (n1); __xx.__i.__l = (n0);				\
+  __asm__ ("divu.d %0,%1,%2"						\
+	   : "=r" (__q)							\
+	   : "r" (__xx.__ll),						\
+	     "r" ((USItype) (d)));					\
+  (r) = (n0) - __q * (d); (q) = __q; })
+#define UMUL_TIME 5
+#define UDIV_TIME 25
+#else
+#define UMUL_TIME 17
+#define UDIV_TIME 150
+#endif /* __mc88110__ */
+#endif /* __m88000__ */
+
+/* Test for gcc >= maj.min, as per __GNUC_PREREQ in glibc */
+#if defined (__GNUC__) && defined (__GNUC_MINOR__)
+#define __GNUC_PREREQ(maj, min) \
+	((__GNUC__ << 16) + __GNUC_MINOR__ >= ((maj) << 16) + (min))
+#else
+#define __GNUC_PREREQ(maj, min)  0
+#endif
+
+/***************************************
+ **************  MIPS  *****************
+ ***************************************/
+#if defined (__mips__) && W_TYPE_SIZE == 32
+#if __GNUC_PREREQ (4,4)
+/* adapted from OpenWRT 001-mips-h-constraint.patch */
+#define umul_ppmm(w1, w0, u, v) \
+  do {                                                                  \
+    UDItype __ll = (UDItype)(u) * (v);                                  \
+    w1 = __ll >> 32;                                                    \
+    w0 = __ll;                                                          \
+  } while (0)
+#else
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("multu %2,%3"                                                \
+	   : "=l" ((USItype)(w0)),                                      \
+	     "=h" ((USItype)(w1))                                       \
+	   : "d" ((USItype)(u)),                                        \
+	     "d" ((USItype)(v)))
+#endif
+
+#define UMUL_TIME 10
+#define UDIV_TIME 100
+#endif /* __mips__ */
+
+#if defined (__ns32000__) && W_TYPE_SIZE == 32
+#define umul_ppmm(w1, w0, u, v) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __l, __h;} __i;				\
+	  } __xx;							\
+  __asm__ ("meid %2,%0"							\
+	   : "=g" (__xx.__ll)						\
+	   : "%0" ((USItype) (u)),					\
+	     "g" ((USItype) (v)));					\
+  (w1) = __xx.__i.__h; (w0) = __xx.__i.__l;})
+#define __umulsidi3(u, v) \
+  ({UDItype __w;							\
+    __asm__ ("meid %2,%0"						\
+	     : "=g" (__w)						\
+	     : "%0" ((USItype) (u)),					\
+	       "g" ((USItype) (v)));					\
+    __w; })
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  ({union {UDItype __ll;						\
+	   struct {USItype __l, __h;} __i;				\
+	  } __xx;							\
+  __xx.__i.__h = (n1); __xx.__i.__l = (n0);				\
+  __asm__ ("deid %2,%0"							\
+	   : "=g" (__xx.__ll)						\
+	   : "0" (__xx.__ll),						\
+	     "g" ((USItype) (d)));					\
+  (r) = __xx.__i.__l; (q) = __xx.__i.__h; })
+#define count_trailing_zeros(count,x) \
+  do {									\
+    __asm__ ("ffsd     %2,%0"						\
+            : "=r" ((USItype) (count))					\
+            : "0" ((USItype) 0),					\
+              "r" ((USItype) (x)));					\
+  } while (0)
+#endif /* __ns32000__ */
+
+/* FIXME: We should test _IBMR2 here when we add assembly support for the
+   system vendor compilers.
+   FIXME: What's needed for gcc PowerPC VxWorks?  __vxworks__ is not good
+   enough, since that hits ARM and m68k too.  */
+#if (defined (_ARCH_PPC)	/* AIX */				\
+     || defined (_ARCH_PWR)	/* AIX */				\
+     || defined (_ARCH_COM)	/* AIX */				\
+     || defined (__powerpc__)	/* gcc */				\
+     || defined (__POWERPC__)	/* BEOS */				\
+     || defined (__ppc__)	/* Darwin */				\
+     || defined (PPC)		/* GNU/Linux, SysV */			\
+     ) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (bh) && (bh) == 0)				\
+      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0)		\
+      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else								\
+      __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3"		\
+	     : "=r" (sh), "=&r" (sl)					\
+	     : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl));		\
+  } while (0)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (ah) && (ah) == 0)				\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (ah) && (ah) == ~(USItype) 0)		\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == 0)			\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(USItype) 0)		\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else								\
+      __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2"	\
+	       : "=r" (sh), "=&r" (sl)					\
+	       : "r" (ah), "r" (bh), "rI" (al), "r" (bl));		\
+  } while (0)
+#define count_leading_zeros(count, x) \
+  __asm__ ("{cntlz|cntlzw} %0,%1" : "=r" (count) : "r" (x))
+#define COUNT_LEADING_ZEROS_0 32
+#if defined (_ARCH_PPC) || defined (__powerpc__) || defined (__POWERPC__) \
+  || defined (__ppc__) || defined (PPC) || defined (__vxworks__)
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    USItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhwu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define UMUL_TIME 15
+#define smul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    SItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhw %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define SMUL_TIME 14
+#define UDIV_TIME 120
+#elif defined (_ARCH_PWR)
+#define UMUL_TIME 8
+#define smul_ppmm(xh, xl, m0, m1) \
+  __asm__ ("mul %0,%2,%3" : "=r" (xh), "=q" (xl) : "r" (m0), "r" (m1))
+#define SMUL_TIME 4
+#define sdiv_qrnnd(q, r, nh, nl, d) \
+  __asm__ ("div %0,%2,%4" : "=r" (q), "=q" (r) : "r" (nh), "1" (nl), "r" (d))
+#define UDIV_TIME 100
+#endif
+#endif /* 32-bit POWER architecture variants.  */
+
+/* We should test _IBMR2 here when we add assembly support for the system
+   vendor compilers.  */
+#if (defined (_ARCH_PPC64) || defined (__powerpc64__)) && W_TYPE_SIZE == 64
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (bh) && (bh) == 0)				\
+      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{aze|addze} %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0)		\
+      __asm__ ("{a%I4|add%I4c} %1,%3,%4\n\t{ame|addme} %0,%2"		\
+	     : "=r" (sh), "=&r" (sl) : "r" (ah), "%r" (al), "rI" (bl));\
+    else								\
+      __asm__ ("{a%I5|add%I5c} %1,%4,%5\n\t{ae|adde} %0,%2,%3"		\
+	     : "=r" (sh), "=&r" (sl)					\
+	     : "%r" (ah), "r" (bh), "%r" (al), "rI" (bl));		\
+  } while (0)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    if (__builtin_constant_p (ah) && (ah) == 0)				\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfze|subfze} %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (ah) && (ah) == ~(UDItype) 0)		\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{sfme|subfme} %0,%2"	\
+	       : "=r" (sh), "=&r" (sl) : "r" (bh), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == 0)			\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{ame|addme} %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else if (__builtin_constant_p (bh) && (bh) == ~(UDItype) 0)		\
+      __asm__ ("{sf%I3|subf%I3c} %1,%4,%3\n\t{aze|addze} %0,%2"		\
+	       : "=r" (sh), "=&r" (sl) : "r" (ah), "rI" (al), "r" (bl));\
+    else								\
+      __asm__ ("{sf%I4|subf%I4c} %1,%5,%4\n\t{sfe|subfe} %0,%3,%2"	\
+	       : "=r" (sh), "=&r" (sl)					\
+	       : "r" (ah), "r" (bh), "rI" (al), "r" (bl));		\
+  } while (0)
+#define count_leading_zeros(count, x) \
+  __asm__ ("cntlzd %0,%1" : "=r" (count) : "r" (x))
+#define COUNT_LEADING_ZEROS_0 64
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    UDItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhdu %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define UMUL_TIME 15
+#define smul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    DItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("mulhd %0,%1,%2" : "=r" (ph) : "%r" (m0), "r" (m1));	\
+    (pl) = __m0 * __m1;							\
+  } while (0)
+#define SMUL_TIME 14  /* ??? */
+#define UDIV_TIME 120 /* ??? */
+#endif /* 64-bit PowerPC.  */
+
+#if defined (__ibm032__) /* RT/ROMP */ && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("a %1,%5\n\tae %0,%3"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("s %1,%5\n\tse %0,%3"					\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "r" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "r" ((USItype) (bl)))
+#define umul_ppmm(ph, pl, m0, m1) \
+  do {									\
+    USItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ (								\
+       "s	r2,r2\n"						\
+"	mts	r10,%2\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	m	r2,%3\n"						\
+"	cas	%0,r2,r0\n"						\
+"	mfs	r10,%1"							\
+	     : "=r" ((USItype) (ph)),					\
+	       "=r" ((USItype) (pl))					\
+	     : "%r" (__m0),						\
+		"r" (__m1)						\
+	     : "r2");							\
+    (ph) += ((((SItype) __m0 >> 31) & __m1)				\
+	     + (((SItype) __m1 >> 31) & __m0));				\
+  } while (0)
+#define UMUL_TIME 20
+#define UDIV_TIME 200
+#define count_leading_zeros(count, x) \
+  do {									\
+    if ((x) >= 0x10000)							\
+      __asm__ ("clz	%0,%1"						\
+	       : "=r" ((USItype) (count))				\
+	       : "r" ((USItype) (x) >> 16));				\
+    else								\
+      {									\
+	__asm__ ("clz	%0,%1"						\
+		 : "=r" ((USItype) (count))				\
+		 : "r" ((USItype) (x)));					\
+	(count) += 16;							\
+      }									\
+  } while (0)
+#endif
+
+#if defined (__sh2__) && W_TYPE_SIZE == 32
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ (								\
+       "dmulu.l	%2,%3\n\tsts	macl,%1\n\tsts	mach,%0"		\
+	   : "=r" ((USItype)(w1)),					\
+	     "=r" ((USItype)(w0))					\
+	   : "r" ((USItype)(u)),					\
+	     "r" ((USItype)(v))						\
+	   : "macl", "mach")
+#define UMUL_TIME 5
+#endif
+
+#if defined (__SH5__) && __SHMEDIA__ && W_TYPE_SIZE == 32
+#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
+#define count_leading_zeros(count, x) \
+  do									\
+    {									\
+      UDItype x_ = (USItype)(x);					\
+      SItype c_;							\
+									\
+      __asm__ ("nsb %1, %0" : "=r" (c_) : "r" (x_));			\
+      (count) = c_ - 31;						\
+    }									\
+  while (0)
+#define COUNT_LEADING_ZEROS_0 32
+#endif
+
+#if defined (__sparc__) && !defined (__arch64__) && !defined (__sparcv9) \
+    && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addcc %r4,%5,%1\n\taddx %r2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "%rJ" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "%rJ" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl))					\
+	   __CLOBBER_CC)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subcc %r4,%5,%1\n\tsubx %r2,%3,%0"				\
+	   : "=r" ((USItype) (sh)),					\
+	     "=&r" ((USItype) (sl))					\
+	   : "rJ" ((USItype) (ah)),					\
+	     "rI" ((USItype) (bh)),					\
+	     "rJ" ((USItype) (al)),					\
+	     "rI" ((USItype) (bl))					\
+	   __CLOBBER_CC)
+#if defined (__sparc_v8__)
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
+	   : "=r" ((USItype) (w1)),					\
+	     "=r" ((USItype) (w0))					\
+	   : "r" ((USItype) (u)),					\
+	     "r" ((USItype) (v)))
+#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
+  __asm__ ("mov %2,%%y;nop;nop;nop;udiv %3,%4,%0;umul %0,%4,%1;sub %3,%1,%1"\
+	   : "=&r" ((USItype) (__q)),					\
+	     "=&r" ((USItype) (__r))					\
+	   : "r" ((USItype) (__n1)),					\
+	     "r" ((USItype) (__n0)),					\
+	     "r" ((USItype) (__d)))
+#else
+#if defined (__sparclite__)
+/* This has hardware multiply but not divide.  It also has two additional
+   instructions scan (ffs from high bit) and divscc.  */
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("umul %2,%3,%1;rd %%y,%0"					\
+	   : "=r" ((USItype) (w1)),					\
+	     "=r" ((USItype) (w0))					\
+	   : "r" ((USItype) (u)),					\
+	     "r" ((USItype) (v)))
+#define udiv_qrnnd(q, r, n1, n0, d) \
+  __asm__ ("! Inlined udiv_qrnnd\n"					\
+"	wr	%%g0,%2,%%y	! Not a delayed write for sparclite\n"	\
+"	tst	%%g0\n"							\
+"	divscc	%3,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%%g1\n"						\
+"	divscc	%%g1,%4,%0\n"						\
+"	rd	%%y,%1\n"						\
+"	bl,a 1f\n"							\
+"	add	%1,%4,%1\n"						\
+"1:	! End of inline udiv_qrnnd"					\
+	   : "=r" ((USItype) (q)),					\
+	     "=r" ((USItype) (r))					\
+	   : "r" ((USItype) (n1)),					\
+	     "r" ((USItype) (n0)),					\
+	     "rI" ((USItype) (d))					\
+	   : "g1" __AND_CLOBBER_CC)
+#define UDIV_TIME 37
+#define count_leading_zeros(count, x) \
+  do {                                                                  \
+  __asm__ ("scan %1,1,%0"                                               \
+           : "=r" ((USItype) (count))                                   \
+           : "r" ((USItype) (x)));					\
+  } while (0)
+/* Early sparclites return 63 for an argument of 0, but they warn that future
+   implementations might change this.  Therefore, leave COUNT_LEADING_ZEROS_0
+   undefined.  */
+#else
+/* SPARC without integer multiplication and divide instructions.
+   (i.e. at least Sun4/20,40,60,65,75,110,260,280,330,360,380,470,490) */
+#define umul_ppmm(w1, w0, u, v) \
+  __asm__ ("! Inlined umul_ppmm\n"					\
+"	wr	%%g0,%2,%%y	! SPARC has 0-3 delay insn after a wr\n"\
+"	sra	%3,31,%%o5	! Don't move this insn\n"		\
+"	and	%2,%%o5,%%o5	! Don't move this insn\n"		\
+"	andcc	%%g0,0,%%g1	! Don't move this insn\n"		\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,%3,%%g1\n"						\
+"	mulscc	%%g1,0,%%g1\n"						\
+"	add	%%g1,%%o5,%0\n"						\
+"	rd	%%y,%1"							\
+	   : "=r" ((USItype) (w1)),					\
+	     "=r" ((USItype) (w0))					\
+	   : "%rI" ((USItype) (u)),					\
+	     "r" ((USItype) (v))						\
+	   : "g1", "o5" __AND_CLOBBER_CC)
+#define UMUL_TIME 39		/* 39 instructions */
+/* It's quite necessary to add this much assembler for the sparc.
+   The default udiv_qrnnd (in C) is more than 10 times slower!  */
+#define udiv_qrnnd(__q, __r, __n1, __n0, __d) \
+  __asm__ ("! Inlined udiv_qrnnd\n"					\
+"	mov	32,%%g1\n"						\
+"	subcc	%1,%2,%%g0\n"						\
+"1:	bcs	5f\n"							\
+"	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb\n"	\
+"	sub	%1,%2,%1	! this kills msb of n\n"		\
+"	addx	%1,%1,%1	! so this can't give carry\n"		\
+"	subcc	%%g1,1,%%g1\n"						\
+"2:	bne	1b\n"							\
+"	 subcc	%1,%2,%%g0\n"						\
+"	bcs	3f\n"							\
+"	 addxcc %0,%0,%0	! shift n1n0 and a q-bit in lsb\n"	\
+"	b	3f\n"							\
+"	 sub	%1,%2,%1	! this kills msb of n\n"		\
+"4:	sub	%1,%2,%1\n"						\
+"5:	addxcc	%1,%1,%1\n"						\
+"	bcc	2b\n"							\
+"	 subcc	%%g1,1,%%g1\n"						\
+"! Got carry from n.  Subtract next step to cancel this carry.\n"	\
+"	bne	4b\n"							\
+"	 addcc	%0,%0,%0	! shift n1n0 and a 0-bit in lsb\n"	\
+"	sub	%1,%2,%1\n"						\
+"3:	xnor	%0,0,%0\n"						\
+"	! End of inline udiv_qrnnd"					\
+	   : "=&r" ((USItype) (__q)),					\
+	     "=&r" ((USItype) (__r))					\
+	   : "r" ((USItype) (__d)),					\
+	     "1" ((USItype) (__n1)),					\
+	     "0" ((USItype) (__n0)) : "g1" __AND_CLOBBER_CC)
+#define UDIV_TIME (3+7*32)	/* 7 instructions/iteration. 32 iterations.  */
+#endif /* __sparclite__ */
+#endif /* __sparc_v8__ */
+#endif /* sparc32 */
+
+#if ((defined (__sparc__) && defined (__arch64__)) || defined (__sparcv9)) \
+    && W_TYPE_SIZE == 64
+#define add_ssaaaa(sh, sl, ah, al, bh, bl)				\
+  __asm__ ("addcc %r4,%5,%1\n\t"					\
+   	   "add %r2,%3,%0\n\t"						\
+   	   "bcs,a,pn %%xcc, 1f\n\t"					\
+   	   "add %0, 1, %0\n"						\
+	   "1:"								\
+	   : "=r" ((UDItype)(sh)),				      	\
+	     "=&r" ((UDItype)(sl))				      	\
+	   : "%rJ" ((UDItype)(ah)),				     	\
+	     "rI" ((UDItype)(bh)),				      	\
+	     "%rJ" ((UDItype)(al)),				     	\
+	     "rI" ((UDItype)(bl))				       	\
+	   __CLOBBER_CC)
+
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) 				\
+  __asm__ ("subcc %r4,%5,%1\n\t"					\
+   	   "sub %r2,%3,%0\n\t"						\
+   	   "bcs,a,pn %%xcc, 1f\n\t"					\
+   	   "sub %0, 1, %0\n\t"						\
+	   "1:"								\
+	   : "=r" ((UDItype)(sh)),				      	\
+	     "=&r" ((UDItype)(sl))				      	\
+	   : "rJ" ((UDItype)(ah)),				     	\
+	     "rI" ((UDItype)(bh)),				      	\
+	     "rJ" ((UDItype)(al)),				     	\
+	     "rI" ((UDItype)(bl))				       	\
+	   __CLOBBER_CC)
+
+#define umul_ppmm(wh, wl, u, v)						\
+  do {									\
+	  UDItype tmp1, tmp2, tmp3, tmp4;				\
+	  __asm__ __volatile__ (					\
+		   "srl %7,0,%3\n\t"					\
+		   "mulx %3,%6,%1\n\t"					\
+		   "srlx %6,32,%2\n\t"					\
+		   "mulx %2,%3,%4\n\t"					\
+		   "sllx %4,32,%5\n\t"					\
+		   "srl %6,0,%3\n\t"					\
+		   "sub %1,%5,%5\n\t"					\
+		   "srlx %5,32,%5\n\t"					\
+		   "addcc %4,%5,%4\n\t"					\
+		   "srlx %7,32,%5\n\t"					\
+		   "mulx %3,%5,%3\n\t"					\
+		   "mulx %2,%5,%5\n\t"					\
+		   "sethi %%hi(0x80000000),%2\n\t"			\
+		   "addcc %4,%3,%4\n\t"					\
+		   "srlx %4,32,%4\n\t"					\
+		   "add %2,%2,%2\n\t"					\
+		   "movcc %%xcc,%%g0,%2\n\t"				\
+		   "addcc %5,%4,%5\n\t"					\
+		   "sllx %3,32,%3\n\t"					\
+		   "add %1,%3,%1\n\t"					\
+		   "add %5,%2,%0"					\
+	   : "=r" ((UDItype)(wh)),					\
+	     "=&r" ((UDItype)(wl)),					\
+	     "=&r" (tmp1), "=&r" (tmp2), "=&r" (tmp3), "=&r" (tmp4)	\
+	   : "r" ((UDItype)(u)),					\
+	     "r" ((UDItype)(v))						\
+	   __CLOBBER_CC);						\
+  } while (0)
+#define UMUL_TIME 96
+#define UDIV_TIME 230
+#endif /* sparc64 */
+
+#if defined (__vax__) && W_TYPE_SIZE == 32
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("addl2 %5,%1\n\tadwc %3,%0"					\
+	   : "=g" ((USItype) (sh)),					\
+	     "=&g" ((USItype) (sl))					\
+	   : "%0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "%1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("subl2 %5,%1\n\tsbwc %3,%0"					\
+	   : "=g" ((USItype) (sh)),					\
+	     "=&g" ((USItype) (sl))					\
+	   : "0" ((USItype) (ah)),					\
+	     "g" ((USItype) (bh)),					\
+	     "1" ((USItype) (al)),					\
+	     "g" ((USItype) (bl)))
+#define umul_ppmm(xh, xl, m0, m1) \
+  do {									\
+    union {								\
+	UDItype __ll;							\
+	struct {USItype __l, __h;} __i;					\
+      } __xx;								\
+    USItype __m0 = (m0), __m1 = (m1);					\
+    __asm__ ("emul %1,%2,$0,%0"						\
+	     : "=r" (__xx.__ll)						\
+	     : "g" (__m0),						\
+	       "g" (__m1));						\
+    (xh) = __xx.__i.__h;						\
+    (xl) = __xx.__i.__l;						\
+    (xh) += ((((SItype) __m0 >> 31) & __m1)				\
+	     + (((SItype) __m1 >> 31) & __m0));				\
+  } while (0)
+#define sdiv_qrnnd(q, r, n1, n0, d) \
+  do {									\
+    union {DItype __ll;							\
+	   struct {SItype __l, __h;} __i;				\
+	  } __xx;							\
+    __xx.__i.__h = n1; __xx.__i.__l = n0;				\
+    __asm__ ("ediv %3,%2,%0,%1"						\
+	     : "=g" (q), "=g" (r)					\
+	     : "g" (__xx.__ll), "g" (d));				\
+  } while (0)
+#endif /* __vax__ */
+
+#if defined (__z8000__) && W_TYPE_SIZE == 16
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  __asm__ ("add	%H1,%H5\n\tadc	%H0,%H3"				\
+	   : "=r" ((unsigned int)(sh)),					\
+	     "=&r" ((unsigned int)(sl))					\
+	   : "%0" ((unsigned int)(ah)),					\
+	     "r" ((unsigned int)(bh)),					\
+	     "%1" ((unsigned int)(al)),					\
+	     "rQR" ((unsigned int)(bl)))
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  __asm__ ("sub	%H1,%H5\n\tsbc	%H0,%H3"				\
+	   : "=r" ((unsigned int)(sh)),					\
+	     "=&r" ((unsigned int)(sl))					\
+	   : "0" ((unsigned int)(ah)),					\
+	     "r" ((unsigned int)(bh)),					\
+	     "1" ((unsigned int)(al)),					\
+	     "rQR" ((unsigned int)(bl)))
+#define umul_ppmm(xh, xl, m0, m1) \
+  do {									\
+    union {long int __ll;						\
+	   struct {unsigned int __h, __l;} __i;				\
+	  } __xx;							\
+    unsigned int __m0 = (m0), __m1 = (m1);				\
+    __asm__ ("mult	%S0,%H3"					\
+	     : "=r" (__xx.__i.__h),					\
+	       "=r" (__xx.__i.__l)					\
+	     : "%1" (__m0),						\
+	       "rQR" (__m1));						\
+    (xh) = __xx.__i.__h; (xl) = __xx.__i.__l;				\
+    (xh) += ((((signed int) __m0 >> 15) & __m1)				\
+	     + (((signed int) __m1 >> 15) & __m0));			\
+  } while (0)
+#endif /* __z8000__ */
+
+#endif /* __GNUC__ */
+
+/* If this machine has no inline assembler, use C macros.  */
+
+#if !defined (add_ssaaaa)
+#define add_ssaaaa(sh, sl, ah, al, bh, bl) \
+  do {									\
+    UWtype __x;								\
+    __x = (al) + (bl);							\
+    (sh) = (ah) + (bh) + (__x < (al));					\
+    (sl) = __x;								\
+  } while (0)
+#endif
+
+#if !defined (sub_ddmmss)
+#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
+  do {									\
+    UWtype __x;								\
+    __x = (al) - (bl);							\
+    (sh) = (ah) - (bh) - (__x > (al));					\
+    (sl) = __x;								\
+  } while (0)
+#endif
+
+/* If we lack umul_ppmm but have smul_ppmm, define umul_ppmm in terms of
+   smul_ppmm.  */
+#if !defined (umul_ppmm) && defined (smul_ppmm)
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    UWtype __w1;							\
+    UWtype __xm0 = (u), __xm1 = (v);					\
+    smul_ppmm (__w1, w0, __xm0, __xm1);					\
+    (w1) = __w1 + (-(__xm0 >> (W_TYPE_SIZE - 1)) & __xm1)		\
+		+ (-(__xm1 >> (W_TYPE_SIZE - 1)) & __xm0);		\
+  } while (0)
+#endif
+
+/* If we still don't have umul_ppmm, define it using plain C.  */
+#if !defined (umul_ppmm)
+#define umul_ppmm(w1, w0, u, v)						\
+  do {									\
+    UWtype __x0, __x1, __x2, __x3;					\
+    UHWtype __ul, __vl, __uh, __vh;					\
+									\
+    __ul = __ll_lowpart (u);						\
+    __uh = __ll_highpart (u);						\
+    __vl = __ll_lowpart (v);						\
+    __vh = __ll_highpart (v);						\
+									\
+    __x0 = (UWtype) __ul * __vl;					\
+    __x1 = (UWtype) __ul * __vh;					\
+    __x2 = (UWtype) __uh * __vl;					\
+    __x3 = (UWtype) __uh * __vh;					\
+									\
+    __x1 += __ll_highpart (__x0);/* this can't give carry */		\
+    __x1 += __x2;		/* but this indeed can */		\
+    if (__x1 < __x2)		/* did we get it? */			\
+      __x3 += __ll_B;		/* yes, add it in the proper pos.  */	\
+									\
+    (w1) = __x3 + __ll_highpart (__x1);					\
+    (w0) = __ll_lowpart (__x1) * __ll_B + __ll_lowpart (__x0);		\
+  } while (0)
+#endif
+
+#if !defined (__umulsidi3)
+#define __umulsidi3(u, v) \
+  ({DWunion __w;							\
+    umul_ppmm (__w.s.high, __w.s.low, u, v);				\
+    __w.ll; })
+#endif
+
+/* Define this unconditionally, so it can be used for debugging.  */
+#define __udiv_qrnnd_c(q, r, n1, n0, d) \
+  do {									\
+    UWtype __d1, __d0, __q1, __q0;					\
+    UWtype __r1, __r0, __m;						\
+    __d1 = __ll_highpart (d);						\
+    __d0 = __ll_lowpart (d);						\
+									\
+    __r1 = (n1) % __d1;							\
+    __q1 = (n1) / __d1;							\
+    __m = (UWtype) __q1 * __d0;						\
+    __r1 = __r1 * __ll_B | __ll_highpart (n0);				\
+    if (__r1 < __m)							\
+      {									\
+	__q1--, __r1 += (d);						\
+	if (__r1 >= (d)) /* i.e. we didn't get carry when adding to __r1 */\
+	  if (__r1 < __m)						\
+	    __q1--, __r1 += (d);					\
+      }									\
+    __r1 -= __m;							\
+									\
+    __r0 = __r1 % __d1;							\
+    __q0 = __r1 / __d1;							\
+    __m = (UWtype) __q0 * __d0;						\
+    __r0 = __r0 * __ll_B | __ll_lowpart (n0);				\
+    if (__r0 < __m)							\
+      {									\
+	__q0--, __r0 += (d);						\
+	if (__r0 >= (d))						\
+	  if (__r0 < __m)						\
+	    __q0--, __r0 += (d);					\
+      }									\
+    __r0 -= __m;							\
+									\
+    (q) = (UWtype) __q1 * __ll_B | __q0;				\
+    (r) = __r0;								\
+  } while (0)
+
+/* If the processor has no udiv_qrnnd but sdiv_qrnnd, go through
+   __udiv_w_sdiv (defined in libgcc or elsewhere).  */
+#if !defined (udiv_qrnnd) && defined (sdiv_qrnnd)
+#define udiv_qrnnd(q, r, nh, nl, d) \
+  do {									\
+    USItype __r;							\
+    (q) = __udiv_w_sdiv (&__r, nh, nl, d);				\
+    (r) = __r;								\
+  } while (0)
+#endif
+
+/* If udiv_qrnnd was not defined for this processor, use __udiv_qrnnd_c.  */
+#if !defined (udiv_qrnnd)
+#define UDIV_NEEDS_NORMALIZATION 1
+#define udiv_qrnnd __udiv_qrnnd_c
+#endif
+
+#if !defined (count_leading_zeros)
+extern const UQItype __clz_tab[];
+#define count_leading_zeros(count, x) \
+  do {									\
+    UWtype __xr = (x);							\
+    UWtype __a;								\
+									\
+    if (W_TYPE_SIZE <= 32)						\
+      {									\
+	__a = __xr < ((UWtype)1<<2*__BITS4)				\
+	  ? (__xr < ((UWtype)1<<__BITS4) ? 0 : __BITS4)			\
+	  : (__xr < ((UWtype)1<<3*__BITS4) ?  2*__BITS4 : 3*__BITS4);	\
+      }									\
+    else								\
+      {									\
+	for (__a = W_TYPE_SIZE - 8; __a > 0; __a -= 8)			\
+	  if (((__xr >> __a) & 0xff) != 0)				\
+	    break;							\
+      }									\
+									\
+    (count) = W_TYPE_SIZE - (__clz_tab[__xr >> __a] + __a);		\
+  } while (0)
+#define COUNT_LEADING_ZEROS_0 W_TYPE_SIZE
+#endif
+
+#if !defined (count_trailing_zeros)
+/* Define count_trailing_zeros using count_leading_zeros.  The latter might be
+   defined in asm, but if it is not, the C version above is good enough.  */
+#define count_trailing_zeros(count, x) \
+  do {									\
+    UWtype __ctz_x = (x);						\
+    UWtype __ctz_c;							\
+    count_leading_zeros (__ctz_c, __ctz_x & -__ctz_x);			\
+    (count) = W_TYPE_SIZE - 1 - __ctz_c;				\
+  } while (0)
+#endif
+
+#ifndef UDIV_NEEDS_NORMALIZATION
+#define UDIV_NEEDS_NORMALIZATION 0
+#endif
diff --git a/arch/mips/lib/udivdi3.c b/arch/mips/lib/udivdi3.c
new file mode 100644
index 0000000..828fc20
--- /dev/null
+++ b/arch/mips/lib/udivdi3.c
@@ -0,0 +1,266 @@
+/* More subroutines needed by GCC output code on some machines.  */
+/* Compile this one with gcc.  */
+/* Copyright (C) 1989, 92-98, 1999 Free Software Foundation, Inc.
+
+This file is part of GNU CC.
+
+GNU CC is free software; you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation; either version 2, or (at your option)
+any later version.
+
+GNU CC is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with GNU CC; see the file COPYING.  If not, write to
+the Free Software Foundation, 59 Temple Place - Suite 330,
+Boston, MA 02111-1307, USA.  */
+
+/* As a special exception, if you link this library with other files,
+   some of which are compiled with GCC, to produce an executable,
+   this library does not by itself cause the resulting executable
+   to be covered by the GNU General Public License.
+   This exception does not however invalidate any other reasons why
+   the executable file might be covered by the GNU General Public License.
+ */
+/* support functions required by the kernel. based on code from gcc-2.95.3 */
+/* I Molton     29/07/01 */
+
+#include <linux/module.h>
+
+#define BITS_PER_UNIT  8
+#define SI_TYPE_SIZE (sizeof (SItype) * BITS_PER_UNIT)
+
+typedef unsigned int UQItype    __attribute__ ((mode (QI)));
+typedef          int SItype     __attribute__ ((mode (SI)));
+typedef unsigned int USItype    __attribute__ ((mode (SI)));
+typedef          int DItype     __attribute__ ((mode (DI)));
+typedef          int word_type 	__attribute__ ((mode (__word__)));
+typedef unsigned int UDItype    __attribute__ ((mode (DI)));
+
+#ifdef CONFIG_CPU_LITTLE_ENDIAN
+  struct DIstruct {USItype low; SItype high;};
+#else
+  struct DIstruct {SItype high; USItype low;};
+#endif
+
+typedef union
+{
+  struct DIstruct s;
+  DItype ll;
+} DIunion;
+
+#include "longlong.h"
+
+const UQItype __clz_tab[] =
+{
+  0,1,2,2,3,3,3,3,4,4,4,4,4,4,4,4,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,
+  6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,6,
+  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
+  7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,
+  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+  8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,8,
+};
+
+UDItype
+__udivmoddi4 (UDItype n, UDItype d, UDItype *rp)
+{
+  DIunion ww;
+  DIunion nn, dd;
+  DIunion rr;
+  USItype d0, d1, n0, n1, n2;
+  USItype q0, q1;
+  USItype b, bm;
+
+  nn.ll = n;
+  dd.ll = d;
+
+  d0 = dd.s.low;
+  d1 = dd.s.high;
+  n0 = nn.s.low;
+  n1 = nn.s.high;
+
+  if (d1 == 0)
+    {
+      if (d0 > n1)
+        {
+          /* 0q = nn / 0D */
+
+          count_leading_zeros (bm, d0);
+
+          if (bm != 0)
+            {
+              /* Normalize, i.e. make the most significant bit of the
+                 denominator set.  */
+
+              d0 = d0 << bm;
+              n1 = (n1 << bm) | (n0 >> (SI_TYPE_SIZE - bm));
+              n0 = n0 << bm;
+            }
+
+          udiv_qrnnd (q0, n0, n1, n0, d0);
+          q1 = 0;
+
+          /* Remainder in n0 >> bm.  */
+        }
+      else
+        {
+          /* qq = NN / 0d */
+
+          if (d0 == 0)
+            d0 = 1 / d0;        /* Divide intentionally by zero.  */
+
+          count_leading_zeros (bm, d0);
+
+          if (bm == 0)
+            {
+              /* From (n1 >= d0) /\ (the most significant bit of d0 is set),
+                 conclude (the most significant bit of n1 is set) /\ (the
+                 leading quotient digit q1 = 1).
+
+                 This special case is necessary, not an optimization.
+                 (Shifts counts of SI_TYPE_SIZE are undefined.)  */
+
+              n1 -= d0;
+              q1 = 1;
+            }
+          else
+            {
+              /* Normalize.  */
+
+              b = SI_TYPE_SIZE - bm;
+
+              d0 = d0 << bm;
+              n2 = n1 >> b;
+              n1 = (n1 << bm) | (n0 >> b);
+              n0 = n0 << bm;
+
+              udiv_qrnnd (q1, n1, n2, n1, d0);
+            }
+
+          /* n1 != d0...  */
+
+          udiv_qrnnd (q0, n0, n1, n0, d0);
+
+          /* Remainder in n0 >> bm.  */
+        }
+
+      if (rp != 0)
+        {
+          rr.s.low = n0 >> bm;
+          rr.s.high = 0;
+          *rp = rr.ll;
+        }
+    }
+  else
+    {
+      if (d1 > n1)
+        {
+          /* 00 = nn / DD */
+
+          q0 = 0;
+          q1 = 0;
+
+          /* Remainder in n1n0.  */
+          if (rp != 0)
+            {
+              rr.s.low = n0;
+              rr.s.high = n1;
+              *rp = rr.ll;
+            }
+        }
+      else
+        {
+          /* 0q = NN / dd */
+
+          count_leading_zeros (bm, d1);
+          if (bm == 0)
+            {
+              /* From (n1 >= d1) /\ (the most significant bit of d1 is set),
+                 conclude (the most significant bit of n1 is set) /\ (the
+                 quotient digit q0 = 0 or 1).
+
+                 This special case is necessary, not an optimization.  */
+
+              /* The condition on the next line takes advantage of that
+                 n1 >= d1 (true due to program flow).  */
+              if (n1 > d1 || n0 >= d0)
+                {
+                  q0 = 1;
+                  sub_ddmmss (n1, n0, n1, n0, d1, d0);
+                }
+              else
+                q0 = 0;
+
+              q1 = 0;
+
+              if (rp != 0)
+                {
+                  rr.s.low = n0;
+                  rr.s.high = n1;
+                  *rp = rr.ll;
+                }
+            }
+          else
+            {
+              USItype m1, m0;
+              /* Normalize.  */
+
+              b = SI_TYPE_SIZE - bm;
+
+              d1 = (d1 << bm) | (d0 >> b);
+              d0 = d0 << bm;
+              n2 = n1 >> b;
+              n1 = (n1 << bm) | (n0 >> b);
+              n0 = n0 << bm;
+
+              udiv_qrnnd (q0, n1, n2, n1, d1);
+              umul_ppmm (m1, m0, q0, d0);
+
+              if (m1 > n1 || (m1 == n1 && m0 > n0))
+                {
+                  q0--;
+                  sub_ddmmss (m1, m0, m1, m0, d1, d0);
+                }
+
+              q1 = 0;
+
+              /* Remainder in (n1n0 - m1m0) >> bm.  */
+              if (rp != 0)
+                {
+                  sub_ddmmss (n1, n0, n1, n0, m1, m0);
+                  rr.s.low = (n1 << b) | (n0 >> bm);
+                  rr.s.high = n1 >> bm;
+                  *rp = rr.ll;
+                }
+            }
+        }
+    }
+
+  ww.s.low = q0;
+  ww.s.high = q1;
+  return ww.ll;
+}
+
+UDItype
+__udivdi3 (UDItype n, UDItype d)
+{
+  return __udivmoddi4 (n, d, (UDItype *) 0);
+}
+EXPORT_SYMBOL(__udivdi3);
+
+UDItype
+__umoddi3 (UDItype u, UDItype v)
+{
+  UDItype w;
+
+  (void) __udivmoddi4 (u ,v, &w);
+
+  return w;
+}
+
diff --git a/arch/mips/mm/Makefile b/arch/mips/mm/Makefile
index b4c64bd..8ca9a06 100644
--- a/arch/mips/mm/Makefile
+++ b/arch/mips/mm/Makefile
@@ -17,7 +17,11 @@
 obj-$(CONFIG_HIGHMEM)		+= highmem.o
 obj-$(CONFIG_HUGETLB_PAGE)	+= hugetlbpage.o
 
+ifeq ($(CONFIG_BRCMSTB),y)
+obj-y				+= c-brcmstb.o cex-gen.o tlb-r4k.o
+else
 obj-$(CONFIG_CPU_R4K_CACHE_TLB) += c-r4k.o cex-gen.o tlb-r4k.o
+endif
 obj-$(CONFIG_CPU_R3000)		+= c-r3k.o tlb-r3k.o
 obj-$(CONFIG_CPU_R8000)		+= c-r4k.o cex-gen.o tlb-r8k.o
 obj-$(CONFIG_CPU_SB1)		+= c-r4k.o cerr-sb1.o cex-sb1.o tlb-r4k.o
diff --git a/arch/mips/mm/c-brcmstb.c b/arch/mips/mm/c-brcmstb.c
new file mode 100644
index 0000000..0686bda
--- /dev/null
+++ b/arch/mips/mm/c-brcmstb.c
@@ -0,0 +1,496 @@
+/*
+ * Copyright (C) 2009 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/pfn.h>
+#include <linux/bitops.h>
+#include <linux/module.h>
+#include <linux/seq_file.h>
+#include <linux/highmem.h>
+
+#include <asm/barrier.h>
+#include <asm/bcache.h>
+#include <asm/bootinfo.h>
+#include <asm/cache.h>
+#include <asm/cacheops.h>
+#include <asm/cpu.h>
+#include <asm/cpu-features.h>
+#include <asm/io.h>
+#include <asm/page.h>
+#include <asm/pgtable.h>
+#include <asm/r4kcache.h>
+#include <asm/mmu_context.h>
+#include <asm/war.h>
+#include <asm/cacheflush.h>
+#include <linux/brcmstb/brcmstb.h>
+#include <dma-coherence.h>
+
+/*
+ * R4K-style cache flush functions
+ *
+ * BMIPS5000 uses an optimized implementation from this file
+ * Everything uses uses a mostly-stock c-r4k.c
+ */
+
+#if !defined(CONFIG_CPU_BMIPS5000)
+#include "c-r4k.c"
+#else /* !defined(CONFIG_CPU_BMIPS5000) */
+
+static unsigned long icache_size __read_mostly;
+static unsigned long dcache_size __read_mostly;
+static unsigned long scache_size __read_mostly;
+
+/*
+ * Dummy cache handling routines for machines without boardcaches
+ */
+static void cache_noop(void) {}
+
+static struct bcache_ops no_sc_ops = {
+	.bc_enable = (void *)cache_noop,
+	.bc_disable = (void *)cache_noop,
+	.bc_wback_inv = (void *)cache_noop,
+	.bc_inv = (void *)cache_noop,
+};
+
+struct bcache_ops *bcops = &no_sc_ops;
+
+static void (* r4k_blast_dcache_page)(unsigned long addr);
+static void (* r4k_blast_dcache_page_indexed)(unsigned long addr);
+static void (* r4k_blast_icache_page)(unsigned long addr);
+static void (* r4k_blast_icache_page_indexed)(unsigned long addr);
+static void (* r4k_blast_scache_page)(unsigned long addr);
+static void (* r4k_blast_scache_page_indexed)(unsigned long addr);
+static void (* r4k_blast_scache)(void);
+
+void (* r4k_blast_dcache)(void);
+EXPORT_SYMBOL(r4k_blast_dcache);
+
+void (* r4k_blast_icache)(void);
+EXPORT_SYMBOL(r4k_blast_icache);
+
+static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
+{
+	blast_dcache32_page(addr);
+}
+
+static void r4k___flush_cache_all(void)
+{
+	/* L2 flush implicitly flushes L1 */
+	r4k_blast_scache();
+	__sync();
+}
+
+static void r4k_noop(void)
+{
+}
+
+static void r4k_instruction_hazard(void)
+{
+	__sync();
+	__sync();
+	__asm__ __volatile__(
+	"	nop; nop; nop; nop; nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop; nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop; nop; nop; nop; nop\n"
+	"	nop; nop; nop; nop; nop; nop; nop; nop\n"
+	: : : "memory");
+}
+
+static void r4k_dma_cache_wback_inv(unsigned long addr, unsigned long size)
+{
+	/* Catch bad driver code */
+	BUG_ON(size == 0);
+
+	/* L2 flush implicitly flushes L1 */
+	if (size >= scache_size)
+		r4k_blast_scache();
+	else
+		bc_wback_inv(addr, size);
+
+	__sync();
+}
+
+static char *way_string[] = { NULL, "direct mapped", "2-way",
+	"3-way", "4-way", "5-way", "6-way", "7-way", "8-way"
+};
+
+static void probe_pcache(void)
+{
+	struct cpuinfo_mips *c = &current_cpu_data;
+	unsigned int config = read_c0_config();
+	unsigned long config1;
+	unsigned int lsize;
+
+	switch (c->cputype) {
+	default:
+		if (!(config & MIPS_CONF_M))
+			panic("Don't know how to probe P-caches on this cpu.");
+
+		/*
+		 * So we seem to be a MIPS32 or MIPS64 CPU
+		 * So let's probe the I-cache ...
+		 */
+		config1 = read_c0_config1();
+
+		if ((lsize = ((config1 >> 19) & 7)))
+			c->icache.linesz = 2 << lsize;
+		else
+			c->icache.linesz = lsize;
+		c->icache.sets = 64 << ((config1 >> 22) & 7);
+		c->icache.ways = 1 + ((config1 >> 16) & 7);
+
+		icache_size = c->icache.sets *
+		              c->icache.ways *
+		              c->icache.linesz;
+		c->icache.waybit = __ffs(icache_size/c->icache.ways);
+
+		if (config & 0x8)		/* VI bit */
+			c->icache.flags |= MIPS_CACHE_VTAG;
+
+		/*
+		 * Now probe the MIPS32 / MIPS64 data cache.
+		 */
+		c->dcache.flags = 0;
+
+		if ((lsize = ((config1 >> 10) & 7)))
+			c->dcache.linesz = 2 << lsize;
+		else
+			c->dcache.linesz= lsize;
+		c->dcache.sets = 64 << ((config1 >> 13) & 7);
+		c->dcache.ways = 1 + ((config1 >> 7) & 7);
+
+		dcache_size = c->dcache.sets *
+		              c->dcache.ways *
+		              c->dcache.linesz;
+		c->dcache.waybit = __ffs(dcache_size/c->dcache.ways);
+
+		c->options |= MIPS_CPU_PREFETCH;
+		break;
+	}
+
+	/* compute a couple of other cache variables */
+	c->icache.waysize = icache_size / c->icache.ways;
+	c->dcache.waysize = dcache_size / c->dcache.ways;
+
+	c->icache.sets = c->icache.linesz ?
+		icache_size / (c->icache.linesz * c->icache.ways) : 0;
+	c->dcache.sets = c->dcache.linesz ?
+		dcache_size / (c->dcache.linesz * c->dcache.ways) : 0;
+
+	printk("Primary instruction cache %ldkB, %s, %s, linesize %d bytes.\n",
+	       icache_size >> 10,
+	       cpu_has_vtag_icache ? "virtually tagged" : "physically tagged",
+	       way_string[c->icache.ways], c->icache.linesz);
+
+	printk("Primary data cache %ldkB, %s, linesize %d bytes.\n",
+	       dcache_size >> 10, way_string[c->dcache.ways], c->dcache.linesz);
+}
+
+extern int mips_sc_init(void);
+
+static void setup_scache(void)
+{
+	struct cpuinfo_mips *c = &current_cpu_data;
+
+	if (mips_sc_init ()) {
+		scache_size = c->scache.ways * c->scache.sets * c->scache.linesz;
+		printk("MIPS secondary cache %ldkB, %s, linesize %d bytes.\n",
+		       scache_size >> 10,
+		       way_string[c->scache.ways], c->scache.linesz);
+	} else {
+		panic("c-r4k cache functions require L2 enabled");
+	}
+	return;
+}
+
+static int cca = -1;
+
+static int __init cca_setup(char *str)
+{
+	get_option(&str, &cca);
+
+	return 1;
+}
+
+__setup("cca=", cca_setup);
+
+static void coherency_setup(void)
+{
+	if (cca < 0 || cca > 7)
+		cca = read_c0_config() & CONF_CM_CMASK;
+	_page_cachable_default = cca << _CACHE_SHIFT;
+
+	pr_debug("Using cache attribute %d\n", cca);
+	change_c0_config(CONF_CM_CMASK, cca);
+}
+
+void r4k_cache_init(void)
+{
+	extern void build_clear_page(void);
+	extern void build_copy_page(void);
+	extern char except_vec2_generic;
+
+	/* Default cache error handler for R4000 and R5000 family */
+	set_uncached_handler (0x100, &except_vec2_generic, 0x80);
+
+	probe_pcache();
+	setup_scache();
+
+	BUG_ON(cpu_icache_line_size() != 64);
+	BUG_ON(cpu_dcache_line_size() != 32);
+	BUG_ON(cpu_scache_line_size() != 128);
+
+	r4k_blast_dcache_page = r4k_blast_dcache_page_dc32;
+	r4k_blast_dcache_page_indexed = blast_dcache32_page_indexed;
+	r4k_blast_dcache = blast_dcache32;
+	r4k_blast_icache_page = blast_icache64_page;
+	r4k_blast_icache_page_indexed = blast_icache64_page_indexed;
+	r4k_blast_icache = blast_icache64;
+	r4k_blast_scache_page = blast_scache128_page;
+	r4k_blast_scache_page_indexed = blast_scache128_page_indexed;
+	r4k_blast_scache = blast_scache128;
+
+	/* SWLINUX-2630: align to the way size (8KB) on Zephyr */
+	shm_align_mask = max_t(unsigned long,
+			       current_cpu_data.dcache.waysize, PAGE_SIZE) - 1;
+
+	__flush_cache_vmap	= r4k___flush_cache_all;
+	__flush_cache_vunmap	= r4k___flush_cache_all;
+
+	flush_cache_all		= (void *)r4k_noop;
+	__flush_cache_all	= r4k___flush_cache_all;
+	flush_cache_mm		= (void *)r4k_noop;
+	flush_cache_page	= (void *)r4k_instruction_hazard;
+	flush_cache_range	= (void *)r4k_instruction_hazard;
+
+	flush_cache_sigtramp	= (void *)r4k_noop;
+	flush_icache_all	= (void *)r4k_noop;
+	local_flush_data_cache_page	= (void *)r4k_instruction_hazard;
+	flush_data_cache_page	= (void *)r4k_instruction_hazard;
+	flush_icache_range	= (void *)r4k_instruction_hazard;
+	local_flush_icache_range	= (void *)r4k_instruction_hazard;
+
+	_dma_cache_wback_inv	= r4k_dma_cache_wback_inv;
+	_dma_cache_wback	= r4k_dma_cache_wback_inv;
+	_dma_cache_inv		= r4k_dma_cache_wback_inv;
+
+	build_clear_page();
+	build_copy_page();
+	r4k___flush_cache_all();
+	coherency_setup();
+}
+
+#endif /* !defined(CONFIG_CPU_BMIPS5000) */
+
+/*
+ * Fine-grained cacheflush() syscall for usermode Nexus
+ */
+int brcm_cacheflush(unsigned long addr, unsigned long bytes,
+	unsigned int cache)
+{
+#if !defined(CONFIG_BRCM_ZSCM_L2)
+	/* partial RAC invalidate is not supported */
+	if (cache == RACACHE) {
+		brcm_inv_prefetch(0, 0);
+		return 0;
+	}
+#else
+	/*
+	 * SWLINUX-2607, BMIPS5000_5200-ES100-R: Flush JTB and CRS on
+	 * user-initiated invalidations, in case a JIT buffer with mixed
+	 * code+data is getting rewritten.  This helps prevent a possible
+	 * CPU hang from prefetching invalid instructions.
+	 */
+	write_c0_brcm_action(4 << 16); /* reset JTB this thread */
+	write_c0_brcm_action(5 << 16); /* reset JTB other thread */
+	write_c0_brcm_action(6 << 16); /* reset CRS this thread */
+	write_c0_brcm_action(7 << 16); /* reset CRS other thread */
+#endif
+	/* ICACHE/BCACHE is handled by the standard implementation */
+	if (cache & ICACHE) {
+		flush_icache_range(addr, addr + bytes);
+		return 0;
+	}
+
+	/* New DCACHE implementation flushes D$/L2 out to RAM for DMA */
+	if (cache & DCACHE) {
+		unsigned long pg = addr & PAGE_MASK, end = addr + bytes;
+
+		if (bytes == 0 || (bytes >= dcache_size)) {
+			preempt_disable();
+			r4k_blast_dcache();
+			r4k_blast_scache();
+			preempt_enable();
+			__sync();
+			return 0;
+		}
+
+		down_read(&current->mm->mmap_sem);
+		while (pg < end) {
+			pgd_t *pgdp = pgd_offset(current->mm, pg);
+			pud_t *pudp = pud_offset(pgdp, pg);
+			pmd_t *pmdp = pmd_offset(pudp, pg);
+			pte_t *ptep = pte_offset(pmdp, pg);
+
+			if (!(pte_val(*ptep) & _PAGE_PRESENT)) {
+				up_read(&current->mm->mmap_sem);
+				return -EFAULT;
+			}
+
+#if !defined(CONFIG_BRCM_ZSCM_L2)
+			r4k_blast_dcache_page(pg);
+#endif
+			r4k_blast_scache_page(pg);
+			pg += PAGE_SIZE;
+		}
+		up_read(&current->mm->mmap_sem);
+	}
+
+	if (cache & RACACHE)
+		brcm_inv_prefetch(addr, bytes);
+
+	__sync();
+	return 0;
+}
+EXPORT_SYMBOL(brcm_cacheflush);
+
+/*
+ * Flush RAC or prefetch lines after DMA from device
+ */
+void brcm_inv_prefetch(unsigned long addr, unsigned long size)
+{
+#if defined(CONFIG_CPU_BMIPS3300)
+	DEV_SET_RB(__BMIPS_GET_CBR() + BMIPS_RAC_CONFIG, 0x100);
+#elif defined(CONFIG_CPU_BMIPS4380)
+	DEV_SET_RB(__BMIPS_GET_CBR() + BMIPS_RAC_CONFIG, 0x100);
+#elif defined(CONFIG_BRCM_ZSCM_L2)
+	unsigned int linesz = cpu_scache_line_size();
+	unsigned long addr0 = addr, addr1;
+
+	BUG_ON(size == 0);
+
+	addr0 &= ~(linesz - 1);
+	addr1 = (addr0 + size - 1) & ~(linesz - 1);
+
+	protected_writeback_scache_line(addr0);
+	if (likely(addr1 != addr0))
+		protected_writeback_scache_line(addr1);
+	else
+		return;
+
+	addr0 += linesz;
+	if (likely(addr1 != addr0))
+		protected_writeback_scache_line(addr0);
+	else
+		return;
+
+	addr1 -= linesz;
+	if (likely(addr1 > addr0))
+		protected_writeback_scache_line(addr0);
+#endif
+}
+EXPORT_SYMBOL(brcm_inv_prefetch);
+
+/*
+ * Hooks for extra RAC/prefetch flush after DMA
+ */
+static inline void __brcm_sync(struct page *page,
+	unsigned long offset, size_t size, enum dma_data_direction direction)
+{
+	size_t left = size;
+
+	if (direction == DMA_TO_DEVICE)
+		return;
+
+	do {
+		size_t len = left;
+
+		if (PageHighMem(page)) {
+			void *addr;
+
+			if (offset + len > PAGE_SIZE) {
+				if (offset >= PAGE_SIZE) {
+					page += offset >> PAGE_SHIFT;
+					offset &= ~PAGE_MASK;
+				}
+				len = PAGE_SIZE - offset;
+			}
+
+			addr = kmap_atomic(page);
+			brcm_inv_prefetch((unsigned long)addr + offset, len);
+			kunmap_atomic(addr);
+		} else
+			brcm_inv_prefetch((unsigned long)page_address(page) +
+				offset, size);
+		offset = 0;
+		page++;
+		left -= len;
+	} while (left);
+}
+
+void plat_unmap_dma_mem(struct device *dev, dma_addr_t dma_addr,
+	size_t size, int dir)
+{
+	unsigned long pa = plat_dma_addr_to_phys(dev, dma_addr);
+	__brcm_sync(pfn_to_page(PFN_DOWN(pa)), pa & ~PAGE_MASK, size, dir);
+}
+
+static void brcm_dma_sync_single_for_cpu(struct device *dev,
+	dma_addr_t dma_handle, size_t size, enum dma_data_direction dir)
+{
+	unsigned long pa = plat_dma_addr_to_phys(dev, dma_handle);
+	__brcm_sync(pfn_to_page(PFN_DOWN(pa)), pa & ~PAGE_MASK, size, dir);
+}
+
+static void brcm_dma_sync_sg_for_cpu(struct device *dev,
+	struct scatterlist *sg, int nelems, enum dma_data_direction direction)
+{
+	int i;
+	for (i = 0; i < nelems; i++, sg++)
+		__brcm_sync(sg_page(sg), sg->offset, sg->length, direction);
+}
+
+static int __init brcm_setup_dma_ops(void)
+{
+	mips_dma_map_ops->sync_single_for_cpu = brcm_dma_sync_single_for_cpu;
+	mips_dma_map_ops->sync_sg_for_cpu = brcm_dma_sync_sg_for_cpu;
+	return 0;
+}
+core_initcall(brcm_setup_dma_ops);
+
+/*
+ * Provide cache details for PI/Nexus
+ */
+void brcm_get_cache_info(struct brcm_cache_info *info)
+{
+	info->max_writeback = cpu_scache_line_size() ? : cpu_dcache_line_size();
+	info->max_writethrough = 0;
+	info->prefetch_enabled = 0;
+
+#if defined(CONFIG_BRCM_ZSCM_L2)
+	/* chips with prefetching L2 */
+	info->prefetch_enabled = 1;
+#elif defined(CONFIG_CPU_BMIPS3300) || defined(CONFIG_CPU_BMIPS4380)
+	/* chips with write-through RAC */
+	info->max_writethrough = info->max_writeback * 4;
+	info->prefetch_enabled = 1;
+#endif
+}
+EXPORT_SYMBOL(brcm_get_cache_info);
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 5d3a25e..88d5980 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -639,7 +639,11 @@
 
 static void r4k_flush_data_cache_page(unsigned long addr)
 {
+#ifdef CONFIG_CPU_BMIPS4380
+	if (1) /* TP0/TP1 share the same D$ */
+#else
 	if (in_atomic())
+#endif
 		local_r4k_flush_data_cache_page((void *)addr);
 	else
 		r4k_on_each_cpu(local_r4k_flush_data_cache_page, (void *) addr);
diff --git a/arch/mips/mm/cache.c b/arch/mips/mm/cache.c
index e87bccd..45c6a36 100644
--- a/arch/mips/mm/cache.c
+++ b/arch/mips/mm/cache.c
@@ -21,6 +21,10 @@
 #include <asm/cpu.h>
 #include <asm/cpu-features.h>
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 /* Cache operations. */
 void (*flush_cache_all)(void);
 void (*__flush_cache_all)(void);
@@ -74,9 +78,13 @@
 	if (!access_ok(VERIFY_WRITE, (void __user *) addr, bytes))
 		return -EFAULT;
 
+#ifdef CONFIG_BRCMSTB
+	return brcm_cacheflush(addr, bytes, cache);
+#else
 	flush_icache_range(addr, addr + bytes);
 
 	return 0;
+#endif
 }
 
 void __flush_dcache_page(struct page *page)
diff --git a/arch/mips/mm/dma-default.c b/arch/mips/mm/dma-default.c
index 730d394..6369ffc 100644
--- a/arch/mips/mm/dma-default.c
+++ b/arch/mips/mm/dma-default.c
@@ -46,6 +46,10 @@
 early_param("nocoherentio", setnocoherentio);
 #endif
 
+#ifdef CONFIG_BRCMSTB
+#include <linux/brcmstb/brcmapi.h>
+#endif
+
 static inline struct page *dma_addr_to_page(struct device *dev,
 	dma_addr_t dma_addr)
 {
@@ -159,8 +163,16 @@
 	*dma_handle = plat_map_dma_mem(dev, ret, size);
 	if (!plat_device_is_coherent(dev)) {
 		dma_cache_wback_inv((unsigned long) ret, size);
+#ifdef CONFIG_BRCM_UPPER_768MB
+		if (brcm_map_coherent(*dma_handle, ret, PFN_ALIGN(size),
+				      &ret, gfp)) {
+			free_pages((unsigned long)ret, size);
+			ret = NULL;
+		}
+#else
 		if (!hw_coherentio)
 			ret = UNCAC_ADDR(ret);
+#endif
 	}
 
 	return ret;
@@ -188,8 +200,12 @@
 
 	plat_unmap_dma_mem(dev, dma_handle, size, DMA_BIDIRECTIONAL);
 
+#ifdef CONFIG_BRCM_UPPER_768MB
+	addr = (unsigned long)brcm_unmap_coherent(vaddr);
+#else
 	if (!plat_device_is_coherent(dev) && !hw_coherentio)
 		addr = CAC_ADDR(addr);
+#endif
 
 	page = virt_to_page((void *) addr);
 
diff --git a/arch/mips/mm/init.c b/arch/mips/mm/init.c
index 8770e61..f38a0f1 100644
--- a/arch/mips/mm/init.c
+++ b/arch/mips/mm/init.c
@@ -440,6 +440,9 @@
 	for (tmp = highstart_pfn; tmp < highend_pfn; tmp++) {
 		struct page *page = pfn_to_page(tmp);
 
+		if (!pfn_valid(tmp))
+			continue;
+
 		if (!page_is_ram(tmp))
 			SetPageReserved(page);
 		else
diff --git a/arch/mips/mm/ioremap.c b/arch/mips/mm/ioremap.c
index 8d5008c..f27c8be 100644
--- a/arch/mips/mm/ioremap.c
+++ b/arch/mips/mm/ioremap.c
@@ -127,6 +127,7 @@
 	if (!size || last_addr < phys_addr)
 		return NULL;
 
+#if !defined(CONFIG_BRCM_UPPER_768MB)
 	/*
 	 * Map uncached objects in the low 512mb of address space using KSEG1,
 	 * otherwise map using page tables.
@@ -134,6 +135,7 @@
 	if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) &&
 	    flags == _CACHE_UNCACHED)
 		return (void __iomem *) CKSEG1ADDR(phys_addr);
+#endif
 
 	/*
 	 * Don't allow anybody to remap normal RAM that we're using..
diff --git a/arch/mips/oprofile/Makefile b/arch/mips/oprofile/Makefile
index 070afdb..bccaf18 100644
--- a/arch/mips/oprofile/Makefile
+++ b/arch/mips/oprofile/Makefile
@@ -15,3 +15,5 @@
 oprofile-$(CONFIG_CPU_XLR)		+= op_model_mipsxx.o
 oprofile-$(CONFIG_CPU_LOONGSON2)	+= op_model_loongson2.o
 oprofile-$(CONFIG_CPU_LOONGSON3)	+= op_model_loongson3.o
+oprofile-$(CONFIG_CPU_BMIPS3300)	+= op_model_bmips.o
+oprofile-$(CONFIG_CPU_BMIPS4380)	+= op_model_bmips.o
diff --git a/arch/mips/oprofile/common.c b/arch/mips/oprofile/common.c
index 3c9ec3d..cc0a242 100644
--- a/arch/mips/oprofile/common.c
+++ b/arch/mips/oprofile/common.c
@@ -19,6 +19,9 @@
 extern struct op_mips_model op_model_mipsxx_ops __weak;
 extern struct op_mips_model op_model_loongson2_ops __weak;
 extern struct op_mips_model op_model_loongson3_ops __weak;
+#ifdef CONFIG_BRCMSTB
+extern struct op_mips_model op_model_bmips_ops __attribute__((weak));
+#endif
 
 static struct op_mips_model *model;
 
@@ -104,6 +107,17 @@
 		lmodel = &op_model_mipsxx_ops;
 		break;
 
+#ifdef CONFIG_BRCMSTB
+	case CPU_BMIPS3300:
+	case CPU_BMIPS4380:
+		lmodel = &op_model_bmips_ops;
+		break;
+
+	case CPU_BMIPS5000:
+		lmodel = &op_model_mipsxx_ops;
+		break;
+#endif
+
 	case CPU_LOONGSON2:
 		lmodel = &op_model_loongson2_ops;
 		break;
diff --git a/arch/mips/oprofile/op_model_bmips.c b/arch/mips/oprofile/op_model_bmips.c
new file mode 100644
index 0000000..e82638a
--- /dev/null
+++ b/arch/mips/oprofile/op_model_bmips.c
@@ -0,0 +1,244 @@
+/*
+ * Copyright (C) 2010 Broadcom Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/init.h>
+#include <linux/oprofile.h>
+#include <linux/interrupt.h>
+#include <linux/smp.h>
+#include <linux/compiler.h>
+#include <linux/brcmstb/brcmstb.h>
+
+#include "op_impl.h"
+
+/*
+ * Events coming from opcontrol look like: 0xXYZZ
+ *   X = ModuleID
+ *   Y = SetID
+ *   ZZ = EventID
+ *
+ * ModuleID and SetID are set globally so they must match for all events.
+ * Exception: events with ModuleID 0 can be used regardless of the
+ * ModuleID / SetID settings.
+ */
+
+#define BMIPS_MOD_SET(event)		(((event) >> 8) & 0xff)
+#define BMIPS_MOD(event)		(((event) >> 12) & 0x0f)
+#define BMIPS_SET(event)		(((event) >> 8) & 0x03)
+#define BMIPS_EVENT(event)		((event) & 0x7f)
+
+/* Default to using TP0 (HW can only profile one thread at a time) */
+#define PMU_TP				0
+
+#define NUM_COUNTERS			4
+
+#define GLOB_ENABLE			0x80000000
+#define GLOB_SET_SHIFT			0
+#define GLOB_MOD_SHIFT			2
+
+#define CTRL_ENABLE			0x8001
+#define CTRL_EVENT_SHIFT		2
+
+#define CNTR_OVERFLOW			0x80000000
+
+#if defined(CONFIG_CPU_BMIPS3300)
+
+/* These registers do not conform to any known MIPS standard */
+#define r_perfcntr0()			__read_32bit_c0_register($25, 0)
+#define r_perfcntr1()			__read_32bit_c0_register($25, 1)
+#define r_perfcntr2()			__read_32bit_c0_register($25, 2)
+#define r_perfcntr3()			__read_32bit_c0_register($25, 3)
+
+#define w_perfcntr0(x)			__write_32bit_c0_register($25, 0, x)
+#define w_perfcntr1(x)			__write_32bit_c0_register($25, 1, x)
+#define w_perfcntr2(x)			__write_32bit_c0_register($25, 2, x)
+#define w_perfcntr3(x)			__write_32bit_c0_register($25, 3, x)
+
+#define w_perfctrl0(x)			__write_32bit_c0_register($25, 4, x)
+#define w_perfctrl1(x)			__write_32bit_c0_register($25, 5, x)
+
+#define r_glob()			__read_32bit_c0_register($25, 6)
+#define w_glob(x)			__write_32bit_c0_register($25, 6, x)
+
+#elif defined(CONFIG_CPU_BMIPS4380)
+
+static unsigned long bmips_cbr;
+
+#define PERF_RD(x)			DEV_RD(bmips_cbr + BMIPS_PERF_ ## x)
+#define PERF_WR(x, y)			DEV_WR_RB(bmips_cbr + \
+						BMIPS_PERF_ ## x, (y))
+
+#define r_perfcntr0()			PERF_RD(COUNTER_0)
+#define r_perfcntr1()			PERF_RD(COUNTER_1)
+#define r_perfcntr2()			PERF_RD(COUNTER_2)
+#define r_perfcntr3()			PERF_RD(COUNTER_3)
+
+#define w_perfcntr0(x)			PERF_WR(COUNTER_0, (x))
+#define w_perfcntr1(x)			PERF_WR(COUNTER_1, (x))
+#define w_perfcntr2(x)			PERF_WR(COUNTER_2, (x))
+#define w_perfcntr3(x)			PERF_WR(COUNTER_3, (x))
+
+#define w_perfctrl0(x)			PERF_WR(CONTROL_0, (x))
+#define w_perfctrl1(x)			PERF_WR(CONTROL_1, (x))
+
+#define r_glob()			PERF_RD(GLOBAL_CONTROL)
+#define w_glob(x)			PERF_WR(GLOBAL_CONTROL, (x))
+
+#endif
+
+static int (*save_perf_irq)(void);
+
+struct op_mips_model op_model_bmips_ops;
+
+static struct bmips_register_config {
+	unsigned int globctrl;
+	unsigned int control[4];
+	unsigned int counter[4];
+} reg;
+
+/* Compute all of the registers in preparation for enabling profiling.  */
+
+static void bmips_reg_setup(struct op_counter_config *ctr)
+{
+	int i;
+	unsigned int mod_set = 0;
+	unsigned int ev;
+
+	memset(&reg, 0, sizeof(reg));
+	reg.globctrl = GLOB_ENABLE;
+
+	for (i = 0; i < NUM_COUNTERS; i++) {
+		if (!ctr[i].enabled)
+			continue;
+		ev = ctr[i].event;
+
+		if (mod_set && BMIPS_MOD_SET(ev) &&
+				mod_set != BMIPS_MOD_SET(ev)) {
+			printk(KERN_WARNING "%s: profiling event 0x%x "
+				"conflicts with another event, disabling\n",
+				__FUNCTION__, ev);
+			continue;
+		}
+		reg.counter[i] = ctr[i].count;
+		reg.control[i] = CTRL_ENABLE |
+			(BMIPS_EVENT(ev) << CTRL_EVENT_SHIFT);
+		if (BMIPS_MOD_SET(ev))
+			mod_set = BMIPS_MOD_SET(ev);
+		reg.globctrl |= (BMIPS_MOD(ev) << GLOB_MOD_SHIFT) |
+			(BMIPS_SET(ev) << GLOB_SET_SHIFT);
+	}
+}
+
+/* Program all of the registers in preparation for enabling profiling.  */
+
+static void bmips_cpu_setup(void *args)
+{
+	w_perfcntr0(reg.counter[0]);
+	w_perfcntr1(reg.counter[1]);
+	w_perfcntr2(reg.counter[2]);
+	w_perfcntr3(reg.counter[3]);
+}
+
+static void bmips_cpu_start(void *args)
+{
+	w_perfctrl0(reg.control[0] | (reg.control[1] << 16));
+	w_perfctrl1(reg.control[2] | (reg.control[3] << 16));
+	w_glob(reg.globctrl);
+}
+
+static void bmips_cpu_stop(void *args)
+{
+	w_perfctrl0(0);
+	w_perfctrl1(0);
+}
+
+static int bmips_perfcount_handler(void)
+{
+	int handled = IRQ_NONE;
+
+	if (!(r_glob() & GLOB_ENABLE))
+		return handled;
+
+#define HANDLE_COUNTER(n) \
+	if (r_perfcntr ## n() & CNTR_OVERFLOW) { \
+		oprofile_add_sample(get_irq_regs(), n); \
+		w_perfcntr ## n(reg.counter[n]); \
+		handled = IRQ_HANDLED; \
+	}
+
+	HANDLE_COUNTER(0)
+	HANDLE_COUNTER(1)
+	HANDLE_COUNTER(2)
+	HANDLE_COUNTER(3)
+
+	if (handled == IRQ_HANDLED)
+		bmips_cpu_start(NULL);
+
+	return handled;
+}
+
+static void bmips_perf_reset(void)
+{
+#ifdef CONFIG_CPU_BMIPS4380
+	bmips_cbr = __BMIPS_GET_CBR();
+	change_c0_brcm_cmt_ctrl(0x3 << 30, PMU_TP << 30);
+#endif
+
+	w_glob(GLOB_ENABLE);
+	w_perfctrl0(0);
+	w_perfctrl1(0);
+	w_perfcntr0(0);
+	w_perfcntr1(0);
+	w_perfcntr2(0);
+	w_perfcntr3(0);
+}
+
+static int __init bmips_init(void)
+{
+	bmips_perf_reset();
+
+	switch (current_cpu_type()) {
+	case CPU_BMIPS3300:
+		op_model_bmips_ops.cpu_type = "mips/bmips3300";
+		break;
+	case CPU_BMIPS4380:
+		op_model_bmips_ops.cpu_type = "mips/bmips4380";
+		break;
+	default:
+		BUG();
+	}
+	save_perf_irq = perf_irq;
+	perf_irq = bmips_perfcount_handler;
+
+	return 0;
+}
+
+static void bmips_exit(void)
+{
+	bmips_perf_reset();
+	w_glob(0);
+	perf_irq = save_perf_irq;
+}
+
+struct op_mips_model op_model_bmips_ops = {
+	.reg_setup	= bmips_reg_setup,
+	.cpu_setup	= bmips_cpu_setup,
+	.init		= bmips_init,
+	.exit		= bmips_exit,
+	.cpu_start	= bmips_cpu_start,
+	.cpu_stop	= bmips_cpu_stop,
+	.num_counters	= 4
+};
diff --git a/arch/mips/oprofile/op_model_mipsxx.c b/arch/mips/oprofile/op_model_mipsxx.c
index 8f988a6..52f71cd 100644
--- a/arch/mips/oprofile/op_model_mipsxx.c
+++ b/arch/mips/oprofile/op_model_mipsxx.c
@@ -170,6 +170,14 @@
 			reg.control[i] |= M_PERFCTL_EXL;
 		if (boot_cpu_type() == CPU_XLR)
 			reg.control[i] |= M_PERFCTL_COUNT_ALL_THREADS;
+#ifdef CONFIG_CPU_BMIPS5000
+		/* unit mask selects the TP(s) to count */
+		reg.control[i] |= ((ctr->unit_mask & 0x3) << 12) | (1 << 30);
+
+		/* default is TP0 + TP1 */
+		if (!ctr->unit_mask)
+			reg.control[i] |= 0x3 << 12;
+#endif
 		reg.counter[i] = 0x80000000 - ctr[i].count;
 	}
 }
@@ -269,6 +277,13 @@
 	return handled;
 }
 
+#ifdef CONFIG_BRCMSTB
+static irqreturn_t mipsxx_perfcount_isr(int irq, void *dev_id)
+{
+	return mipsxx_perfcount_handler();
+}
+#endif
+
 #define M_CONFIG1_PC	(1 << 4)
 
 static inline int __n_counters(void)
@@ -433,6 +448,12 @@
 		op_model_mipsxx_ops.cpu_type = "mips/xlr";
 		break;
 
+#ifdef CONFIG_CPU_BMIPS5000
+	case CPU_BMIPS5000:
+		op_model_mipsxx_ops.cpu_type = "mips/bmips5000";
+		break;
+#endif
+
 	default:
 		printk(KERN_ERR "Profiling unsupported for this CPU\n");
 
@@ -456,7 +477,13 @@
 				   IRQF_SHARED,
 				   "Perfcounter", save_perf_irq);
 
-	return 0;
+#ifdef CONFIG_BRCMSTB
+	if (cp0_perfcount_irq >= 0)
+		return request_irq(MIPS_CPU_IRQ_BASE + cp0_perfcount_irq,
+			mipsxx_perfcount_isr, 0, "Perfcounter", NULL);
+	else
+#endif
+		return 0;
 }
 
 static void mipsxx_exit(void)
@@ -469,6 +496,11 @@
 	counters = counters_per_cpu_to_total(counters);
 	on_each_cpu(reset_counters, (void *)(long)counters, 1);
 
+#ifdef CONFIG_BRCMSTB
+	if (cp0_perfcount_irq >= 0)
+		free_irq(MIPS_CPU_IRQ_BASE + cp0_perfcount_irq, NULL);
+#endif
+
 	perf_irq = save_perf_irq;
 }
 
diff --git a/arch/mips/pci/pci.c b/arch/mips/pci/pci.c
index b8a0bf5..c68ebfa 100644
--- a/arch/mips/pci/pci.c
+++ b/arch/mips/pci/pci.c
@@ -86,7 +86,11 @@
 	if (!hose->iommu)
 		PCI_DMA_BUS_IS_PHYS = 1;
 
+#ifdef CONFIG_BRCMSTB
+	if (hose->get_busno)
+#else
 	if (hose->get_busno && pci_has_flag(PCI_PROBE_ONLY))
+#endif
 		next_busno = (*hose->get_busno)();
 
 	pci_add_resource_offset(&resources,
diff --git a/arch/x86/configs/kvm_defconfig b/arch/x86/configs/kvm_defconfig
new file mode 100644
index 0000000..1b007b2
--- /dev/null
+++ b/arch/x86/configs/kvm_defconfig
@@ -0,0 +1,2183 @@
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SYSVIPC=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_FHANDLE=y
+# CONFIG_USELIB is not set
+CONFIG_AR_CLOCK=y
+CONFIG_NO_HZ_FULL=y
+CONFIG_NO_HZ_FULL_SYSIDLE=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BSD_PROCESS_ACCT=y
+CONFIG_BSD_PROCESS_ACCT_V3=y
+CONFIG_TASK_XACCT=y
+CONFIG_TASK_IO_ACCOUNTING=y
+CONFIG_RCU_FAST_NO_HZ=y
+CONFIG_LOG_BUF_SHIFT=18
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_RESOURCE_COUNTERS=y
+CONFIG_MEMCG=y
+CONFIG_MEMCG_SWAP=y
+# CONFIG_MEMCG_SWAP_ENABLED is not set
+CONFIG_MEMCG_KMEM=y
+CONFIG_CGROUP_HUGETLB=y
+CONFIG_CGROUP_PERF=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CHECKPOINT_RESTORE=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE="/usr/local/google/home/dgentry/Code/Athena/master/out/images/simpleramfs.cpio"
+CONFIG_RD_BZIP2=y
+CONFIG_RD_LZMA=y
+CONFIG_RD_XZ=y
+CONFIG_RD_LZO=y
+CONFIG_RD_LZ4=y
+CONFIG_EXPERT=y
+CONFIG_SYSCTL_SYSCALL=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=m
+CONFIG_KPROBES=y
+CONFIG_JUMP_LABEL=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_MODULE_SIG=y
+CONFIG_MODULE_SIG_SHA512=y
+CONFIG_BLK_DEV_THROTTLING=y
+CONFIG_PARTITION_ADVANCED=y
+CONFIG_BSD_DISKLABEL=y
+CONFIG_MINIX_SUBPARTITION=y
+CONFIG_SOLARIS_X86_PARTITION=y
+CONFIG_UNIXWARE_DISKLABEL=y
+CONFIG_LDM_PARTITION=y
+CONFIG_CMDLINE_PARTITION=y
+CONFIG_CFQ_GROUP_IOSCHED=y
+CONFIG_DEFAULT_DEADLINE=y
+CONFIG_SMP=y
+CONFIG_X86_X2APIC=y
+CONFIG_X86_NUMACHIP=y
+CONFIG_X86_INTEL_LPSS=y
+CONFIG_HYPERVISOR_GUEST=y
+CONFIG_PARAVIRT=y
+CONFIG_PARAVIRT_SPINLOCKS=y
+CONFIG_XEN=y
+CONFIG_KVM_DEBUG_FS=y
+CONFIG_MEMTEST=y
+CONFIG_PROCESSOR_SELECT=y
+CONFIG_GART_IOMMU=y
+CONFIG_CALGARY_IOMMU=y
+CONFIG_NR_CPUS=256
+CONFIG_SCHED_SMT=y
+CONFIG_PREEMPT_VOLUNTARY=y
+CONFIG_X86_REROUTE_FOR_BROKEN_BOOT_IRQS=y
+CONFIG_X86_MCE_INJECT=m
+CONFIG_I8K=m
+CONFIG_MICROCODE=y
+CONFIG_MICROCODE_AMD=y
+CONFIG_X86_MSR=m
+CONFIG_X86_CPUID=m
+CONFIG_NUMA=y
+CONFIG_ARCH_MEMORY_PROBE=y
+CONFIG_MOVABLE_NODE=y
+CONFIG_MEMORY_HOTPLUG=y
+CONFIG_MEMORY_HOTREMOVE=y
+CONFIG_KSM=y
+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536
+CONFIG_MEMORY_FAILURE=y
+CONFIG_HWPOISON_INJECT=m
+CONFIG_TRANSPARENT_HUGEPAGE=y
+CONFIG_CLEANCACHE=y
+CONFIG_FRONTSWAP=y
+CONFIG_CMA=y
+CONFIG_ZSWAP=y
+CONFIG_MEM_SOFT_DIRTY=y
+CONFIG_ZSMALLOC=y
+CONFIG_X86_CHECK_BIOS_CORRUPTION=y
+CONFIG_MTRR_SANITIZER_ENABLE_DEFAULT=1
+CONFIG_EFI=y
+CONFIG_EFI_STUB=y
+CONFIG_KEXEC=y
+CONFIG_CRASH_DUMP=y
+CONFIG_KEXEC_JUMP=y
+CONFIG_PHYSICAL_ALIGN=0x1000000
+CONFIG_HIBERNATION=y
+CONFIG_PM_RUNTIME=y
+CONFIG_PM_DEBUG=y
+CONFIG_PM_ADVANCED_DEBUG=y
+CONFIG_PM_TRACE_RTC=y
+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y
+CONFIG_ACPI_PROCFS_POWER=y
+CONFIG_ACPI_EC_DEBUGFS=m
+CONFIG_ACPI_DOCK=y
+CONFIG_ACPI_IPMI=m
+CONFIG_ACPI_PROCESSOR_AGGREGATOR=m
+CONFIG_ACPI_PCI_SLOT=y
+CONFIG_ACPI_HOTPLUG_MEMORY=y
+CONFIG_ACPI_SBS=m
+CONFIG_ACPI_BGRT=y
+CONFIG_ACPI_APEI=y
+CONFIG_ACPI_APEI_GHES=y
+CONFIG_ACPI_APEI_PCIEAER=y
+CONFIG_ACPI_APEI_MEMORY_FAILURE=y
+CONFIG_ACPI_APEI_EINJ=m
+CONFIG_ACPI_EXTLOG=m
+CONFIG_SFI=y
+CONFIG_CPU_FREQ=y
+CONFIG_CPU_FREQ_STAT_DETAILS=y
+CONFIG_CPU_FREQ_GOV_POWERSAVE=y
+CONFIG_CPU_FREQ_GOV_USERSPACE=y
+CONFIG_CPU_FREQ_GOV_ONDEMAND=y
+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y
+CONFIG_X86_INTEL_PSTATE=y
+CONFIG_X86_PCC_CPUFREQ=y
+CONFIG_X86_ACPI_CPUFREQ=y
+CONFIG_X86_POWERNOW_K8=y
+CONFIG_X86_AMD_FREQ_SENSITIVITY=m
+CONFIG_X86_SPEEDSTEP_CENTRINO=y
+CONFIG_X86_P4_CLOCKMOD=m
+CONFIG_CPU_IDLE_MULTIPLE_DRIVERS=y
+CONFIG_INTEL_IDLE=y
+CONFIG_I7300_IDLE=m
+CONFIG_PCI_MMCONFIG=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_HOTPLUG_PCI_PCIE=y
+CONFIG_PCI_REALLOC_ENABLE_AUTO=y
+CONFIG_PCI_STUB=m
+CONFIG_XEN_PCIDEV_FRONTEND=m
+CONFIG_PCI_IOV=y
+CONFIG_PCI_IOAPIC=y
+CONFIG_PCCARD=m
+CONFIG_YENTA=m
+CONFIG_PD6729=m
+CONFIG_I82092=m
+CONFIG_HOTPLUG_PCI=y
+CONFIG_HOTPLUG_PCI_ACPI=y
+CONFIG_HOTPLUG_PCI_ACPI_IBM=m
+CONFIG_HOTPLUG_PCI_CPCI=y
+CONFIG_HOTPLUG_PCI_CPCI_ZT5550=m
+CONFIG_HOTPLUG_PCI_CPCI_GENERIC=m
+CONFIG_HOTPLUG_PCI_SHPC=m
+CONFIG_BINFMT_MISC=m
+CONFIG_IA32_EMULATION=y
+CONFIG_X86_X32=y
+CONFIG_PACKET=y
+CONFIG_PACKET_DIAG=m
+CONFIG_UNIX=y
+CONFIG_UNIX_DIAG=m
+CONFIG_XFRM_USER=m
+CONFIG_NET_KEY=m
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_IP_FIB_TRIE_STATS=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+CONFIG_IP_ROUTE_VERBOSE=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NET_IPIP=m
+CONFIG_NET_IPGRE_DEMUX=m
+CONFIG_NET_IPGRE=m
+CONFIG_NET_IPGRE_BROADCAST=y
+CONFIG_IP_MROUTE=y
+CONFIG_IP_PIMSM_V1=y
+CONFIG_IP_PIMSM_V2=y
+CONFIG_NET_IPVTI=m
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=m
+CONFIG_INET_XFRM_MODE_TUNNEL=m
+CONFIG_INET_XFRM_MODE_BEET=m
+CONFIG_INET_DIAG=m
+CONFIG_INET_UDP_DIAG=m
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_TCP_MD5SIG=y
+CONFIG_IPV6=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_VTI=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_SIT_6RD=y
+CONFIG_IPV6_GRE=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+CONFIG_IPV6_MROUTE=y
+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y
+CONFIG_IPV6_PIMSM_V2=y
+CONFIG_NETFILTER=y
+CONFIG_NF_CONNTRACK=m
+CONFIG_NF_CONNTRACK_SECMARK=y
+CONFIG_NF_CONNTRACK_ZONES=y
+# CONFIG_NF_CONNTRACK_PROCFS is not set
+CONFIG_NF_CONNTRACK_EVENTS=y
+CONFIG_NF_CONNTRACK_TIMEOUT=y
+CONFIG_NF_CONNTRACK_TIMESTAMP=y
+CONFIG_NF_CT_PROTO_UDPLITE=m
+CONFIG_NF_CONNTRACK_AMANDA=m
+CONFIG_NF_CONNTRACK_FTP=m
+CONFIG_NF_CONNTRACK_H323=m
+CONFIG_NF_CONNTRACK_IRC=m
+CONFIG_NF_CONNTRACK_NETBIOS_NS=m
+CONFIG_NF_CONNTRACK_SNMP=m
+CONFIG_NF_CONNTRACK_PPTP=m
+CONFIG_NF_CONNTRACK_SANE=m
+CONFIG_NF_CONNTRACK_SIP=m
+CONFIG_NF_CONNTRACK_TFTP=m
+CONFIG_NF_CT_NETLINK=m
+CONFIG_NF_CT_NETLINK_TIMEOUT=m
+CONFIG_NF_CT_NETLINK_HELPER=m
+CONFIG_NETFILTER_NETLINK_QUEUE_CT=y
+CONFIG_NF_TABLES=m
+CONFIG_NFT_EXTHDR=m
+CONFIG_NFT_META=m
+CONFIG_NFT_CT=m
+CONFIG_NFT_RBTREE=m
+CONFIG_NFT_HASH=m
+CONFIG_NFT_COUNTER=m
+CONFIG_NFT_LOG=m
+CONFIG_NFT_LIMIT=m
+CONFIG_NFT_NAT=m
+CONFIG_NFT_COMPAT=m
+CONFIG_NETFILTER_XT_SET=m
+CONFIG_NETFILTER_XT_TARGET_AUDIT=m
+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m
+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m
+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m
+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m
+CONFIG_NETFILTER_XT_TARGET_DSCP=m
+CONFIG_NETFILTER_XT_TARGET_HMARK=m
+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m
+CONFIG_NETFILTER_XT_TARGET_LED=m
+CONFIG_NETFILTER_XT_TARGET_LOG=m
+CONFIG_NETFILTER_XT_TARGET_MARK=m
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m
+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m
+CONFIG_NETFILTER_XT_TARGET_TEE=m
+CONFIG_NETFILTER_XT_TARGET_TPROXY=m
+CONFIG_NETFILTER_XT_TARGET_TRACE=m
+CONFIG_NETFILTER_XT_TARGET_SECMARK=m
+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m
+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m
+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m
+CONFIG_NETFILTER_XT_MATCH_BPF=m
+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m
+CONFIG_NETFILTER_XT_MATCH_COMMENT=m
+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m
+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m
+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m
+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m
+CONFIG_NETFILTER_XT_MATCH_CPU=m
+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m
+CONFIG_NETFILTER_XT_MATCH_DSCP=m
+CONFIG_NETFILTER_XT_MATCH_ESP=m
+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m
+CONFIG_NETFILTER_XT_MATCH_HELPER=m
+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m
+CONFIG_NETFILTER_XT_MATCH_IPVS=m
+CONFIG_NETFILTER_XT_MATCH_LENGTH=m
+CONFIG_NETFILTER_XT_MATCH_LIMIT=m
+CONFIG_NETFILTER_XT_MATCH_MAC=m
+CONFIG_NETFILTER_XT_MATCH_MARK=m
+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m
+CONFIG_NETFILTER_XT_MATCH_NFACCT=m
+CONFIG_NETFILTER_XT_MATCH_OSF=m
+CONFIG_NETFILTER_XT_MATCH_OWNER=m
+CONFIG_NETFILTER_XT_MATCH_POLICY=m
+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m
+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m
+CONFIG_NETFILTER_XT_MATCH_QUOTA=m
+CONFIG_NETFILTER_XT_MATCH_RATEEST=m
+CONFIG_NETFILTER_XT_MATCH_REALM=m
+CONFIG_NETFILTER_XT_MATCH_RECENT=m
+CONFIG_NETFILTER_XT_MATCH_SOCKET=m
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m
+CONFIG_NETFILTER_XT_MATCH_STRING=m
+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m
+CONFIG_NETFILTER_XT_MATCH_TIME=m
+CONFIG_NETFILTER_XT_MATCH_U32=m
+CONFIG_IP_SET=m
+CONFIG_IP_SET_BITMAP_IP=m
+CONFIG_IP_SET_BITMAP_IPMAC=m
+CONFIG_IP_SET_BITMAP_PORT=m
+CONFIG_IP_SET_HASH_IP=m
+CONFIG_IP_SET_HASH_IPPORT=m
+CONFIG_IP_SET_HASH_IPPORTIP=m
+CONFIG_IP_SET_HASH_IPPORTNET=m
+CONFIG_IP_SET_HASH_NETPORTNET=m
+CONFIG_IP_SET_HASH_NET=m
+CONFIG_IP_SET_HASH_NETNET=m
+CONFIG_IP_SET_HASH_NETPORT=m
+CONFIG_IP_SET_HASH_NETIFACE=m
+CONFIG_IP_SET_LIST_SET=m
+CONFIG_IP_VS=m
+CONFIG_IP_VS_IPV6=y
+CONFIG_IP_VS_PROTO_TCP=y
+CONFIG_IP_VS_PROTO_UDP=y
+CONFIG_IP_VS_PROTO_ESP=y
+CONFIG_IP_VS_PROTO_AH=y
+CONFIG_IP_VS_PROTO_SCTP=y
+CONFIG_IP_VS_RR=m
+CONFIG_IP_VS_WRR=m
+CONFIG_IP_VS_LC=m
+CONFIG_IP_VS_WLC=m
+CONFIG_IP_VS_LBLC=m
+CONFIG_IP_VS_LBLCR=m
+CONFIG_IP_VS_DH=m
+CONFIG_IP_VS_SH=m
+CONFIG_IP_VS_SED=m
+CONFIG_IP_VS_NQ=m
+CONFIG_IP_VS_FTP=m
+CONFIG_IP_VS_PE_SIP=m
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_TABLES_IPV4=m
+CONFIG_NFT_CHAIN_ROUTE_IPV4=m
+CONFIG_NFT_CHAIN_NAT_IPV4=m
+CONFIG_NF_TABLES_ARP=m
+CONFIG_IP_NF_IPTABLES=m
+CONFIG_IP_NF_MATCH_AH=m
+CONFIG_IP_NF_MATCH_ECN=m
+CONFIG_IP_NF_MATCH_RPFILTER=m
+CONFIG_IP_NF_MATCH_TTL=m
+CONFIG_IP_NF_FILTER=m
+CONFIG_IP_NF_TARGET_REJECT=m
+CONFIG_IP_NF_TARGET_SYNPROXY=m
+CONFIG_IP_NF_TARGET_ULOG=m
+CONFIG_NF_NAT_IPV4=m
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+CONFIG_IP_NF_TARGET_NETMAP=m
+CONFIG_IP_NF_TARGET_REDIRECT=m
+CONFIG_IP_NF_MANGLE=m
+CONFIG_IP_NF_TARGET_CLUSTERIP=m
+CONFIG_IP_NF_TARGET_ECN=m
+CONFIG_IP_NF_TARGET_TTL=m
+CONFIG_IP_NF_RAW=m
+CONFIG_IP_NF_SECURITY=m
+CONFIG_IP_NF_ARPTABLES=m
+CONFIG_IP_NF_ARPFILTER=m
+CONFIG_IP_NF_ARP_MANGLE=m
+CONFIG_NF_CONNTRACK_IPV6=m
+CONFIG_NF_TABLES_IPV6=m
+CONFIG_NFT_CHAIN_ROUTE_IPV6=m
+CONFIG_NFT_CHAIN_NAT_IPV6=m
+CONFIG_IP6_NF_MATCH_AH=m
+CONFIG_IP6_NF_MATCH_EUI64=m
+CONFIG_IP6_NF_MATCH_FRAG=m
+CONFIG_IP6_NF_MATCH_OPTS=m
+CONFIG_IP6_NF_MATCH_HL=m
+CONFIG_IP6_NF_MATCH_IPV6HEADER=m
+CONFIG_IP6_NF_MATCH_MH=m
+CONFIG_IP6_NF_MATCH_RPFILTER=m
+CONFIG_IP6_NF_MATCH_RT=m
+CONFIG_IP6_NF_TARGET_HL=m
+CONFIG_IP6_NF_FILTER=m
+CONFIG_IP6_NF_TARGET_REJECT=m
+CONFIG_IP6_NF_TARGET_SYNPROXY=m
+CONFIG_IP6_NF_MANGLE=m
+CONFIG_IP6_NF_RAW=m
+CONFIG_IP6_NF_SECURITY=m
+CONFIG_NF_NAT_IPV6=m
+CONFIG_IP6_NF_TARGET_MASQUERADE=m
+CONFIG_IP6_NF_TARGET_NPT=m
+CONFIG_DECNET_NF_GRABULATOR=m
+CONFIG_NF_TABLES_BRIDGE=m
+CONFIG_BRIDGE_NF_EBTABLES=m
+CONFIG_BRIDGE_EBT_BROUTE=m
+CONFIG_BRIDGE_EBT_T_FILTER=m
+CONFIG_BRIDGE_EBT_T_NAT=m
+CONFIG_BRIDGE_EBT_802_3=m
+CONFIG_BRIDGE_EBT_AMONG=m
+CONFIG_BRIDGE_EBT_ARP=m
+CONFIG_BRIDGE_EBT_IP=m
+CONFIG_BRIDGE_EBT_IP6=m
+CONFIG_BRIDGE_EBT_LIMIT=m
+CONFIG_BRIDGE_EBT_MARK=m
+CONFIG_BRIDGE_EBT_PKTTYPE=m
+CONFIG_BRIDGE_EBT_STP=m
+CONFIG_BRIDGE_EBT_VLAN=m
+CONFIG_BRIDGE_EBT_ARPREPLY=m
+CONFIG_BRIDGE_EBT_DNAT=m
+CONFIG_BRIDGE_EBT_MARK_T=m
+CONFIG_BRIDGE_EBT_REDIRECT=m
+CONFIG_BRIDGE_EBT_SNAT=m
+CONFIG_BRIDGE_EBT_LOG=m
+CONFIG_BRIDGE_EBT_NFLOG=m
+CONFIG_IP_DCCP=m
+# CONFIG_IP_DCCP_CCID3 is not set
+CONFIG_NET_DCCPPROBE=m
+CONFIG_NET_SCTPPROBE=m
+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y
+CONFIG_SCTP_COOKIE_HMAC_MD5=y
+CONFIG_RDS=m
+CONFIG_RDS_TCP=m
+CONFIG_TIPC=m
+CONFIG_ATM=m
+CONFIG_ATM_CLIP=m
+CONFIG_ATM_LANE=m
+CONFIG_ATM_MPOA=m
+CONFIG_ATM_BR2684=m
+CONFIG_L2TP=m
+CONFIG_L2TP_DEBUGFS=m
+CONFIG_L2TP_V3=y
+CONFIG_L2TP_IP=m
+CONFIG_L2TP_ETH=m
+CONFIG_BRIDGE=m
+CONFIG_BRIDGE_VLAN_FILTERING=y
+CONFIG_VLAN_8021Q=m
+CONFIG_VLAN_8021Q_GVRP=y
+CONFIG_VLAN_8021Q_MVRP=y
+CONFIG_DECNET=m
+CONFIG_LLC2=m
+CONFIG_IPX=m
+CONFIG_ATALK=m
+CONFIG_DEV_APPLETALK=m
+CONFIG_IPDDP=m
+CONFIG_IPDDP_ENCAP=y
+CONFIG_X25=m
+CONFIG_LAPB=m
+CONFIG_PHONET=m
+CONFIG_IEEE802154=m
+CONFIG_IEEE802154_6LOWPAN=m
+CONFIG_MAC802154=m
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_ATM=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_MULTIQ=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFB=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_DRR=m
+CONFIG_NET_SCH_MQPRIO=m
+CONFIG_NET_SCH_CHOKE=m
+CONFIG_NET_SCH_QFQ=m
+CONFIG_NET_SCH_CODEL=m
+CONFIG_NET_SCH_FQ_CODEL=m
+CONFIG_NET_SCH_FQ=m
+CONFIG_NET_SCH_INGRESS=m
+CONFIG_NET_SCH_PLUG=m
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_CLS_FLOW=m
+CONFIG_NET_CLS_CGROUP=m
+CONFIG_NET_CLS_BPF=m
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_EMATCH_IPSET=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=m
+CONFIG_NET_ACT_IPT=m
+CONFIG_NET_ACT_NAT=m
+CONFIG_NET_ACT_PEDIT=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_ACT_SKBEDIT=m
+CONFIG_NET_ACT_CSUM=m
+CONFIG_DCB=y
+CONFIG_DNS_RESOLVER=y
+CONFIG_BATMAN_ADV=m
+CONFIG_BATMAN_ADV_DAT=y
+CONFIG_BATMAN_ADV_NC=y
+CONFIG_OPENVSWITCH=m
+CONFIG_VSOCKETS=m
+CONFIG_VMWARE_VMCI_VSOCKETS=m
+CONFIG_NETLINK_MMAP=y
+CONFIG_NETLINK_DIAG=m
+CONFIG_NET_MPLS_GSO=m
+CONFIG_HSR=m
+CONFIG_BPF_JIT=y
+CONFIG_NET_PKTGEN=m
+CONFIG_NET_TCPPROBE=m
+CONFIG_IRDA=m
+CONFIG_IRLAN=m
+CONFIG_IRNET=m
+CONFIG_IRCOMM=m
+CONFIG_IRDA_ULTRA=y
+CONFIG_IRDA_CACHE_LAST_LSAP=y
+CONFIG_IRDA_FAST_RR=y
+CONFIG_IRTTY_SIR=m
+CONFIG_DONGLE=y
+CONFIG_ESI_DONGLE=m
+CONFIG_ACTISYS_DONGLE=m
+CONFIG_TEKRAM_DONGLE=m
+CONFIG_TOIM3232_DONGLE=m
+CONFIG_LITELINK_DONGLE=m
+CONFIG_MA600_DONGLE=m
+CONFIG_GIRBIL_DONGLE=m
+CONFIG_MCP2120_DONGLE=m
+CONFIG_OLD_BELKIN_DONGLE=m
+CONFIG_ACT200L_DONGLE=m
+CONFIG_KINGSUN_DONGLE=m
+CONFIG_KSDAZZLE_DONGLE=m
+CONFIG_KS959_DONGLE=m
+CONFIG_USB_IRDA=m
+CONFIG_SIGMATEL_FIR=m
+CONFIG_NSC_FIR=m
+CONFIG_WINBOND_FIR=m
+CONFIG_SMC_IRCC_FIR=m
+CONFIG_ALI_FIR=m
+CONFIG_VLSI_FIR=m
+CONFIG_VIA_FIR=m
+CONFIG_MCS_FIR=m
+CONFIG_BT=m
+CONFIG_BT_RFCOMM=m
+CONFIG_BT_RFCOMM_TTY=y
+CONFIG_BT_BNEP=m
+CONFIG_BT_BNEP_MC_FILTER=y
+CONFIG_BT_BNEP_PROTO_FILTER=y
+CONFIG_BT_HIDP=m
+CONFIG_BT_HCIBTUSB=m
+CONFIG_BT_HCIUART=m
+CONFIG_BT_HCIUART_H4=y
+CONFIG_BT_HCIUART_BCSP=y
+CONFIG_BT_HCIUART_ATH3K=y
+CONFIG_BT_HCIUART_LL=y
+CONFIG_BT_HCIUART_3WIRE=y
+CONFIG_BT_HCIBCM203X=m
+CONFIG_BT_HCIBPA10X=m
+CONFIG_BT_HCIBFUSB=m
+CONFIG_BT_HCIDTL1=m
+CONFIG_BT_HCIBT3C=m
+CONFIG_BT_HCIBLUECARD=m
+CONFIG_BT_HCIBTUART=m
+CONFIG_BT_HCIVHCI=m
+CONFIG_BT_MRVL=m
+CONFIG_BT_ATH3K=m
+CONFIG_BT_WILINK=m
+CONFIG_CFG80211=m
+CONFIG_CFG80211_DEBUGFS=y
+CONFIG_CFG80211_WEXT=y
+CONFIG_MAC80211=m
+CONFIG_MAC80211_RC_PID=y
+CONFIG_MAC80211_MESH=y
+CONFIG_MAC80211_LEDS=y
+CONFIG_MAC80211_DEBUGFS=y
+CONFIG_MAC80211_MESSAGE_TRACING=y
+CONFIG_RFKILL=y
+CONFIG_RFKILL_INPUT=y
+CONFIG_RFKILL_REGULATOR=m
+CONFIG_RFKILL_GPIO=m
+CONFIG_NET_9P=m
+CONFIG_NET_9P_VIRTIO=m
+CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+# CONFIG_STANDALONE is not set
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_REDBOOT_PARTS=m
+CONFIG_MTD_CMDLINE_PARTS=m
+CONFIG_MTD_AR7_PARTS=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_BLOCK_RO=m
+CONFIG_FTL=m
+CONFIG_NFTL=m
+CONFIG_NFTL_RW=y
+CONFIG_INFTL=m
+CONFIG_RFD_FTL=m
+CONFIG_SSFDC=m
+CONFIG_SM_FTL=m
+CONFIG_MTD_OOPS=m
+CONFIG_MTD_SWAP=m
+CONFIG_MTD_CFI=m
+CONFIG_MTD_JEDECPROBE=m
+CONFIG_MTD_CFI_INTELEXT=m
+CONFIG_MTD_CFI_AMDSTD=m
+CONFIG_MTD_CFI_STAA=m
+CONFIG_MTD_ROM=m
+CONFIG_MTD_ABSENT=m
+CONFIG_MTD_COMPLEX_MAPPINGS=y
+CONFIG_MTD_PHYSMAP=m
+CONFIG_MTD_SBC_GXX=m
+CONFIG_MTD_AMD76XROM=m
+CONFIG_MTD_ICHXROM=m
+CONFIG_MTD_ESB2ROM=m
+CONFIG_MTD_CK804XROM=m
+CONFIG_MTD_SCB2_FLASH=m
+CONFIG_MTD_NETtel=m
+CONFIG_MTD_L440GX=m
+CONFIG_MTD_PCI=m
+CONFIG_MTD_PCMCIA=m
+CONFIG_MTD_GPIO_ADDR=m
+CONFIG_MTD_INTEL_VR_NOR=m
+CONFIG_MTD_PLATRAM=m
+CONFIG_MTD_LATCH_ADDR=m
+CONFIG_MTD_PMC551=m
+CONFIG_MTD_SLRAM=m
+CONFIG_MTD_PHRAM=m
+CONFIG_MTD_MTDRAM=m
+CONFIG_MTD_BLOCK2MTD=m
+CONFIG_MTD_DOCG3=m
+CONFIG_MTD_NAND=m
+CONFIG_MTD_NAND_ECC_BCH=y
+CONFIG_MTD_NAND_DENALI=m
+CONFIG_MTD_NAND_DENALI_PCI=m
+CONFIG_MTD_NAND_DENALI_DT=m
+CONFIG_MTD_NAND_GPIO=m
+CONFIG_MTD_NAND_RICOH=m
+CONFIG_MTD_NAND_DISKONCHIP=m
+CONFIG_MTD_NAND_DOCG4=m
+CONFIG_MTD_NAND_CAFE=m
+CONFIG_MTD_NAND_NANDSIM=m
+CONFIG_MTD_NAND_PLATFORM=m
+CONFIG_MTD_ONENAND=m
+CONFIG_MTD_ONENAND_VERIFY_WRITE=y
+CONFIG_MTD_ONENAND_GENERIC=m
+CONFIG_MTD_ONENAND_2X_PROGRAM=y
+CONFIG_MTD_LPDDR=m
+CONFIG_MTD_UBI=m
+CONFIG_MTD_UBI_FASTMAP=y
+CONFIG_MTD_UBI_GLUEBI=m
+CONFIG_PARPORT=m
+CONFIG_PARPORT_PC=m
+CONFIG_PARPORT_SERIAL=m
+CONFIG_PARPORT_PC_FIFO=y
+CONFIG_PARPORT_PC_PCMCIA=m
+CONFIG_PARPORT_AX88796=m
+CONFIG_PARPORT_1284=y
+# CONFIG_PNP_DEBUG_MESSAGES is not set
+CONFIG_BLK_DEV_NULL_BLK=m
+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m
+CONFIG_ZRAM=m
+CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_DRBD=m
+CONFIG_BLK_DEV_NBD=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_SIZE=65536
+CONFIG_XEN_BLKDEV_BACKEND=m
+CONFIG_VIRTIO_BLK=y
+CONFIG_AD525X_DPOT=m
+CONFIG_AD525X_DPOT_I2C=m
+CONFIG_DUMMY_IRQ=m
+CONFIG_IBM_ASM=m
+CONFIG_PHANTOM=m
+CONFIG_SGI_IOC4=m
+CONFIG_TIFM_CORE=m
+CONFIG_ICS932S401=m
+CONFIG_ENCLOSURE_SERVICES=m
+CONFIG_HP_ILO=m
+CONFIG_APDS9802ALS=m
+CONFIG_ISL29003=m
+CONFIG_ISL29020=m
+CONFIG_SENSORS_TSL2550=m
+CONFIG_SENSORS_BH1780=m
+CONFIG_SENSORS_BH1770=m
+CONFIG_SENSORS_APDS990X=m
+CONFIG_HMC6352=m
+CONFIG_DS1682=m
+CONFIG_VMWARE_BALLOON=m
+CONFIG_BMP085_I2C=m
+CONFIG_USB_SWITCH_FSA9480=m
+CONFIG_SRAM=y
+CONFIG_C2PORT=m
+CONFIG_C2PORT_DURAMAR_2150=m
+CONFIG_EEPROM_AT24=m
+CONFIG_EEPROM_LEGACY=m
+CONFIG_EEPROM_MAX6875=m
+CONFIG_EEPROM_93CX6=m
+CONFIG_CB710_CORE=m
+CONFIG_TI_ST=m
+CONFIG_SENSORS_LIS3_I2C=m
+CONFIG_ALTERA_STAPL=m
+CONFIG_INTEL_MEI_ME=m
+CONFIG_VMWARE_VMCI=m
+CONFIG_INTEL_MIC_HOST=m
+CONFIG_INTEL_MIC_CARD=m
+CONFIG_ECHO=m
+CONFIG_BLK_DEV_SD=y
+CONFIG_CHR_DEV_ST=m
+CONFIG_CHR_DEV_OSST=m
+CONFIG_BLK_DEV_SR=y
+CONFIG_CHR_DEV_SG=y
+CONFIG_CHR_DEV_SCH=m
+CONFIG_SCSI_ENCLOSURE=m
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+CONFIG_SCSI_SCAN_ASYNC=y
+CONFIG_SCSI_SPI_ATTRS=y
+CONFIG_SCSI_FC_TGT_ATTRS=y
+CONFIG_SCSI_SAS_ATA=y
+CONFIG_SCSI_SRP_ATTRS=m
+CONFIG_SCSI_SRP_TGT_ATTRS=y
+CONFIG_ISCSI_TCP=m
+CONFIG_SCSI_CXGB3_ISCSI=m
+CONFIG_SCSI_CXGB4_ISCSI=m
+CONFIG_SCSI_BNX2_ISCSI=m
+CONFIG_SCSI_BNX2X_FCOE=m
+CONFIG_BE2ISCSI=m
+CONFIG_BLK_DEV_3W_XXXX_RAID=m
+CONFIG_SCSI_HPSA=m
+CONFIG_SCSI_3W_9XXX=m
+CONFIG_SCSI_3W_SAS=m
+CONFIG_SCSI_ACARD=m
+CONFIG_SCSI_AACRAID=m
+CONFIG_SCSI_AIC7XXX=m
+CONFIG_AIC7XXX_CMDS_PER_DEVICE=8
+CONFIG_AIC7XXX_RESET_DELAY_MS=15000
+# CONFIG_AIC7XXX_DEBUG_ENABLE is not set
+CONFIG_SCSI_AIC79XX=m
+# CONFIG_AIC79XX_DEBUG_ENABLE is not set
+CONFIG_SCSI_AIC94XX=m
+# CONFIG_AIC94XX_DEBUG is not set
+CONFIG_SCSI_MVSAS=m
+# CONFIG_SCSI_MVSAS_DEBUG is not set
+CONFIG_SCSI_MVUMI=m
+CONFIG_SCSI_DPT_I2O=m
+CONFIG_SCSI_ADVANSYS=m
+CONFIG_SCSI_ARCMSR=m
+CONFIG_SCSI_ESAS2R=m
+CONFIG_MEGARAID_NEWGEN=y
+CONFIG_MEGARAID_MM=m
+CONFIG_MEGARAID_MAILBOX=m
+CONFIG_MEGARAID_LEGACY=m
+CONFIG_MEGARAID_SAS=m
+CONFIG_SCSI_MPT2SAS=m
+CONFIG_SCSI_MPT3SAS=m
+CONFIG_SCSI_UFSHCD=m
+CONFIG_SCSI_UFSHCD_PCI=m
+CONFIG_SCSI_UFSHCD_PLATFORM=m
+CONFIG_SCSI_HPTIOP=m
+CONFIG_SCSI_BUSLOGIC=m
+CONFIG_SCSI_FLASHPOINT=y
+CONFIG_VMWARE_PVSCSI=m
+CONFIG_FCOE=m
+CONFIG_FCOE_FNIC=m
+CONFIG_SCSI_DMX3191D=m
+CONFIG_SCSI_EATA=m
+CONFIG_SCSI_EATA_TAGGED_QUEUE=y
+CONFIG_SCSI_EATA_LINKED_COMMANDS=y
+CONFIG_SCSI_FUTURE_DOMAIN=m
+CONFIG_SCSI_GDTH=m
+CONFIG_SCSI_ISCI=m
+CONFIG_SCSI_IPS=m
+CONFIG_SCSI_INITIO=m
+CONFIG_SCSI_INIA100=m
+CONFIG_SCSI_PPA=m
+CONFIG_SCSI_IMM=m
+CONFIG_SCSI_STEX=m
+CONFIG_SCSI_SYM53C8XX_2=m
+CONFIG_SCSI_IPR=m
+CONFIG_SCSI_QLOGIC_1280=m
+CONFIG_SCSI_QLA_FC=m
+CONFIG_TCM_QLA2XXX=m
+CONFIG_SCSI_QLA_ISCSI=m
+CONFIG_SCSI_LPFC=m
+CONFIG_SCSI_DC395x=m
+CONFIG_SCSI_DC390T=m
+CONFIG_SCSI_DEBUG=m
+CONFIG_SCSI_PMCRAID=m
+CONFIG_SCSI_PM8001=m
+CONFIG_SCSI_SRP=m
+CONFIG_SCSI_BFA_FC=m
+CONFIG_SCSI_VIRTIO=m
+CONFIG_SCSI_CHELSIO_FCOE=m
+CONFIG_SCSI_LOWLEVEL_PCMCIA=y
+CONFIG_PCMCIA_AHA152X=m
+CONFIG_PCMCIA_FDOMAIN=m
+CONFIG_PCMCIA_QLOGIC=m
+CONFIG_PCMCIA_SYM53C500=m
+CONFIG_SCSI_DH=m
+CONFIG_SCSI_DH_RDAC=m
+CONFIG_SCSI_DH_HP_SW=m
+CONFIG_SCSI_DH_EMC=m
+CONFIG_SCSI_DH_ALUA=m
+CONFIG_SCSI_OSD_INITIATOR=m
+CONFIG_SCSI_OSD_ULD=m
+CONFIG_ATA=y
+CONFIG_SATA_ZPODD=y
+CONFIG_SATA_AHCI=m
+CONFIG_SATA_AHCI_PLATFORM=m
+CONFIG_SATA_INIC162X=m
+CONFIG_SATA_ACARD_AHCI=m
+CONFIG_SATA_SIL24=m
+CONFIG_PDC_ADMA=m
+CONFIG_SATA_QSTOR=m
+CONFIG_SATA_SX4=m
+CONFIG_ATA_PIIX=y
+CONFIG_SATA_MV=m
+CONFIG_SATA_NV=m
+CONFIG_SATA_PROMISE=m
+CONFIG_SATA_SIL=m
+CONFIG_SATA_SIS=m
+CONFIG_SATA_SVW=m
+CONFIG_SATA_ULI=m
+CONFIG_SATA_VIA=m
+CONFIG_SATA_VITESSE=m
+CONFIG_PATA_ALI=m
+CONFIG_PATA_AMD=m
+CONFIG_PATA_ARTOP=m
+CONFIG_PATA_ATIIXP=m
+CONFIG_PATA_ATP867X=m
+CONFIG_PATA_CMD64X=m
+CONFIG_PATA_CYPRESS=m
+CONFIG_PATA_EFAR=m
+CONFIG_PATA_HPT366=m
+CONFIG_PATA_HPT37X=m
+CONFIG_PATA_HPT3X2N=m
+CONFIG_PATA_HPT3X3=m
+CONFIG_PATA_IT8213=m
+CONFIG_PATA_IT821X=m
+CONFIG_PATA_JMICRON=m
+CONFIG_PATA_MARVELL=m
+CONFIG_PATA_NETCELL=m
+CONFIG_PATA_NINJA32=m
+CONFIG_PATA_NS87415=m
+CONFIG_PATA_OLDPIIX=m
+CONFIG_PATA_OPTIDMA=m
+CONFIG_PATA_PDC2027X=m
+CONFIG_PATA_PDC_OLD=m
+CONFIG_PATA_RADISYS=m
+CONFIG_PATA_RDC=m
+CONFIG_PATA_SCH=m
+CONFIG_PATA_SERVERWORKS=m
+CONFIG_PATA_SIL680=m
+CONFIG_PATA_SIS=y
+CONFIG_PATA_TOSHIBA=m
+CONFIG_PATA_TRIFLEX=m
+CONFIG_PATA_VIA=m
+CONFIG_PATA_WINBOND=m
+CONFIG_PATA_CMD640_PCI=m
+CONFIG_PATA_MPIIX=m
+CONFIG_PATA_NS87410=m
+CONFIG_PATA_OPTI=m
+CONFIG_PATA_PCMCIA=m
+CONFIG_PATA_PLATFORM=m
+CONFIG_PATA_RZ1000=m
+CONFIG_PATA_ACPI=m
+CONFIG_ATA_GENERIC=y
+CONFIG_PATA_LEGACY=m
+CONFIG_MD=y
+CONFIG_BLK_DEV_MD=y
+CONFIG_MD_LINEAR=m
+CONFIG_MD_RAID0=m
+CONFIG_MD_MULTIPATH=m
+CONFIG_MD_FAULTY=m
+CONFIG_BCACHE=m
+CONFIG_BLK_DEV_DM=y
+CONFIG_DM_CRYPT=m
+CONFIG_DM_SNAPSHOT=m
+CONFIG_DM_THIN_PROVISIONING=m
+CONFIG_DM_CACHE=m
+CONFIG_DM_MIRROR=m
+CONFIG_DM_LOG_USERSPACE=m
+CONFIG_DM_RAID=m
+CONFIG_DM_ZERO=m
+CONFIG_DM_MULTIPATH=m
+CONFIG_DM_MULTIPATH_QL=m
+CONFIG_DM_MULTIPATH_ST=m
+CONFIG_DM_DELAY=m
+CONFIG_DM_UEVENT=y
+CONFIG_DM_FLAKEY=m
+CONFIG_DM_VERITY=m
+CONFIG_DM_SWITCH=m
+CONFIG_TARGET_CORE=m
+CONFIG_TCM_IBLOCK=m
+CONFIG_TCM_FILEIO=m
+CONFIG_TCM_PSCSI=m
+CONFIG_LOOPBACK_TARGET=m
+CONFIG_TCM_FC=m
+CONFIG_ISCSI_TARGET=m
+CONFIG_SBP_TARGET=m
+CONFIG_FIREWIRE=m
+CONFIG_FIREWIRE_OHCI=m
+CONFIG_FIREWIRE_SBP2=m
+CONFIG_FIREWIRE_NET=m
+CONFIG_FIREWIRE_NOSY=m
+CONFIG_I2O=m
+CONFIG_I2O_CONFIG=m
+# CONFIG_I2O_CONFIG_OLD_IOCTL is not set
+CONFIG_I2O_BUS=m
+CONFIG_I2O_BLOCK=m
+CONFIG_I2O_SCSI=m
+CONFIG_I2O_PROC=m
+CONFIG_BONDING=m
+CONFIG_DUMMY=m
+CONFIG_EQUALIZER=m
+CONFIG_IFB=m
+CONFIG_NET_TEAM=m
+CONFIG_NET_TEAM_MODE_BROADCAST=m
+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m
+CONFIG_NET_TEAM_MODE_RANDOM=m
+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m
+CONFIG_NET_TEAM_MODE_LOADBALANCE=m
+CONFIG_MACVLAN=m
+CONFIG_MACVTAP=m
+CONFIG_VXLAN=m
+CONFIG_NETCONSOLE=m
+CONFIG_NETCONSOLE_DYNAMIC=y
+CONFIG_NTB_NETDEV=m
+CONFIG_TUN=y
+CONFIG_VETH=m
+CONFIG_VIRTIO_NET=y
+CONFIG_NLMON=m
+# CONFIG_ATM_DRIVERS is not set
+CONFIG_VHOST_NET=m
+CONFIG_VHOST_SCSI=m
+CONFIG_NET_DSA_MV88E6060=m
+CONFIG_NET_DSA_MV88E6131=m
+CONFIG_NET_DSA_MV88E6123_61_65=m
+CONFIG_PCMCIA_3C574=m
+CONFIG_PCMCIA_3C589=m
+CONFIG_VORTEX=m
+CONFIG_TYPHOON=m
+CONFIG_ADAPTEC_STARFIRE=m
+CONFIG_ACENIC=m
+CONFIG_AMD8111_ETH=m
+CONFIG_PCNET32=m
+CONFIG_PCMCIA_NMCLAN=m
+CONFIG_ATL2=m
+CONFIG_ATL1=m
+CONFIG_ATL1E=m
+CONFIG_ATL1C=m
+CONFIG_ALX=m
+CONFIG_B44=m
+CONFIG_TIGON3=m
+CONFIG_BNX2X=m
+CONFIG_BNA=m
+CONFIG_NET_CALXEDA_XGMAC=m
+CONFIG_CHELSIO_T1=m
+CONFIG_CHELSIO_T1_1G=y
+CONFIG_CHELSIO_T4VF=m
+CONFIG_ENIC=m
+CONFIG_DNET=m
+CONFIG_NET_TULIP=y
+CONFIG_DE2104X=m
+CONFIG_TULIP=m
+CONFIG_DE4X5=m
+CONFIG_WINBOND_840=m
+CONFIG_DM9102=m
+CONFIG_ULI526X=m
+CONFIG_PCMCIA_XIRCOM=m
+CONFIG_DL2K=m
+CONFIG_SUNDANCE=m
+CONFIG_BE2NET=m
+CONFIG_S2IO=m
+CONFIG_VXGE=m
+CONFIG_PCMCIA_FMVJ18X=m
+CONFIG_HP100=m
+CONFIG_E100=m
+CONFIG_E1000=m
+CONFIG_E1000E=m
+CONFIG_IGB=m
+CONFIG_IGBVF=m
+CONFIG_IXGB=m
+CONFIG_IXGBE=m
+CONFIG_IXGBE_DCB=y
+CONFIG_IXGBEVF=m
+CONFIG_I40E=m
+CONFIG_I40E_VXLAN=y
+CONFIG_I40E_DCB=y
+CONFIG_I40EVF=m
+CONFIG_IP1000=m
+CONFIG_JME=m
+CONFIG_MVMDIO=m
+CONFIG_SKGE=m
+CONFIG_SKGE_GENESIS=y
+CONFIG_SKY2=m
+CONFIG_MLX4_EN=m
+CONFIG_KS8842=m
+CONFIG_KS8851_MLL=m
+CONFIG_KSZ884X_PCI=m
+CONFIG_MYRI10GE=m
+CONFIG_FEALNX=m
+CONFIG_NATSEMI=m
+CONFIG_NS83820=m
+CONFIG_PCMCIA_AXNET=m
+CONFIG_NE2K_PCI=m
+CONFIG_PCMCIA_PCNET=m
+CONFIG_FORCEDETH=m
+CONFIG_ETHOC=m
+CONFIG_HAMACHI=m
+CONFIG_YELLOWFIN=m
+CONFIG_QLA3XXX=m
+CONFIG_QLCNIC=m
+CONFIG_QLGE=m
+CONFIG_NETXEN_NIC=m
+CONFIG_ATP=m
+CONFIG_8139CP=m
+CONFIG_8139TOO=m
+CONFIG_8139TOO_8129=y
+CONFIG_R8169=m
+CONFIG_SH_ETH=m
+CONFIG_R6040=m
+CONFIG_SC92031=m
+CONFIG_SIS900=m
+CONFIG_SIS190=m
+CONFIG_SFC=m
+CONFIG_PCMCIA_SMC91C92=m
+CONFIG_EPIC100=m
+CONFIG_SMSC911X=m
+CONFIG_SMSC9420=m
+CONFIG_STMMAC_ETH=m
+CONFIG_HAPPYMEAL=m
+CONFIG_SUNGEM=m
+CONFIG_CASSINI=m
+CONFIG_NIU=m
+CONFIG_TEHUTI=m
+CONFIG_TLAN=m
+CONFIG_VIA_RHINE=m
+CONFIG_VIA_RHINE_MMIO=y
+CONFIG_VIA_VELOCITY=m
+CONFIG_WIZNET_W5100=m
+CONFIG_WIZNET_W5300=m
+CONFIG_PCMCIA_XIRC2PS=m
+CONFIG_PHYLIB=y
+CONFIG_AT803X_PHY=y
+CONFIG_AMD_PHY=y
+CONFIG_MARVELL_PHY=y
+CONFIG_DAVICOM_PHY=y
+CONFIG_QSEMI_PHY=y
+CONFIG_LXT_PHY=y
+CONFIG_CICADA_PHY=y
+CONFIG_VITESSE_PHY=y
+CONFIG_SMSC_PHY=y
+CONFIG_BROADCOM_PHY=y
+CONFIG_BCM87XX_PHY=y
+CONFIG_ICPLUS_PHY=y
+CONFIG_REALTEK_PHY=y
+CONFIG_NATIONAL_PHY=y
+CONFIG_STE10XP=y
+CONFIG_LSI_ET1011C_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_FIXED_PHY=y
+CONFIG_MDIO_BITBANG=y
+CONFIG_MDIO_GPIO=y
+CONFIG_PPP=y
+# CONFIG_WLAN is not set
+CONFIG_WAN=y
+# CONFIG_IEEE802154_DRIVERS is not set
+CONFIG_XEN_NETDEV_BACKEND=m
+CONFIG_INPUT_SPARSEKMAP=m
+CONFIG_INPUT_MATRIXKMAP=m
+CONFIG_INPUT_EVDEV=y
+CONFIG_INPUT_EVBUG=m
+# CONFIG_INPUT_KEYBOARD is not set
+# CONFIG_INPUT_MOUSE is not set
+CONFIG_SERIO_SERPORT=m
+CONFIG_SERIO_RAW=m
+CONFIG_VT_HW_CONSOLE_BINDING=y
+CONFIG_DEVPTS_MULTIPLE_INSTANCES=y
+CONFIG_LEGACY_PTY_COUNT=0
+CONFIG_SERIAL_NONSTANDARD=y
+CONFIG_N_HDLC=m
+# CONFIG_DEVKMEM is not set
+CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_CS=m
+CONFIG_SERIAL_8250_NR_UARTS=48
+CONFIG_SERIAL_8250_RUNTIME_UARTS=32
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+CONFIG_SERIAL_8250_DW=m
+CONFIG_SERIAL_KGDB_NMI=y
+CONFIG_SERIAL_MFD_HSU=m
+CONFIG_SERIAL_UARTLITE=m
+CONFIG_SERIAL_JSM=m
+CONFIG_SERIAL_SCCNXP=y
+CONFIG_SERIAL_SCCNXP_CONSOLE=y
+CONFIG_SERIAL_ALTERA_JTAGUART=m
+CONFIG_SERIAL_ALTERA_UART=m
+CONFIG_SERIAL_ARC=m
+CONFIG_SERIAL_RP2=m
+CONFIG_TTY_PRINTK=y
+CONFIG_VIRTIO_CONSOLE=y
+CONFIG_IPMI_HANDLER=y
+CONFIG_IPMI_DEVICE_INTERFACE=m
+CONFIG_IPMI_SI_PROBE_DEFAULTS=y
+CONFIG_IPMI_WATCHDOG=m
+CONFIG_IPMI_POWEROFF=m
+CONFIG_HW_RANDOM=y
+CONFIG_HW_RANDOM_TIMERIOMEM=m
+CONFIG_HW_RANDOM_INTEL=m
+CONFIG_HW_RANDOM_AMD=m
+CONFIG_HW_RANDOM_VIA=m
+CONFIG_HW_RANDOM_VIRTIO=y
+CONFIG_HW_RANDOM_TPM=m
+CONFIG_NVRAM=m
+CONFIG_SYNCLINK_CS=m
+CONFIG_CARDMAN_4000=m
+CONFIG_CARDMAN_4040=m
+CONFIG_IPWIRELESS=m
+CONFIG_RAW_DRIVER=m
+CONFIG_HPET=y
+CONFIG_HANGCHECK_TIMER=m
+CONFIG_TCG_TIS_I2C_ATMEL=m
+CONFIG_TCG_TIS_I2C_INFINEON=m
+CONFIG_TCG_TIS_I2C_NUVOTON=m
+CONFIG_TCG_NSC=m
+CONFIG_TCG_ATMEL=m
+CONFIG_TCG_INFINEON=m
+CONFIG_TCG_ST33_I2C=m
+CONFIG_TCG_XEN=m
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=m
+CONFIG_I2C_MUX=m
+CONFIG_I2C_MUX_GPIO=m
+CONFIG_I2C_MUX_PCA9541=m
+CONFIG_I2C_MUX_PCA954x=m
+CONFIG_I2C_MUX_PINCTRL=m
+CONFIG_I2C_AMD756=m
+CONFIG_I2C_AMD756_S4882=m
+CONFIG_I2C_AMD8111=m
+CONFIG_I2C_I801=m
+CONFIG_I2C_ISCH=m
+CONFIG_I2C_ISMT=m
+CONFIG_I2C_PIIX4=m
+CONFIG_I2C_NFORCE2=m
+CONFIG_I2C_NFORCE2_S4985=m
+CONFIG_I2C_SIS5595=m
+CONFIG_I2C_SIS630=m
+CONFIG_I2C_SIS96X=m
+CONFIG_I2C_VIA=m
+CONFIG_I2C_VIAPRO=m
+CONFIG_I2C_SCMI=m
+CONFIG_I2C_CBUS_GPIO=m
+CONFIG_I2C_DESIGNWARE_PLATFORM=m
+CONFIG_I2C_DESIGNWARE_PCI=m
+CONFIG_I2C_GPIO=m
+CONFIG_I2C_KEMPLD=m
+CONFIG_I2C_OCORES=m
+CONFIG_I2C_PCA_PLATFORM=m
+CONFIG_I2C_SIMTEC=m
+CONFIG_I2C_XILINX=m
+CONFIG_I2C_STUB=m
+CONFIG_PINMUX=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_BAYTRAIL=y
+CONFIG_GPIO_SYSFS=y
+CONFIG_GPIO_GENERIC_PLATFORM=m
+CONFIG_GPIO_SCH=m
+CONFIG_GPIO_ICH=m
+CONFIG_GPIO_VX855=m
+CONFIG_GPIO_LYNXPOINT=y
+CONFIG_W1=m
+# CONFIG_W1_CON is not set
+CONFIG_W1_SLAVE_DS2780=m
+CONFIG_W1_SLAVE_DS2781=m
+CONFIG_POWER_RESET=y
+CONFIG_POWER_AVS=y
+CONFIG_SENSORS_ABITUGURU=m
+CONFIG_SENSORS_ABITUGURU3=m
+CONFIG_SENSORS_AD7414=m
+CONFIG_SENSORS_AD7418=m
+CONFIG_SENSORS_ADM1021=m
+CONFIG_SENSORS_ADM1025=m
+CONFIG_SENSORS_ADM1026=m
+CONFIG_SENSORS_ADM1029=m
+CONFIG_SENSORS_ADM1031=m
+CONFIG_SENSORS_ADM9240=m
+CONFIG_SENSORS_ADT7410=m
+CONFIG_SENSORS_ADT7411=m
+CONFIG_SENSORS_ADT7462=m
+CONFIG_SENSORS_ADT7470=m
+CONFIG_SENSORS_ADT7475=m
+CONFIG_SENSORS_ASC7621=m
+CONFIG_SENSORS_K8TEMP=m
+CONFIG_SENSORS_K10TEMP=m
+CONFIG_SENSORS_FAM15H_POWER=m
+CONFIG_SENSORS_APPLESMC=m
+CONFIG_SENSORS_ASB100=m
+CONFIG_SENSORS_ATXP1=m
+CONFIG_SENSORS_DS620=m
+CONFIG_SENSORS_DS1621=m
+CONFIG_SENSORS_DA9052_ADC=m
+CONFIG_SENSORS_DA9055=m
+CONFIG_SENSORS_I5K_AMB=m
+CONFIG_SENSORS_F71805F=m
+CONFIG_SENSORS_F71882FG=m
+CONFIG_SENSORS_F75375S=m
+CONFIG_SENSORS_MC13783_ADC=m
+CONFIG_SENSORS_FSCHMD=m
+CONFIG_SENSORS_GL518SM=m
+CONFIG_SENSORS_GL520SM=m
+CONFIG_SENSORS_G760A=m
+CONFIG_SENSORS_G762=m
+CONFIG_SENSORS_GPIO_FAN=m
+CONFIG_SENSORS_HIH6130=m
+CONFIG_SENSORS_IBMAEM=m
+CONFIG_SENSORS_IBMPEX=m
+CONFIG_SENSORS_IIO_HWMON=m
+CONFIG_SENSORS_CORETEMP=m
+CONFIG_SENSORS_IT87=m
+CONFIG_SENSORS_JC42=m
+CONFIG_SENSORS_LINEAGE=m
+CONFIG_SENSORS_LTC4151=m
+CONFIG_SENSORS_LTC4215=m
+CONFIG_SENSORS_LTC4245=m
+CONFIG_SENSORS_LTC4261=m
+CONFIG_SENSORS_MAX16065=m
+CONFIG_SENSORS_MAX1619=m
+CONFIG_SENSORS_MAX1668=m
+CONFIG_SENSORS_MAX197=m
+CONFIG_SENSORS_MAX6639=m
+CONFIG_SENSORS_MAX6642=m
+CONFIG_SENSORS_MAX6650=m
+CONFIG_SENSORS_MAX6697=m
+CONFIG_SENSORS_HTU21=m
+CONFIG_SENSORS_MCP3021=m
+CONFIG_SENSORS_LM63=m
+CONFIG_SENSORS_LM73=m
+CONFIG_SENSORS_LM75=m
+CONFIG_SENSORS_LM77=m
+CONFIG_SENSORS_LM78=m
+CONFIG_SENSORS_LM80=m
+CONFIG_SENSORS_LM83=m
+CONFIG_SENSORS_LM85=m
+CONFIG_SENSORS_LM87=m
+CONFIG_SENSORS_LM90=m
+CONFIG_SENSORS_LM92=m
+CONFIG_SENSORS_LM93=m
+CONFIG_SENSORS_LM95234=m
+CONFIG_SENSORS_LM95241=m
+CONFIG_SENSORS_LM95245=m
+CONFIG_SENSORS_PC87360=m
+CONFIG_SENSORS_PC87427=m
+CONFIG_SENSORS_NTC_THERMISTOR=m
+CONFIG_SENSORS_NCT6775=m
+CONFIG_SENSORS_PCF8591=m
+CONFIG_PMBUS=m
+CONFIG_SENSORS_ADM1275=m
+CONFIG_SENSORS_LM25066=m
+CONFIG_SENSORS_LTC2978=m
+CONFIG_SENSORS_MAX16064=m
+CONFIG_SENSORS_MAX34440=m
+CONFIG_SENSORS_MAX8688=m
+CONFIG_SENSORS_UCD9000=m
+CONFIG_SENSORS_UCD9200=m
+CONFIG_SENSORS_ZL6100=m
+CONFIG_SENSORS_SHT15=m
+CONFIG_SENSORS_SHT21=m
+CONFIG_SENSORS_SIS5595=m
+CONFIG_SENSORS_DME1737=m
+CONFIG_SENSORS_EMC1403=m
+CONFIG_SENSORS_EMC2103=m
+CONFIG_SENSORS_EMC6W201=m
+CONFIG_SENSORS_SMSC47M1=m
+CONFIG_SENSORS_SMSC47M192=m
+CONFIG_SENSORS_SMSC47B397=m
+CONFIG_SENSORS_SCH5627=m
+CONFIG_SENSORS_SCH5636=m
+CONFIG_SENSORS_SMM665=m
+CONFIG_SENSORS_ADS1015=m
+CONFIG_SENSORS_ADS7828=m
+CONFIG_SENSORS_AMC6821=m
+CONFIG_SENSORS_INA209=m
+CONFIG_SENSORS_INA2XX=m
+CONFIG_SENSORS_THMC50=m
+CONFIG_SENSORS_TMP102=m
+CONFIG_SENSORS_TMP401=m
+CONFIG_SENSORS_TMP421=m
+CONFIG_SENSORS_VIA_CPUTEMP=m
+CONFIG_SENSORS_VIA686A=m
+CONFIG_SENSORS_VT1211=m
+CONFIG_SENSORS_VT8231=m
+CONFIG_SENSORS_W83781D=m
+CONFIG_SENSORS_W83791D=m
+CONFIG_SENSORS_W83792D=m
+CONFIG_SENSORS_W83793=m
+CONFIG_SENSORS_W83795=m
+CONFIG_SENSORS_W83L785TS=m
+CONFIG_SENSORS_W83L786NG=m
+CONFIG_SENSORS_W83627HF=m
+CONFIG_SENSORS_W83627EHF=m
+CONFIG_SENSORS_WM831X=m
+CONFIG_SENSORS_WM8350=m
+CONFIG_SENSORS_ACPI_POWER=m
+CONFIG_SENSORS_ATK0110=m
+CONFIG_THERMAL_GOV_FAIR_SHARE=y
+CONFIG_THERMAL_EMULATION=y
+CONFIG_INTEL_POWERCLAMP=m
+CONFIG_WATCHDOG=y
+CONFIG_SOFT_WATCHDOG=m
+CONFIG_DA9052_WATCHDOG=m
+CONFIG_DA9055_WATCHDOG=m
+CONFIG_WM831X_WATCHDOG=m
+CONFIG_WM8350_WATCHDOG=m
+CONFIG_RETU_WATCHDOG=m
+CONFIG_ACQUIRE_WDT=m
+CONFIG_ADVANTECH_WDT=m
+CONFIG_ALIM1535_WDT=m
+CONFIG_ALIM7101_WDT=m
+CONFIG_F71808E_WDT=m
+CONFIG_SP5100_TCO=m
+CONFIG_SBC_FITPC2_WATCHDOG=m
+CONFIG_EUROTECH_WDT=m
+CONFIG_IB700_WDT=m
+CONFIG_IBMASR=m
+CONFIG_WAFER_WDT=m
+CONFIG_I6300ESB_WDT=m
+CONFIG_IE6XX_WDT=m
+CONFIG_ITCO_WDT=m
+CONFIG_ITCO_VENDOR_SUPPORT=y
+CONFIG_IT8712F_WDT=m
+CONFIG_IT87_WDT=m
+CONFIG_HP_WATCHDOG=m
+CONFIG_KEMPLD_WDT=m
+CONFIG_SC1200_WDT=m
+CONFIG_PC87413_WDT=m
+CONFIG_NV_TCO=m
+CONFIG_60XX_WDT=m
+CONFIG_CPU5_WDT=m
+CONFIG_SMSC_SCH311X_WDT=m
+CONFIG_SMSC37B787_WDT=m
+CONFIG_VIA_WDT=m
+CONFIG_W83627HF_WDT=m
+CONFIG_W83877F_WDT=m
+CONFIG_W83977F_WDT=m
+CONFIG_MACHZ_WDT=m
+CONFIG_SBC_EPX_C3_WATCHDOG=m
+CONFIG_MEN_A21_WDT=m
+CONFIG_XEN_WDT=m
+CONFIG_PCIPCWATCHDOG=m
+CONFIG_WDTPCI=m
+CONFIG_USBPCWATCHDOG=m
+CONFIG_SSB_DRIVER_GPIO=y
+CONFIG_BCMA=m
+CONFIG_BCMA_HOST_SOC=y
+CONFIG_BCMA_DRIVER_GMAC_CMN=y
+CONFIG_BCMA_DRIVER_GPIO=y
+CONFIG_MFD_CS5535=m
+CONFIG_MFD_AS3711=y
+CONFIG_PMIC_ADP5520=y
+CONFIG_MFD_AAT2870_CORE=y
+CONFIG_MFD_CROS_EC=m
+CONFIG_MFD_CROS_EC_I2C=m
+CONFIG_PMIC_DA903X=y
+CONFIG_MFD_DA9052_I2C=y
+CONFIG_MFD_DA9055=y
+CONFIG_MFD_DA9063=y
+CONFIG_MFD_MC13XXX_I2C=m
+CONFIG_HTC_PASIC3=m
+CONFIG_HTC_I2CPLD=y
+CONFIG_MFD_JANZ_CMODIO=m
+CONFIG_MFD_KEMPLD=m
+CONFIG_MFD_88PM800=m
+CONFIG_MFD_88PM805=m
+CONFIG_MFD_88PM860X=y
+CONFIG_MFD_MAX77686=y
+CONFIG_MFD_MAX77693=y
+CONFIG_MFD_MAX8907=m
+CONFIG_MFD_MAX8925=y
+CONFIG_MFD_MAX8997=y
+CONFIG_MFD_MAX8998=y
+CONFIG_MFD_VIPERBOARD=m
+CONFIG_MFD_RETU=m
+CONFIG_MFD_PCF50633=m
+CONFIG_PCF50633_ADC=m
+CONFIG_PCF50633_GPIO=m
+CONFIG_MFD_RDC321X=m
+CONFIG_MFD_RTSX_PCI=m
+CONFIG_MFD_RC5T583=y
+CONFIG_MFD_SEC_CORE=y
+CONFIG_MFD_SI476X_CORE=m
+CONFIG_MFD_SM501=m
+CONFIG_MFD_SMSC=y
+CONFIG_ABX500_CORE=y
+CONFIG_AB3100_CORE=y
+CONFIG_AB3100_OTP=m
+CONFIG_MFD_SYSCON=y
+CONFIG_MFD_LP8788=y
+CONFIG_MFD_PALMAS=y
+CONFIG_TPS6105X=m
+CONFIG_TPS65010=m
+CONFIG_TPS6507X=m
+CONFIG_MFD_TPS65090=y
+CONFIG_MFD_TPS65217=m
+CONFIG_MFD_TPS6586X=y
+CONFIG_MFD_TPS65910=y
+CONFIG_MFD_TPS65912_I2C=y
+CONFIG_MFD_TPS80031=y
+CONFIG_TWL6040_CORE=y
+CONFIG_MFD_WL1273_CORE=m
+CONFIG_MFD_LM3533=m
+CONFIG_MFD_TIMBERDALE=m
+CONFIG_MFD_TC3589X=y
+CONFIG_MFD_ARIZONA_I2C=m
+CONFIG_MFD_WM5102=y
+CONFIG_MFD_WM5110=y
+CONFIG_MFD_WM8997=y
+CONFIG_MFD_WM8400=y
+CONFIG_MFD_WM831X_I2C=y
+CONFIG_MFD_WM8350_I2C=y
+CONFIG_MFD_WM8994=y
+CONFIG_REGULATOR_VIRTUAL_CONSUMER=m
+CONFIG_REGULATOR_USERSPACE_CONSUMER=m
+CONFIG_REGULATOR_88PM800=m
+CONFIG_REGULATOR_88PM8607=y
+CONFIG_REGULATOR_AD5398=m
+CONFIG_REGULATOR_ANATOP=m
+CONFIG_REGULATOR_AAT2870=m
+CONFIG_REGULATOR_AB3100=m
+CONFIG_REGULATOR_AS3711=m
+CONFIG_REGULATOR_DA903X=m
+CONFIG_REGULATOR_DA9052=m
+CONFIG_REGULATOR_DA9055=m
+CONFIG_REGULATOR_DA9063=m
+CONFIG_REGULATOR_DA9210=m
+CONFIG_REGULATOR_FAN53555=m
+CONFIG_REGULATOR_GPIO=m
+CONFIG_REGULATOR_ISL6271A=m
+CONFIG_REGULATOR_LP3971=m
+CONFIG_REGULATOR_LP3972=m
+CONFIG_REGULATOR_LP872X=y
+CONFIG_REGULATOR_LP8755=m
+CONFIG_REGULATOR_LP8788=y
+CONFIG_REGULATOR_MAX1586=m
+CONFIG_REGULATOR_MAX8649=m
+CONFIG_REGULATOR_MAX8660=m
+CONFIG_REGULATOR_MAX8907=m
+CONFIG_REGULATOR_MAX8925=m
+CONFIG_REGULATOR_MAX8952=m
+CONFIG_REGULATOR_MAX8973=m
+CONFIG_REGULATOR_MAX8997=m
+CONFIG_REGULATOR_MAX8998=m
+CONFIG_REGULATOR_MAX77686=m
+CONFIG_REGULATOR_MAX77693=m
+CONFIG_REGULATOR_MC13783=m
+CONFIG_REGULATOR_MC13892=m
+CONFIG_REGULATOR_PALMAS=m
+CONFIG_REGULATOR_PCF50633=m
+CONFIG_REGULATOR_PFUZE100=m
+CONFIG_REGULATOR_RC5T583=m
+CONFIG_REGULATOR_S5M8767=m
+CONFIG_REGULATOR_TPS51632=m
+CONFIG_REGULATOR_TPS62360=m
+CONFIG_REGULATOR_TPS65023=m
+CONFIG_REGULATOR_TPS6507X=m
+CONFIG_REGULATOR_TPS65090=m
+CONFIG_REGULATOR_TPS65217=m
+CONFIG_REGULATOR_TPS6586X=m
+CONFIG_REGULATOR_TPS65910=m
+CONFIG_REGULATOR_TPS65912=m
+CONFIG_REGULATOR_TPS80031=m
+CONFIG_REGULATOR_WM831X=m
+CONFIG_REGULATOR_WM8350=m
+CONFIG_REGULATOR_WM8400=m
+CONFIG_REGULATOR_WM8994=m
+# CONFIG_VGA_ARB is not set
+CONFIG_DRM=m
+CONFIG_DRM_LOAD_EDID_FIRMWARE=y
+CONFIG_DRM_I2C_NXP_TDA998X=m
+CONFIG_DRM_TDFX=m
+CONFIG_DRM_R128=m
+CONFIG_DRM_RADEON=m
+CONFIG_DRM_RADEON_UMS=y
+CONFIG_DRM_NOUVEAU=m
+CONFIG_DRM_I915=m
+CONFIG_DRM_I915_PRELIMINARY_HW_SUPPORT=y
+CONFIG_DRM_MGA=m
+CONFIG_DRM_VIA=m
+CONFIG_DRM_SAVAGE=m
+CONFIG_DRM_VMWGFX=m
+CONFIG_DRM_VMWGFX_FBCON=y
+CONFIG_DRM_GMA500=m
+CONFIG_DRM_GMA600=y
+CONFIG_DRM_GMA3600=y
+CONFIG_DRM_UDL=m
+CONFIG_DRM_AST=m
+CONFIG_DRM_CIRRUS_QEMU=m
+CONFIG_DRM_QXL=m
+CONFIG_FB=y
+CONFIG_FIRMWARE_EDID=y
+CONFIG_FB_CIRRUS=m
+CONFIG_FB_PM2=m
+CONFIG_FB_PM2_FIFO_DISCONNECT=y
+CONFIG_FB_CYBER2000=m
+CONFIG_FB_ARC=m
+CONFIG_FB_ASILIANT=y
+CONFIG_FB_IMSTT=y
+CONFIG_FB_VGA16=m
+CONFIG_FB_UVESA=m
+CONFIG_FB_VESA=y
+CONFIG_FB_EFI=y
+CONFIG_FB_N411=m
+CONFIG_FB_HGA=m
+CONFIG_FB_S1D13XXX=m
+CONFIG_FB_NVIDIA=m
+CONFIG_FB_NVIDIA_I2C=y
+CONFIG_FB_RIVA=m
+CONFIG_FB_RIVA_I2C=y
+CONFIG_FB_I740=m
+CONFIG_FB_LE80578=m
+CONFIG_FB_CARILLO_RANCH=m
+CONFIG_FB_MATROX=m
+CONFIG_FB_MATROX_MILLENIUM=y
+CONFIG_FB_MATROX_MYSTIQUE=y
+CONFIG_FB_MATROX_G=y
+CONFIG_FB_MATROX_I2C=m
+CONFIG_FB_MATROX_MAVEN=m
+CONFIG_FB_RADEON=m
+CONFIG_FB_ATY128=m
+CONFIG_FB_ATY=m
+CONFIG_FB_ATY_CT=y
+CONFIG_FB_ATY_GX=y
+CONFIG_FB_S3=m
+CONFIG_FB_SAVAGE=m
+CONFIG_FB_SAVAGE_I2C=y
+CONFIG_FB_SIS=m
+CONFIG_FB_SIS_300=y
+CONFIG_FB_SIS_315=y
+CONFIG_FB_VIA=m
+CONFIG_FB_VIA_X_COMPATIBILITY=y
+CONFIG_FB_NEOMAGIC=m
+CONFIG_FB_KYRO=m
+CONFIG_FB_3DFX=m
+CONFIG_FB_3DFX_ACCEL=y
+CONFIG_FB_VOODOO1=m
+CONFIG_FB_VT8623=m
+CONFIG_FB_TRIDENT=m
+CONFIG_FB_ARK=m
+CONFIG_FB_PM3=m
+CONFIG_FB_CARMINE=m
+CONFIG_FB_SM501=m
+CONFIG_FB_SMSCUFX=m
+CONFIG_FB_UDL=m
+CONFIG_XEN_FBDEV_FRONTEND=m
+CONFIG_FB_METRONOME=m
+CONFIG_FB_MB862XX=m
+CONFIG_FB_BROADSHEET=m
+CONFIG_FB_AUO_K190X=m
+CONFIG_FB_AUO_K1900=m
+CONFIG_FB_AUO_K1901=m
+CONFIG_FB_SIMPLE=y
+# CONFIG_LCD_CLASS_DEVICE is not set
+# CONFIG_BACKLIGHT_GENERIC is not set
+# CONFIG_VGA_CONSOLE is not set
+CONFIG_HID=m
+CONFIG_HIDRAW=y
+CONFIG_UHID=m
+CONFIG_HID_A4TECH=m
+CONFIG_HID_ACRUX=m
+CONFIG_HID_ACRUX_FF=y
+CONFIG_HID_APPLE=m
+CONFIG_HID_APPLEIR=m
+CONFIG_HID_AUREAL=m
+CONFIG_HID_BELKIN=m
+CONFIG_HID_CHERRY=m
+CONFIG_HID_CHICONY=m
+CONFIG_HID_CYPRESS=m
+CONFIG_HID_DRAGONRISE=m
+CONFIG_DRAGONRISE_FF=y
+CONFIG_HID_EMS_FF=m
+CONFIG_HID_ELECOM=m
+CONFIG_HID_ELO=m
+CONFIG_HID_EZKEY=m
+CONFIG_HID_HOLTEK=m
+CONFIG_HOLTEK_FF=y
+CONFIG_HID_HUION=m
+CONFIG_HID_KEYTOUCH=m
+CONFIG_HID_KYE=m
+CONFIG_HID_UCLOGIC=m
+CONFIG_HID_WALTOP=m
+CONFIG_HID_GYRATION=m
+CONFIG_HID_ICADE=m
+CONFIG_HID_TWINHAN=m
+CONFIG_HID_KENSINGTON=m
+CONFIG_HID_LCPOWER=m
+CONFIG_HID_LENOVO_TPKBD=m
+CONFIG_HID_LOGITECH=m
+CONFIG_HID_LOGITECH_DJ=m
+CONFIG_LOGITECH_FF=y
+CONFIG_LOGIRUMBLEPAD2_FF=y
+CONFIG_LOGIG940_FF=y
+CONFIG_HID_MAGICMOUSE=m
+CONFIG_HID_MICROSOFT=m
+CONFIG_HID_MONTEREY=m
+CONFIG_HID_MULTITOUCH=m
+CONFIG_HID_NTRIG=m
+CONFIG_HID_ORTEK=m
+CONFIG_HID_PANTHERLORD=m
+CONFIG_PANTHERLORD_FF=y
+CONFIG_HID_PETALYNX=m
+CONFIG_HID_PICOLCD=m
+CONFIG_HID_PICOLCD_FB=y
+CONFIG_HID_PICOLCD_BACKLIGHT=y
+CONFIG_HID_PICOLCD_LEDS=y
+CONFIG_HID_PRIMAX=m
+CONFIG_HID_ROCCAT=m
+CONFIG_HID_SAITEK=m
+CONFIG_HID_SAMSUNG=m
+CONFIG_HID_SONY=m
+CONFIG_SONY_FF=y
+CONFIG_HID_SPEEDLINK=m
+CONFIG_HID_STEELSERIES=m
+CONFIG_HID_SUNPLUS=m
+CONFIG_HID_RMI=m
+CONFIG_HID_GREENASIA=m
+CONFIG_GREENASIA_FF=y
+CONFIG_HID_SMARTJOYPLUS=m
+CONFIG_SMARTJOYPLUS_FF=y
+CONFIG_HID_TIVO=m
+CONFIG_HID_TOPSEED=m
+CONFIG_HID_THINGM=m
+CONFIG_H