/***************************************************************************
 *     Copyright (c) 1999-2010, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Fri May  7 20:17:57 2010
 *                 MD5 Checksum         9170aeef162fecc7d1a70fbd8134c303
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7468/rdb/b0/bchp_sun_top_ctrl.h $
 * 
 * Hydra_Software_Devel/1   5/7/10 11:31p albertl
 * SW7468-226: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_SUN_TOP_CTRL_H__
#define BCHP_SUN_TOP_CTRL_H__

/***************************************************************************
 *SUN_TOP_CTRL - Top Control registers
 ***************************************************************************/
#define BCHP_SUN_TOP_CTRL_PROD_REVISION          0x00304000 /* Product Revision ID */
#define BCHP_SUN_TOP_CTRL_SUN_REVISION           0x00304004 /* Sundry Revision ID */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL             0x00304008 /* Reset control */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL               0x00304010 /* Control register for NMI */
#define BCHP_SUN_TOP_CTRL_SW_RESET               0x00304014 /* Software reset register */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY          0x00304018 /* Reset history */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0          0x0030401c /* Strapping values */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1          0x00304020 /* Strapping values */
#define BCHP_SUN_TOP_CTRL_BOND_STATUS            0x00304024 /* Bond option value register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0      0x00304028 /* OTP option test register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1      0x0030402c /* OTP option test register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0    0x00304030 /* OTP option status register */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1    0x00304034 /* OTP option status register */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0            0x00304038 /* Semaphore channel 0 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1            0x0030403c /* Semaphore channel 1 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2            0x00304040 /* Semaphore channel 2 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3            0x00304044 /* Semaphore channel 3 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4            0x00304048 /* Semaphore channel 4 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5            0x0030404c /* Semaphore channel 5 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6            0x00304050 /* Semaphore channel 6 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7            0x00304054 /* Semaphore channel 7 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8            0x00304058 /* Semaphore channel 8 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9            0x0030405c /* Semaphore channel 9 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10           0x00304060 /* Semaphore channel 10 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11           0x00304064 /* Semaphore channel 11 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12           0x00304068 /* Semaphore channel 12 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13           0x0030406c /* Semaphore channel 13 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14           0x00304070 /* Semaphore channel 14 */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15           0x00304074 /* Semaphore channel 15 */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0         0x00304078 /* General watchdog timer 0 */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1         0x0030407c /* General watchdog timer 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0         0x00304080 /* General control register 0 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1         0x00304084 /* General control register 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2         0x00304088 /* General control register 2 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3         0x0030408c /* General control register 3 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4         0x00304090 /* General control register 4 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5         0x00304094 /* General control register 5 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0       0x00304098 /* General status register 0 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1       0x0030409c /* General status register 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2       0x003040a0 /* General status register 2 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x003040a4 /* General control register without scan 0 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x003040a8 /* General control register without scan 1 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x003040ac /* General control register without scan 2 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x003040b0 /* General control register without scan 3 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x003040b4 /* General control register without scan 4 */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x003040b8 /* General control register without scan 5 */
#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH      0x003040bc /* Scratch register */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL             0x003040c0 /* Spare control bits reserved for future use */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0         0x00304100 /* Pinmux control register 0 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1         0x00304104 /* Pinmux control register 1 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2         0x00304108 /* Pinmux control register 2 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3         0x0030410c /* Pinmux control register 3 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4         0x00304110 /* Pinmux control register 4 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5         0x00304114 /* Pinmux control register 5 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6         0x00304118 /* Pinmux control register 6 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7         0x0030411c /* Pinmux control register 7 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8         0x00304120 /* Pinmux control register 8 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9         0x00304124 /* Pinmux control register 9 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0     0x00304140 /* Pad pull-up/pull-down control register 0 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1     0x00304144 /* Pad pull-up/pull-down control register 1 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2     0x00304148 /* Pad pull-up/pull-down control register 2 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3     0x0030414c /* Pad pull-up/pull-down control register 3 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4     0x00304150 /* Pad pull-up/pull-down control register 4 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5     0x00304154 /* Pad pull-up/pull-down control register 5 */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6     0x00304158 /* Pad pull-up/pull-down control register 6 */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0     0x00304180 /* Bypass clock unselect register 0 */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL         0x00304200 /* Test port control */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK     0x00304204 /* Testport peek register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE     0x00304208 /* Testport poke register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK      0x0030420c /* Testport peek register */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE      0x00304210 /* Testport poke register */
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN         0x00304214 /* EJTAG input bus enables */
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL       0x00304218 /* EJTAG output select */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL        0x0030421c /* UART Router select */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG             0x00304300 /* Serial Slave Port configuration register */
#define BCHP_SUN_TOP_CTRL_SERS_REV               0x00304320 /* SERS Revision Register */
#define BCHP_SUN_TOP_CTRL_SERS_CFG               0x00304324 /* SERS Configuration Register */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL      0x00304400 /* Block select for RO testmode */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL         0x00304500 /* Test_mode control register */
#define BCHP_SUN_TOP_CTRL_TEST_MODE              0x00304504 /* Register source for test_mode */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE          0x00304508 /* Register source for sub_test_mode */
#define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE      0x0030450c /* Final latched testmode value */
#define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE  0x00304510 /* Final latched sub-testmode value */
#define BCHP_SUN_TOP_CTRL_PM_CTRL                0x00304600 /* Control register for Power Controller */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS    0x00304604 /* Power Management IRQ input status */
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT     0x00304608 /* Power Management Wait counter in place of Wait for MIPS IRQ */

/***************************************************************************
 *PROD_REVISION - Product Revision ID
 ***************************************************************************/
/* SUN_TOP_CTRL :: PROD_REVISION :: product_revision [31:00] */
#define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_MASK      0xffffffff
#define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_SHIFT     0

/***************************************************************************
 *SUN_REVISION - Sundry Revision ID
 ***************************************************************************/
/* SUN_TOP_CTRL :: SUN_REVISION :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_MASK              0xffff0000
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_SHIFT             16

/* SUN_TOP_CTRL :: SUN_REVISION :: sundry_revision [15:00] */
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_MASK        0x0000ffff
#define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_SHIFT       0

/***************************************************************************
 *RESET_CTRL - Reset control
 ***************************************************************************/
/* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_monitor [31:31] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_MASK       0x80000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_SHIFT      31

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_monitor [30:30] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_MASK 0x40000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_SHIFT 30

/* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_def_val_monitor [29:29] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_def_val_monitor_MASK 0x20000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_def_val_monitor_SHIFT 29

/* SUN_TOP_CTRL :: RESET_CTRL :: reset_ext_mode_monitor [28:28] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_ext_mode_monitor_MASK   0x10000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_ext_mode_monitor_SHIFT  28

/* SUN_TOP_CTRL :: RESET_CTRL :: reset_timer_205_monitor [27:27] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_205_monitor_MASK  0x08000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_205_monitor_SHIFT 27

/* SUN_TOP_CTRL :: RESET_CTRL :: reset_timer_200_monitor [26:26] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_200_monitor_MASK  0x04000000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_200_monitor_SHIFT 26

/* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [25:12] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK                0x03fff000
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT               12

/* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [11:11] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK      0x00000800
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT     11

/* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable_lock [10:10] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_SHIFT 10

/* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable [09:09] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_SHIFT 9

/* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable_lock [08:08] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_SHIFT 8

/* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable [07:07] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_MASK    0x00000080
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_SHIFT   7

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [06:06] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 6

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable [05:05] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT 5

/* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_polarity [04:04] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT 4

/* SUN_TOP_CTRL :: RESET_CTRL :: master_reset_en [03:03] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_MASK          0x00000008
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_SHIFT         3

/* SUN_TOP_CTRL :: RESET_CTRL :: reserved1 [02:01] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_MASK                0x00000006
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_SHIFT               1

/* SUN_TOP_CTRL :: RESET_CTRL :: sc_insert_reset_en [00:00] */
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_MASK       0x00000001
#define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_SHIFT      0

/***************************************************************************
 *NMI_CTRL - Control register for NMI
 ***************************************************************************/
/* SUN_TOP_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_config_lock_MASK            0x80000000
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_config_lock_SHIFT           31

/* SUN_TOP_CTRL :: NMI_CTRL :: reserved0 [30:03] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_reserved0_MASK                  0x7ffffff8
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_reserved0_SHIFT                 3

/* SUN_TOP_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_pad_monitor_MASK            0x00000004
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT           2

/* SUN_TOP_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_config_nmi_polarity_MASK        0x00000002
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT       1

/* SUN_TOP_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_disable_pad_nmi_MASK            0x00000001
#define BCHP_SUN_TOP_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT           0

/***************************************************************************
 *SW_RESET - Software reset register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SW_RESET :: chip_master_reset [31:31] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_MASK          0x80000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_SHIFT         31

/* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_1shot [30:30] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_MASK         0x40000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_SHIFT        30

/* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_1shot [29:29] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_MASK        0x20000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_SHIFT       29

/* SUN_TOP_CTRL :: SW_RESET :: reserved0 [28:28] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_MASK                  0x10000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_SHIFT                 28

/* SUN_TOP_CTRL :: SW_RESET :: spare_sw_reset [27:27] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_spare_sw_reset_MASK             0x08000000
#define BCHP_SUN_TOP_CTRL_SW_RESET_spare_sw_reset_SHIFT            27

/* SUN_TOP_CTRL :: SW_RESET :: reserved1 [26:22] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved1_MASK                  0x07c00000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved1_SHIFT                 22

/* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_level [21:21] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_MASK        0x00200000
#define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_SHIFT       21

/* SUN_TOP_CTRL :: SW_RESET :: reserved2 [20:17] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved2_MASK                  0x001e0000
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved2_SHIFT                 17

/* SUN_TOP_CTRL :: SW_RESET :: ddr0_sw_reset [16:16] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ddr0_sw_reset_MASK              0x00010000
#define BCHP_SUN_TOP_CTRL_SW_RESET_ddr0_sw_reset_SHIFT             16

/* SUN_TOP_CTRL :: SW_RESET :: memc_0_sw_reset [15:15] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_memc_0_sw_reset_MASK            0x00008000
#define BCHP_SUN_TOP_CTRL_SW_RESET_memc_0_sw_reset_SHIFT           15

/* SUN_TOP_CTRL :: SW_RESET :: m2mc_sw_reset [14:14] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_m2mc_sw_reset_MASK              0x00004000
#define BCHP_SUN_TOP_CTRL_SW_RESET_m2mc_sw_reset_SHIFT             14

/* SUN_TOP_CTRL :: SW_RESET :: usb_sw_reset [13:13] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_usb_sw_reset_MASK               0x00002000
#define BCHP_SUN_TOP_CTRL_SW_RESET_usb_sw_reset_SHIFT              13

/* SUN_TOP_CTRL :: SW_RESET :: vec_sw_reset [12:12] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_vec_sw_reset_MASK               0x00001000
#define BCHP_SUN_TOP_CTRL_SW_RESET_vec_sw_reset_SHIFT              12

/* SUN_TOP_CTRL :: SW_RESET :: bvn_sw_reset [11:11] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_sw_reset_MASK               0x00000800
#define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_sw_reset_SHIFT              11

/* SUN_TOP_CTRL :: SW_RESET :: hdmi_sw_reset [10:10] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_hdmi_sw_reset_MASK              0x00000400
#define BCHP_SUN_TOP_CTRL_SW_RESET_hdmi_sw_reset_SHIFT             10

/* SUN_TOP_CTRL :: SW_RESET :: xpt_sw_reset [09:09] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_MASK               0x00000200
#define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_SHIFT              9

/* SUN_TOP_CTRL :: SW_RESET :: avd0_sw_reset [08:08] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_MASK              0x00000100
#define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_SHIFT             8

/* SUN_TOP_CTRL :: SW_RESET :: aio_sw_reset [07:07] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_aio_sw_reset_MASK               0x00000080
#define BCHP_SUN_TOP_CTRL_SW_RESET_aio_sw_reset_SHIFT              7

/* SUN_TOP_CTRL :: SW_RESET :: rptd_sw_reset [06:06] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_rptd_sw_reset_MASK              0x00000040
#define BCHP_SUN_TOP_CTRL_SW_RESET_rptd_sw_reset_SHIFT             6

/* SUN_TOP_CTRL :: SW_RESET :: jtag_otp_sw_reset [05:05] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_MASK          0x00000020
#define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_SHIFT         5

/* SUN_TOP_CTRL :: SW_RESET :: enet_sw_reset [04:04] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_enet_sw_reset_MASK              0x00000010
#define BCHP_SUN_TOP_CTRL_SW_RESET_enet_sw_reset_SHIFT             4

/* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_level [03:03] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_MASK         0x00000008
#define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_SHIFT        3

/* SUN_TOP_CTRL :: SW_RESET :: ebi_sw_reset [02:02] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_ebi_sw_reset_MASK               0x00000004
#define BCHP_SUN_TOP_CTRL_SW_RESET_ebi_sw_reset_SHIFT              2

/* SUN_TOP_CTRL :: SW_RESET :: reserved3 [01:01] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved3_MASK                  0x00000002
#define BCHP_SUN_TOP_CTRL_SW_RESET_reserved3_SHIFT                 1

/* SUN_TOP_CTRL :: SW_RESET :: sundry_sw_reset [00:00] */
#define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_MASK            0x00000001
#define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_SHIFT           0

/***************************************************************************
 *RESET_HISTORY - Reset history
 ***************************************************************************/
/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:12] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK             0xfffff000
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT            12

/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset [11:11] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_MASK   0x00000800
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_SHIFT  11

/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_sft_sft_rst_b [10:10] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_SHIFT 10

/* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_hrd_sft_rst_b [09:09] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_SHIFT 9

/* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [08:08] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 8

/* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset [07:07] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_MASK  0x00000080
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_SHIFT 7

/* SUN_TOP_CTRL :: RESET_HISTORY :: special_sw_reset [06:06] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_MASK      0x00000040
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_SHIFT     6

/* SUN_TOP_CTRL :: RESET_HISTORY :: reserved1 [05:05] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_MASK             0x00000020
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_SHIFT            5

/* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [04:04] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK  0x00000010
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 4

/* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [03:03] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 3

/* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [02:02] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 2

/* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1

/* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK        0x00000001
#define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT       0

/***************************************************************************
 *STRAP_VALUE_0 - Strapping values
 ***************************************************************************/
/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:06] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK             0xffffffc0
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT            6

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_xtal_highpass [05:05] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_highpass_MASK   0x00000020
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_highpass_SHIFT  5

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_xtal_adj [04:04] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_adj_MASK        0x00000010
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_xtal_adj_SHIFT       4

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_boot_device [03:01] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_device_MASK     0x0000000e
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_boot_device_SHIFT    1

/* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_system_big_endian [00:00] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_system_big_endian_SHIFT 0

/***************************************************************************
 *STRAP_VALUE_1 - Strapping values
 ***************************************************************************/
/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:03] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK             0xfffffff8
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT            3

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_2 [02:02] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_SHIFT 2

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_1_SHIFT 1

/* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_0_SHIFT 0

/***************************************************************************
 *BOND_STATUS - Bond option value register
 ***************************************************************************/
/* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK               0xfffffffe
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT              1

/* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK           0x00000001
#define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT          0

/***************************************************************************
 *OTP_OPTION_TEST_0 - OTP option test register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [31:15] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK         0xffff8000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT        15

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_pwm_pair_disable [14:14] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pwm_pair_disable_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_pwm_pair_disable_SHIFT 14

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_av_output_disable [13:13] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_av_output_disable_SHIFT 13

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_usb_disable [12:12] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_usb_disable_SHIFT 12

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_rave_verify_enable [11:11] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_rave_verify_enable_SHIFT 11

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_audio_spdif_disable [10:10] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_audio_spdif_disable_SHIFT 10

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [09:08] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK  0x00000300
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 8

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [07:07] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 7

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_hd_display [06:06] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_hd_display_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_hd_display_SHIFT 6

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_hdcp_disable [05:05] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_hdcp_disable_SHIFT 5

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_macrovision_enable [04:04] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_enable_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_macrovision_enable_SHIFT 4

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_product_id [03:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_product_id_MASK 0x0000000f
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_product_id_SHIFT 0

/***************************************************************************
 *OTP_OPTION_TEST_1 - OTP option test register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: reserved0 [31:25] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved0_MASK         0xfe000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved0_SHIFT        25

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_8 [24:24] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_8_MASK 0x01000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_8_SHIFT 24

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_7 [23:23] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_7_MASK 0x00800000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_7_SHIFT 23

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_6 [22:22] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_6_MASK 0x00400000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_6_SHIFT 22

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_5 [21:21] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_5_MASK 0x00200000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_5_SHIFT 21

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_4 [20:20] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_4_MASK 0x00100000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_4_SHIFT 20

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_3 [19:19] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_3_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_3_SHIFT 19

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_jtag_otp_2 [18:18] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_2_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_jtag_otp_2_SHIFT 18

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_componentdac_disable [17:17] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_componentdac_disable_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_componentdac_disable_SHIFT 17

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option_chip_id_sel [16:16] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_chip_id_sel_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option_chip_id_sel_SHIFT 16

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: reserved1 [15:04] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved1_MASK         0x0000fff0
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved1_SHIFT        4

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_3 [03:03] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_3_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_3_SHIFT 3

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_2 [02:02] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_2_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_2_SHIFT 2

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_1_SHIFT 1

/* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_bsp_otp_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_bsp_otp_0_SHIFT 0

/***************************************************************************
 *OTP_OPTION_STATUS_0 - OTP option status register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [31:15] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK       0xffff8000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT      15

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_pwm_pair_disable [14:14] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pwm_pair_disable_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_pwm_pair_disable_SHIFT 14

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_av_output_disable [13:13] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_av_output_disable_SHIFT 13

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_usb_disable [12:12] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_usb_disable_SHIFT 12

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_rave_verify_enable [11:11] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_rave_verify_enable_SHIFT 11

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_audio_spdif_disable [10:10] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_audio_spdif_disable_SHIFT 10

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [09:08] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 8

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [07:07] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 7

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_hd_display [06:06] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_hd_display_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_hd_display_SHIFT 6

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_hdcp_disable [05:05] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_hdcp_disable_SHIFT 5

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_macrovision_enable [04:04] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_enable_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_macrovision_enable_SHIFT 4

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_product_id [03:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_product_id_MASK 0x0000000f
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_product_id_SHIFT 0

/***************************************************************************
 *OTP_OPTION_STATUS_1 - OTP option status register
 ***************************************************************************/
/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: reserved0 [31:25] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved0_MASK       0xfe000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved0_SHIFT      25

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_8 [24:24] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_8_MASK 0x01000000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_8_SHIFT 24

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_7 [23:23] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_7_MASK 0x00800000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_7_SHIFT 23

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_6 [22:22] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_6_MASK 0x00400000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_6_SHIFT 22

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_5 [21:21] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_5_MASK 0x00200000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_5_SHIFT 21

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_4 [20:20] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_4_MASK 0x00100000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_4_SHIFT 20

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_3 [19:19] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_3_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_3_SHIFT 19

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_jtag_otp_2 [18:18] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_2_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_jtag_otp_2_SHIFT 18

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_componentdac_disable [17:17] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_componentdac_disable_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_componentdac_disable_SHIFT 17

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option_chip_id_sel [16:16] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_chip_id_sel_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option_chip_id_sel_SHIFT 16

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: reserved1 [15:04] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved1_MASK       0x0000fff0
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved1_SHIFT      4

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_3 [03:03] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_3_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_3_SHIFT 3

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_2 [02:02] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_2_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_2_SHIFT 2

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_1_SHIFT 1

/* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_bsp_otp_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_bsp_otp_0_SHIFT 0

/***************************************************************************
 *SEMAPHORE_0 - Semaphore channel 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_1 - Semaphore channel 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_2 - Semaphore channel 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_3 - Semaphore channel 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_4 - Semaphore channel 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_5 - Semaphore channel 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_6 - Semaphore channel 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_7 - Semaphore channel 7
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_8 - Semaphore channel 8
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_9 - Semaphore channel 9
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK               0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT              8

/* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK          0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT         0

/***************************************************************************
 *SEMAPHORE_10 - Semaphore channel 10
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_11 - Semaphore channel 11
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_12 - Semaphore channel 12
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_13 - Semaphore channel 13
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_14 - Semaphore channel 14
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *SEMAPHORE_15 - Semaphore channel 15
 ***************************************************************************/
/* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK              0xffffff00
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT             8

/* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK         0x000000ff
#define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT        0

/***************************************************************************
 *GEN_WATCHDOG_0 - General watchdog timer 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0

/***************************************************************************
 *GEN_WATCHDOG_1 - General watchdog timer 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_0 - General control register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_MASK            0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_reserved0_SHIFT           2

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: general_ctrl0_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_general_ctrl0_0_SHIFT     0

/***************************************************************************
 *GENERAL_CTRL_1 - General control register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK            0xffff0000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT           16

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_15 [15:15] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_MASK     0x00008000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_15_SHIFT    15

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_14 [14:14] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_MASK     0x00004000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_14_SHIFT    14

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_13 [13:13] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_MASK     0x00002000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_13_SHIFT    13

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_12 [12:12] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_MASK     0x00001000
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_12_SHIFT    12

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: mips_mbist_tm0_reg [11:11] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_mips_mbist_tm0_reg_MASK   0x00000800
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_mips_mbist_tm0_reg_SHIFT  11

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: mips_mbist_tm1_reg [10:10] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_mips_mbist_tm1_reg_MASK   0x00000400
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_mips_mbist_tm1_reg_SHIFT  10

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_9 [09:09] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_MASK      0x00000200
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_9_SHIFT     9

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_8 [08:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_MASK      0x00000100
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_8_SHIFT     8

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_7 [07:07] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_MASK      0x00000080
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_7_SHIFT     7

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_6 [06:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_MASK      0x00000040
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_6_SHIFT     6

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_5 [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_MASK      0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_5_SHIFT     5

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_4 [04:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_MASK      0x00000010
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_4_SHIFT     4

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_3 [03:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_MASK      0x00000008
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_3_SHIFT     3

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_2 [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_MASK      0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_2_SHIFT     2

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: general_ctrl1_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_general_ctrl1_0_SHIFT     0

/***************************************************************************
 *GENERAL_CTRL_2 - General control register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_MASK            0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_reserved0_SHIFT           2

/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl2_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl2_0_SHIFT     0

/***************************************************************************
 *GENERAL_CTRL_3 - General control register 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK            0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT           2

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT     0

/***************************************************************************
 *GENERAL_CTRL_4 - General control register 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK            0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT           2

/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT     0

/***************************************************************************
 *GENERAL_CTRL_5 - General control register 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK            0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT           2

/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT     1

/* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT     0

/***************************************************************************
 *GENERAL_STATUS_0 - General status register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: reserved0 [31:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_MASK          0xfffffff8
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_reserved0_SHIFT         3

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_2 [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_MASK  0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_2_SHIFT 2

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: general_status0_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_MASK  0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_general_status0_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: hif_strap_invalid [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_MASK  0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_hif_strap_invalid_SHIFT 0

/***************************************************************************
 *GENERAL_STATUS_1 - General status register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK          0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT         2

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_MASK  0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: general_status1_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_MASK  0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_general_status1_0_SHIFT 0

/***************************************************************************
 *GENERAL_STATUS_2 - General status register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK          0xffffff00
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT         8

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_07 [07:07] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_07_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_07_SHIFT 7

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_06 [06:06] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_06_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_06_SHIFT 6

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_05 [05:05] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_05_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_05_SHIFT 5

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_04 [04:04] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_04_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_04_SHIFT 4

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_03 [03:03] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_03_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_03_SHIFT 3

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_02 [02:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_02_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_02_SHIFT 2

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_01 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_01_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_01_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_00 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_00_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_00_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0

/***************************************************************************
 *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK    0xfffffffc
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT   2

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1

/* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0

/***************************************************************************
 *UNCLEARED_SCRATCH - Scratch register
 ***************************************************************************/
/* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */
#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0

/***************************************************************************
 *SPARE_CTRL - Spare control bits reserved for future use
 ***************************************************************************/
/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK            0x80000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT           31

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK            0x40000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT           30

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK            0x20000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT           29

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK            0x10000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT           28

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK            0x08000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT           27

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK            0x04000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT           26

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK            0x02000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT           25

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK            0x01000000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT           24

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK            0x00800000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT           23

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK            0x00400000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT           22

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK            0x00200000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT           21

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK            0x00100000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT           20

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK            0x00080000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT           19

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK            0x00040000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT           18

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK            0x00020000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT           17

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK            0x00010000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT           16

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK            0x00008000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT           15

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK            0x00004000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT           14

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK            0x00002000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT           13

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK            0x00001000
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT           12

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK            0x00000800
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT           11

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK            0x00000400
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT           10

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK            0x00000200
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT           9

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK            0x00000100
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT           8

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK            0x00000080
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT           7

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK            0x00000040
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT           6

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK            0x00000020
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT           5

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK            0x00000010
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT           4

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK            0x00000008
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT           3

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK            0x00000004
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT           2

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK            0x00000002
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT           1

/* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK            0x00000001
#define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT           0

/***************************************************************************
 *PIN_MUX_CTRL_0 - Pinmux control register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: nand_data6 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data6_MASK           0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data6_SHIFT          28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data6_NAND_DATA6     0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data6_PM_NAND_DATA6  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data6_TP_OUT_06      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data6_RC_TP_OUT_06   3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: nand_data5 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data5_MASK           0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data5_SHIFT          24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data5_NAND_DATA5     0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data5_PM_NAND_DATA5  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data5_TP_IN_15       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data5_RC_TP_IN_15    3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: nand_data4 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data4_MASK           0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data4_SHIFT          20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data4_NAND_DATA4     0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data4_PM_NAND_DATA4  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data4_TP_IN_14       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data4_RC_TP_IN_14    3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: nand_data3 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data3_MASK           0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data3_SHIFT          16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data3_NAND_DATA3     0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data3_PM_NAND_DATA3  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data3_TP_IN_13       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data3_RC_TP_IN_13    3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: nand_data2 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data2_MASK           0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data2_SHIFT          12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data2_NAND_DATA2     0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data2_PM_NAND_DATA2  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data2_TP_IN_11       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data2_RC_TP_IN_11    3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: nand_data1 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data1_MASK           0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data1_SHIFT          8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data1_NAND_DATA1     0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data1_PM_NAND_DATA1  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data1_TP_IN_10       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data1_RC_TP_IN_10    3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: nand_data0 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data0_MASK           0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data0_SHIFT          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data0_NAND_DATA0     0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data0_PM_NAND_DATA0  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data0_TP_IN_09       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_nand_data0_RC_TP_IN_09    3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: aud0_spdif [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aud0_spdif_MASK           0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aud0_spdif_SHIFT          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aud0_spdif_AUD0_SPDIF     0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aud0_spdif_TP_OUT_14      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_aud0_spdif_RC_TP_OUT_14   2

/***************************************************************************
 *PIN_MUX_CTRL_1 - Pinmux control register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: sf_miso [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_sf_miso_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_sf_miso_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_sf_miso_SF_MISO           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_sf_miso_PM_SF_MISO        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_sf_miso_TP_OUT_16         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_sf_miso_RC_TP_OUT_16      3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: sf_sck [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_sf_sck_MASK               0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_sf_sck_SHIFT              24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_sf_sck_SF_SCK             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_sf_sck_PM_SF_SCK          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_sf_sck_TP_OUT_15          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_sf_sck_RC_TP_OUT_15       3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: nand_rbb [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_rbb_MASK             0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_rbb_SHIFT            20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_rbb_NAND_RBB         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_rbb_PM_NAND_RBB      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_rbb_TP_OUT_13        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_rbb_RC_TP_OUT_13     3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: nand_web [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_web_MASK             0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_web_SHIFT            16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_web_NAND_WEB         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_web_PM_NAND_WEB      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_web_TP_OUT_12        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_web_RC_TP_OUT_12     3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: nand_cle [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_cle_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_cle_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_cle_NAND_CLE         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_cle_PM_NAND_CLE      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_cle_TP_OUT_11        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_cle_RC_TP_OUT_11     3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: nand_reb [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_reb_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_reb_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_reb_NAND_REB         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_reb_PM_NAND_REB      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_reb_TP_OUT_10        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_reb_RC_TP_OUT_10     3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: nand_ale [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_ale_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_ale_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_ale_NAND_ALE         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_ale_PM_NAND_ALE      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_ale_TP_OUT_09        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_ale_RC_TP_OUT_09     3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: nand_data7 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_data7_MASK           0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_data7_SHIFT          0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_data7_NAND_DATA7     0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_data7_PM_NAND_DATA7  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_data7_TP_OUT_07      2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_nand_data7_RC_TP_OUT_07   3

/***************************************************************************
 *PIN_MUX_CTRL_2 - Pinmux control register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: gpio_00 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_00_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_00_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_00_GPIO_00           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_00_VCXO27A           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_00_AUD_FS_CLK0       2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_00_PM_GPIO_00        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_00_TP_IN_26          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_gpio_00_RC_TP_IN_26       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: enet_link [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_enet_link_MASK            0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_enet_link_SHIFT           24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_enet_link_ENET_LINK       0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_enet_link_LED_LD3         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_enet_link_PM_ENET_LINK    2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: enet_activity [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_enet_activity_MASK        0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_enet_activity_SHIFT       20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_enet_activity_ENET_ACTIVITY 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_enet_activity_LED_LD2     1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_enet_activity_PM_ENET_ACTIVITY 2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: usb0_pwron [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_usb0_pwron_MASK           0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_usb0_pwron_SHIFT          16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_usb0_pwron_USB0_PWRON     0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_usb0_pwron_TP_OUT_19      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_usb0_pwron_RC_TP_OUT_19   2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: hif_cs2b [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs2b_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs2b_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs2b_HIF_CS2B         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs2b_PM_HIF_CS2B      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs2b_TP_OUT_18        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs2b_RC_TP_OUT_18     3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: hif_cs1b [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs1b_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs1b_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs1b_HIF_CS1B         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs1b_PM_HIF_CS1B      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs1b_TP_IN_28         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs1b_RC_TP_IN_28      3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: hif_cs0b [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs0b_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs0b_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs0b_HIF_CS0B         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs0b_PM_HIF_CS0B      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs0b_TP_OUT_08        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_hif_cs0b_RC_TP_OUT_08     3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_2 :: sf_mosi [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_sf_mosi_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_sf_mosi_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_sf_mosi_SF_MOSI           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_sf_mosi_PM_SF_MOSI        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_sf_mosi_TP_OUT_17         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_2_sf_mosi_RC_TP_OUT_17      3

/***************************************************************************
 *PIN_MUX_CTRL_3 - Pinmux control register 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_08 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_08_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_08_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_08_GPIO_08           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_08_SDIO_DAT2         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_08_I2S_DATA0         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_08_UART_RTS_0        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_08_PM_GPIO_08        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_08_TP_OUT_27         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_08_RC_TP_OUT_27      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_07 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_07_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_07_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_07_GPIO_07           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_07_SDIO_DAT1         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_07_PWM_1             2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_07_UART_CTS_0        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_07_PM_GPIO_07        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_07_TP_OUT_26         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_07_RC_TP_OUT_26      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_06 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_06_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_06_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_06_GPIO_06           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_06_SDIO_DAT0         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_06_PWM_0             2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_06_PM_GPIO_06        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_06_TP_OUT_25         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_06_RC_TP_OUT_25      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_05 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_05_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_05_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_05_GPIO_05           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_05_SDIO_CLK          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_05_LED_LD8           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_05_PM_GPIO_05        3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_04 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_04_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_04_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_04_GPIO_04           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_04_SDIO_PWR0         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_04_UART_TX1          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_04_PM_GPIO_04        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_04_TP_OUT_23         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_04_RC_TP_OUT_23      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_03 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_03_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_03_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_03_GPIO_03           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_03_SDIO_WPROT        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_03_UART_RX1          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_03_PM_GPIO_03        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_03_TP_IN_23          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_03_RC_TP_IN_23       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_02 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_02_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_02_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_02_GPIO_02           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_02_SDIO_CMD          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_02_UART_TX0          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_02_PM_GPIO_02        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_02_TP_OUT_20         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_02_RC_TP_OUT_20      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_3 :: gpio_01 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_01_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_01_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_01_GPIO_01           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_01_SDIO_DAT3         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_01_UART_RX0          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_01_PM_GPIO_01        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_01_TP_IN_31          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_3_gpio_01_RC_TP_IN_31       5

/***************************************************************************
 *PIN_MUX_CTRL_4 - Pinmux control register 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_16 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_16_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_16_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_16_GPIO_16           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_16_LED_LD5           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_16_MII_RX_CLK        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_16_UART_CTS_0        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_16_TP_IN_16          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_16_RC_TP_IN_16       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_15 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_15_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_15_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_15_GPIO_15           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_15_LED_LD4           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_15_MII_TX_EN         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_15_UART_TX1          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_15_TP_OUT_01         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_15_RC_TP_OUT_01      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_14 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_14_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_14_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_14_GPIO_14           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_14_LED_LD3           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_14_MII_COL           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_14_UART_RX1          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_14_TP_IN_01          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_14_RC_TP_IN_01       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_13 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_13_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_13_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_13_GPIO_13           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_13_LED_LD2           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_13_MII_TX_ER         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_13_UART_TX0          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_13_TP_OUT_00         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_13_RC_TP_OUT_00      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_12 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_12_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_12_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_12_GPIO_12           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_12_LED_LD9           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_12_MII_RX_ER         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_12_UART_RX0          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_12_TP_IN_00          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_12_RC_TP_IN_00       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_11 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_11_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_11_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_11_GPIO_11           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_11_LED_LD8           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_11_MII_RX_EN         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_11_IRQB0             3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_11_TP_IN_07          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_11_RC_TP_IN_07       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_10 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_10_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_10_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_10_GPIO_10           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_10_SDIO_LED          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_10_I2S_CLK0          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_10_UART_RTS_1        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_10_PM_GPIO_10        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_10_TP_IN_12          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_10_RC_TP_IN_12       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_4 :: gpio_09 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_09_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_09_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_09_GPIO_09           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_09_SDIO_PRES         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_09_I2S_LR0           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_09_UART_CTS_1        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_09_PM_GPIO_09        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_09_TP_IN_08          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_4_gpio_09_RC_TP_IN_08       6

/***************************************************************************
 *PIN_MUX_CTRL_5 - Pinmux control register 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_24 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_24_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_24_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_24_GPIO_24           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_24_LED_KD0           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_24_MII_TXD_01        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_24_PKT_SYNC1         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_24_TP_IN_20          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_24_RC_TP_IN_20       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_23 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_23_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_23_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_23_GPIO_23           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_23_LED_LS4           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_23_MII_TXD_02        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_23_PKT_DATA1         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_23_TP_IN_19          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_23_RC_TP_IN_19       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_22 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_22_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_22_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_22_GPIO_22           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_22_LED_LS3           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_22_MII_TXD_03        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_22_PKT_CLK1          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_22_TP_IN_18          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_22_RC_TP_IN_18       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_21 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_21_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_21_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_21_GPIO_21           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_21_LED_LS2           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_21_MII_RXD_00        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_21_PKT_VALID1        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_21_TP_OUT_05         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_21_RC_TP_OUT_05      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_20 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_20_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_20_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_20_GPIO_20           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_20_LED_LS1           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_20_MII_RXD_01        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_20_PKT_ERROR1        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_20_TP_OUT_04         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_20_RC_TP_OUT_04      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_19 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_19_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_19_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_19_GPIO_19           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_19_LED_LS0           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_19_MII_RXD_02        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_19_UART_RTS_1        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_19_IRQB2             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_19_TP_OUT_03         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_19_RC_TP_OUT_03      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_18 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_18_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_18_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_18_GPIO_18           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_18_LED_LD7           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_18_MII_RXD_03        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_18_UART_CTS_1        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_18_IRQB1             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_18_TP_IN_17          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_18_RC_TP_IN_17       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_5 :: gpio_17 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_17_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_17_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_17_GPIO_17           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_17_LED_LD6           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_17_MII_TX_CLK        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_17_UART_RTS_0        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_17_TP_OUT_02         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_5_gpio_17_RC_TP_OUT_02      5

/***************************************************************************
 *PIN_MUX_CTRL_6 - Pinmux control register 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_32 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_32_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_32_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_32_GPIO_32           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_32_PKT_DATA0         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_32_PM_GPIO_32        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_32_TP_OUT_29         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_32_RC_TP_OUT_29      4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_31 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_31_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_31_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_31_GPIO_31           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_31_PKT_CLK0          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_31_PM_GPIO_31        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_31_TP_IN_02          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_31_RC_TP_IN_02       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_30 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_30_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_30_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_30_GPIO_30           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_30_UART_RX0          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_30_UART_RX1          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_30_IRQB1             3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_30_PM_GPIO_30        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_30_TP_IN_30          5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_30_RC_TP_IN_30       6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_29 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_29_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_29_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_29_GPIO_29           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_29_UART_TX0          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_29_UART_TX1          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_29_PM_GPIO_29        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_29_TP_OUT_28         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_29_RC_TP_OUT_28      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_28 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_28_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_28_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_28_GPIO_28           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_28_PWM_0             1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_28_MII_MDC           2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_27 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_27_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_27_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_27_GPIO_27           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_27_LED_KD3           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_27_MII_MDIO          2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_26 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_26_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_26_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_26_GPIO_26           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_26_LED_KD2           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_26_MII_CRS           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_26_TP_IN_22          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_26_RC_TP_IN_22       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_6 :: gpio_25 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_25_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_25_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_25_GPIO_25           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_25_LED_KD1           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_25_MII_TXD_00        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_25_TP_IN_21          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_6_gpio_25_RC_TP_IN_21       4

/***************************************************************************
 *PIN_MUX_CTRL_7 - Pinmux control register 7
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_40 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_40_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_40_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_40_GPIO_40           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_40_NDS_SC_PRES       1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_40_SC_PRES           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_40_PM_GPIO_40        3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_39 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_39_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_39_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_39_GPIO_39           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_39_NDS_SC_IO         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_39_SC_IO             2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_39_PM_GPIO_39        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_39_TP_IN_04          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_39_RC_TP_IN_04       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_38 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_38_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_38_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_38_GPIO_38           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_38_NDS_SC_RST        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_38_SC_RST            2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_38_PM_GPIO_38        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_38_TP_IN_03          4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_38_RC_TP_IN_03       5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_37 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_37_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_37_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_37_GPIO_37           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_37_NDS_SC_CLK        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_37_SC_CLK            2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_37_PM_GPIO_37        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_37_TP_OUT_24         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_37_RC_TP_OUT_24      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_36 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_36_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_36_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_36_GPIO_36           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_36_NDS_SC_VCC        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_36_SC_VCC            2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_36_PM_GPIO_36        3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_36_TP_OUT_22         4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_36_RC_TP_OUT_22      5

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_35 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_35_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_35_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_35_GPIO_35           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_35_PKT_VALID0        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_35_PM_GPIO_35        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_35_TP_OUT_21         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_35_RC_TP_OUT_21      4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_34 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_34_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_34_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_34_GPIO_34           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_34_PKT_ERROR0        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_34_PM_GPIO_34        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_34_TP_IN_06          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_34_RC_TP_IN_06       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_7 :: gpio_33 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_33_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_33_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_33_GPIO_33           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_33_PKT_SYNC0         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_33_PM_GPIO_33        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_33_TP_OUT_30         3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_7_gpio_33_RC_TP_OUT_30      4

/***************************************************************************
 *PIN_MUX_CTRL_8 - Pinmux control register 8
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_48 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_48_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_48_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_48_GPIO_48           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_48_LED_LD1           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_48_PM_GPIO_48        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_48_TP_IN_25          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_48_RC_TP_IN_25       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_47 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_47_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_47_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_47_GPIO_47           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_47_LED_LD0           1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_47_PM_GPIO_47        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_47_TP_IN_24          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_47_RC_TP_IN_24       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_46 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_46_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_46_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_46_GPIO_46           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_46_PKT_ERROR1        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_46_SC_EXT_CLK        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_46_PM_GPIO_46        3

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_45 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_45_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_45_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_45_GPIO_45           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_45_SPI_S_SS0B        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_45_VSYNC             2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_45_IRQB4             3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_45_PM_GPIO_45        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_44 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_44_MASK              0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_44_SHIFT             12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_44_GPIO_44           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_44_SPI_S_MISO        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_44_HSYNC             2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_44_IRQB3             3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_44_PM_GPIO_44        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_43 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_43_MASK              0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_43_SHIFT             8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_43_GPIO_43           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_43_NDS_SC_AUX_1      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_43_I2S_LR0           2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_43_LED_LD2           3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_43_PM_GPIO_43        4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_42 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_MASK              0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_SHIFT             4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_GPIO_42           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_NDS_SC_AUX_0      1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_I2S_DATA0         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_LED_LD5           3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_PM_GPIO_42        4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_TP_OUT_31         5
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_42_RC_TP_OUT_31      6

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_8 :: gpio_41 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_41_MASK              0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_41_SHIFT             0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_41_GPIO_41           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_41_NDS_SC_VPP        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_41_I2S_CLK0          2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_41_IRQB2             3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_8_gpio_41_PM_GPIO_41        4

/***************************************************************************
 *PIN_MUX_CTRL_9 - Pinmux control register 9
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_52 [31:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_52_MASK              0xf0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_52_SHIFT             28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_52_GPIO_52           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_52_PKT_SYNC1         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_52_PM_GPIO_52        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_52_TP_IN_27          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_52_RC_TP_IN_27       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_51 [27:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_51_MASK              0x0f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_51_SHIFT             24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_51_GPIO_51           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_51_PKT_DATA1         1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_51_PM_GPIO_51        2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_51_TP_IN_29          3
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_51_RC_TP_IN_29       4

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_50 [23:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_50_MASK              0x00f00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_50_SHIFT             20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_50_GPIO_50           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_50_PKT_CLK1          1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_50_PM_GPIO_50        2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: gpio_49 [19:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_49_MASK              0x000f0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_49_SHIFT             16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_49_GPIO_49           0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_49_PKT_VALID1        1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_gpio_49_PM_GPIO_49        2

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: sgpio_03 [15:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_03_MASK             0x0000f000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_03_SHIFT            12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_03_SGPIO_03         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_03_BSC_M1_SDA       1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: sgpio_02 [11:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_02_MASK             0x00000f00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_02_SHIFT            8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_02_SGPIO_02         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_02_BSC_M1_SCL       1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: sgpio_01 [07:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_01_MASK             0x000000f0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_01_SHIFT            4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_01_SGPIO_01         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_01_HDMI_BSC_M0_SDA  1

/* SUN_TOP_CTRL :: PIN_MUX_CTRL_9 :: sgpio_00 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_00_MASK             0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_00_SHIFT            0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_00_SGPIO_00         0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_00_HDMI_BSC_M0_SCL  1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_00_TP_IN_05         2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_9_sgpio_00_RC_TP_IN_05      3

/***************************************************************************
 *PIN_MUX_PAD_CTRL_0 - Pad pull-up/pull-down control register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: spare_pad_ctrl_0 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_spare_pad_ctrl_0_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_rbb_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_rbb_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_rbb_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_rbb_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_rbb_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_rbb_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_web_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_web_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_web_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_web_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_web_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_web_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_cle_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_cle_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_cle_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_cle_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_cle_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_cle_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_reb_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_reb_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_reb_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_reb_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_reb_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_reb_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_ale_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_ale_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_ale_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_ale_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_ale_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_ale_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_data7_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data7_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data7_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data7_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data7_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data7_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_data6_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data6_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data6_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data6_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data6_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data6_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_data5_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data5_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data5_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data5_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data5_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data5_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_data4_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data4_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data4_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data4_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data4_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data4_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_data3_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data3_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data3_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data3_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data3_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data3_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_data2_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data2_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data2_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data2_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data2_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data2_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_data1_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data1_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data1_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data1_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data1_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data1_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: nand_data0_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data0_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data0_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data0_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data0_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_nand_data0_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_0 :: reserved0 [03:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_MASK        0x0000000f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_0_reserved0_SHIFT       0

/***************************************************************************
 *PIN_MUX_PAD_CTRL_1 - Pad pull-up/pull-down control register 1
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: spare_pad_ctrl_1 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_spare_pad_ctrl_1_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved0 [29:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_MASK        0x3f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved0_SHIFT       24

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: enet_link_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_enet_link_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_enet_link_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_enet_link_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_enet_link_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_enet_link_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: enet_activity_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_enet_activity_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_enet_activity_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_enet_activity_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_enet_activity_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_enet_activity_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: reserved1 [19:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_MASK        0x000ff000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_reserved1_SHIFT       12

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: hif_cs2b_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs2b_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs2b_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs2b_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs2b_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs2b_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: hif_cs1b_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs1b_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs1b_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs1b_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs1b_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs1b_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: hif_cs0b_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs0b_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs0b_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs0b_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs0b_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_hif_cs0b_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_mosi_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_mosi_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_miso_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_miso_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_1 :: sf_sck_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_MASK  0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_1_sf_sck_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_2 - Pad pull-up/pull-down control register 2
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: spare_pad_ctrl_2 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_spare_pad_ctrl_2_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_14_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_14_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_14_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_14_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_14_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_14_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_13_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_13_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_13_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_13_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_13_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_13_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_12_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_12_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_12_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_12_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_12_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_12_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_11_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_11_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_11_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_11_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_11_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_11_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_10_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_10_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_10_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_10_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_10_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_10_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_09_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_09_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_09_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_09_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_09_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_09_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_08_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_08_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_08_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_08_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_08_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_08_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_07_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_07_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_07_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_07_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_07_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_07_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_06_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_06_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_06_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_06_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_06_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_06_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_05_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_05_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_05_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_05_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_05_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_05_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_04_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_04_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_04_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_04_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_04_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_04_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_03_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_03_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_03_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_03_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_03_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_03_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_02_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_02_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_02_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_02_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_02_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_02_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_01_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_01_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_01_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_01_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_01_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_01_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_2 :: gpio_00_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_00_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_00_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_00_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_00_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_2_gpio_00_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_3 - Pad pull-up/pull-down control register 3
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: spare_pad_ctrl_3 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_spare_pad_ctrl_3_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_29_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_29_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_29_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_29_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_29_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_29_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_28_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_28_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_28_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_28_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_28_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_28_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_27_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_27_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_27_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_27_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_27_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_27_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_26_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_26_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_26_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_26_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_26_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_26_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_25_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_25_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_25_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_25_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_25_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_25_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_24_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_24_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_24_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_24_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_24_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_24_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_23_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_23_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_23_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_23_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_23_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_23_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_22_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_22_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_22_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_22_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_22_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_22_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_21_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_21_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_21_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_21_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_21_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_21_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_20_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_20_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_20_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_20_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_20_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_20_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_19_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_19_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_19_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_19_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_19_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_19_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_18_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_18_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_18_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_18_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_18_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_18_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_17_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_17_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_17_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_17_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_17_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_17_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_16_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_16_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_16_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_16_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_16_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_16_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_3 :: gpio_15_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_15_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_15_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_15_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_15_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_3_gpio_15_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_4 - Pad pull-up/pull-down control register 4
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: spare_pad_ctrl_4 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_spare_pad_ctrl_4_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_44_pad_ctrl [29:28] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_44_pad_ctrl_MASK 0x30000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_44_pad_ctrl_SHIFT 28
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_44_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_44_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_44_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_43_pad_ctrl [27:26] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_43_pad_ctrl_MASK 0x0c000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_43_pad_ctrl_SHIFT 26
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_43_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_43_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_43_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_42_pad_ctrl [25:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_42_pad_ctrl_MASK 0x03000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_42_pad_ctrl_SHIFT 24
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_42_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_42_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_42_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_41_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_41_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_41_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_41_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_41_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_41_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_40_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_40_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_40_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_40_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_40_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_40_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_39_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_39_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_39_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_39_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_39_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_39_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_38_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_38_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_38_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_38_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_38_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_38_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_37_pad_ctrl [15:14] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_37_pad_ctrl_MASK 0x0000c000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_37_pad_ctrl_SHIFT 14
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_37_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_37_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_37_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_36_pad_ctrl [13:12] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_36_pad_ctrl_MASK 0x00003000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_36_pad_ctrl_SHIFT 12
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_36_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_36_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_36_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_35_pad_ctrl [11:10] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_35_pad_ctrl_MASK 0x00000c00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_35_pad_ctrl_SHIFT 10
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_35_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_35_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_35_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_34_pad_ctrl [09:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_34_pad_ctrl_MASK 0x00000300
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_34_pad_ctrl_SHIFT 8
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_34_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_34_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_34_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_33_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_33_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_33_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_33_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_33_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_33_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_32_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_32_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_32_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_32_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_32_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_32_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_31_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_31_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_31_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_31_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_31_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_31_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_4 :: gpio_30_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_30_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_30_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_30_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_30_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_4_gpio_30_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_5 - Pad pull-up/pull-down control register 5
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: spare_pad_ctrl_5 [31:30] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_MASK 0xc0000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_SHIFT 30
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_spare_pad_ctrl_5_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved0 [29:24] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_MASK        0x3f000000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved0_SHIFT       24

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_52_pad_ctrl [23:22] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_52_pad_ctrl_MASK 0x00c00000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_52_pad_ctrl_SHIFT 22
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_52_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_52_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_52_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_51_pad_ctrl [21:20] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_51_pad_ctrl_MASK 0x00300000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_51_pad_ctrl_SHIFT 20
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_51_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_51_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_51_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_50_pad_ctrl [19:18] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_50_pad_ctrl_MASK 0x000c0000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_50_pad_ctrl_SHIFT 18
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_50_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_50_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_50_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_49_pad_ctrl [17:16] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_49_pad_ctrl_MASK 0x00030000
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_49_pad_ctrl_SHIFT 16
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_49_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_49_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_49_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: reserved1 [15:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved1_MASK        0x0000ff00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_reserved1_SHIFT       8

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_48_pad_ctrl [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_48_pad_ctrl_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_48_pad_ctrl_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_48_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_48_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_48_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_47_pad_ctrl [05:04] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_47_pad_ctrl_MASK 0x00000030
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_47_pad_ctrl_SHIFT 4
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_47_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_47_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_47_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_46_pad_ctrl [03:02] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_46_pad_ctrl_MASK 0x0000000c
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_46_pad_ctrl_SHIFT 2
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_46_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_46_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_46_pad_ctrl_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_5 :: gpio_45_pad_ctrl [01:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_45_pad_ctrl_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_45_pad_ctrl_SHIFT 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_45_pad_ctrl_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_45_pad_ctrl_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_5_gpio_45_pad_ctrl_PULL_UP 2

/***************************************************************************
 *PIN_MUX_PAD_CTRL_6 - Pad pull-up/pull-down control register 6
 ***************************************************************************/
/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: reserved0 [31:08] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved0_MASK        0xffffff00
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved0_SHIFT       8

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: spare_pad_ctrl_6 [07:06] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_MASK 0x000000c0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_SHIFT 6
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_NONE 0
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_DOWN 1
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_spare_pad_ctrl_6_PULL_UP 2

/* SUN_TOP_CTRL :: PIN_MUX_PAD_CTRL_6 :: reserved1 [05:00] */
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved1_MASK        0x0000003f
#define BCHP_SUN_TOP_CTRL_PIN_MUX_PAD_CTRL_6_reserved1_SHIFT       0

/***************************************************************************
 *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0
 ***************************************************************************/
/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:20] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK        0xfff00000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT       20

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_dsp_clk [19:19] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_dsp_clk_MASK 0x00080000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_dsp_clk_SHIFT 19

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_avd_clk [18:18] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_avd_clk_MASK 0x00040000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_avd_clk_SHIFT 18

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_obsrv_pll [17:17] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_obsrv_pll_MASK 0x00020000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_obsrv_pll_SHIFT 17

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_216_clk [16:16] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_216_clk_MASK 0x00010000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_216_clk_SHIFT 16

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_cpu_clk [15:15] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_MASK 0x00008000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_cpu_clk_SHIFT 15

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_byp_sys9_clk [14:14] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_sys9_clk_MASK 0x00004000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_byp_sys9_clk_SHIFT 14

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_50 [13:13] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_50_MASK 0x00002000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_50_SHIFT 13

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_49 [12:12] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_49_MASK 0x00001000
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_49_SHIFT 12

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_03 [11:11] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_03_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_03_SHIFT 11

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_02 [10:10] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_02_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_02_SHIFT 10

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_sgpio_01 [09:09] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_sgpio_01_SHIFT 9

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_43 [08:08] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_43_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_43_SHIFT 8

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_41 [07:07] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_41_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_41_SHIFT 7

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_28 [06:06] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_28_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_28_SHIFT 6

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_27 [05:05] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_27_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_27_SHIFT 5

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_gpio_05 [04:04] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_05_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_gpio_05_SHIFT 4

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_enet_link [03:03] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_enet_link_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_enet_link_SHIFT 3

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_enet_activity [02:02] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_enet_activity_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_enet_activity_SHIFT 2

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_usb1_pwrflt [01:01] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb1_pwrflt_MASK 0x00000002
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb1_pwrflt_SHIFT 1

/* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_usb0_pwrflt [00:00] */
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb0_pwrflt_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_usb0_pwrflt_SHIFT 0

/***************************************************************************
 *TEST_PORT_CTRL - Test port control
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sundry_local_tp_out_sel [31:28] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MASK 0xf0000000
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SHIFT 28
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_0 0
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_1 1
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_FP_RST_CNT 2
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MISC_TEST 3
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SSP 4
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_OUT_POKE_REG 5
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_IN 6
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_7 7
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_8 8
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_9 9
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_PWR_CTRL_STATUS 10
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_PWR_CTRL_IRQ_IN 11
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TOP_AUX_TP_OUT 15

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK            0x0ffffc00
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT           10

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK  0x00000200
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK            0x00000180
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT           7

/* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK    0x0000007f
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT   0
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_ENET    0
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CPU     1
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HIF     2
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNM    3
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_HDMI    4
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BVNE    5
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_VEC     6
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_M2MC    7
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_USB     8
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SUN     9
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MAD     10
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_XPT     11
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_RPTD    12
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AIO     13
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD0    14
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BSP     15
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MEMC0   16
#define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UNUSED_127 127

/***************************************************************************
 *TEST_PORT_OUT_PEEK - Testport peek register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0

/***************************************************************************
 *TEST_PORT_OUT_POKE - Testport poke register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0

/***************************************************************************
 *TEST_PORT_IN_PEEK - Testport peek register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0

/***************************************************************************
 *TEST_PORT_IN_POKE - Testport poke register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0

/***************************************************************************
 *EJTAG_INPUT_EN - EJTAG input bus enables
 ***************************************************************************/
/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:04] */
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK            0xfffffff0
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT           4

/* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [03:00] */
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK   0x0000000f
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT  0
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MAIN_MIPS_CPU_ONE_HOT 2
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_AUDIO_ZSP_CPU_ONE_HOT 4
#define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_BSP_8051_CPU_ONE_HOT 8

/***************************************************************************
 *EJTAG_OUTPUT_SEL - EJTAG output select
 ***************************************************************************/
/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:04] */
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK          0xfffffff0
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT         4

/* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [03:00] */
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK   0x0000000f
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT  0
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MAIN_MIPS_CPU 1
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_AUDIO_ZSP_CPU 2
#define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_BSP_8051_CPU 3

/***************************************************************************
 *UART_ROUTER_SEL - UART Router select
 ***************************************************************************/
/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK      0xf0000000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT     28
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK      0x0f000000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT     24
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK      0x00f00000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT     20
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK      0x000f0000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT     16
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK      0x0000f000
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT     12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK      0x00000f00
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT     8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK      0x000000f0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT     4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15

/* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK      0x0000000f
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT     0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU    0
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AUDIO_ZSP 1
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL   2
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL   3
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14
#define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15

/***************************************************************************
 *SSP_CONFIG - Serial Slave Port configuration register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK                0xfffff800
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT               11

/* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK           0x00000780
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT          7

/* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK            0x00000078
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT           3

/* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK              0x00000004
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT             2

/* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK                 0x00000002
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT                1

/* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK        0x00000001
#define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT       0

/***************************************************************************
 *SERS_REV - SERS Revision Register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK                  0xffff0000
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT                 16

/* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK          0x0000ff00
#define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT         8

/* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */
#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK        0x000000ff
#define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT       0

/***************************************************************************
 *SERS_CFG - SERS Configuration Register
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK          0xe0000000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT         29

/* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK                   0x10000000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT                  28
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode     0
#define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode          1

/* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK              0x08000000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT             27

/* union - case mapped_buffer_mode [26:08] */
/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9

/* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8

/* union - case cmd_fifo_mode [26:08] */
/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK    0x07c00000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT   22

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK    0x003e0000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT   17

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK     0x00000c00
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT    10

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK  0x00000200
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9

/* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK    0x00000100
#define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT   8

/* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK                    0x000000fe
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT                   1

/* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK               0x00000001
#define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT              0

/***************************************************************************
 *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
 ***************************************************************************/
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE                0x00304328
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START               0
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END                 7
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE        32

/***************************************************************************
 *SERS_CMD_BUF_%i - Host Serial Write Command Buffer
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK         0xffffffff
#define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT        0


/***************************************************************************
 *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
 ***************************************************************************/
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE               0x00304348
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START              0
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END                1
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE       32

/***************************************************************************
 *SERS_STAT_BUF_%i - Host Serial Read Status Buffer
 ***************************************************************************/
/* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK       0xffffffff
#define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT      0


/***************************************************************************
 *RO_TEST_BLOCK_SEL - Block select for RO testmode
 ***************************************************************************/
/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK         0xffffffe0
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT        5

/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [04:03] */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x00000018
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 3

/* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [02:00] */
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000007
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0
#define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0

/***************************************************************************
 *TEST_MODE_CTRL - Test_mode control register
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_MODE_CTRL :: reserved0 [31:01] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_reserved0_MASK            0xfffffffe
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_reserved0_SHIFT           1

/* SUN_TOP_CTRL :: TEST_MODE_CTRL :: use_test_mode_reg_src [00:00] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_use_test_mode_reg_src_MASK 0x00000001
#define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_use_test_mode_reg_src_SHIFT 0

/***************************************************************************
 *TEST_MODE - Register source for test_mode
 ***************************************************************************/
/* SUN_TOP_CTRL :: TEST_MODE :: reserved0 [31:04] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_MASK                 0xfffffff0
#define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_SHIFT                4

/* SUN_TOP_CTRL :: TEST_MODE :: test_mode [03:00] */
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_MASK                 0x0000000f
#define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_SHIFT                0

/***************************************************************************
 *SUB_TEST_MODE - Register source for sub_test_mode
 ***************************************************************************/
/* SUN_TOP_CTRL :: SUB_TEST_MODE :: reserved0 [31:09] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_reserved0_MASK             0xfffffe00
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_reserved0_SHIFT            9

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [08:08] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT 8

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_mem_bypass_enable [07:07] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_mem_bypass_enable_MASK 0x00000080
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_mem_bypass_enable_SHIFT 7

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_d2cdiff_ac [06:06] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_d2cdiff_ac_SHIFT 6

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_fast_tspi [05:05] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_MASK 0x00000020
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_fast_tspi_SHIFT 5

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_hold_mips_in_reset [04:04] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_MASK 0x00000010
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_hold_mips_in_reset_SHIFT 4

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spi_slave_enable [03:03] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_MASK 0x00000008
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spi_slave_enable_SHIFT 3

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_extend_reset [02:02] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_MASK 0x00000004
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_extend_reset_SHIFT 2

/* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_bsp_debug [01:00] */
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_MASK 0x00000003
#define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_bsp_debug_SHIFT 0

/***************************************************************************
 *LATCHED_TEST_MODE - Final latched testmode value
 ***************************************************************************/
/* SUN_TOP_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */
#define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT 0

/***************************************************************************
 *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value
 ***************************************************************************/
/* SUN_TOP_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */
#define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff
#define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0

/***************************************************************************
 *PM_CTRL - Control register for Power Controller
 ***************************************************************************/
/* SUN_TOP_CTRL :: PM_CTRL :: pm_power_ctrl_disable [31:31] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_power_ctrl_disable_MASK       0x80000000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_power_ctrl_disable_SHIFT      31

/* SUN_TOP_CTRL :: PM_CTRL :: pm_wait_count_upper_bits [30:20] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_count_upper_bits_MASK    0x7ff00000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_count_upper_bits_SHIFT   20

/* SUN_TOP_CTRL :: PM_CTRL :: pm_wait_counter_active [19:19] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_counter_active_MASK      0x00080000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_counter_active_SHIFT     19

/* SUN_TOP_CTRL :: PM_CTRL :: pm_rst_clock_div [18:18] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_rst_clock_div_MASK            0x00040000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_rst_clock_div_SHIFT           18

/* SUN_TOP_CTRL :: PM_CTRL :: pm_pwrdn_pll_req [17:17] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pwrdn_pll_req_MASK            0x00020000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pwrdn_pll_req_SHIFT           17

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_cml_clocks [16:16] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cml_clocks_MASK           0x00010000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cml_clocks_SHIFT          16

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_all_clocks [15:15] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_all_clocks_MASK           0x00008000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_all_clocks_SHIFT          15

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_cpu_clock [14:14] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cpu_clock_MASK            0x00004000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cpu_clock_SHIFT           14

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_avd_rptd_clock [13:13] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_avd_rptd_clock_MASK       0x00002000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_avd_rptd_clock_SHIFT      13

/* SUN_TOP_CTRL :: PM_CTRL :: pm_pll_lock [12:12] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pll_lock_MASK                 0x00001000
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pll_lock_SHIFT                12

/* SUN_TOP_CTRL :: PM_CTRL :: pm_dram_ready_for_pwrdn [11:11] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dram_ready_for_pwrdn_MASK     0x00000800
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dram_ready_for_pwrdn_SHIFT    11

/* SUN_TOP_CTRL :: PM_CTRL :: pm_bsp_ready_for_pwrdn [10:10] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_MASK      0x00000400
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_SHIFT     10

/* SUN_TOP_CTRL :: PM_CTRL :: pm_mips_ready_for_pwrdn [09:09] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_mips_ready_for_pwrdn_MASK     0x00000200
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_mips_ready_for_pwrdn_SHIFT    9

/* SUN_TOP_CTRL :: PM_CTRL :: pm_sec_avd_rptd_clk_disable [08:08] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_sec_avd_rptd_clk_disable_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_sec_avd_rptd_clk_disable_SHIFT 8

/* SUN_TOP_CTRL :: PM_CTRL :: pm_state [07:04] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_MASK                    0x000000f0
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_SHIFT                   4
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_ACTIVE               0
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_PWRDN_RDY            1
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_DISABLE_AVD_RPTD     2
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_DISABLE_CPU          3
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_TRANSITION_TO_STANDBY 4
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_STANDBY              5
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_STANDBY_WITH_PLLS_ON 6
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_RESET_216_108_CLKS   7
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_TRANSITION_TO_ACTIVE 8

/* SUN_TOP_CTRL :: PM_CTRL :: pm_clk_divider_reset_en [03:03] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_clk_divider_reset_en_MASK     0x00000008
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_clk_divider_reset_en_SHIFT    3

/* SUN_TOP_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK      0x00000004
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT     2

/* SUN_TOP_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK         0x00000002
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT        1

/* SUN_TOP_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_start_pwrdn_MASK              0x00000001
#define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT             0

/***************************************************************************
 *PM_IRQ_INPUT_STATUS - Power Management IRQ input status
 ***************************************************************************/
/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: reserved0 [31:09] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_reserved0_MASK       0xfffffe00
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_reserved0_SHIFT      9

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: spare_wakeup_event_0 [08:08] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_spare_wakeup_event_0_MASK 0x00000100
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_spare_wakeup_event_0_SHIFT 8

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: xpt_pmu_wakeup [07:07] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_xpt_pmu_wakeup_MASK  0x00000080
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_xpt_pmu_wakeup_SHIFT 7

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: wol_enet_wakeup [06:06] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_wol_enet_wakeup_MASK 0x00000040
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_wol_enet_wakeup_SHIFT 6

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: gpio_wakeup [05:05] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_gpio_wakeup_MASK     0x00000020
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_gpio_wakeup_SHIFT    5

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: nmi_wakeup [04:04] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_nmi_wakeup_MASK      0x00000010
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_nmi_wakeup_SHIFT     4

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: timer_wakeup [03:03] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_timer_wakeup_MASK    0x00000008
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_timer_wakeup_SHIFT   3

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: kpd_wakeup [02:02] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_kpd_wakeup_MASK      0x00000004
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_kpd_wakeup_SHIFT     2

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: irr_wakeup [01:01] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_irr_wakeup_MASK      0x00000002
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_irr_wakeup_SHIFT     1

/* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: cec_wakeup [00:00] */
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_cec_wakeup_MASK      0x00000001
#define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_cec_wakeup_SHIFT     0

/***************************************************************************
 *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ
 ***************************************************************************/
/* SUN_TOP_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK        0xffff0000
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT       16

/* SUN_TOP_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK 0x0000ffff
#define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0

#endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */

/* End of File */