/***************************************************************************
 *     Copyright (c) 1999-2009, Broadcom Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
 *
 * Module Description:
 *                     DO NOT EDIT THIS FILE DIRECTLY
 *
 * This module was generated magically with RDB from a source description
 * file. You must edit the source file for changes to be made to this file.
 *
 *
 * Date:           Generated on         Wed Nov 18 01:13:42 2009
 *                 MD5 Checksum         8e4822e2d8c445f841e653dc06da5e41
 *
 * Compiled with:  RDB Utility          combo_header.pl
 *                 RDB Parser           3.0
 *                 unknown              unknown
 *                 Perl Interpreter     5.008008
 *                 Operating System     linux
 *
 * Revision History:
 *
 * $brcm_Log: /magnum/basemodules/chp/7340/rdb/b0/bchp_hif_cpu_tp1_intr1.h $
 * 
 * Hydra_Software_Devel/1   11/18/09 6:43a albertl
 * SW7340-102: Initial revision.
 *
 ***************************************************************************/

#ifndef BCHP_HIF_CPU_TP1_INTR1_H__
#define BCHP_HIF_CPU_TP1_INTR1_H__

/***************************************************************************
 *HIF_CPU_TP1_INTR1 - HIF CPU Thread Processor 1 Level 1 Interrupt Controller Registers
 ***************************************************************************/
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS    0x00001600 /* Interrupt Status Register */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS    0x00001604 /* Interrupt Status Register */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS    0x00001608 /* Interrupt Status Register */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS 0x0000160c /* Interrupt Mask Status Register */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS 0x00001610 /* Interrupt Mask Status Register */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS 0x00001614 /* Interrupt Mask Status Register */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET  0x00001618 /* Interrupt Mask Set Register */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET  0x0000161c /* Interrupt Mask Set Register */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET  0x00001620 /* Interrupt Mask Set Register */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR 0x00001624 /* Interrupt Mask Clear Register */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR 0x00001628 /* Interrupt Mask Clear Register */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR 0x0000162c /* Interrupt Mask Clear Register */

/***************************************************************************
 *INTR_W0_STATUS - Interrupt Status Register
 ***************************************************************************/
/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: XPT_RAV_CPU_INTR [31:31] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_XPT_RAV_CPU_INTR_MASK 0x80000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_XPT_RAV_CPU_INTR_SHIFT 31

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AVD0_CPU_INTR_0 [30:30] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AVD0_CPU_INTR_0_MASK 0x40000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AVD0_CPU_INTR_0_SHIFT 30

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: FTM_CPU_INTR [29:29] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_MASK    0x20000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_FTM_CPU_INTR_SHIFT   29

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_CPU_INTR_5 [28:28] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_5_MASK 0x10000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_5_SHIFT 28

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: MC_CPU_INTR [27:27] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MC_CPU_INTR_MASK     0x08000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MC_CPU_INTR_SHIFT    27

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: USB_CPU_INTR [26:26] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_USB_CPU_INTR_MASK    0x04000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_USB_CPU_INTR_SHIFT   26

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: reserved0 [25:25] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_reserved0_MASK       0x02000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_reserved0_SHIFT      25

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: UHF1_CPU_INTR [24:24] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UHF1_CPU_INTR_MASK   0x01000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UHF1_CPU_INTR_SHIFT  24

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: SUN_CPU_INTR [23:23] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_SUN_CPU_INTR_MASK    0x00800000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_SUN_CPU_INTR_SHIFT   23

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: UPG_SC_CPU_INTR [22:22] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UPG_SC_CPU_INTR_MASK 0x00400000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UPG_SC_CPU_INTR_SHIFT 22

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: UPG_UART0_CPU_INTR [21:21] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UPG_UART0_CPU_INTR_MASK 0x00200000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UPG_UART0_CPU_INTR_SHIFT 21

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: UPG_SPI_CPU_INTR [20:20] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UPG_SPI_CPU_INTR_MASK 0x00100000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UPG_SPI_CPU_INTR_SHIFT 20

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: UPG_BSC_CPU_INTR [19:19] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UPG_BSC_CPU_INTR_MASK 0x00080000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UPG_BSC_CPU_INTR_SHIFT 19

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: UPG_CPU_INTR [18:18] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_MASK    0x00040000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UPG_CPU_INTR_SHIFT   18

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: UPG_TMR_CPU_INTR [17:17] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UPG_TMR_CPU_INTR_MASK 0x00020000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_UPG_TMR_CPU_INTR_SHIFT 17

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_SPI_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_SPI_CPU_INTR_SHIFT 16

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GENET_0_A_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_MASK 0x00008000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GENET_0_A_CPU_INTR_SHIFT 15

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: MEMC_0_CPU_INTR [14:14] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC_0_CPU_INTR_MASK 0x00004000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_MEMC_0_CPU_INTR_SHIFT 14

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_CPU_INTR_1 [13:13] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_1_MASK 0x00002000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_1_SHIFT 13

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNF_CPU_INTR_0 [12:12] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_0_MASK 0x00001000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNF_CPU_INTR_0_SHIFT 12

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BVNB_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_CPU_INTR_MASK   0x00000800
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BVNB_CPU_INTR_SHIFT  11

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: VEC_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_VEC_CPU_INTR_MASK    0x00000400
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_VEC_CPU_INTR_SHIFT   10

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: RPTD_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_RPTD_CPU_INTR_MASK   0x00000200
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_RPTD_CPU_INTR_SHIFT  9

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HDMI_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_CPU_INTR_MASK   0x00000100
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HDMI_CPU_INTR_SHIFT  8

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: GFX_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_MASK    0x00000080
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_GFX_CPU_INTR_SHIFT   7

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: AIO_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_MASK    0x00000040
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_AIO_CPU_INTR_SHIFT   6

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: BSP_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_MASK    0x00000020
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_BSP_CPU_INTR_SHIFT   5

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: XPT_ICAM_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_XPT_ICAM_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_XPT_ICAM_CPU_INTR_SHIFT 4

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: XPT_MSG_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_XPT_MSG_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_XPT_MSG_CPU_INTR_SHIFT 3

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: XPT_OVFL_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_XPT_OVFL_CPU_INTR_SHIFT 2

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: XPT_STATUS_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_XPT_STATUS_CPU_INTR_SHIFT 1

/* HIF_CPU_TP1_INTR1 :: INTR_W0_STATUS :: HIF_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_MASK    0x00000001
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_STATUS_HIF_CPU_INTR_SHIFT   0

/***************************************************************************
 *INTR_W1_STATUS - Interrupt Status Register
 ***************************************************************************/
/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB_OHCI_0_CPU_INTR [31:31] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x80000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 31

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB_EHCI_1_CPU_INTR [30:30] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB_EHCI_1_CPU_INTR_MASK 0x40000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB_EHCI_1_CPU_INTR_SHIFT 30

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB_EHCI_0_CPU_INTR [29:29] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x20000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 29

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: XPT_FE_CPU_INTR [28:28] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_XPT_FE_CPU_INTR_MASK 0x10000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_XPT_FE_CPU_INTR_SHIFT 28

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: XPT_PCR_CPU_INTR [27:27] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_XPT_PCR_CPU_INTR_MASK 0x08000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_XPT_PCR_CPU_INTR_SHIFT 27

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: USB_OHCI_1_CPU_INTR [26:26] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB_OHCI_1_CPU_INTR_MASK 0x04000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_USB_OHCI_1_CPU_INTR_SHIFT 26

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: SM_CPU_INTR [25:25] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SM_CPU_INTR_MASK     0x02000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_SM_CPU_INTR_SHIFT    25

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: AFEC_CORE_CPU_INTR [24:24] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_AFEC_CORE_CPU_INTR_MASK 0x01000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_AFEC_CORE_CPU_INTR_SHIFT 24

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: BVNF_CPU_INTR_6 [23:23] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_BVNF_CPU_INTR_6_MASK 0x00800000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_BVNF_CPU_INTR_6_SHIFT 23

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: XPT_MSG_STAT_CPU_INTR [22:22] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00400000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 22

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI1_CPU_INTR [21:21] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_MASK   0x00200000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI1_CPU_INTR_SHIFT  21

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: IPI0_CPU_INTR [20:20] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_MASK   0x00100000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_IPI0_CPU_INTR_SHIFT  20

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_14_CPU_INTR [19:19] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00080000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 19

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_13_CPU_INTR [18:18] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00040000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 18

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_12_CPU_INTR [17:17] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00020000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 17

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_11_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 16

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_10_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00008000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 15

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_9_CPU_INTR [14:14] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_9_CPU_INTR_MASK 0x00004000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_9_CPU_INTR_SHIFT 14

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_8_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_8_CPU_INTR_MASK 0x00002000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_8_CPU_INTR_SHIFT 13

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_7_CPU_INTR [12:12] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_7_CPU_INTR_MASK 0x00001000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_7_CPU_INTR_SHIFT 12

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_6_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_6_CPU_INTR_MASK 0x00000800
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_6_CPU_INTR_SHIFT 11

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_5_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_5_CPU_INTR_MASK 0x00000400
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_5_CPU_INTR_SHIFT 10

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: reserved0 [09:09] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_reserved0_MASK       0x00000200
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_reserved0_SHIFT      9

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_4_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_4_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_4_CPU_INTR_SHIFT 8

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_3_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_3_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_3_CPU_INTR_SHIFT 7

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_2_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_2_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_2_CPU_INTR_SHIFT 6

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_1_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_1_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_1_CPU_INTR_SHIFT 5

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: EXT_IRQ_0_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_0_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_EXT_IRQ_0_CPU_INTR_SHIFT 4

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: QPSK_RCVR_0_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_QPSK_RCVR_0_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_QPSK_RCVR_0_CPU_INTR_SHIFT 3

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCI_INTA_2_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCI_INTA_2_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCI_INTA_2_CPU_INTR_SHIFT 2

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCI_INTA_1_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCI_INTA_1_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCI_INTA_1_CPU_INTR_SHIFT 1

/* HIF_CPU_TP1_INTR1 :: INTR_W1_STATUS :: PCI_INTA_0_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCI_INTA_0_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_STATUS_PCI_INTA_0_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W2_STATUS - Interrupt Status Register
 ***************************************************************************/
/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: reserved0 [31:17] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_MASK       0xfffe0000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved0_SHIFT      17

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: MOCA_GENET_0_B_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_MOCA_GENET_0_B_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_MOCA_GENET_0_B_CPU_INTR_SHIFT 16

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: GENET_0_B_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_GENET_0_B_CPU_INTR_MASK 0x00008000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_GENET_0_B_CPU_INTR_SHIFT 15

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: reserved1 [14:10] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved1_MASK       0x00007c00
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_reserved1_SHIFT      10

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: SUNDRY_PM_INTR_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SUNDRY_PM_INTR_CPU_INTR_MASK 0x00000200
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SUNDRY_PM_INTR_CPU_INTR_SHIFT 9

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: NMI_INTR_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_NMI_INTR_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_NMI_INTR_CPU_INTR_SHIFT 8

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: SDS_RCVR_1_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDS_RCVR_1_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDS_RCVR_1_CPU_INTR_SHIFT 7

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: TFEC_CORE_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_TFEC_CORE_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_TFEC_CORE_CPU_INTR_SHIFT 6

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: QPSK_RCVR_1_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_QPSK_RCVR_1_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_QPSK_RCVR_1_CPU_INTR_SHIFT 5

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: MOCA_GENET_0_A_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_MOCA_GENET_0_A_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_MOCA_GENET_0_A_CPU_INTR_SHIFT 4

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: MOCA_INTR_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_MOCA_INTR_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_MOCA_INTR_CPU_INTR_SHIFT 3

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART2_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART2_CPU_INTR_SHIFT 2

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: UPG_UART1_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_UPG_UART1_CPU_INTR_SHIFT 1

/* HIF_CPU_TP1_INTR1 :: INTR_W2_STATUS :: SDS_RCVR_0_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDS_RCVR_0_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_STATUS_SDS_RCVR_0_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W0_MASK_STATUS - Interrupt Mask Status Register
 ***************************************************************************/
/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: XPT_RAV_CPU_INTR [31:31] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_XPT_RAV_CPU_INTR_MASK 0x80000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_XPT_RAV_CPU_INTR_SHIFT 31

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AVD0_CPU_INTR_0 [30:30] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AVD0_CPU_INTR_0_MASK 0x40000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AVD0_CPU_INTR_0_SHIFT 30

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: FTM_CPU_INTR [29:29] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_MASK 0x20000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_FTM_CPU_INTR_SHIFT 29

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_CPU_INTR_5 [28:28] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_CPU_INTR_5_MASK 0x10000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_CPU_INTR_5_SHIFT 28

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: MC_CPU_INTR [27:27] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MC_CPU_INTR_MASK 0x08000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MC_CPU_INTR_SHIFT 27

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: USB_CPU_INTR [26:26] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_USB_CPU_INTR_MASK 0x04000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_USB_CPU_INTR_SHIFT 26

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: reserved0 [25:25] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_reserved0_MASK  0x02000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_reserved0_SHIFT 25

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: UHF1_CPU_INTR [24:24] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UHF1_CPU_INTR_MASK 0x01000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UHF1_CPU_INTR_SHIFT 24

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: SUN_CPU_INTR [23:23] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_SUN_CPU_INTR_MASK 0x00800000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_SUN_CPU_INTR_SHIFT 23

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: UPG_SC_CPU_INTR [22:22] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UPG_SC_CPU_INTR_MASK 0x00400000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UPG_SC_CPU_INTR_SHIFT 22

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: UPG_UART0_CPU_INTR [21:21] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UPG_UART0_CPU_INTR_MASK 0x00200000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UPG_UART0_CPU_INTR_SHIFT 21

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: UPG_SPI_CPU_INTR [20:20] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UPG_SPI_CPU_INTR_MASK 0x00100000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UPG_SPI_CPU_INTR_SHIFT 20

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: UPG_BSC_CPU_INTR [19:19] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UPG_BSC_CPU_INTR_MASK 0x00080000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UPG_BSC_CPU_INTR_SHIFT 19

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: UPG_CPU_INTR [18:18] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UPG_CPU_INTR_MASK 0x00040000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UPG_CPU_INTR_SHIFT 18

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: UPG_TMR_CPU_INTR [17:17] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UPG_TMR_CPU_INTR_MASK 0x00020000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_UPG_TMR_CPU_INTR_SHIFT 17

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_SPI_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_SPI_CPU_INTR_SHIFT 16

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GENET_0_A_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_MASK 0x00008000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GENET_0_A_CPU_INTR_SHIFT 15

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: MEMC_0_CPU_INTR [14:14] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC_0_CPU_INTR_MASK 0x00004000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_MEMC_0_CPU_INTR_SHIFT 14

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_CPU_INTR_1 [13:13] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_CPU_INTR_1_MASK 0x00002000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_CPU_INTR_1_SHIFT 13

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNF_CPU_INTR_0 [12:12] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_CPU_INTR_0_MASK 0x00001000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNF_CPU_INTR_0_SHIFT 12

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BVNB_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_CPU_INTR_MASK 0x00000800
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BVNB_CPU_INTR_SHIFT 11

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: VEC_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_VEC_CPU_INTR_MASK 0x00000400
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_VEC_CPU_INTR_SHIFT 10

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: RPTD_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_RPTD_CPU_INTR_MASK 0x00000200
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_RPTD_CPU_INTR_SHIFT 9

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HDMI_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HDMI_CPU_INTR_SHIFT 8

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: GFX_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_GFX_CPU_INTR_SHIFT 7

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: AIO_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_AIO_CPU_INTR_SHIFT 6

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: BSP_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_BSP_CPU_INTR_SHIFT 5

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: XPT_ICAM_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_XPT_ICAM_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_XPT_ICAM_CPU_INTR_SHIFT 4

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: XPT_MSG_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_XPT_MSG_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_XPT_MSG_CPU_INTR_SHIFT 3

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: XPT_OVFL_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_XPT_OVFL_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_XPT_OVFL_CPU_INTR_SHIFT 2

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: XPT_STATUS_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_XPT_STATUS_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_XPT_STATUS_CPU_INTR_SHIFT 1

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_STATUS :: HIF_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_STATUS_HIF_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W1_MASK_STATUS - Interrupt Mask Status Register
 ***************************************************************************/
/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB_OHCI_0_CPU_INTR [31:31] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB_OHCI_0_CPU_INTR_MASK 0x80000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB_OHCI_0_CPU_INTR_SHIFT 31

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB_EHCI_1_CPU_INTR [30:30] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB_EHCI_1_CPU_INTR_MASK 0x40000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB_EHCI_1_CPU_INTR_SHIFT 30

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB_EHCI_0_CPU_INTR [29:29] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB_EHCI_0_CPU_INTR_MASK 0x20000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB_EHCI_0_CPU_INTR_SHIFT 29

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: XPT_FE_CPU_INTR [28:28] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_XPT_FE_CPU_INTR_MASK 0x10000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_XPT_FE_CPU_INTR_SHIFT 28

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: XPT_PCR_CPU_INTR [27:27] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_XPT_PCR_CPU_INTR_MASK 0x08000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_XPT_PCR_CPU_INTR_SHIFT 27

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: USB_OHCI_1_CPU_INTR [26:26] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB_OHCI_1_CPU_INTR_MASK 0x04000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_USB_OHCI_1_CPU_INTR_SHIFT 26

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: SM_CPU_INTR [25:25] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SM_CPU_INTR_MASK 0x02000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_SM_CPU_INTR_SHIFT 25

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: AFEC_CORE_CPU_INTR [24:24] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_AFEC_CORE_CPU_INTR_MASK 0x01000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_AFEC_CORE_CPU_INTR_SHIFT 24

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: BVNF_CPU_INTR_6 [23:23] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_BVNF_CPU_INTR_6_MASK 0x00800000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_BVNF_CPU_INTR_6_SHIFT 23

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: XPT_MSG_STAT_CPU_INTR [22:22] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_MASK 0x00400000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_XPT_MSG_STAT_CPU_INTR_SHIFT 22

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI1_CPU_INTR [21:21] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_MASK 0x00200000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI1_CPU_INTR_SHIFT 21

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: IPI0_CPU_INTR [20:20] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_MASK 0x00100000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_IPI0_CPU_INTR_SHIFT 20

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_14_CPU_INTR [19:19] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_14_CPU_INTR_MASK 0x00080000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_14_CPU_INTR_SHIFT 19

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_13_CPU_INTR [18:18] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_13_CPU_INTR_MASK 0x00040000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_13_CPU_INTR_SHIFT 18

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_12_CPU_INTR [17:17] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_12_CPU_INTR_MASK 0x00020000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_12_CPU_INTR_SHIFT 17

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_11_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_11_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_11_CPU_INTR_SHIFT 16

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_10_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_10_CPU_INTR_MASK 0x00008000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_10_CPU_INTR_SHIFT 15

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_9_CPU_INTR [14:14] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_9_CPU_INTR_MASK 0x00004000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_9_CPU_INTR_SHIFT 14

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_8_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_8_CPU_INTR_MASK 0x00002000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_8_CPU_INTR_SHIFT 13

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_7_CPU_INTR [12:12] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_7_CPU_INTR_MASK 0x00001000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_7_CPU_INTR_SHIFT 12

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_6_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_6_CPU_INTR_MASK 0x00000800
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_6_CPU_INTR_SHIFT 11

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_5_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_5_CPU_INTR_MASK 0x00000400
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_5_CPU_INTR_SHIFT 10

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: reserved0 [09:09] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_reserved0_MASK  0x00000200
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_reserved0_SHIFT 9

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_4_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_4_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_4_CPU_INTR_SHIFT 8

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_3_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_3_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_3_CPU_INTR_SHIFT 7

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_2_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_2_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_2_CPU_INTR_SHIFT 6

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_1_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_1_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_1_CPU_INTR_SHIFT 5

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: EXT_IRQ_0_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_0_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_EXT_IRQ_0_CPU_INTR_SHIFT 4

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: QPSK_RCVR_0_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_QPSK_RCVR_0_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_QPSK_RCVR_0_CPU_INTR_SHIFT 3

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCI_INTA_2_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCI_INTA_2_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCI_INTA_2_CPU_INTR_SHIFT 2

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCI_INTA_1_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCI_INTA_1_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCI_INTA_1_CPU_INTR_SHIFT 1

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_STATUS :: PCI_INTA_0_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCI_INTA_0_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_STATUS_PCI_INTA_0_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W2_MASK_STATUS - Interrupt Mask Status Register
 ***************************************************************************/
/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: reserved0 [31:17] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_MASK  0xfffe0000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved0_SHIFT 17

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: MOCA_GENET_0_B_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_MOCA_GENET_0_B_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_MOCA_GENET_0_B_CPU_INTR_SHIFT 16

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: GENET_0_B_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_GENET_0_B_CPU_INTR_MASK 0x00008000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_GENET_0_B_CPU_INTR_SHIFT 15

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: reserved1 [14:10] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved1_MASK  0x00007c00
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_reserved1_SHIFT 10

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: SUNDRY_PM_INTR_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SUNDRY_PM_INTR_CPU_INTR_MASK 0x00000200
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SUNDRY_PM_INTR_CPU_INTR_SHIFT 9

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: NMI_INTR_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_NMI_INTR_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_NMI_INTR_CPU_INTR_SHIFT 8

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: SDS_RCVR_1_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDS_RCVR_1_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDS_RCVR_1_CPU_INTR_SHIFT 7

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: TFEC_CORE_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_TFEC_CORE_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_TFEC_CORE_CPU_INTR_SHIFT 6

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: QPSK_RCVR_1_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_QPSK_RCVR_1_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_QPSK_RCVR_1_CPU_INTR_SHIFT 5

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: MOCA_GENET_0_A_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_MOCA_GENET_0_A_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_MOCA_GENET_0_A_CPU_INTR_SHIFT 4

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: MOCA_INTR_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_MOCA_INTR_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_MOCA_INTR_CPU_INTR_SHIFT 3

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART2_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART2_CPU_INTR_SHIFT 2

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: UPG_UART1_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_UPG_UART1_CPU_INTR_SHIFT 1

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_STATUS :: SDS_RCVR_0_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDS_RCVR_0_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_STATUS_SDS_RCVR_0_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W0_MASK_SET - Interrupt Mask Set Register
 ***************************************************************************/
/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: XPT_RAV_CPU_INTR [31:31] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_XPT_RAV_CPU_INTR_MASK 0x80000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_XPT_RAV_CPU_INTR_SHIFT 31

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AVD0_CPU_INTR_0 [30:30] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AVD0_CPU_INTR_0_MASK 0x40000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AVD0_CPU_INTR_0_SHIFT 30

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: FTM_CPU_INTR [29:29] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_MASK  0x20000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_FTM_CPU_INTR_SHIFT 29

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_CPU_INTR_5 [28:28] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_CPU_INTR_5_MASK 0x10000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_CPU_INTR_5_SHIFT 28

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: MC_CPU_INTR [27:27] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MC_CPU_INTR_MASK   0x08000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MC_CPU_INTR_SHIFT  27

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: USB_CPU_INTR [26:26] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_USB_CPU_INTR_MASK  0x04000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_USB_CPU_INTR_SHIFT 26

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: reserved0 [25:25] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_reserved0_MASK     0x02000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_reserved0_SHIFT    25

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: UHF1_CPU_INTR [24:24] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UHF1_CPU_INTR_MASK 0x01000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UHF1_CPU_INTR_SHIFT 24

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: SUN_CPU_INTR [23:23] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_SUN_CPU_INTR_MASK  0x00800000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_SUN_CPU_INTR_SHIFT 23

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: UPG_SC_CPU_INTR [22:22] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UPG_SC_CPU_INTR_MASK 0x00400000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UPG_SC_CPU_INTR_SHIFT 22

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: UPG_UART0_CPU_INTR [21:21] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UPG_UART0_CPU_INTR_MASK 0x00200000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UPG_UART0_CPU_INTR_SHIFT 21

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: UPG_SPI_CPU_INTR [20:20] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UPG_SPI_CPU_INTR_MASK 0x00100000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UPG_SPI_CPU_INTR_SHIFT 20

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: UPG_BSC_CPU_INTR [19:19] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UPG_BSC_CPU_INTR_MASK 0x00080000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UPG_BSC_CPU_INTR_SHIFT 19

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: UPG_CPU_INTR [18:18] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UPG_CPU_INTR_MASK  0x00040000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UPG_CPU_INTR_SHIFT 18

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: UPG_TMR_CPU_INTR [17:17] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UPG_TMR_CPU_INTR_MASK 0x00020000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_UPG_TMR_CPU_INTR_SHIFT 17

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_SPI_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_SPI_CPU_INTR_SHIFT 16

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GENET_0_A_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_MASK 0x00008000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GENET_0_A_CPU_INTR_SHIFT 15

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: MEMC_0_CPU_INTR [14:14] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC_0_CPU_INTR_MASK 0x00004000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_MEMC_0_CPU_INTR_SHIFT 14

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_CPU_INTR_1 [13:13] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_CPU_INTR_1_MASK 0x00002000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_CPU_INTR_1_SHIFT 13

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNF_CPU_INTR_0 [12:12] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_CPU_INTR_0_MASK 0x00001000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNF_CPU_INTR_0_SHIFT 12

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BVNB_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_CPU_INTR_MASK 0x00000800
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BVNB_CPU_INTR_SHIFT 11

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: VEC_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_VEC_CPU_INTR_MASK  0x00000400
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_VEC_CPU_INTR_SHIFT 10

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: RPTD_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_RPTD_CPU_INTR_MASK 0x00000200
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_RPTD_CPU_INTR_SHIFT 9

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HDMI_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HDMI_CPU_INTR_SHIFT 8

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: GFX_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_MASK  0x00000080
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_GFX_CPU_INTR_SHIFT 7

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: AIO_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_MASK  0x00000040
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_AIO_CPU_INTR_SHIFT 6

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: BSP_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_MASK  0x00000020
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_BSP_CPU_INTR_SHIFT 5

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: XPT_ICAM_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_XPT_ICAM_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_XPT_ICAM_CPU_INTR_SHIFT 4

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: XPT_MSG_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_XPT_MSG_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_XPT_MSG_CPU_INTR_SHIFT 3

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: XPT_OVFL_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_XPT_OVFL_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_XPT_OVFL_CPU_INTR_SHIFT 2

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: XPT_STATUS_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_XPT_STATUS_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_XPT_STATUS_CPU_INTR_SHIFT 1

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_SET :: HIF_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_MASK  0x00000001
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_SET_HIF_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W1_MASK_SET - Interrupt Mask Set Register
 ***************************************************************************/
/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB_OHCI_0_CPU_INTR [31:31] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB_OHCI_0_CPU_INTR_MASK 0x80000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB_OHCI_0_CPU_INTR_SHIFT 31

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB_EHCI_1_CPU_INTR [30:30] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB_EHCI_1_CPU_INTR_MASK 0x40000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB_EHCI_1_CPU_INTR_SHIFT 30

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB_EHCI_0_CPU_INTR [29:29] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB_EHCI_0_CPU_INTR_MASK 0x20000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB_EHCI_0_CPU_INTR_SHIFT 29

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: XPT_FE_CPU_INTR [28:28] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_XPT_FE_CPU_INTR_MASK 0x10000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_XPT_FE_CPU_INTR_SHIFT 28

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: XPT_PCR_CPU_INTR [27:27] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_XPT_PCR_CPU_INTR_MASK 0x08000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_XPT_PCR_CPU_INTR_SHIFT 27

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: USB_OHCI_1_CPU_INTR [26:26] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB_OHCI_1_CPU_INTR_MASK 0x04000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_USB_OHCI_1_CPU_INTR_SHIFT 26

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: SM_CPU_INTR [25:25] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SM_CPU_INTR_MASK   0x02000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_SM_CPU_INTR_SHIFT  25

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: AFEC_CORE_CPU_INTR [24:24] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_AFEC_CORE_CPU_INTR_MASK 0x01000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_AFEC_CORE_CPU_INTR_SHIFT 24

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: BVNF_CPU_INTR_6 [23:23] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_BVNF_CPU_INTR_6_MASK 0x00800000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_BVNF_CPU_INTR_6_SHIFT 23

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: XPT_MSG_STAT_CPU_INTR [22:22] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_XPT_MSG_STAT_CPU_INTR_MASK 0x00400000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_XPT_MSG_STAT_CPU_INTR_SHIFT 22

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI1_CPU_INTR [21:21] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_MASK 0x00200000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI1_CPU_INTR_SHIFT 21

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: IPI0_CPU_INTR [20:20] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_MASK 0x00100000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_IPI0_CPU_INTR_SHIFT 20

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_14_CPU_INTR [19:19] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_14_CPU_INTR_MASK 0x00080000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_14_CPU_INTR_SHIFT 19

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_13_CPU_INTR [18:18] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_13_CPU_INTR_MASK 0x00040000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_13_CPU_INTR_SHIFT 18

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_12_CPU_INTR [17:17] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_12_CPU_INTR_MASK 0x00020000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_12_CPU_INTR_SHIFT 17

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_11_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_11_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_11_CPU_INTR_SHIFT 16

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_10_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_10_CPU_INTR_MASK 0x00008000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_10_CPU_INTR_SHIFT 15

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_9_CPU_INTR [14:14] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_9_CPU_INTR_MASK 0x00004000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_9_CPU_INTR_SHIFT 14

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_8_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_8_CPU_INTR_MASK 0x00002000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_8_CPU_INTR_SHIFT 13

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_7_CPU_INTR [12:12] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_7_CPU_INTR_MASK 0x00001000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_7_CPU_INTR_SHIFT 12

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_6_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_6_CPU_INTR_MASK 0x00000800
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_6_CPU_INTR_SHIFT 11

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_5_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_5_CPU_INTR_MASK 0x00000400
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_5_CPU_INTR_SHIFT 10

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: reserved0 [09:09] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_reserved0_MASK     0x00000200
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_reserved0_SHIFT    9

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_4_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_4_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_4_CPU_INTR_SHIFT 8

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_3_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_3_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_3_CPU_INTR_SHIFT 7

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_2_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_2_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_2_CPU_INTR_SHIFT 6

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_1_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_1_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_1_CPU_INTR_SHIFT 5

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: EXT_IRQ_0_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_0_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_EXT_IRQ_0_CPU_INTR_SHIFT 4

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: QPSK_RCVR_0_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_QPSK_RCVR_0_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_QPSK_RCVR_0_CPU_INTR_SHIFT 3

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCI_INTA_2_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCI_INTA_2_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCI_INTA_2_CPU_INTR_SHIFT 2

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCI_INTA_1_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCI_INTA_1_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCI_INTA_1_CPU_INTR_SHIFT 1

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_SET :: PCI_INTA_0_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCI_INTA_0_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_SET_PCI_INTA_0_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W2_MASK_SET - Interrupt Mask Set Register
 ***************************************************************************/
/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: reserved0 [31:17] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_MASK     0xfffe0000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved0_SHIFT    17

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: MOCA_GENET_0_B_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_MOCA_GENET_0_B_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_MOCA_GENET_0_B_CPU_INTR_SHIFT 16

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: GENET_0_B_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_GENET_0_B_CPU_INTR_MASK 0x00008000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_GENET_0_B_CPU_INTR_SHIFT 15

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: reserved1 [14:10] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved1_MASK     0x00007c00
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_reserved1_SHIFT    10

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: SUNDRY_PM_INTR_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SUNDRY_PM_INTR_CPU_INTR_MASK 0x00000200
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SUNDRY_PM_INTR_CPU_INTR_SHIFT 9

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: NMI_INTR_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_NMI_INTR_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_NMI_INTR_CPU_INTR_SHIFT 8

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: SDS_RCVR_1_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDS_RCVR_1_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDS_RCVR_1_CPU_INTR_SHIFT 7

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: TFEC_CORE_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_TFEC_CORE_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_TFEC_CORE_CPU_INTR_SHIFT 6

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: QPSK_RCVR_1_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_QPSK_RCVR_1_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_QPSK_RCVR_1_CPU_INTR_SHIFT 5

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: MOCA_GENET_0_A_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_MOCA_GENET_0_A_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_MOCA_GENET_0_A_CPU_INTR_SHIFT 4

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: MOCA_INTR_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_MOCA_INTR_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_MOCA_INTR_CPU_INTR_SHIFT 3

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART2_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART2_CPU_INTR_SHIFT 2

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: UPG_UART1_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_UPG_UART1_CPU_INTR_SHIFT 1

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_SET :: SDS_RCVR_0_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDS_RCVR_0_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_SET_SDS_RCVR_0_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register
 ***************************************************************************/
/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: XPT_RAV_CPU_INTR [31:31] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_XPT_RAV_CPU_INTR_MASK 0x80000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_XPT_RAV_CPU_INTR_SHIFT 31

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AVD0_CPU_INTR_0 [30:30] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AVD0_CPU_INTR_0_MASK 0x40000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AVD0_CPU_INTR_0_SHIFT 30

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: FTM_CPU_INTR [29:29] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_MASK 0x20000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_FTM_CPU_INTR_SHIFT 29

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_CPU_INTR_5 [28:28] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_CPU_INTR_5_MASK 0x10000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_CPU_INTR_5_SHIFT 28

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: MC_CPU_INTR [27:27] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MC_CPU_INTR_MASK 0x08000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MC_CPU_INTR_SHIFT 27

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: USB_CPU_INTR [26:26] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_USB_CPU_INTR_MASK 0x04000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_USB_CPU_INTR_SHIFT 26

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: reserved0 [25:25] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_reserved0_MASK   0x02000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_reserved0_SHIFT  25

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: UHF1_CPU_INTR [24:24] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UHF1_CPU_INTR_MASK 0x01000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UHF1_CPU_INTR_SHIFT 24

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: SUN_CPU_INTR [23:23] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_SUN_CPU_INTR_MASK 0x00800000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_SUN_CPU_INTR_SHIFT 23

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_SC_CPU_INTR [22:22] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UPG_SC_CPU_INTR_MASK 0x00400000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UPG_SC_CPU_INTR_SHIFT 22

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_UART0_CPU_INTR [21:21] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UPG_UART0_CPU_INTR_MASK 0x00200000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UPG_UART0_CPU_INTR_SHIFT 21

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_SPI_CPU_INTR [20:20] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UPG_SPI_CPU_INTR_MASK 0x00100000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UPG_SPI_CPU_INTR_SHIFT 20

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_BSC_CPU_INTR [19:19] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UPG_BSC_CPU_INTR_MASK 0x00080000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UPG_BSC_CPU_INTR_SHIFT 19

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_CPU_INTR [18:18] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UPG_CPU_INTR_MASK 0x00040000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UPG_CPU_INTR_SHIFT 18

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: UPG_TMR_CPU_INTR [17:17] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UPG_TMR_CPU_INTR_MASK 0x00020000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_UPG_TMR_CPU_INTR_SHIFT 17

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_SPI_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_SPI_CPU_INTR_SHIFT 16

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GENET_0_A_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_MASK 0x00008000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GENET_0_A_CPU_INTR_SHIFT 15

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: MEMC_0_CPU_INTR [14:14] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC_0_CPU_INTR_MASK 0x00004000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_MEMC_0_CPU_INTR_SHIFT 14

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_CPU_INTR_1 [13:13] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_CPU_INTR_1_MASK 0x00002000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_CPU_INTR_1_SHIFT 13

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNF_CPU_INTR_0 [12:12] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_CPU_INTR_0_MASK 0x00001000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNF_CPU_INTR_0_SHIFT 12

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BVNB_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_CPU_INTR_MASK 0x00000800
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BVNB_CPU_INTR_SHIFT 11

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: VEC_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_VEC_CPU_INTR_MASK 0x00000400
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_VEC_CPU_INTR_SHIFT 10

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: RPTD_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_RPTD_CPU_INTR_MASK 0x00000200
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_RPTD_CPU_INTR_SHIFT 9

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HDMI_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HDMI_CPU_INTR_SHIFT 8

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: GFX_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_GFX_CPU_INTR_SHIFT 7

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: AIO_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_AIO_CPU_INTR_SHIFT 6

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: BSP_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_BSP_CPU_INTR_SHIFT 5

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: XPT_ICAM_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_XPT_ICAM_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_XPT_ICAM_CPU_INTR_SHIFT 4

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: XPT_MSG_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_XPT_MSG_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_XPT_MSG_CPU_INTR_SHIFT 3

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: XPT_OVFL_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_XPT_OVFL_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_XPT_OVFL_CPU_INTR_SHIFT 2

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: XPT_STATUS_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_XPT_STATUS_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_XPT_STATUS_CPU_INTR_SHIFT 1

/* HIF_CPU_TP1_INTR1 :: INTR_W0_MASK_CLEAR :: HIF_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W0_MASK_CLEAR_HIF_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register
 ***************************************************************************/
/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB_OHCI_0_CPU_INTR [31:31] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB_OHCI_0_CPU_INTR_MASK 0x80000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB_OHCI_0_CPU_INTR_SHIFT 31

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB_EHCI_1_CPU_INTR [30:30] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB_EHCI_1_CPU_INTR_MASK 0x40000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB_EHCI_1_CPU_INTR_SHIFT 30

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB_EHCI_0_CPU_INTR [29:29] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB_EHCI_0_CPU_INTR_MASK 0x20000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB_EHCI_0_CPU_INTR_SHIFT 29

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: XPT_FE_CPU_INTR [28:28] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_XPT_FE_CPU_INTR_MASK 0x10000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_XPT_FE_CPU_INTR_SHIFT 28

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: XPT_PCR_CPU_INTR [27:27] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_XPT_PCR_CPU_INTR_MASK 0x08000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_XPT_PCR_CPU_INTR_SHIFT 27

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: USB_OHCI_1_CPU_INTR [26:26] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB_OHCI_1_CPU_INTR_MASK 0x04000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_USB_OHCI_1_CPU_INTR_SHIFT 26

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: SM_CPU_INTR [25:25] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SM_CPU_INTR_MASK 0x02000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_SM_CPU_INTR_SHIFT 25

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: AFEC_CORE_CPU_INTR [24:24] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_AFEC_CORE_CPU_INTR_MASK 0x01000000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_AFEC_CORE_CPU_INTR_SHIFT 24

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: BVNF_CPU_INTR_6 [23:23] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_BVNF_CPU_INTR_6_MASK 0x00800000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_BVNF_CPU_INTR_6_SHIFT 23

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: XPT_MSG_STAT_CPU_INTR [22:22] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_MASK 0x00400000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_XPT_MSG_STAT_CPU_INTR_SHIFT 22

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI1_CPU_INTR [21:21] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_MASK 0x00200000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI1_CPU_INTR_SHIFT 21

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: IPI0_CPU_INTR [20:20] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_MASK 0x00100000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_IPI0_CPU_INTR_SHIFT 20

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_14_CPU_INTR [19:19] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_MASK 0x00080000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_14_CPU_INTR_SHIFT 19

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_13_CPU_INTR [18:18] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_MASK 0x00040000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_13_CPU_INTR_SHIFT 18

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_12_CPU_INTR [17:17] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_MASK 0x00020000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_12_CPU_INTR_SHIFT 17

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_11_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_11_CPU_INTR_SHIFT 16

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_10_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_MASK 0x00008000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_10_CPU_INTR_SHIFT 15

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_9_CPU_INTR [14:14] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_9_CPU_INTR_MASK 0x00004000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_9_CPU_INTR_SHIFT 14

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_8_CPU_INTR [13:13] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_8_CPU_INTR_MASK 0x00002000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_8_CPU_INTR_SHIFT 13

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_7_CPU_INTR [12:12] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_7_CPU_INTR_MASK 0x00001000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_7_CPU_INTR_SHIFT 12

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_6_CPU_INTR [11:11] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_6_CPU_INTR_MASK 0x00000800
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_6_CPU_INTR_SHIFT 11

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_5_CPU_INTR [10:10] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_5_CPU_INTR_MASK 0x00000400
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_5_CPU_INTR_SHIFT 10

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: reserved0 [09:09] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_reserved0_MASK   0x00000200
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_reserved0_SHIFT  9

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_4_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_4_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_4_CPU_INTR_SHIFT 8

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_3_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_3_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_3_CPU_INTR_SHIFT 7

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_2_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_2_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_2_CPU_INTR_SHIFT 6

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_1_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_1_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_1_CPU_INTR_SHIFT 5

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: EXT_IRQ_0_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_0_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_EXT_IRQ_0_CPU_INTR_SHIFT 4

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: QPSK_RCVR_0_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_QPSK_RCVR_0_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_QPSK_RCVR_0_CPU_INTR_SHIFT 3

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCI_INTA_2_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCI_INTA_2_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCI_INTA_2_CPU_INTR_SHIFT 2

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCI_INTA_1_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCI_INTA_1_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCI_INTA_1_CPU_INTR_SHIFT 1

/* HIF_CPU_TP1_INTR1 :: INTR_W1_MASK_CLEAR :: PCI_INTA_0_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCI_INTA_0_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W1_MASK_CLEAR_PCI_INTA_0_CPU_INTR_SHIFT 0

/***************************************************************************
 *INTR_W2_MASK_CLEAR - Interrupt Mask Clear Register
 ***************************************************************************/
/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: reserved0 [31:17] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_MASK   0xfffe0000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved0_SHIFT  17

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: MOCA_GENET_0_B_CPU_INTR [16:16] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_MOCA_GENET_0_B_CPU_INTR_MASK 0x00010000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_MOCA_GENET_0_B_CPU_INTR_SHIFT 16

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: GENET_0_B_CPU_INTR [15:15] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_GENET_0_B_CPU_INTR_MASK 0x00008000
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_GENET_0_B_CPU_INTR_SHIFT 15

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: reserved1 [14:10] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved1_MASK   0x00007c00
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_reserved1_SHIFT  10

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: SUNDRY_PM_INTR_CPU_INTR [09:09] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SUNDRY_PM_INTR_CPU_INTR_MASK 0x00000200
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SUNDRY_PM_INTR_CPU_INTR_SHIFT 9

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: NMI_INTR_CPU_INTR [08:08] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_NMI_INTR_CPU_INTR_MASK 0x00000100
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_NMI_INTR_CPU_INTR_SHIFT 8

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: SDS_RCVR_1_CPU_INTR [07:07] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDS_RCVR_1_CPU_INTR_MASK 0x00000080
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDS_RCVR_1_CPU_INTR_SHIFT 7

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: TFEC_CORE_CPU_INTR [06:06] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_TFEC_CORE_CPU_INTR_MASK 0x00000040
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_TFEC_CORE_CPU_INTR_SHIFT 6

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: QPSK_RCVR_1_CPU_INTR [05:05] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_QPSK_RCVR_1_CPU_INTR_MASK 0x00000020
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_QPSK_RCVR_1_CPU_INTR_SHIFT 5

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: MOCA_GENET_0_A_CPU_INTR [04:04] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_MOCA_GENET_0_A_CPU_INTR_MASK 0x00000010
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_MOCA_GENET_0_A_CPU_INTR_SHIFT 4

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: MOCA_INTR_CPU_INTR [03:03] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_MOCA_INTR_CPU_INTR_MASK 0x00000008
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_MOCA_INTR_CPU_INTR_SHIFT 3

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART2_CPU_INTR [02:02] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_MASK 0x00000004
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART2_CPU_INTR_SHIFT 2

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: UPG_UART1_CPU_INTR [01:01] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_MASK 0x00000002
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_UPG_UART1_CPU_INTR_SHIFT 1

/* HIF_CPU_TP1_INTR1 :: INTR_W2_MASK_CLEAR :: SDS_RCVR_0_CPU_INTR [00:00] */
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDS_RCVR_0_CPU_INTR_MASK 0x00000001
#define BCHP_HIF_CPU_TP1_INTR1_INTR_W2_MASK_CLEAR_SDS_RCVR_0_CPU_INTR_SHIFT 0

#endif /* #ifndef BCHP_HIF_CPU_TP1_INTR1_H__ */

/* End of File */