blob: 220a6e624d2b4bd1255644c38b8680ffff0e2559 [file] [log] [blame]
<?xml version="1.0"?>
<cnfg>
<eth_complex_config>
<!-- 1=TPM_PON_WAN_DUAL_MAC_INT_SWITCH 2=TPM_PON_WAN_G0_INT_SWITCH 3=TPM_PON_WAN_G1_LAN_G0_INT_SWITCH 4=TPM_G0_WAN_G1_INT_SWITCH
5=TPM_G1_WAN_G0_INT_SWITCH 6=TPM_PON_G1_WAN_G0_INT_SWITCH 7=TPM_PON_G0_WAN_G1_INT_SWITCH 8=TPM_PON_WAN_DUAL_MAC_EXT_SWITCH
9=TPM_PON_WAN_G1_MNG_EXT_SWITCH 10=TPM_PON_WAN_G0_SINGLE_PORT 11=TPM_PON_WAN_G1_SINGLE_PORT 12=TPM_PON_G1_WAN_G0_SINGLE_PORT
13=TPM_PON_G0_WAN_G1_SINGLE_PORT 14=TPM_PON_WAN_G0_G1_LPBK 15=TPM_PON_WAN_G0_G1_DUAL_LAN 16=TPM_PON_WAN_G0_SINGLE_PORT_SGMII
17=TPM_PON_G1_SGMII_WAN_G0_SINGLE_PORT
-->
<profile>17</profile>
<!-- src 0) TPM_SRC_PORT_UNI_0
1) TPM_SRC_PORT_UNI_1
...
7) TPM_SRC_PORT_UNI7 -->
<switch_ports>
<port id="0" src_port="0"/>
<port id="1" src_port="1"/>
<port id="2" src_port="2"/>
<port id="3" src_port="3"/>
</switch_ports>
<gmac_ports>
<port id="0" src_port="0"/>
</gmac_ports>
<!-- active_wan 0=TPM_ENUM_GMAC_0 1=TPM_ENUM_GMAC_1 2=TPM_ENUM_PMAC -->
<active_wan>1</active_wan>
</eth_complex_config>
<traffic_setting>
<!-- pppoe_add_enable: 0 = disable, 1 = enable
Indicates system can be required to insert pppoe_header in upstream for routed/napt traffic.-->
<pppoe_add_enable>1</pppoe_add_enable>
<!-- Maximum required number of Vlan Tags.
Influences the modification chain_size and the max. mru -->
<num_vlan_tags>2</num_vlan_tags>
<!-- Action for packets with illegal TTL -->
<!-- 0 = no action, 1 = drop, 2 = trap to CPU -->
<ttl_illegal_action>2</ttl_illegal_action>
<!-- Check TCP FIN & RES flags, to trap 5-tuples w/ these flags raised to CPU -->
<!-- 0 = do not check, 1 = check -->
<tcp_flag_check>1</tcp_flag_check>
<!-- CPU Rx Queue for all trapped packets (trapped due to packet TTL , TCP flags, ) -->
<cpu_trap_rx_queue>0</cpu_trap_rx_queue>
<!-- Put Switch Port connected to packet Processor in EtherType_DSA_Tag mode -->
<ety_dsa_enable>0</ety_dsa_enable>
</traffic_setting>
<mtu_setting>
<!-- mtu_setting_enabled: 0 = disable, 1 = enable
Indicates if Layer3 Hardware_forward packets that are (> MTU) must be trapped to CPU -->
<mtu_setting_enabled>0</mtu_setting_enabled>
<!-- In GPON US, the max packet size PON MAC can handle is 2000 -->
<!-- IPv4oE downstream mtu -->
<ipv4_mtu_ds>1978 </ipv4_mtu_ds>
<!-- IPv4oE upstream mtu
MTU=2000-DA(6)-SA(6)-2*VLAN(4)-ETY(2) -->
<ipv4_mtu_us>1978</ipv4_mtu_us>
<!-- IPv4oPPPoE upstream mtu (for routed/napt traffic w/ pppoe_hdr insertion), also dependent on <pppoe_add_enable> -->
<!-- MTU=2000-DA(6)-SA(6)-2*VLAN(4)-ETY(2)-PPPoE HEADER(8) -->
<ipv4_pppoe_mtu_us>1970</ipv4_pppoe_mtu_us>
</mtu_setting>
<igmp_snoop>
<!-- Snooping enabled: 0 = FALSE, 1 = TRUE
When set to TRUE, the igmp_range must be created, and the following params determine igmp behavior -->
<enabled>1</enabled>
<!-- CPU rx queue for trapped IGMP packets: 0 -7 -->
<igmp_cpu_rx_queue>7</igmp_cpu_rx_queue>
<!-- Per UNI IGMP packet forwarding mode :
0 = drop, 1 = forward, 2= snoop -->
<igmp_frwrd_mode_wan>2</igmp_frwrd_mode_wan>
<igmp_frwrd_mode_uni0>2</igmp_frwrd_mode_uni0>
<igmp_frwrd_mode_uni1>2</igmp_frwrd_mode_uni1>
<igmp_frwrd_mode_uni2>2</igmp_frwrd_mode_uni2>
<igmp_frwrd_mode_uni3>2</igmp_frwrd_mode_uni3>
<igmp_frwrd_mode_uni4>2</igmp_frwrd_mode_uni4>
</igmp_snoop>
<multicast>
<!-- Multicast over PPPoE allowed: (0 = FALSE, 1 = TRUE) -->
<mc_pppoe_enable>1</mc_pppoe_enable>
<!-- Per UNI Vlan translation: 0 = no_per_uni_translation, 1 = per_uni_translation
when this feature is enabled, range size of TPM_PNC_VIRT_UNI must be increased by 4 -->
<mc_per_uni_vlan_xlat>0</mc_per_uni_vlan_xlat>
<!-- Multicast per uni vlan xlat support for IPv4/6: 0 = no support, 1 = support -->
<ipv4_mc_support>1</ipv4_mc_support>
<ipv6_mc_support>1</ipv6_mc_support>
<!-- Multicast filtering mode -->
<!-- 0 = Forward all Multicast traffic to CPU
1 = Multicast traffic is forwarded to the Internal Switch, where it is filtered based on MAC_DA.
2 = Multicast traffic is filtered in packet processor according to (vid, dip, sip).
The stream specific target uni_port(s) are determined in Internal Switch based on MAC_DA
3 = Multicast traffic is forwarded exclusively by (vid, dip, sip) including setting the target uni_ports -->
<mc_filter_mode>3</mc_filter_mode>
<!-- Multicast hwf queue: Set to highest txq of GMAC0, whose owner is PMAC. -->
<mc_hwf_queue>7</mc_hwf_queue>
<!-- Multicast cpu queue: Set to highest PMAC rx queue -->
<mc_cpu_queue>0</mc_cpu_queue>
</multicast>
<port_init>
<gmac_config>
<pon_config>
<!-- Max. number of configured TCONTs(GPON), LLIDs(EPON) -->
<num_tcont_llid>8</num_tcont_llid>
</pon_config>
<gmac_mh_en>
<!-- GMAC Marvell_Header configuration - GMAC adds 2B Marvell header at beginning of packet
mh_enabled 0 = FALSE, 1 = TRUE, 2 = AUTO (enabled if connected to Switch) -->
<gmac0_mh_en>0</gmac0_mh_en>
<gmac1_mh_en>0</gmac1_mh_en>
</gmac_mh_en>
<gmac_bm_buffers>
<!-- BM pool buffers per MAC -->
<!-- id=0 (GMAC0), id=1(GMAC1), id=2(PON_MAC) -->
<!-- Number of buffers for large packets must be ( >= 128) -->
<!-- Number of buffers for small packets must each be ( >= 128) -->
<!-- Undefined BM Pools will receive kernel default values -->
<!-- If interfaces are raised before TPM is initialized, the <gmac_bm_buffers> definitions will have no effect,
kernel default values are used instead. -->
<gmac id="0" large_pkt_pool_bufs="2048" small_pkt_pool_bufs="4096" />
<gmac id="1" large_pkt_pool_bufs="2048" small_pkt_pool_bufs="4096" />
<gmac id="2" large_pkt_pool_bufs="128" small_pkt_pool_bufs="512" />
</gmac_bm_buffers>
<gmac_rx_queues>
<!-- Rx queue sizes per MAC -->
<!-- id=0 (GMAC0), id=1(GMAC1), id=2(PON_MAC) -->
<!-- size must be >0 -->
<!-- Undefined queues will be set to size=0 in hardware -->
<!-- If interfaces are raised before TPM is initialized, the <gmac_rx_queues> definitions will have no effect,
kernel default values are used instead. -->
<gmac id="0">
<queue id="0" size="128"/>
<queue id="1" size="128"/>
<queue id="2" size="128"/>
<queue id="3" size="128"/>
<queue id="4" size="128"/>
<queue id="5" size="128"/>
<queue id="6" size="128"/>
<queue id="7" size="128"/>
</gmac>
<gmac id="1">
<queue id="0" size="128"/>
<queue id="1" size="128"/>
<queue id="2" size="128"/>
<queue id="3" size="128"/>
<queue id="4" size="128"/>
<queue id="5" size="128"/>
<queue id="6" size="128"/>
<queue id="7" size="128"/>
</gmac>
<gmac id="2">
<queue id="0" size="128"/>
<queue id="1" size="128"/>
<queue id="2" size="128"/>
<queue id="3" size="128"/>
<queue id="4" size="128"/>
<queue id="5" size="128"/>
<queue id="6" size="128"/>
<queue id="7" size="128"/>
</gmac>
</gmac_rx_queues>
</gmac_config>
<tx_module_parameters>
<!-- id : 0 = GMAC0, 1 = GMAC1, 2 = PMAC_0, 3 = PMAC_1, 4 = PMAC_2, 5 = PMAC_3, -->
<!-- : 6 = PMAC_4, 7 = PMAC_5, 8 = PMAC_6, 9 = PMAC_7 -->
<tx_mod id="0">
<!-- id : queue number -->
<!-- sched_method: 0 = STRICT, 1 = WRR -->
<!-- owner : 0 = CPU, 1 = GMAC0, 2 = GMAC1, 3 = PMAC -->
<!-- owner_q_num : owner queue number -->
<!-- size : queue size must be >0 -->
<!-- Undefined queues will not be created in hardware -->
<queue_map>
<queue id="0" sched_method="0" owner="0" owner_q_num="0" size="0256" weight="0" />
<queue id="1" sched_method="0" owner="2" owner_q_num="0" size="0256" weight="0" />
<queue id="2" sched_method="0" owner="0" owner_q_num="1" size="0256" weight="0" />
<queue id="3" sched_method="0" owner="2" owner_q_num="1" size="0256" weight="0" />
<queue id="4" sched_method="0" owner="0" owner_q_num="2" size="0256" weight="0" />
<queue id="5" sched_method="0" owner="2" owner_q_num="2" size="0256" weight="0" />
<queue id="6" sched_method="0" owner="0" owner_q_num="3" size="0256" weight="0" />
<queue id="7" sched_method="0" owner="2" owner_q_num="3" size="0256" weight="0" />
</queue_map>
</tx_mod>
<!-- id : 0 = GMAC0, 1 = GMAC1, 2 = PMAC_0, 3 = PMAC_1, 4 = PMAC_2, 5 = PMAC_3, -->
<!-- : 6 = PMAC_4, 7 = PMAC_5, 8 = PMAC_6, 9 = PMAC_7 -->
<tx_mod id="1">
<!-- id : queue number -->
<!-- sched_method: 0 = STRICT, 1 = WRR -->
<!-- owner : 0 = CPU, 1 = GMAC0, 2 = GMAC1, 3 = PMAC -->
<!-- owner_q_num : owner queue number -->
<!-- size : queue size must be >0 -->
<!-- Undefined queues will not be created in hardware -->
<queue_map>
<queue id="0" sched_method="0" owner="0" owner_q_num="0" size="0256" weight="0" />
<queue id="1" sched_method="0" owner="1" owner_q_num="0" size="0256" weight="0" />
<queue id="2" sched_method="0" owner="0" owner_q_num="1" size="0256" weight="0" />
<queue id="3" sched_method="0" owner="1" owner_q_num="1" size="0256" weight="0" />
<queue id="4" sched_method="0" owner="0" owner_q_num="2" size="0256" weight="0" />
<queue id="5" sched_method="0" owner="1" owner_q_num="2" size="0256" weight="0" />
<queue id="6" sched_method="0" owner="0" owner_q_num="3" size="0256" weight="0" />
<queue id="7" sched_method="0" owner="1" owner_q_num="3" size="0256" weight="0" />
</queue_map>
</tx_mod>
<!-- id : 0 = GMAC0, 1 = GMAC1, 2 = PMAC_0, 3 = PMAC_1, 4 = PMAC_2, 5 = PMAC_3, -->
<!-- : 6 = PMAC_4, 7 = PMAC_5, 8 = PMAC_6, 9 = PMAC_7 -->
<tx_mod id="2">
<!-- id : queue number -->
<!-- sched_method: 0 = STRICT, 1 = WRR -->
<!-- owner : 0 = CPU, 1 = GMAC0, 2 = GMAC1, 3 = PMAC -->
<!-- owner_q_num : owner queue number -->
<!-- size : queue size must be >0 -->
<!-- Undefined queues will not be created in hardware -->
<queue_map>
<queue id="0" sched_method="0" owner="0" owner_q_num="0" size="1024" weight="0" />
<queue id="1" sched_method="0" owner="1" owner_q_num="0" size="1024" weight="0" />
<queue id="2" sched_method="0" owner="0" owner_q_num="1" size="1024" weight="0" />
<queue id="3" sched_method="0" owner="1" owner_q_num="1" size="1024" weight="0" />
<queue id="4" sched_method="0" owner="0" owner_q_num="2" size="1024" weight="0" />
<queue id="5" sched_method="0" owner="1" owner_q_num="2" size="1024" weight="0" />
<queue id="6" sched_method="0" owner="0" owner_q_num="3" size="1024" weight="0" />
<queue id="7" sched_method="0" owner="1" owner_q_num="3" size="1024" weight="0" />
</queue_map>
</tx_mod>
<!-- id : 0 = GMAC0, 1 = GMAC1, 2 = PMAC_0, 3 = PMAC_1, 4 = PMAC_2, 5 = PMAC_3, -->
<!-- : 6 = PMAC_4, 7 = PMAC_5, 8 = PMAC_6, 9 = PMAC_7 -->
<tx_mod id="3">
<!-- id : queue number -->
<!-- sched_method: 0 = STRICT, 1 = WRR -->
<!-- owner : 0 = CPU, 1 = GMAC0, 2 = GMAC1, 3 = PMAC -->
<!-- owner_q_num : owner queue number -->
<!-- size : queue size must be >0 -->
<!-- Undefined queues will not be created in hardware -->
<queue_map>
<queue id="0" sched_method="0" owner="0" owner_q_num="0" size="1024" weight="0" />
<queue id="1" sched_method="0" owner="1" owner_q_num="0" size="1024" weight="0" />
<queue id="2" sched_method="0" owner="0" owner_q_num="1" size="1024" weight="0" />
<queue id="3" sched_method="0" owner="1" owner_q_num="1" size="1024" weight="0" />
<queue id="4" sched_method="0" owner="0" owner_q_num="2" size="1024" weight="0" />
<queue id="5" sched_method="0" owner="1" owner_q_num="2" size="1024" weight="0" />
<queue id="6" sched_method="0" owner="0" owner_q_num="3" size="1024" weight="0" />
<queue id="7" sched_method="0" owner="1" owner_q_num="3" size="1024" weight="0" />
</queue_map>
</tx_mod>
<!-- id : 0 = GMAC0, 1 = GMAC1, 2 = PMAC_0, 3 = PMAC_1, 4 = PMAC_2, 5 = PMAC_3, -->
<!-- : 6 = PMAC_4, 7 = PMAC_5, 8 = PMAC_6, 9 = PMAC_7 -->
<tx_mod id="4">
<!-- id : queue number -->
<!-- sched_method: 0 = STRICT, 1 = WRR -->
<!-- owner : 0 = CPU, 1 = GMAC0, 2 = GMAC1, 3 = PMAC -->
<!-- owner_q_num : owner queue number -->
<!-- size : queue size must be >0 -->
<!-- Undefined queues will not be created in hardware -->
<queue_map>
<queue id="0" sched_method="0" owner="0" owner_q_num="0" size="1024" weight="0" />
<queue id="1" sched_method="0" owner="1" owner_q_num="0" size="1024" weight="0" />
<queue id="2" sched_method="0" owner="0" owner_q_num="1" size="1024" weight="0" />
<queue id="3" sched_method="0" owner="1" owner_q_num="1" size="1024" weight="0" />
<queue id="4" sched_method="0" owner="0" owner_q_num="2" size="1024" weight="0" />
<queue id="5" sched_method="0" owner="1" owner_q_num="2" size="1024" weight="0" />
<queue id="6" sched_method="0" owner="0" owner_q_num="3" size="1024" weight="0" />
<queue id="7" sched_method="0" owner="1" owner_q_num="3" size="1024" weight="0" />
</queue_map>
</tx_mod>
<!-- id : 0 = GMAC0, 1 = GMAC1, 2 = PMAC_0, 3 = PMAC_1, 4 = PMAC_2, 5 = PMAC_3, -->
<!-- : 6 = PMAC_4, 7 = PMAC_5, 8 = PMAC_6, 9 = PMAC_7 -->
<tx_mod id="5">
<!-- id : queue number -->
<!-- sched_method: 0 = STRICT, 1 = WRR -->
<!-- owner : 0 = CPU, 1 = GMAC0, 2 = GMAC1, 3 = PMAC -->
<!-- owner_q_num : owner queue number -->
<!-- size : queue size must be >0 -->
<!-- Undefined queues will not be created in hardware -->
<queue_map>
<queue id="0" sched_method="0" owner="0" owner_q_num="0" size="1024" weight="0" />
<queue id="1" sched_method="0" owner="1" owner_q_num="0" size="1024" weight="0" />
<queue id="2" sched_method="0" owner="0" owner_q_num="1" size="1024" weight="0" />
<queue id="3" sched_method="0" owner="1" owner_q_num="1" size="1024" weight="0" />
<queue id="4" sched_method="0" owner="0" owner_q_num="2" size="1024" weight="0" />
<queue id="5" sched_method="0" owner="1" owner_q_num="2" size="1024" weight="0" />
<queue id="6" sched_method="0" owner="0" owner_q_num="3" size="1024" weight="0" />
<queue id="7" sched_method="0" owner="1" owner_q_num="3" size="1024" weight="0" />
</queue_map>
</tx_mod>
<!-- id : 0 = GMAC0, 1 = GMAC1, 2 = PMAC_0, 3 = PMAC_1, 4 = PMAC_2, 5 = PMAC_3, -->
<!-- : 6 = PMAC_4, 7 = PMAC_5, 8 = PMAC_6, 9 = PMAC_7 -->
<tx_mod id="6">
<!-- id : queue number -->
<!-- sched_method: 0 = STRICT, 1 = WRR -->
<!-- owner : 0 = CPU, 1 = GMAC0, 2 = GMAC1, 3 = PMAC -->
<!-- owner_q_num : owner queue number -->
<!-- size : queue size must be >0 -->
<!-- Undefined queues will not be created in hardware -->
<queue_map>
<queue id="0" sched_method="0" owner="0" owner_q_num="0" size="1024" weight="0" />
<queue id="1" sched_method="0" owner="1" owner_q_num="0" size="1024" weight="0" />
<queue id="2" sched_method="0" owner="0" owner_q_num="1" size="1024" weight="0" />
<queue id="3" sched_method="0" owner="1" owner_q_num="1" size="1024" weight="0" />
<queue id="4" sched_method="0" owner="0" owner_q_num="2" size="1024" weight="0" />
<queue id="5" sched_method="0" owner="1" owner_q_num="2" size="1024" weight="0" />
<queue id="6" sched_method="0" owner="0" owner_q_num="3" size="1024" weight="0" />
<queue id="7" sched_method="0" owner="1" owner_q_num="3" size="1024" weight="0" />
</queue_map>
</tx_mod>
<!-- id : 0 = GMAC0, 1 = GMAC1, 2 = PMAC_0, 3 = PMAC_1, 4 = PMAC_2, 5 = PMAC_3, -->
<!-- : 6 = PMAC_4, 7 = PMAC_5, 8 = PMAC_6, 9 = PMAC_7 -->
<tx_mod id="7">
<!-- id : queue number -->
<!-- sched_method: 0 = STRICT, 1 = WRR -->
<!-- owner : 0 = CPU, 1 = GMAC0, 2 = GMAC1, 3 = PMAC -->
<!-- owner_q_num : owner queue number -->
<!-- size : queue size must be >0 -->
<!-- Undefined queues will not be created in hardware -->
<queue_map>
<queue id="0" sched_method="0" owner="0" owner_q_num="0" size="1024" weight="0" />
<queue id="1" sched_method="0" owner="1" owner_q_num="0" size="1024" weight="0" />
<queue id="2" sched_method="0" owner="0" owner_q_num="1" size="1024" weight="0" />
<queue id="3" sched_method="0" owner="1" owner_q_num="1" size="1024" weight="0" />
<queue id="4" sched_method="0" owner="0" owner_q_num="2" size="1024" weight="0" />
<queue id="5" sched_method="0" owner="1" owner_q_num="2" size="1024" weight="0" />
<queue id="6" sched_method="0" owner="0" owner_q_num="3" size="1024" weight="0" />
<queue id="7" sched_method="0" owner="1" owner_q_num="3" size="1024" weight="0" />
</queue_map>
</tx_mod>
<!-- id : 0 = GMAC0, 1 = GMAC1, 2 = PMAC_0, 3 = PMAC_1, 4 = PMAC_2, 5 = PMAC_3, -->
<!-- : 6 = PMAC_4, 7 = PMAC_5, 8 = PMAC_6, 9 = PMAC_7 -->
<tx_mod id="8">
<!-- id : queue number -->
<!-- sched_method: 0 = STRICT, 1 = WRR -->
<!-- owner : 0 = CPU, 1 = GMAC0, 2 = GMAC1, 3 = PMAC -->
<!-- owner_q_num : owner queue number -->
<!-- size : queue size must be >0 -->
<!-- Undefined queues will not be created in hardware -->
<queue_map>
<queue id="0" sched_method="0" owner="0" owner_q_num="0" size="1024" weight="0" />
<queue id="1" sched_method="0" owner="1" owner_q_num="0" size="1024" weight="0" />
<queue id="2" sched_method="0" owner="0" owner_q_num="1" size="1024" weight="0" />
<queue id="3" sched_method="0" owner="1" owner_q_num="1" size="1024" weight="0" />
<queue id="4" sched_method="0" owner="0" owner_q_num="2" size="1024" weight="0" />
<queue id="5" sched_method="0" owner="1" owner_q_num="2" size="1024" weight="0" />
<queue id="6" sched_method="0" owner="0" owner_q_num="3" size="1024" weight="0" />
<queue id="7" sched_method="0" owner="1" owner_q_num="3" size="1024" weight="0" />
</queue_map>
</tx_mod>
<!-- id : 0 = GMAC0, 1 = GMAC1, 2 = PMAC_0, 3 = PMAC_1, 4 = PMAC_2, 5 = PMAC_3, -->
<!-- : 6 = PMAC_4, 7 = PMAC_5, 8 = PMAC_6, 9 = PMAC_7 -->
<tx_mod id="9">
<!-- id : queue number -->
<!-- sched_method: 0 = STRICT, 1 = WRR -->
<!-- owner : 0 = CPU, 1 = GMAC0, 2 = GMAC1, 3 = PMAC -->
<!-- owner_q_num : owner queue number -->
<!-- size : queue size must be >0 -->
<!-- Undefined queues will not be created in hardware -->
<queue_map>
<queue id="0" sched_method="0" owner="0" owner_q_num="0" size="1024" weight="0" />
<queue id="1" sched_method="0" owner="1" owner_q_num="0" size="1024" weight="0" />
<queue id="2" sched_method="0" owner="0" owner_q_num="1" size="1024" weight="0" />
<queue id="3" sched_method="0" owner="1" owner_q_num="1" size="1024" weight="0" />
<queue id="4" sched_method="0" owner="0" owner_q_num="2" size="1024" weight="0" />
<queue id="5" sched_method="0" owner="1" owner_q_num="2" size="1024" weight="0" />
<queue id="6" sched_method="0" owner="0" owner_q_num="3" size="1024" weight="0" />
<queue id="7" sched_method="0" owner="1" owner_q_num="3" size="1024" weight="0" />
</queue_map>
</tx_mod>
</tx_module_parameters>
</port_init>
<flow_control>
<enabled>0</enabled>
<queue_sample_freq>1000</queue_sample_freq>
<thresh_high>560</thresh_high>
<thresh_low>300</thresh_low>
<port>1</port>
<tgt_port>0</tgt_port>
<tx_port>0</tx_port>
<tx_queue>1</tx_queue>
</flow_control>
<TPM>
<!-- Get TPM configuration mode: 0 = Application, 1 = Kernel -->
<GET_config_mode>1</GET_config_mode>
<!-- VALIDATION type: 0 = DISABLED, 1 = ENABLED -->
<validation_enable>1</validation_enable>
<!-- Support 2G DS with GMAC0/1: 0 = disable, 1 = enable -->
<ds_mac_based_trunking>0</ds_mac_based_trunking>
<!-- Init switch or not: 0 = do not Init, 1 = do Init -->
<switch_init>0</switch_init>
<!-- PNC_config:
0 = PNC is configured by the MV neta driver,
1 = PNC is configured by the TPM SW
-->
<pnc_config>1</pnc_config>
<ds_mh_set>0</ds_mh_set>
<!-- cpu_wan_egr_loopback:
0 = CPU WAN Egress Loopback - disabled
1 = CPU WAN Egress Loopback - enabled
-->
<cpu_wan_egr_loopback>0</cpu_wan_egr_loopback>
<!-- IPV6 5-tuple status :
0 = IPV6 is configured by normal API,
1 = ipv6 is configured by 5-tuple API
-->
<ipv6_5t_enable>1</ipv6_5t_enable>
<!-- GMAC1 acts as virtual UNI :
0 = virtual UNI via GMAC1 - disabled,
1 = virtual UNI via GMAC1 - enabled
-->
<gmac1_virt_uni>0</gmac1_virt_uni>
<vlan_filter_tpid>
<!-- id : option id -->
<!-- comb : tpid combination
format - 0xAABB[,0xCCDD] -->
<filter_tpid id="0" type="0x8100,0x8100" />
<filter_tpid id="1" type="0x9100,0x8100" />
<filter_tpid id="2" type="0x88A8,0x8100" />
<filter_tpid id="3" type="0x88A8,0x88A8" />
<filter_tpid id="4" type="0x8100,0x88A8" />
<filter_tpid id="5" type="0x8100" />
<filter_tpid id="6" type="0x88A8" />
<filter_tpid id="7" type="0x9100" />
</vlan_filter_tpid>
<!-- trace_debug_info:
0xAAAABBBB = AAAA = trace levels
BBBB = debug printouts
0x00000000 = trace & debug printouts are disabled,
0x80000000 = FATAL_TRACE_LEVEL 0x00000001 = TPM_DB_MOD
0xC0000000 = ERROR_TRACE_LEVEL 0x00000002 = TPM_PNCL_MOD
0xE0000000 = WARN_TRACE_LEVEL 0x00000004 = TPM_INIT_MOD
0xF0000000 = INFO_TRACE_LEVEL 0x00000008 = TPM_HWM_MOD
0xF8000000 = DEBUG_TRACE_LEVEL 0x00000010 = TPM_MODL_MOD
0x00000020 = TPM_TPM_LOG_MOD
0xFFFF0000 = ALL_TRACE_LEVEL 0x00000040 = TPM_CLI_MOD
0x00000080 = TPM_PNC_HM_MOD
0x00000100 = TPM_MODZ1_HM_MOD
0x00000200 = TPM_MODZ2_HM_MOD
0x0000FFFF = TPM_ALL_MODULES
0xFFFFFFFF = trace & debug printouts are ALL ENABLED
0xE000FFFF = default value = (WARN + ERRORS ) for trace level
ALL for debug printouts
-->
<trace_debug_info>0xE000FFFF</trace_debug_info>
<!-- Values for VLAN ETY registers -->
<vlan_mod_tpid>
<!-- id : type number -->
<!-- type : VLAN type (0xFFFF - NULL value) -->
<mod_tpid id="0" type="0x8100" />
<mod_tpid id="1" type="0x88A8" />
<mod_tpid id="2" type="0x9100" />
<mod_tpid id="3" type="0xAABB" />
</vlan_mod_tpid>
<modification>
<!-- configuration of modification chains: -->
<!-- id : chain id -->
<!-- type : chain type
1 - MH_MOD_SUBR_CHAIN
2 - MAC_MOD_SUBR_CHAIN
3 - VLAN_MOD_SUBR_CHAIN
4 - PPPOE_MOD_SUBR_CHAIN
5 - IPV6_PPPOE_MOD_SUBR_CHAIN
6 - L2_MAIN_CHAIN
7 - IPV4_NAPT_MAIN_CHAIN
8 - IPV4_MULTICAST_MAIN_CHAIN
9 - IPV6_ROUTING_MAIN_CHAIN
10 - IPV6_MULTICAST_MAIN_CHAIN -->
<!-- num : number of modification chain entries
4096 - "all remaining", fills up remaining part of the modification tables with this chain_type.
Only "L2_MAIN_CHAIN" OR "IPV4_NAPT_MAIN_CHAIN" can be assigned "all remaining" -->
<chain_parameters>
<chain id="0" type="1" num="32" />
<chain id="1" type="2" num="64" />
<chain id="2" type="3" num="300" />
<chain id="3" type="4" num="8" />
<chain id="4" type="5" num="6" />
<chain id="5" type="6" num="170" />
<chain id="6" type="7" num="4096" />
<chain id="7" type="8" num="16" />
<chain id="8" type="9" num="64" />
<chain id="9" type="10" num="16" />
</chain_parameters>
<udp_checksum_use_init>0</udp_checksum_use_init>
<udp_checksum_calc>0</udp_checksum_calc>
<split_mod>
<!-- enable/disable split pbit and vid modification, 1: enable, 0: disable -->
<enable>1</enable>
<!--p_bit that supported -->
<p_bits>0, 1, 2, 3, 4, 5, 6, 7</p_bits >
<!--vlan number that needs split pbit and vid modification, 0~16 -->
<vlan_num>16</vlan_num>
</split_mod>
</modification>
<!-- CTC CnM status :
0 = CTC CnM - disabled,
1 = CTC CnM - enabled
-->
<ctc_cnm_enable>0</ctc_cnm_enable>
<!-- PNC MAC learning status :
0 = PNC MAC learn - disabled,
1 = PNC MAC learn - enabled
-->
<split_mod_mode>1</split_mod_mode>
<!-- split modification work mode :
0 = CTC mode,
1 = TR156 mode
-->
<pnc_mac_learn_enable>0</pnc_mac_learn_enable>
<!-- CTC IPv6 CNM parsing window: 0 = first 24 bytes of IPv6 header, 1 = second 24 bytes -->
<ctc_cnm_ipv6_parsing_window>0</ctc_cnm_ipv6_parsing_window>
<PnC>
<!-- num : -->
<!-- type : 0 = ACL, 1 = TABLE -->
<!-- cntr_grp : 0 = GROUP_0(Default), 1-3 = GROUP_1/GROUP_2/GROUP_3/ -->
<!-- lu_mask_all : 0 = DONT_MASK, 1 = MASK -->
<!-- min_reset_level: 0 = level_0(Default), 1 = level_1(hard_reset), 2 = Never -->
<range_parameters>
<!-- TPM_PNC_MNGMT_DS -->
<range num="00" type="0" size="01" cntr_grp="0" lu_mask="1" min_reset_level = "1" />
<!-- TPM_PNC_MAC_LEARN -->
<range num="01" type="0" size="0" cntr_grp="3" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_CPU_WAN_LPBK_US -->
<range num="02" type="0" size="5" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_NUM_VLAN_TAGS -->
<range num="03" type="0" size="09" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_DS_LOAD_BALANCE -->
<range num="04" type="0" size="00" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_MULTI_LPBK -->
<range num="05" type="0" size="20" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_VIRT_UNI -->
<range num="06" type="0" size="13" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_LOOP_DET_US -->
<range num="07" type="0" size="03" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_DROP_PRECEDENCE -->
<range num="08" type="0" size="04" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_L2_MAIN -->
<range num="09" type="0" size="154" cntr_grp="1" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_ETH_TYPE -->
<range num="10" type="0" size="16" cntr_grp="2" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IGMP -->
<range num="11" type="0" size="06" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV4_MC_DS -->
<range num="12" type="1" size="16" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV4_MAIN -->
<range num="13" type="1" size="64" cntr_grp="3" lu_mask="0" min_reset_level = "0" />
<!-- TPM_PNC_IPV4_TCP_FLAG -->
<range num="14" type="0" size="12" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_TTL -->
<range num="15" type="0" size="04" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV4_PROTO -->
<range num="16" type="0" size="03" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV4_FRAG -->
<range num="17" type="0" size="04" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV4_LEN -->
<range num="18" type="0" size="03" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV6_NH -->
<range num="19" type="1" size="16" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV6_L4_MC_DS -->
<range num="20" type="1" size="16" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV6_TCP_FLAG -->
<range num="21" type="1" size="02" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV6_L4 -->
<range num="22" type="1" size="17" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV6_HOPL -->
<range num="23" type="1" size="03" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV6_MC_SIP -->
<range num="24" type="1" size="08" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV6_GEN -->
<range num="25" type="1" size="22" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV6_MC_DS -->
<range num="26" type="1" size="32" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_IPV6_DIP -->
<range num="27" type="1" size="22" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_CNM_IPV4_PRE -->
<range num="28" type="1" size="0" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_CNM_MAIN -->
<range num="29" type="0" size="0" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
<!-- TPM_PNC_CATCH_ALL -->
<range num="30" type="0" size="01" cntr_grp="0" lu_mask="1" min_reset_level = "0" />
</range_parameters>
<!-- 0 = drop, 1 = trap to CPU -->
<catch_all_pkt_action>1</catch_all_pkt_action>
</PnC>
</TPM>
</cnfg>