
#define BASE_ADDR_GPIO		0x90470000
#define BASE_ADDR_CLOCK_RESET	0x904B0000
#define BASE_ADDR_SPI		0x90498000
#define BASE_ADDR_TDM		0x90400000
#define BASE_ADDR_TDMA		0x90420000
#define BASE_ADDR_NTG		0x904B0280

// TDM Registers
#define TDM0_VERISON		(BASE_ADDR_TDM + 0x0000)
#define TDM0_NETWORK		(BASE_ADDR_TDM + 0x0004)
#define TDM0_TX			(BASE_ADDR_TDM + 0x0010)
#define TDM0_TX_TSEN_A		(BASE_ADDR_TDM + 0x0014)
#define TDM0_TX_TSEN_B		(BASE_ADDR_TDM + 0x0018)
#define TDM0_TX_TSEN_C		(BASE_ADDR_TDM + 0x001c)
#define TDM0_TX_TSEN_D		(BASE_ADDR_TDM + 0x0020)
#define TDM0_RX			(BASE_ADDR_TDM + 0x0030)
#define TDM0_RX_TSEN_A		(BASE_ADDR_TDM + 0x0034)
#define TDM0_RX_TSEN_B		(BASE_ADDR_TDM + 0x0038)
#define TDM0_RX_TSEN_C		(BASE_ADDR_TDM + 0x003c)
#define TDM0_RX_TSEN_D		(BASE_ADDR_TDM + 0x0040)
#define TDM0_CTSEN_A		(BASE_ADDR_TDM + 0x0050)
#define TDM0_CTSEN_B		(BASE_ADDR_TDM + 0x0054)
#define TDM0_CTSEN_C		(BASE_ADDR_TDM + 0x0058)
#define TDM0_CTSEN_D		(BASE_ADDR_TDM + 0x005c)
#define TDM1_VERISON		(BASE_ADDR_TDM + 0x1000)
#define TDM1_NETWORK		(BASE_ADDR_TDM + 0x1004)
#define TDM1_TX			(BASE_ADDR_TDM + 0x1010)
#define TDM1_TX_TSEN_A		(BASE_ADDR_TDM + 0x1014)
#define TDM1_RX			(BASE_ADDR_TDM + 0x1030)
#define TDM1_RX_TSEN_A		(BASE_ADDR_TDM + 0x1034)
#define TDM1_CTSEN		(BASE_ADDR_TDM + 0x1050)

// TDMA Registers
#define TDM_RX_DMA_ENABLE	(BASE_ADDR_TDMA + 0x0004)
#define TDM_TX_DMA_ENABLE	(BASE_ADDR_TDMA + 0x0008)
#define IRQ2TDMA_INTERRUPT_ENABLE      (BASE_ADDR_TDMA + 0x0010)
#define TDMA_BASE_BIST_CTRL	(BASE_ADDR_TDMA + 0x0014)
#define TDMA_TDM0RX_BIST_CTRL	(BASE_ADDR_TDMA + 0x0018)
#define TDMA_TDM0TX_BIST_CTRL	(BASE_ADDR_TDMA + 0x001c)
#define TDM_BLOCK_SIZE		(BASE_ADDR_TDMA + 0x0020)
#define TDMA_TDM1RX_BIST_CTRL	(BASE_ADDR_TDMA + 0x2018)
#define TDMA_TDM1TX_BIST_CTRL	(BASE_ADDR_TDMA + 0x201c)
#define TDMA0_MEMSEG		(BASE_ADDR_TDMA + 0x0000)
#define TDMA0_RXDMAEN		(BASE_ADDR_TDMA + 0x0004)
#define TDMA0_TXDMAEN		(BASE_ADDR_TDMA + 0x0008)
#define TDMA0_BLKSIZE		(BASE_ADDR_TDMA + 0x0020)
#define TDMA0_INTSIZE		(BASE_ADDR_TDMA + 0x0024)
#define TDMA0_RXBFPTR		(BASE_ADDR_TDMA + 0x0028)
#define TDMA0_TXBFPTR		(BASE_ADDR_TDMA + 0x002c)
#define TDMA0_BACKCOM		(BASE_ADDR_TDMA + 0x0030)
#define TDMA0_RXCHEN_A		(BASE_ADDR_TDMA + 0x0060)
#define TDMA0_RXCHEN_B		(BASE_ADDR_TDMA + 0x0064)
#define TDMA0_RXCHEN_C		(BASE_ADDR_TDMA + 0x0068)
#define TDMA0_RXCHEN_D		(BASE_ADDR_TDMA + 0x006c)
#define TDMA0_TXCHEN_A		(BASE_ADDR_TDMA + 0x0070)
#define TDMA0_TXCHEN_B		(BASE_ADDR_TDMA + 0x0074)
#define TDMA0_TXCHEN_C		(BASE_ADDR_TDMA + 0x0078)
#define TDMA0_TXCHEN_D		(BASE_ADDR_TDMA + 0x007c)
#define TDMA0_RXBASE0		 (BASE_ADDR_TDMA + 0x1000)
#define TDMA0_TXBASE0		 (BASE_ADDR_TDMA + 0x1200)
#define TDMA0_RXLKTB0		 (BASE_ADDR_TDMA + 0x1400)
#define TDMA0_TXLKTB0		 (BASE_ADDR_TDMA + 0x1600)
#define TDMA0_TXBUF		 (BASE_ADDR_TDMA + 0x1C00)
#define TDMA1_MEMSEG		(BASE_ADDR_TDMA + 0x2000)
#define TDMA1_RXDMAEN		(BASE_ADDR_TDMA + 0x2004)
#define TDMA1_TXDMAEN		(BASE_ADDR_TDMA + 0x2008)
#define TDMA1_BLKSIZE		(BASE_ADDR_TDMA + 0x2020)
#define TDMA1_INTSIZE		(BASE_ADDR_TDMA + 0x2024)
#define TDMA1_RXBFPTR		(BASE_ADDR_TDMA + 0x2028)
#define TDMA1_TXBFPTR		(BASE_ADDR_TDMA + 0x202c)
#define TDMA1_BACKCOM		(BASE_ADDR_TDMA + 0x2030)
#define TDMA1_RXCHEN_A		(BASE_ADDR_TDMA + 0x2060)
#define TDMA1_RXCHEN_B		(BASE_ADDR_TDMA + 0x2064)
#define TDMA1_RXCHEN_C		(BASE_ADDR_TDMA + 0x2068)
#define TDMA1_RXCHEN_D		(BASE_ADDR_TDMA + 0x206c)
#define TDMA1_TXCHEN_A		(BASE_ADDR_TDMA + 0x2070)
#define TDMA1_TXCHEN_B		(BASE_ADDR_TDMA + 0x2074)
#define TDMA1_TXCHEN_C		(BASE_ADDR_TDMA + 0x2078)
#define TDMA1_TXCHEN_D		(BASE_ADDR_TDMA + 0x207c)
#define TDMA1_RXBASE0		 (BASE_ADDR_TDMA + 0x3000)
#define TDMA1_TXBASE0		 (BASE_ADDR_TDMA + 0x3200)
#define TDMA1_RXLKTB0		 (BASE_ADDR_TDMA + 0x3400)
#define TDMA1_TXLKTB0		 (BASE_ADDR_TDMA + 0x3600)
#define TDMA1_TXBUF		 (BASE_ADDR_TDMA + 0x3C00)
#define TDMA0_IRQ2STAT		(BASE_ADDR_TDMA + 0x000c)
#define TDMA1_IRQ2STAT		(BASE_ADDR_TDMA + 0x200c)

#define GPIO_TDM_MUX_CONTROL			(BASE_ADDR_GPIO + 0x28)
#define GPIO_BOOTSTRAP_TEST_PIN_OVERRIDE	(BASE_ADDR_GPIO + 0x44)
#define GPIO_MISC_PIN_SELECT			(BASE_ADDR_GPIO + 0x60)

#define NTG_FREQ_SET_INT	(BASE_ADDR_NTG + 0x00)
#define NTG_FREQ_SET_FRA	(BASE_ADDR_NTG + 0x04)
#define NTG_PHASE_ADJ_FREQ_INT	(BASE_ADDR_NTG + 0x10)

#define CLOCK_RESET_SLIC_CONTROL		(BASE_ADDR_CLOCK_RESET + 0x14C)

#define SPI_CTRLR0	(BASE_ADDR_SPI + 0x00)
#define SPI_CTRLR1	(BASE_ADDR_SPI + 0x04)
#define SPI_SSIENR	(BASE_ADDR_SPI + 0x08)
#define SPI_SER		(BASE_ADDR_SPI + 0x10)
#define SPI_BAUDR	(BASE_ADDR_SPI + 0x14)
#define SPI_RXFTLR	(BASE_ADDR_SPI + 0x1C)
#define SPI_FLR		(BASE_ADDR_SPI + 0x24)
#define SPI_SR		(BASE_ADDR_SPI + 0x28)
#define SPI_IMR		(BASE_ADDR_SPI + 0x2C)
#define SPI_DR		(BASE_ADDR_SPI + 0x60)

#define IRAM_CHKER_SRC_ADDR        0x83000000
#define IRAM_CHKER_DEST_ADDR       0x83000004
#define IRAM_CHKER_LENGTH          0x83000008
#define IRAM_CHKER_CONTROL         0x8300000C
#define IRAM_CHKER_START 31
#define ENABLE	0x1