PF_RING-5.6.0/drivers/PF_RING_aware/2.6.x/broadcom/netxtreme2-5.2.50/bnx2x-1.52.12/src/bnx2x_init_values_e1h.c

/* init_ops array contains the list of operations needed to initialize the chip.
 *
 * For each block in the chip there are three init stages:
 * common - HW used by both ports,
 * port1 and port2 - initialization for a specific Ethernet port.
 * When a port is opened or closed, the management CPU tells the driver
 * whether to init/disable common HW in addition to the port HW.
 * This way the first port going up will first initializes the common HW,
 * and the last port going down also resets the common HW
 *
 * For each init stage/block there is a list of actions needed in a format:
 * {operation, register, data}
 * where:
 * OP_WR - write a value to the chip.
 * OP_RD - read a register (usually a clear on read register).
 * OP_SW - string write, write a section of consecutive addresses to the chip.
 * OP_SI - copy a string using indirect writes.
 * OP_ZR - clear a range of memory.
 * OP_ZP - unzip and copy using DMAE.
 * OP_WB - string copy using DMAE.
 *
 * The #defines mark the stages.
 *
 */
#include <linux/version.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/netdevice.h>
#include <linux/delay.h>
#include "bnx2x_compat.h"
#include "bnx2x_init.h"
#include "bnx2x.h"


static const struct raw_op init_ops_e1h[] = {
/* #define PRS_COMMON_START        0 */
	{OP_WR, PRS_REG_INC_VALUE, 0xf},
	{OP_WR, PRS_REG_EVENT_ID_1, 0x45},
	{OP_WR, PRS_REG_EVENT_ID_2, 0x84},
	{OP_WR, PRS_REG_EVENT_ID_3, 0x6},
	{OP_WR, PRS_REG_NO_MATCH_EVENT_ID, 0x4},
	{OP_WR, PRS_REG_CM_HDR_TYPE_0, 0x0},
	{OP_WR, PRS_REG_CM_HDR_TYPE_1, 0x12170000},
	{OP_WR, PRS_REG_CM_HDR_TYPE_2, 0x22170000},
	{OP_WR, PRS_REG_CM_HDR_TYPE_3, 0x32170000},
	{OP_ZR, PRS_REG_CM_HDR_TYPE_4, 0x5},
	{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_1, 0x12150000},
	{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_2, 0x22150000},
	{OP_WR, PRS_REG_CM_HDR_LOOPBACK_TYPE_3, 0x32150000},
	{OP_ZR, PRS_REG_CM_HDR_LOOPBACK_TYPE_4, 0x4},
	{OP_WR, PRS_REG_CM_NO_MATCH_HDR, 0x2100000},
	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_0, 0x100000},
	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_1, 0x10100000},
	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_2, 0x20100000},
	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_3, 0x30100000},
	{OP_WR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_4, 0x40100000},
	{OP_ZR, PRS_REG_CM_HDR_FLUSH_NO_LOAD_TYPE_5, 0x3},
	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_0, 0x100000},
	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_1, 0x12140000},
	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_2, 0x22140000},
	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_3, 0x32140000},
	{OP_WR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_4, 0x42140000},
	{OP_ZR, PRS_REG_CM_HDR_FLUSH_LOAD_TYPE_5, 0x3},
	{OP_RD, PRS_REG_NUM_OF_PACKETS, 0x0},
	{OP_RD, PRS_REG_NUM_OF_CFC_FLUSH_MESSAGES, 0x0},
	{OP_RD, PRS_REG_NUM_OF_TRANSPARENT_FLUSH_MESSAGES, 0x0},
	{OP_RD, PRS_REG_NUM_OF_DEAD_CYCLES, 0x0},
	{OP_WR, PRS_REG_FCOE_TYPE, 0x8906},
	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_0, 0xff},
	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_1, 0xff},
	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_2, 0xff},
	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_3, 0xff},
	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_4, 0xff},
	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_5, 0xff},
	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_6, 0xff},
	{OP_WR, PRS_REG_FLUSH_REGIONS_TYPE_7, 0xff},
	{OP_WR, PRS_REG_PURE_REGIONS, 0x3e},
	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_0, 0x0},
	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_1, 0x3f},
	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_2, 0x3f},
	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_3, 0x3f},
	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_4, 0x3f},
	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_5, 0x3f},
	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_6, 0x3f},
	{OP_WR, PRS_REG_PACKET_REGIONS_TYPE_7, 0x3f},
/* #define PRS_COMMON_END          1 */
/* #define SRCH_COMMON_START       22 */
	{OP_WR, SRC_REG_E1HMF_ENABLE, 0x1},
/* #define SRCH_COMMON_END         23 */
/* #define TSDM_COMMON_START       44 */
	{OP_WR, TSDM_REG_CFC_RSP_START_ADDR, 0x211},
	{OP_WR, TSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
	{OP_WR, TSDM_REG_Q_COUNTER_START_ADDR, 0x204},
	{OP_WR, TSDM_REG_PCK_END_MSG_START_ADDR, 0x219},
	{OP_WR, TSDM_REG_CMP_COUNTER_MAX0, 0xffff},
	{OP_WR, TSDM_REG_CMP_COUNTER_MAX1, 0xffff},
	{OP_WR, TSDM_REG_CMP_COUNTER_MAX2, 0xffff},
	{OP_WR, TSDM_REG_CMP_COUNTER_MAX3, 0xffff},
	{OP_WR, TSDM_REG_AGG_INT_EVENT_0, 0x20},
	{OP_WR, TSDM_REG_AGG_INT_EVENT_1, 0x0},
	{OP_WR, TSDM_REG_AGG_INT_EVENT_2, 0x34},
	{OP_WR, TSDM_REG_AGG_INT_EVENT_3, 0x35},
	{OP_ZR, TSDM_REG_AGG_INT_EVENT_4, 0x1c},
	{OP_WR, TSDM_REG_AGG_INT_T_0, 0x1},
	{OP_ZR, TSDM_REG_AGG_INT_T_1, 0x5f},
	{OP_WR, TSDM_REG_ENABLE_IN1, 0x7ffffff},
	{OP_WR, TSDM_REG_ENABLE_IN2, 0x3f},
	{OP_WR, TSDM_REG_ENABLE_OUT1, 0x7ffffff},
	{OP_WR, TSDM_REG_ENABLE_OUT2, 0xf},
	{OP_RD, TSDM_REG_NUM_OF_Q0_CMD, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_Q1_CMD, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_Q3_CMD, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_Q4_CMD, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_Q5_CMD, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_Q6_CMD, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_Q7_CMD, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_Q8_CMD, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_Q9_CMD, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_Q10_CMD, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_Q11_CMD, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
	{OP_RD, TSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
	{OP_WR_ASIC, TSDM_REG_TIMER_TICK, 0x3e8},
	{OP_WR_EMUL, TSDM_REG_TIMER_TICK, 0x1},
	{OP_WR_FPGA, TSDM_REG_TIMER_TICK, 0xa},
/* #define TSDM_COMMON_END         45 */
/* #define TCM_COMMON_START        66 */
	{OP_WR, TCM_REG_XX_MAX_LL_SZ, 0x20},
	{OP_WR, TCM_REG_XX_OVFL_EVNT_ID, 0x32},
	{OP_WR, TCM_REG_TQM_TCM_HDR_P, 0x2150020},
	{OP_WR, TCM_REG_TQM_TCM_HDR_S, 0x2150020},
	{OP_WR, TCM_REG_TM_TCM_HDR, 0x30},
	{OP_WR, TCM_REG_ERR_TCM_HDR, 0x8100000},
	{OP_WR, TCM_REG_ERR_EVNT_ID, 0x33},
	{OP_WR, TCM_REG_EXPR_EVNT_ID, 0x30},
	{OP_WR, TCM_REG_STOP_EVNT_ID, 0x31},
	{OP_WR, TCM_REG_STORM_WEIGHT, 0x2},
	{OP_WR, TCM_REG_PRS_WEIGHT, 0x5},
	{OP_WR, TCM_REG_PBF_WEIGHT, 0x6},
	{OP_WR, TCM_REG_USEM_WEIGHT, 0x2},
	{OP_WR, TCM_REG_CSEM_WEIGHT, 0x2},
	{OP_WR, TCM_REG_CP_WEIGHT, 0x0},
	{OP_WR, TCM_REG_TSDM_WEIGHT, 0x5},
	{OP_WR, TCM_REG_TQM_P_WEIGHT, 0x2},
	{OP_WR, TCM_REG_TQM_S_WEIGHT, 0x2},
	{OP_WR, TCM_REG_TM_WEIGHT, 0x2},
	{OP_WR, TCM_REG_TCM_TQM_USE_Q, 0x1},
	{OP_WR, TCM_REG_GR_ARB_TYPE, 0x1},
	{OP_WR, TCM_REG_GR_LD0_PR, 0x1},
	{OP_WR, TCM_REG_GR_LD1_PR, 0x2},
	{OP_WR, TCM_REG_CFC_INIT_CRD, 0x1},
	{OP_WR, TCM_REG_FIC0_INIT_CRD, 0x40},
	{OP_WR, TCM_REG_FIC1_INIT_CRD, 0x40},
	{OP_WR, TCM_REG_TQM_INIT_CRD, 0x20},
	{OP_WR, TCM_REG_XX_INIT_CRD, 0x13},
	{OP_WR, TCM_REG_XX_MSG_NUM, 0x20},
	{OP_ZR, TCM_REG_XX_TABLE, 0xa},
	{OP_SW, TCM_REG_XX_DESCR_TABLE, 0x200000},
	{OP_WR, TCM_REG_N_SM_CTX_LD_0, 0x7},
	{OP_WR, TCM_REG_N_SM_CTX_LD_1, 0x7},
	{OP_WR, TCM_REG_N_SM_CTX_LD_2, 0x8},
	{OP_WR, TCM_REG_N_SM_CTX_LD_3, 0x8},
	{OP_WR, TCM_REG_N_SM_CTX_LD_4, 0x1},
	{OP_ZR, TCM_REG_N_SM_CTX_LD_5, 0x3},
	{OP_WR, TCM_REG_TCM_REG0_SZ, 0x6},
	{OP_WR, TCM_REG_TCM_STORM0_IFEN, 0x1},
	{OP_WR, TCM_REG_TCM_STORM1_IFEN, 0x1},
	{OP_WR, TCM_REG_TCM_TQM_IFEN, 0x1},
	{OP_WR, TCM_REG_STORM_TCM_IFEN, 0x1},
	{OP_WR, TCM_REG_TQM_TCM_IFEN, 0x1},
	{OP_WR, TCM_REG_TSDM_IFEN, 0x1},
	{OP_WR, TCM_REG_TM_TCM_IFEN, 0x1},
	{OP_WR, TCM_REG_PRS_IFEN, 0x1},
	{OP_WR, TCM_REG_PBF_IFEN, 0x1},
	{OP_WR, TCM_REG_USEM_IFEN, 0x1},
	{OP_WR, TCM_REG_CSEM_IFEN, 0x1},
	{OP_WR, TCM_REG_CDU_AG_WR_IFEN, 0x1},
	{OP_WR, TCM_REG_CDU_AG_RD_IFEN, 0x1},
	{OP_WR, TCM_REG_CDU_SM_WR_IFEN, 0x1},
	{OP_WR, TCM_REG_CDU_SM_RD_IFEN, 0x1},
	{OP_WR, TCM_REG_TCM_CFC_IFEN, 0x1},
/* #define TCM_COMMON_END          67 */
/* #define TCM_FUNC0_START         72 */
	{OP_WR, TCM_REG_PHYS_QNUM0_0, 0xd},
	{OP_WR, TCM_REG_PHYS_QNUM1_0, 0x7},
	{OP_WR, TCM_REG_PHYS_QNUM2_0, 0x7},
	{OP_WR, TCM_REG_PHYS_QNUM3_0, 0x7},
/* #define TCM_FUNC0_END           73 */
/* #define TCM_FUNC1_START         74 */
	{OP_WR, TCM_REG_PHYS_QNUM0_1, 0x2d},
	{OP_WR, TCM_REG_PHYS_QNUM1_1, 0x27},
	{OP_WR, TCM_REG_PHYS_QNUM2_1, 0x27},
	{OP_WR, TCM_REG_PHYS_QNUM3_1, 0x27},
/* #define TCM_FUNC1_END           75 */
/* #define TCM_FUNC2_START         76 */
	{OP_WR, TCM_REG_PHYS_QNUM0_0, 0x1d},
	{OP_WR, TCM_REG_PHYS_QNUM1_0, 0x17},
	{OP_WR, TCM_REG_PHYS_QNUM2_0, 0x17},
	{OP_WR, TCM_REG_PHYS_QNUM3_0, 0x17},
/* #define TCM_FUNC2_END           77 */
/* #define TCM_FUNC3_START         78 */
	{OP_WR, TCM_REG_PHYS_QNUM0_1, 0x3d},
	{OP_WR, TCM_REG_PHYS_QNUM1_1, 0x37},
	{OP_WR, TCM_REG_PHYS_QNUM2_1, 0x37},
	{OP_WR, TCM_REG_PHYS_QNUM3_1, 0x37},
/* #define TCM_FUNC3_END           79 */
/* #define TCM_FUNC4_START         80 */
	{OP_WR, TCM_REG_PHYS_QNUM0_0, 0x4d},
	{OP_WR, TCM_REG_PHYS_QNUM1_0, 0x47},
	{OP_WR, TCM_REG_PHYS_QNUM2_0, 0x47},
	{OP_WR, TCM_REG_PHYS_QNUM3_0, 0x47},
/* #define TCM_FUNC4_END           81 */
/* #define TCM_FUNC5_START         82 */
	{OP_WR, TCM_REG_PHYS_QNUM0_1, 0x6d},
	{OP_WR, TCM_REG_PHYS_QNUM1_1, 0x67},
	{OP_WR, TCM_REG_PHYS_QNUM2_1, 0x67},
	{OP_WR, TCM_REG_PHYS_QNUM3_1, 0x67},
/* #define TCM_FUNC5_END           83 */
/* #define TCM_FUNC6_START         84 */
	{OP_WR, TCM_REG_PHYS_QNUM0_0, 0x5d},
	{OP_WR, TCM_REG_PHYS_QNUM1_0, 0x57},
	{OP_WR, TCM_REG_PHYS_QNUM2_0, 0x57},
	{OP_WR, TCM_REG_PHYS_QNUM3_0, 0x57},
/* #define TCM_FUNC6_END           85 */
/* #define TCM_FUNC7_START         86 */
	{OP_WR, TCM_REG_PHYS_QNUM0_1, 0x7d},
	{OP_WR, TCM_REG_PHYS_QNUM1_1, 0x77},
	{OP_WR, TCM_REG_PHYS_QNUM2_1, 0x77},
	{OP_WR, TCM_REG_PHYS_QNUM3_1, 0x77},
/* #define TCM_FUNC7_END           87 */
/* #define BRB1_COMMON_START       88 */
	{OP_SW, BRB1_REG_LL_RAM, 0x2000020},
	{OP_WR, BRB1_REG_SOFT_RESET, 0x1},
	{OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_4, 0x0},
	{OP_SW, BRB1_REG_FREE_LIST_PRS_CRDT, 0x30220},
	{OP_WR, BRB1_REG_SOFT_RESET, 0x0},
/* #define BRB1_COMMON_END         89 */
/* #define BRB1_PORT0_START        90 */
	{OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_0, 0x0},
	{OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_0, 0x0},
/* #define BRB1_PORT0_END          91 */
/* #define BRB1_PORT1_START        92 */
	{OP_RD, BRB1_REG_NUM_OF_PAUSE_CYCLES_1, 0x0},
	{OP_RD, BRB1_REG_NUM_OF_FULL_CYCLES_1, 0x0},
/* #define BRB1_PORT1_END          93 */
/* #define TSEM_COMMON_START       110 */
	{OP_ZP, TSEM_REG_INT_TABLE, 0xa90000},
	{OP_WR_64, TSEM_REG_INT_TABLE + 0x3c8, 0x70223},
	{OP_ZP, TSEM_REG_PRAM, 0x2c2c0000},
	{OP_ZP, TSEM_REG_PRAM + 0x8000, 0x38930b0c},
	{OP_ZP, TSEM_REG_PRAM + 0x10000, 0x29311931},
	{OP_WR_64, TSEM_REG_PRAM + 0x16860, 0x52f40225},
	{OP_RD, TSEM_REG_MSG_NUM_FIC0, 0x0},
	{OP_RD, TSEM_REG_MSG_NUM_FIC1, 0x0},
	{OP_RD, TSEM_REG_MSG_NUM_FOC0, 0x0},
	{OP_RD, TSEM_REG_MSG_NUM_FOC1, 0x0},
	{OP_RD, TSEM_REG_MSG_NUM_FOC2, 0x0},
	{OP_RD, TSEM_REG_MSG_NUM_FOC3, 0x0},
	{OP_WR, TSEM_REG_ARB_ELEMENT0, 0x1},
	{OP_WR, TSEM_REG_ARB_ELEMENT1, 0x2},
	{OP_WR, TSEM_REG_ARB_ELEMENT2, 0x3},
	{OP_WR, TSEM_REG_ARB_ELEMENT3, 0x0},
	{OP_WR, TSEM_REG_ARB_ELEMENT4, 0x4},
	{OP_WR, TSEM_REG_ARB_CYCLE_SIZE, 0x1},
	{OP_WR, TSEM_REG_TS_0_AS, 0x0},
	{OP_WR, TSEM_REG_TS_1_AS, 0x1},
	{OP_WR, TSEM_REG_TS_2_AS, 0x4},
	{OP_WR, TSEM_REG_TS_3_AS, 0x0},
	{OP_WR, TSEM_REG_TS_4_AS, 0x1},
	{OP_WR, TSEM_REG_TS_5_AS, 0x3},
	{OP_WR, TSEM_REG_TS_6_AS, 0x0},
	{OP_WR, TSEM_REG_TS_7_AS, 0x1},
	{OP_WR, TSEM_REG_TS_8_AS, 0x4},
	{OP_WR, TSEM_REG_TS_9_AS, 0x0},
	{OP_WR, TSEM_REG_TS_10_AS, 0x1},
	{OP_WR, TSEM_REG_TS_11_AS, 0x3},
	{OP_WR, TSEM_REG_TS_12_AS, 0x0},
	{OP_WR, TSEM_REG_TS_13_AS, 0x1},
	{OP_WR, TSEM_REG_TS_14_AS, 0x4},
	{OP_WR, TSEM_REG_TS_15_AS, 0x0},
	{OP_WR, TSEM_REG_TS_16_AS, 0x4},
	{OP_WR, TSEM_REG_TS_17_AS, 0x3},
	{OP_ZR, TSEM_REG_TS_18_AS, 0x2},
	{OP_WR, TSEM_REG_ENABLE_IN, 0x3fff},
	{OP_WR, TSEM_REG_ENABLE_OUT, 0x3ff},
	{OP_WR, TSEM_REG_FIC0_DISABLE, 0x0},
	{OP_WR, TSEM_REG_FIC1_DISABLE, 0x0},
	{OP_WR, TSEM_REG_PAS_DISABLE, 0x0},
	{OP_WR, TSEM_REG_THREADS_LIST, 0xff},
	{OP_ZR, TSEM_REG_PASSIVE_BUFFER, 0x400},
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18000, 0x34},
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18040, 0x18},
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x18080, 0xc},
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x180c0, 0x20},
	{OP_WR_ASIC, TSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
	{OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x18300, 0x138},
	{OP_WR_FPGA, TSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x11480, 0x1},
	{OP_WR_EMUL, TSEM_REG_FAST_MEMORY + 0x11480, 0x0},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1000, 0x3b3},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x1000 + 0xecc, 0x10227},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xa020, 0xc8},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xa000, 0x2},
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x1ed0, 0x0},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x1ed8, 0x6},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x36e8, 0x4},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x36e0, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5008, 0x4},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5018, 0x4},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5028, 0x4},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5038, 0x4},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5048, 0x4},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5058, 0x4},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5068, 0x4},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5078, 0x2},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4040, 0x20228},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x62c0, 0x20022a},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd100, 0x2},
/* #define TSEM_COMMON_END         111 */
/* #define TSEM_PORT0_START        112 */
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x2000, 0x124},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xb000, 0x28},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xb140, 0xc},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3300, 0x14},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x33a0, 0x68},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x8108, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd1c8, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd1d8, 0x20},
/* #define TSEM_PORT0_END          113 */
/* #define TSEM_PORT1_START        114 */
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x2490, 0x124},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xb0a0, 0x28},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xb170, 0xc},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3350, 0x14},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3540, 0x68},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x8110, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd1d0, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd258, 0x20},
/* #define TSEM_PORT1_END          115 */
/* #define TSEM_FUNC0_START        116 */
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x2920, 0x0},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3000, 0x2},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x3000 + 0x8, 0x5024a},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3000 + 0x1c, 0x9},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3200, 0x8},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5000, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5080, 0x12},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x4000, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0c0, 0x2},
/* #define TSEM_FUNC0_END          117 */
/* #define TSEM_FUNC1_START        118 */
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x2924, 0x0},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3040, 0x2},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x3040 + 0x8, 0x5024f},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3040 + 0x1c, 0x9},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3220, 0x8},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5010, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x50c8, 0x12},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x4008, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0c8, 0x2},
/* #define TSEM_FUNC1_END          119 */
/* #define TSEM_FUNC2_START        120 */
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x2928, 0x0},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3080, 0x2},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x3080 + 0x8, 0x50254},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3080 + 0x1c, 0x9},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3240, 0x8},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5020, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5110, 0x12},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4010, 0x20259},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0d0, 0x2},
/* #define TSEM_FUNC2_END          121 */
/* #define TSEM_FUNC3_START        122 */
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x292c, 0x0},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x30c0, 0x2},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x30c0 + 0x8, 0x5025b},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x30c0 + 0x1c, 0x9},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3260, 0x8},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5030, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5158, 0x12},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4018, 0x20260},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0d8, 0x2},
/* #define TSEM_FUNC3_END          123 */
/* #define TSEM_FUNC4_START        124 */
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x2930, 0x0},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3100, 0x2},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x3100 + 0x8, 0x50262},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3100 + 0x1c, 0x9},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3280, 0x8},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5040, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x51a0, 0x12},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4020, 0x20267},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0e0, 0x2},
/* #define TSEM_FUNC4_END          125 */
/* #define TSEM_FUNC5_START        126 */
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x2934, 0x0},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3140, 0x2},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x3140 + 0x8, 0x50269},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3140 + 0x1c, 0x9},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x32a0, 0x8},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5050, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x51e8, 0x12},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4028, 0x2026e},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0e8, 0x2},
/* #define TSEM_FUNC5_END          127 */
/* #define TSEM_FUNC6_START        128 */
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x2938, 0x0},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3180, 0x2},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x3180 + 0x8, 0x50270},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x3180 + 0x1c, 0x9},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x32c0, 0x8},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5060, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5230, 0x12},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4030, 0x20275},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0f0, 0x2},
/* #define TSEM_FUNC6_END          129 */
/* #define TSEM_FUNC7_START        130 */
	{OP_WR, TSEM_REG_FAST_MEMORY + 0x293c, 0x0},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x31c0, 0x2},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x31c0 + 0x8, 0x50277},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x31c0 + 0x1c, 0x9},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x32e0, 0x8},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5070, 0x2},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0x5278, 0x12},
	{OP_SW, TSEM_REG_FAST_MEMORY + 0x4038, 0x2027c},
	{OP_ZR, TSEM_REG_FAST_MEMORY + 0xd0f8, 0x2},
/* #define TSEM_FUNC7_END          131 */
/* #define MISC_COMMON_START       220 */
	{OP_WR, MISC_REG_PLL_STORM_CTRL_1, 0x71d2911},
	{OP_WR, MISC_REG_PLL_STORM_CTRL_2, 0x0},
	{OP_WR, MISC_REG_PLL_STORM_CTRL_3, 0x9c0424},
	{OP_WR, MISC_REG_PLL_STORM_CTRL_4, 0x0},
	{OP_WR, MISC_REG_LCPLL_CTRL_1, 0x209},
/* #define MISC_COMMON_END         221 */
/* #define MISC_FUNC0_START        226 */
	{OP_WR, MISC_REG_NIG_WOL_P0, 0x0},
/* #define MISC_FUNC0_END          227 */
/* #define MISC_FUNC1_START        228 */
	{OP_WR, MISC_REG_NIG_WOL_P1, 0x0},
/* #define MISC_FUNC1_END          229 */
/* #define MISC_FUNC2_START        230 */
	{OP_WR, MISC_REG_NIG_WOL_P0, 0x0},
/* #define MISC_FUNC2_END          231 */
/* #define MISC_FUNC3_START        232 */
	{OP_WR, MISC_REG_NIG_WOL_P1, 0x0},
/* #define MISC_FUNC3_END          233 */
/* #define MISC_FUNC4_START        234 */
	{OP_WR, MISC_REG_NIG_WOL_P0, 0x0},
/* #define MISC_FUNC4_END          235 */
/* #define MISC_FUNC5_START        236 */
	{OP_WR, MISC_REG_NIG_WOL_P1, 0x0},
/* #define MISC_FUNC5_END          237 */
/* #define MISC_FUNC6_START        238 */
	{OP_WR, MISC_REG_NIG_WOL_P0, 0x0},
/* #define MISC_FUNC6_END          239 */
/* #define MISC_FUNC7_START        240 */
	{OP_WR, MISC_REG_NIG_WOL_P1, 0x0},
/* #define MISC_FUNC7_END          241 */
/* #define NIG_COMMON_START        264 */
	{OP_WR, NIG_REG_PBF_LB_IN_EN, 0x1},
	{OP_WR, NIG_REG_PRS_REQ_IN_EN, 0x1},
	{OP_WR, NIG_REG_EGRESS_DEBUG_IN_EN, 0x1},
	{OP_WR, NIG_REG_BRB_LB_OUT_EN, 0x1},
	{OP_WR, NIG_REG_PRS_EOP_OUT_EN, 0x1},
/* #define NIG_COMMON_END          265 */
/* #define NIG_PORT0_START         266 */
	{OP_WR, NIG_REG_LLH0_CM_HEADER, 0x300000},
	{OP_WR, NIG_REG_LLH0_EVENT_ID, 0x28},
	{OP_WR, NIG_REG_LLH0_ERROR_MASK, 0x0},
	{OP_WR, NIG_REG_LLH0_XCM_MASK, 0x4},
	{OP_WR, NIG_REG_LLH0_BRB1_NOT_MCP, 0x1},
	{OP_WR, NIG_REG_STATUS_INTERRUPT_PORT0, 0x0},
	{OP_WR, NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7},
	{OP_WR, NIG_REG_LLH0_CLS_TYPE, 0x1},
	{OP_WR, NIG_REG_LLH0_XCM_INIT_CREDIT, 0x30},
	{OP_WR, NIG_REG_BRB0_PAUSE_IN_EN, 0x1},
	{OP_WR, NIG_REG_EGRESS_PBF0_IN_EN, 0x1},
	{OP_WR, NIG_REG_BRB0_OUT_EN, 0x1},
	{OP_WR, NIG_REG_XCM0_OUT_EN, 0x1},
/* #define NIG_PORT0_END           267 */
/* #define NIG_PORT1_START         268 */
	{OP_WR, NIG_REG_LLH1_CM_HEADER, 0x300000},
	{OP_WR, NIG_REG_LLH1_EVENT_ID, 0x28},
	{OP_WR, NIG_REG_LLH1_ERROR_MASK, 0x0},
	{OP_WR, NIG_REG_LLH1_XCM_MASK, 0x4},
	{OP_WR, NIG_REG_LLH1_BRB1_NOT_MCP, 0x1},
	{OP_WR, NIG_REG_STATUS_INTERRUPT_PORT1, 0x0},
	{OP_WR, NIG_REG_LLFC_EGRESS_SRC_ENABLE_1, 0x7},
	{OP_WR, NIG_REG_LLH1_CLS_TYPE, 0x1},
	{OP_WR, NIG_REG_LLH1_XCM_INIT_CREDIT, 0x30},
	{OP_WR, NIG_REG_BRB1_PAUSE_IN_EN, 0x1},
	{OP_WR, NIG_REG_EGRESS_PBF1_IN_EN, 0x1},
	{OP_WR, NIG_REG_BRB1_OUT_EN, 0x1},
	{OP_WR, NIG_REG_XCM1_OUT_EN, 0x1},
/* #define NIG_PORT1_END           269 */
/* #define UPB_COMMON_START        308 */
	{OP_WR, GRCBASE_UPB + PB_REG_CONTROL, 0x20},
/* #define UPB_COMMON_END          309 */
/* #define CSDM_COMMON_START       330 */
	{OP_WR, CSDM_REG_CFC_RSP_START_ADDR, 0x211},
	{OP_WR, CSDM_REG_CMP_COUNTER_START_ADDR, 0x200},
	{OP_WR, CSDM_REG_Q_COUNTER_START_ADDR, 0x204},
	{OP_WR, CSDM_REG_CMP_COUNTER_MAX0, 0xffff},
	{OP_WR, CSDM_REG_CMP_COUNTER_MAX1, 0xffff},
	{OP_WR, CSDM_REG_CMP_COUNTER_MAX2, 0xffff},
	{OP_WR, CSDM_REG_CMP_COUNTER_MAX3, 0xffff},
	{OP_ZR, CSDM_REG_AGG_INT_EVENT_0, 0x2},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_2, 0x34},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_3, 0x35},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_4, 0x20},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_5, 0x21},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_6, 0x22},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_7, 0x23},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_8, 0x24},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_9, 0x25},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_10, 0x26},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_11, 0x27},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_12, 0x28},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_13, 0x29},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_14, 0x2a},
	{OP_WR, CSDM_REG_AGG_INT_EVENT_15, 0x2b},
	{OP_ZR, CSDM_REG_AGG_INT_EVENT_16, 0x56},
	{OP_WR, CSDM_REG_AGG_INT_MODE_6, 0x1},
	{OP_WR, CSDM_REG_AGG_INT_MODE_7, 0x1},
	{OP_WR, CSDM_REG_AGG_INT_MODE_8, 0x1},
	{OP_WR, CSDM_REG_AGG_INT_MODE_9, 0x1},
	{OP_WR, CSDM_REG_AGG_INT_MODE_10, 0x1},
	{OP_WR, CSDM_REG_AGG_INT_MODE_11, 0x1},
	{OP_WR, CSDM_REG_AGG_INT_MODE_12, 0x1},
	{OP_WR, CSDM_REG_AGG_INT_MODE_13, 0x1},
	{OP_WR, CSDM_REG_AGG_INT_MODE_14, 0x1},
	{OP_WR, CSDM_REG_AGG_INT_MODE_15, 0x1},
	{OP_ZR, CSDM_REG_AGG_INT_MODE_16, 0x10},
	{OP_WR, CSDM_REG_ENABLE_IN1, 0x7ffffff},
	{OP_WR, CSDM_REG_ENABLE_IN2, 0x3f},
	{OP_WR, CSDM_REG_ENABLE_OUT1, 0x7ffffff},
	{OP_WR, CSDM_REG_ENABLE_OUT2, 0xf},
	{OP_RD, CSDM_REG_NUM_OF_Q0_CMD, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_Q1_CMD, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_Q3_CMD, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_Q4_CMD, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_Q5_CMD, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_Q6_CMD, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_Q7_CMD, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_Q8_CMD, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_Q9_CMD, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_Q10_CMD, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_Q11_CMD, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
	{OP_RD, CSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
	{OP_WR_ASIC, CSDM_REG_TIMER_TICK, 0x3e8},
	{OP_WR_EMUL, CSDM_REG_TIMER_TICK, 0x1},
	{OP_WR_FPGA, CSDM_REG_TIMER_TICK, 0xa},
/* #define CSDM_COMMON_END         331 */
/* #define USDM_COMMON_START       352 */
	{OP_WR, USDM_REG_CFC_RSP_START_ADDR, 0x411},
	{OP_WR, USDM_REG_CMP_COUNTER_START_ADDR, 0x400},
	{OP_WR, USDM_REG_Q_COUNTER_START_ADDR, 0x404},
	{OP_WR, USDM_REG_PCK_END_MSG_START_ADDR, 0x421},
	{OP_WR, USDM_REG_CMP_COUNTER_MAX0, 0xffff},
	{OP_WR, USDM_REG_CMP_COUNTER_MAX1, 0xffff},
	{OP_WR, USDM_REG_CMP_COUNTER_MAX2, 0xffff},
	{OP_WR, USDM_REG_CMP_COUNTER_MAX3, 0xffff},
	{OP_WR, USDM_REG_AGG_INT_EVENT_0, 0x46},
	{OP_WR, USDM_REG_AGG_INT_EVENT_1, 0x5},
	{OP_ZR, USDM_REG_AGG_INT_EVENT_2, 0x2},
	{OP_WR, USDM_REG_AGG_INT_EVENT_4, 0xa},
	{OP_WR, USDM_REG_AGG_INT_EVENT_5, 0xf0},
	{OP_ZR, USDM_REG_AGG_INT_EVENT_6, 0x1f},
	{OP_WR, USDM_REG_AGG_INT_T_5, 0x1},
	{OP_ZR, USDM_REG_AGG_INT_T_6, 0x3a},
	{OP_WR, USDM_REG_AGG_INT_MODE_0, 0x1},
	{OP_ZR, USDM_REG_AGG_INT_MODE_1, 0x3},
	{OP_WR, USDM_REG_AGG_INT_MODE_4, 0x1},
	{OP_WR, USDM_REG_AGG_INT_MODE_5, 0x1},
	{OP_ZR, USDM_REG_AGG_INT_MODE_6, 0x1a},
	{OP_WR, USDM_REG_ENABLE_IN1, 0x7ffffff},
	{OP_WR, USDM_REG_ENABLE_IN2, 0x3f},
	{OP_WR, USDM_REG_ENABLE_OUT1, 0x7ffffff},
	{OP_WR, USDM_REG_ENABLE_OUT2, 0xf},
	{OP_RD, USDM_REG_NUM_OF_Q0_CMD, 0x0},
	{OP_RD, USDM_REG_NUM_OF_Q1_CMD, 0x0},
	{OP_RD, USDM_REG_NUM_OF_Q2_CMD, 0x0},
	{OP_RD, USDM_REG_NUM_OF_Q3_CMD, 0x0},
	{OP_RD, USDM_REG_NUM_OF_Q4_CMD, 0x0},
	{OP_RD, USDM_REG_NUM_OF_Q5_CMD, 0x0},
	{OP_RD, USDM_REG_NUM_OF_Q6_CMD, 0x0},
	{OP_RD, USDM_REG_NUM_OF_Q7_CMD, 0x0},
	{OP_RD, USDM_REG_NUM_OF_Q8_CMD, 0x0},
	{OP_RD, USDM_REG_NUM_OF_Q9_CMD, 0x0},
	{OP_RD, USDM_REG_NUM_OF_Q10_CMD, 0x0},
	{OP_RD, USDM_REG_NUM_OF_Q11_CMD, 0x0},
	{OP_RD, USDM_REG_NUM_OF_PKT_END_MSG, 0x0},
	{OP_RD, USDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
	{OP_RD, USDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
	{OP_WR_ASIC, USDM_REG_TIMER_TICK, 0x3e8},
	{OP_WR_EMUL, USDM_REG_TIMER_TICK, 0x1},
	{OP_WR_FPGA, USDM_REG_TIMER_TICK, 0xa},
/* #define USDM_COMMON_END         353 */
/* #define CCM_COMMON_START        374 */
	{OP_WR, CCM_REG_XX_OVFL_EVNT_ID, 0x32},
	{OP_WR, CCM_REG_CQM_CCM_HDR_P, 0x2150020},
	{OP_WR, CCM_REG_CQM_CCM_HDR_S, 0x2150020},
	{OP_WR, CCM_REG_ERR_CCM_HDR, 0x8100000},
	{OP_WR, CCM_REG_ERR_EVNT_ID, 0x33},
	{OP_WR, CCM_REG_STORM_WEIGHT, 0x2},
	{OP_WR, CCM_REG_TSEM_WEIGHT, 0x0},
	{OP_WR, CCM_REG_XSEM_WEIGHT, 0x5},
	{OP_WR, CCM_REG_USEM_WEIGHT, 0x5},
	{OP_ZR, CCM_REG_PBF_WEIGHT, 0x2},
	{OP_WR, CCM_REG_CSDM_WEIGHT, 0x2},
	{OP_WR, CCM_REG_CQM_P_WEIGHT, 0x3},
	{OP_WR, CCM_REG_CQM_S_WEIGHT, 0x2},
	{OP_WR, CCM_REG_CCM_CQM_USE_Q, 0x1},
	{OP_WR, CCM_REG_CNT_AUX1_Q, 0x2},
	{OP_WR, CCM_REG_CNT_AUX2_Q, 0x2},
	{OP_WR, CCM_REG_INV_DONE_Q, 0x1},
	{OP_WR, CCM_REG_GR_ARB_TYPE, 0x1},
	{OP_WR, CCM_REG_GR_LD0_PR, 0x1},
	{OP_WR, CCM_REG_GR_LD1_PR, 0x2},
	{OP_WR, CCM_REG_CFC_INIT_CRD, 0x1},
	{OP_WR, CCM_REG_CQM_INIT_CRD, 0x20},
	{OP_WR, CCM_REG_FIC0_INIT_CRD, 0x40},
	{OP_WR, CCM_REG_FIC1_INIT_CRD, 0x40},
	{OP_WR, CCM_REG_XX_INIT_CRD, 0x3},
	{OP_WR, CCM_REG_XX_MSG_NUM, 0x18},
	{OP_ZR, CCM_REG_XX_TABLE, 0x12},
	{OP_SW, CCM_REG_XX_DESCR_TABLE, 0x24027e},
	{OP_WR, CCM_REG_N_SM_CTX_LD_0, 0x1},
	{OP_WR, CCM_REG_N_SM_CTX_LD_1, 0x2},
	{OP_WR, CCM_REG_N_SM_CTX_LD_2, 0x8},
	{OP_WR, CCM_REG_N_SM_CTX_LD_3, 0x8},
	{OP_ZR, CCM_REG_N_SM_CTX_LD_4, 0x4},
	{OP_WR, CCM_REG_CCM_REG0_SZ, 0x4},
	{OP_WR, CCM_REG_CCM_STORM0_IFEN, 0x1},
	{OP_WR, CCM_REG_CCM_STORM1_IFEN, 0x1},
	{OP_WR, CCM_REG_CCM_CQM_IFEN, 0x1},
	{OP_WR, CCM_REG_STORM_CCM_IFEN, 0x1},
	{OP_WR, CCM_REG_CQM_CCM_IFEN, 0x1},
	{OP_WR, CCM_REG_CSDM_IFEN, 0x1},
	{OP_WR, CCM_REG_TSEM_IFEN, 0x1},
	{OP_WR, CCM_REG_XSEM_IFEN, 0x1},
	{OP_WR, CCM_REG_USEM_IFEN, 0x1},
	{OP_WR, CCM_REG_PBF_IFEN, 0x1},
	{OP_WR, CCM_REG_CDU_AG_WR_IFEN, 0x1},
	{OP_WR, CCM_REG_CDU_AG_RD_IFEN, 0x1},
	{OP_WR, CCM_REG_CDU_SM_WR_IFEN, 0x1},
	{OP_WR, CCM_REG_CDU_SM_RD_IFEN, 0x1},
	{OP_WR, CCM_REG_CCM_CFC_IFEN, 0x1},
/* #define CCM_COMMON_END          375 */
/* #define CCM_FUNC0_START         380 */
	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x9},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0xa},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x7},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x7},
	{OP_WR, CCM_REG_PHYS_QNUM1_0, 0xc},
	{OP_WR, CCM_REG_PHYS_QNUM2_0, 0xb},
	{OP_WR, CCM_REG_PHYS_QNUM3_0, 0x7},
/* #define CCM_FUNC0_END           381 */
/* #define CCM_FUNC1_START         382 */
	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x29},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x2a},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x27},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x27},
	{OP_WR, CCM_REG_PHYS_QNUM1_1, 0x2c},
	{OP_WR, CCM_REG_PHYS_QNUM2_1, 0x2b},
	{OP_WR, CCM_REG_PHYS_QNUM3_1, 0x27},
/* #define CCM_FUNC1_END           383 */
/* #define CCM_FUNC2_START         384 */
	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x19},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0x1a},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x17},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x17},
	{OP_WR, CCM_REG_PHYS_QNUM1_0, 0x1c},
	{OP_WR, CCM_REG_PHYS_QNUM2_0, 0x1b},
	{OP_WR, CCM_REG_PHYS_QNUM3_0, 0x17},
/* #define CCM_FUNC2_END           385 */
/* #define CCM_FUNC3_START         386 */
	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x39},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x3a},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x37},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x37},
	{OP_WR, CCM_REG_PHYS_QNUM1_1, 0x3c},
	{OP_WR, CCM_REG_PHYS_QNUM2_1, 0x3b},
	{OP_WR, CCM_REG_PHYS_QNUM3_1, 0x37},
/* #define CCM_FUNC3_END           387 */
/* #define CCM_FUNC4_START         388 */
	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x49},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0x4a},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x47},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x47},
	{OP_WR, CCM_REG_PHYS_QNUM1_0, 0x4c},
	{OP_WR, CCM_REG_PHYS_QNUM2_0, 0x4b},
	{OP_WR, CCM_REG_PHYS_QNUM3_0, 0x47},
/* #define CCM_FUNC4_END           389 */
/* #define CCM_FUNC5_START         390 */
	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x69},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x6a},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x67},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x67},
	{OP_WR, CCM_REG_PHYS_QNUM1_1, 0x6c},
	{OP_WR, CCM_REG_PHYS_QNUM2_1, 0x6b},
	{OP_WR, CCM_REG_PHYS_QNUM3_1, 0x67},
/* #define CCM_FUNC5_END           391 */
/* #define CCM_FUNC6_START         392 */
	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_0, 0x59},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_0, 0x5a},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_0, 0x57},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_0, 0x57},
	{OP_WR, CCM_REG_PHYS_QNUM1_0, 0x5c},
	{OP_WR, CCM_REG_PHYS_QNUM2_0, 0x5b},
	{OP_WR, CCM_REG_PHYS_QNUM3_0, 0x57},
/* #define CCM_FUNC6_END           393 */
/* #define CCM_FUNC7_START         394 */
	{OP_WR, CCM_REG_QOS_PHYS_QNUM0_1, 0x79},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM1_1, 0x7a},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM2_1, 0x77},
	{OP_WR, CCM_REG_QOS_PHYS_QNUM3_1, 0x77},
	{OP_WR, CCM_REG_PHYS_QNUM1_1, 0x7c},
	{OP_WR, CCM_REG_PHYS_QNUM2_1, 0x7b},
	{OP_WR, CCM_REG_PHYS_QNUM3_1, 0x77},
/* #define CCM_FUNC7_END           395 */
/* #define UCM_COMMON_START        396 */
	{OP_WR, UCM_REG_XX_OVFL_EVNT_ID, 0x32},
	{OP_WR, UCM_REG_UQM_UCM_HDR_P, 0x2150020},
	{OP_WR, UCM_REG_UQM_UCM_HDR_S, 0x2150020},
	{OP_WR, UCM_REG_TM_UCM_HDR, 0x30},
	{OP_WR, UCM_REG_ERR_UCM_HDR, 0x8100000},
	{OP_WR, UCM_REG_ERR_EVNT_ID, 0x33},
	{OP_WR, UCM_REG_EXPR_EVNT_ID, 0x30},
	{OP_WR, UCM_REG_STOP_EVNT_ID, 0x31},
	{OP_WR, UCM_REG_STORM_WEIGHT, 0x2},
	{OP_WR, UCM_REG_TSEM_WEIGHT, 0x4},
	{OP_WR, UCM_REG_CSEM_WEIGHT, 0x0},
	{OP_WR, UCM_REG_XSEM_WEIGHT, 0x2},
	{OP_WR, UCM_REG_DORQ_WEIGHT, 0x2},
	{OP_WR, UCM_REG_CP_WEIGHT, 0x0},
	{OP_WR, UCM_REG_USDM_WEIGHT, 0x2},
	{OP_WR, UCM_REG_UQM_P_WEIGHT, 0x7},
	{OP_WR, UCM_REG_UQM_S_WEIGHT, 0x2},
	{OP_WR, UCM_REG_TM_WEIGHT, 0x2},
	{OP_WR, UCM_REG_UCM_UQM_USE_Q, 0x1},
	{OP_WR, UCM_REG_INV_CFLG_Q, 0x1},
	{OP_WR, UCM_REG_GR_ARB_TYPE, 0x1},
	{OP_WR, UCM_REG_GR_LD0_PR, 0x1},
	{OP_WR, UCM_REG_GR_LD1_PR, 0x2},
	{OP_WR, UCM_REG_CFC_INIT_CRD, 0x1},
	{OP_WR, UCM_REG_FIC0_INIT_CRD, 0x40},
	{OP_WR, UCM_REG_FIC1_INIT_CRD, 0x40},
	{OP_WR, UCM_REG_TM_INIT_CRD, 0x4},
	{OP_WR, UCM_REG_UQM_INIT_CRD, 0x20},
	{OP_WR, UCM_REG_XX_INIT_CRD, 0xe},
	{OP_WR, UCM_REG_XX_MSG_NUM, 0x1b},
	{OP_ZR, UCM_REG_XX_TABLE, 0x12},
	{OP_SW, UCM_REG_XX_DESCR_TABLE, 0x1b02a2},
	{OP_WR, UCM_REG_N_SM_CTX_LD_0, 0xc},
	{OP_WR, UCM_REG_N_SM_CTX_LD_1, 0x9},
	{OP_WR, UCM_REG_N_SM_CTX_LD_2, 0xf},
	{OP_WR, UCM_REG_N_SM_CTX_LD_3, 0x10},
	{OP_WR, UCM_REG_N_SM_CTX_LD_4, 0xb},
	{OP_ZR, UCM_REG_N_SM_CTX_LD_5, 0x3},
	{OP_WR, UCM_REG_UCM_REG0_SZ, 0x3},
	{OP_WR, UCM_REG_UCM_STORM0_IFEN, 0x1},
	{OP_WR, UCM_REG_UCM_STORM1_IFEN, 0x1},
	{OP_WR, UCM_REG_UCM_UQM_IFEN, 0x1},
	{OP_WR, UCM_REG_STORM_UCM_IFEN, 0x1},
	{OP_WR, UCM_REG_UQM_UCM_IFEN, 0x1},
	{OP_WR, UCM_REG_USDM_IFEN, 0x1},
	{OP_WR, UCM_REG_TM_UCM_IFEN, 0x1},
	{OP_WR, UCM_REG_UCM_TM_IFEN, 0x1},
	{OP_WR, UCM_REG_TSEM_IFEN, 0x1},
	{OP_WR, UCM_REG_CSEM_IFEN, 0x1},
	{OP_WR, UCM_REG_XSEM_IFEN, 0x1},
	{OP_WR, UCM_REG_DORQ_IFEN, 0x1},
	{OP_WR, UCM_REG_CDU_AG_WR_IFEN, 0x1},
	{OP_WR, UCM_REG_CDU_AG_RD_IFEN, 0x1},
	{OP_WR, UCM_REG_CDU_SM_WR_IFEN, 0x1},
	{OP_WR, UCM_REG_CDU_SM_RD_IFEN, 0x1},
	{OP_WR, UCM_REG_UCM_CFC_IFEN, 0x1},
/* #define UCM_COMMON_END          397 */
/* #define UCM_FUNC0_START         402 */
	{OP_WR, UCM_REG_PHYS_QNUM0_0, 0xf},
	{OP_WR, UCM_REG_PHYS_QNUM1_0, 0xe},
	{OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0},
	{OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0},
/* #define UCM_FUNC0_END           403 */
/* #define UCM_FUNC1_START         404 */
	{OP_WR, UCM_REG_PHYS_QNUM0_1, 0x2f},
	{OP_WR, UCM_REG_PHYS_QNUM1_1, 0x2e},
	{OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0},
	{OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0},
/* #define UCM_FUNC1_END           405 */
/* #define UCM_FUNC2_START         406 */
	{OP_WR, UCM_REG_PHYS_QNUM0_0, 0x1f},
	{OP_WR, UCM_REG_PHYS_QNUM1_0, 0x1e},
	{OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0},
	{OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0},
/* #define UCM_FUNC2_END           407 */
/* #define UCM_FUNC3_START         408 */
	{OP_WR, UCM_REG_PHYS_QNUM0_1, 0x3f},
	{OP_WR, UCM_REG_PHYS_QNUM1_1, 0x3e},
	{OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0},
	{OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0},
/* #define UCM_FUNC3_END           409 */
/* #define UCM_FUNC4_START         410 */
	{OP_WR, UCM_REG_PHYS_QNUM0_0, 0x4f},
	{OP_WR, UCM_REG_PHYS_QNUM1_0, 0x4e},
	{OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0},
	{OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0},
/* #define UCM_FUNC4_END           411 */
/* #define UCM_FUNC5_START         412 */
	{OP_WR, UCM_REG_PHYS_QNUM0_1, 0x6f},
	{OP_WR, UCM_REG_PHYS_QNUM1_1, 0x6e},
	{OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0},
	{OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0},
/* #define UCM_FUNC5_END           413 */
/* #define UCM_FUNC6_START         414 */
	{OP_WR, UCM_REG_PHYS_QNUM0_0, 0x5f},
	{OP_WR, UCM_REG_PHYS_QNUM1_0, 0x5e},
	{OP_WR, UCM_REG_PHYS_QNUM2_0, 0x0},
	{OP_WR, UCM_REG_PHYS_QNUM3_0, 0x0},
/* #define UCM_FUNC6_END           415 */
/* #define UCM_FUNC7_START         416 */
	{OP_WR, UCM_REG_PHYS_QNUM0_1, 0x7f},
	{OP_WR, UCM_REG_PHYS_QNUM1_1, 0x7e},
	{OP_WR, UCM_REG_PHYS_QNUM2_1, 0x0},
	{OP_WR, UCM_REG_PHYS_QNUM3_1, 0x0},
/* #define UCM_FUNC7_END           417 */
/* #define USEM_COMMON_START       418 */
	{OP_ZP, USEM_REG_INT_TABLE, 0xe50000},
	{OP_WR_64, USEM_REG_INT_TABLE + 0x3d8, 0x502bd},
	{OP_ZP, USEM_REG_PRAM, 0x2ef70000},
	{OP_ZP, USEM_REG_PRAM + 0x8000, 0x311a0bbe},
	{OP_ZP, USEM_REG_PRAM + 0x10000, 0x356f1805},
	{OP_ZP, USEM_REG_PRAM + 0x18000, 0x38c42561},
	{OP_ZP, USEM_REG_PRAM + 0x20000, 0x14c53393},
	{OP_WR_64, USEM_REG_PRAM + 0x23400, 0x398002bf},
	{OP_RD, USEM_REG_MSG_NUM_FIC0, 0x0},
	{OP_RD, USEM_REG_MSG_NUM_FIC1, 0x0},
	{OP_RD, USEM_REG_MSG_NUM_FOC0, 0x0},
	{OP_RD, USEM_REG_MSG_NUM_FOC1, 0x0},
	{OP_RD, USEM_REG_MSG_NUM_FOC2, 0x0},
	{OP_RD, USEM_REG_MSG_NUM_FOC3, 0x0},
	{OP_WR, USEM_REG_ARB_ELEMENT0, 0x1},
	{OP_WR, USEM_REG_ARB_ELEMENT1, 0x2},
	{OP_WR, USEM_REG_ARB_ELEMENT2, 0x3},
	{OP_WR, USEM_REG_ARB_ELEMENT3, 0x0},
	{OP_WR, USEM_REG_ARB_ELEMENT4, 0x4},
	{OP_WR, USEM_REG_ARB_CYCLE_SIZE, 0x1},
	{OP_WR, USEM_REG_TS_0_AS, 0x0},
	{OP_WR, USEM_REG_TS_1_AS, 0x1},
	{OP_WR, USEM_REG_TS_2_AS, 0x4},
	{OP_WR, USEM_REG_TS_3_AS, 0x0},
	{OP_WR, USEM_REG_TS_4_AS, 0x1},
	{OP_WR, USEM_REG_TS_5_AS, 0x3},
	{OP_WR, USEM_REG_TS_6_AS, 0x0},
	{OP_WR, USEM_REG_TS_7_AS, 0x1},
	{OP_WR, USEM_REG_TS_8_AS, 0x4},
	{OP_WR, USEM_REG_TS_9_AS, 0x0},
	{OP_WR, USEM_REG_TS_10_AS, 0x1},
	{OP_WR, USEM_REG_TS_11_AS, 0x3},
	{OP_WR, USEM_REG_TS_12_AS, 0x0},
	{OP_WR, USEM_REG_TS_13_AS, 0x1},
	{OP_WR, USEM_REG_TS_14_AS, 0x4},
	{OP_WR, USEM_REG_TS_15_AS, 0x0},
	{OP_WR, USEM_REG_TS_16_AS, 0x4},
	{OP_WR, USEM_REG_TS_17_AS, 0x3},
	{OP_ZR, USEM_REG_TS_18_AS, 0x2},
	{OP_WR, USEM_REG_ENABLE_IN, 0x3fff},
	{OP_WR, USEM_REG_ENABLE_OUT, 0x3ff},
	{OP_WR, USEM_REG_FIC0_DISABLE, 0x0},
	{OP_WR, USEM_REG_FIC1_DISABLE, 0x0},
	{OP_WR, USEM_REG_PAS_DISABLE, 0x0},
	{OP_WR, USEM_REG_THREADS_LIST, 0xffff},
	{OP_ZR, USEM_REG_PASSIVE_BUFFER, 0x800},
	{OP_WR, USEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
	{OP_WR, USEM_REG_FAST_MEMORY + 0x18000, 0x1a},
	{OP_WR, USEM_REG_FAST_MEMORY + 0x18040, 0x4e},
	{OP_WR, USEM_REG_FAST_MEMORY + 0x18080, 0x10},
	{OP_WR, USEM_REG_FAST_MEMORY + 0x180c0, 0x20},
	{OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
	{OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18300, 0x138},
	{OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18300, 0x1388},
	{OP_WR, USEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
	{OP_WR_ASIC, USEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
	{OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
	{OP_WR_FPGA, USEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
	{OP_WR_EMUL, USEM_REG_FAST_MEMORY + 0x11480, 0x0},
	{OP_WR, USEM_REG_FAST_MEMORY + 0x11480, 0x1},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x2000, 0x102},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x8020, 0xc8},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x8000, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x3da8, 0x4},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x3d80, 0x9},
	{OP_SW, USEM_REG_FAST_MEMORY + 0x3d80 + 0x24, 0x102c1},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x3d00, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x400},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4000, 0x4},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x40d0, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x6b68, 0x2},
	{OP_SW, USEM_REG_FAST_MEMORY + 0x6b68 + 0x8, 0x202c2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x6b10, 0x2},
	{OP_SW, USEM_REG_FAST_MEMORY + 0x74c0, 0x202c4},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0xda40, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0xe000, 0x800},
	{OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
	{OP_SW, USEM_REG_FAST_MEMORY + 0x10c00, 0x1002c6},
	{OP_WR, USEM_REG_FAST_MEMORY + 0x10800, 0x0},
	{OP_SW, USEM_REG_FAST_MEMORY + 0x10c40, 0x1002d6},
/* #define USEM_COMMON_END         419 */
/* #define USEM_PORT0_START        420 */
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x2450, 0xb4},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x2ad0, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x1000, 0x1a0},
	{OP_WR, USEM_REG_FAST_MEMORY + 0x3db8, 0x0},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5000, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5100, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5200, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5300, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5400, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5500, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5600, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5700, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5800, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5900, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5a00, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5b00, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5c00, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5d00, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5e00, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5f00, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x6b78, 0x52},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x6e08, 0xc},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0xda88, 0x2},
/* #define USEM_PORT0_END          421 */
/* #define USEM_PORT1_START        422 */
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x2720, 0xb4},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x2ad8, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x1680, 0x1a0},
	{OP_WR, USEM_REG_FAST_MEMORY + 0x3dbc, 0x0},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5080, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5180, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5280, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5380, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5480, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5580, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5680, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5780, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5880, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5980, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5a80, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5b80, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5c80, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5d80, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5e80, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x5f80, 0x20},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x6cc0, 0x52},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x6e38, 0xc},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0xda90, 0x2},
/* #define USEM_PORT1_END          423 */
/* #define USEM_FUNC0_START        424 */
	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a30, 0x0},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4010, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd000, 0x6},
/* #define USEM_FUNC0_END          425 */
/* #define USEM_FUNC1_START        426 */
	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a34, 0x0},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4020, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd018, 0x6},
/* #define USEM_FUNC1_END          427 */
/* #define USEM_FUNC2_START        428 */
	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a38, 0x0},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4030, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd030, 0x6},
/* #define USEM_FUNC2_END          429 */
/* #define USEM_FUNC3_START        430 */
	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a3c, 0x0},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4040, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd048, 0x6},
/* #define USEM_FUNC3_END          431 */
/* #define USEM_FUNC4_START        432 */
	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a40, 0x0},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4050, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd060, 0x6},
/* #define USEM_FUNC4_END          433 */
/* #define USEM_FUNC5_START        434 */
	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a44, 0x0},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4060, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd078, 0x6},
/* #define USEM_FUNC5_END          435 */
/* #define USEM_FUNC6_START        436 */
	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a48, 0x0},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4070, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd090, 0x6},
/* #define USEM_FUNC6_END          437 */
/* #define USEM_FUNC7_START        438 */
	{OP_WR, USEM_REG_FAST_MEMORY + 0x2a4c, 0x0},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0x4080, 0x2},
	{OP_ZR, USEM_REG_FAST_MEMORY + 0xd0a8, 0x6},
/* #define USEM_FUNC7_END          439 */
/* #define CSEM_COMMON_START       440 */
	{OP_ZP, CSEM_REG_INT_TABLE, 0x930000},
	{OP_WR_64, CSEM_REG_INT_TABLE + 0x380, 0x1002e6},
	{OP_ZP, CSEM_REG_PRAM, 0x2ade0000},
	{OP_ZP, CSEM_REG_PRAM + 0x8000, 0x2e050ab8},
	{OP_WR_64, CSEM_REG_PRAM + 0xe4a0, 0x61d202e8},
	{OP_RD, CSEM_REG_MSG_NUM_FIC0, 0x0},
	{OP_RD, CSEM_REG_MSG_NUM_FIC1, 0x0},
	{OP_RD, CSEM_REG_MSG_NUM_FOC0, 0x0},
	{OP_RD, CSEM_REG_MSG_NUM_FOC1, 0x0},
	{OP_RD, CSEM_REG_MSG_NUM_FOC2, 0x0},
	{OP_RD, CSEM_REG_MSG_NUM_FOC3, 0x0},
	{OP_WR, CSEM_REG_ARB_ELEMENT0, 0x1},
	{OP_WR, CSEM_REG_ARB_ELEMENT1, 0x2},
	{OP_WR, CSEM_REG_ARB_ELEMENT2, 0x3},
	{OP_WR, CSEM_REG_ARB_ELEMENT3, 0x0},
	{OP_WR, CSEM_REG_ARB_ELEMENT4, 0x4},
	{OP_WR, CSEM_REG_ARB_CYCLE_SIZE, 0x1},
	{OP_WR, CSEM_REG_TS_0_AS, 0x0},
	{OP_WR, CSEM_REG_TS_1_AS, 0x1},
	{OP_WR, CSEM_REG_TS_2_AS, 0x4},
	{OP_WR, CSEM_REG_TS_3_AS, 0x0},
	{OP_WR, CSEM_REG_TS_4_AS, 0x1},
	{OP_WR, CSEM_REG_TS_5_AS, 0x3},
	{OP_WR, CSEM_REG_TS_6_AS, 0x0},
	{OP_WR, CSEM_REG_TS_7_AS, 0x1},
	{OP_WR, CSEM_REG_TS_8_AS, 0x4},
	{OP_WR, CSEM_REG_TS_9_AS, 0x0},
	{OP_WR, CSEM_REG_TS_10_AS, 0x1},
	{OP_WR, CSEM_REG_TS_11_AS, 0x3},
	{OP_WR, CSEM_REG_TS_12_AS, 0x0},
	{OP_WR, CSEM_REG_TS_13_AS, 0x1},
	{OP_WR, CSEM_REG_TS_14_AS, 0x4},
	{OP_WR, CSEM_REG_TS_15_AS, 0x0},
	{OP_WR, CSEM_REG_TS_16_AS, 0x4},
	{OP_WR, CSEM_REG_TS_17_AS, 0x3},
	{OP_ZR, CSEM_REG_TS_18_AS, 0x2},
	{OP_WR, CSEM_REG_ENABLE_IN, 0x3fff},
	{OP_WR, CSEM_REG_ENABLE_OUT, 0x3ff},
	{OP_WR, CSEM_REG_FIC0_DISABLE, 0x0},
	{OP_WR, CSEM_REG_FIC1_DISABLE, 0x0},
	{OP_WR, CSEM_REG_PAS_DISABLE, 0x0},
	{OP_WR, CSEM_REG_THREADS_LIST, 0xffff},
	{OP_ZR, CSEM_REG_PASSIVE_BUFFER, 0x800},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x18000, 0x10},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x18040, 0x12},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x18080, 0x30},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x180c0, 0xe},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x11480, 0x1},
	{OP_WR_EMUL, CSEM_REG_FAST_MEMORY + 0x11480, 0x0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x1000, 0x42},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x7020, 0xc8},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x7000, 0x2},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x11e8, 0x0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3000, 0xc0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x4070, 0x80},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x5280, 0x4},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6700, 0x100},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x9000, 0x400},
	{OP_SW, CSEM_REG_FAST_MEMORY + 0x6b08, 0x2002ea},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x13fffff},
	{OP_SW, CSEM_REG_FAST_MEMORY + 0x10c00, 0x10030a},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x10800, 0x0},
	{OP_SW, CSEM_REG_FAST_MEMORY + 0x10c40, 0x10031a},
/* #define CSEM_COMMON_END         441 */
/* #define CSEM_PORT0_START        442 */
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8100, 0xa0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8600, 0x40},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8c00, 0x3c},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0xb000, 0x200},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8800, 0x80},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8de0, 0x3c},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x4040, 0x6},
/* #define CSEM_PORT0_END          443 */
/* #define CSEM_PORT1_START        444 */
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8380, 0xa0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8700, 0x40},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8cf0, 0x3c},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0xb800, 0x200},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8a00, 0x80},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8ed0, 0x3c},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x4058, 0x6},
/* #define CSEM_PORT1_END          445 */
/* #define CSEM_FUNC0_START        446 */
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8000, 0x8},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x1148, 0x0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3300, 0x2},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6040, 0x30},
/* #define CSEM_FUNC0_END          447 */
/* #define CSEM_FUNC1_START        448 */
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8020, 0x8},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x114c, 0x0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3308, 0x2},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6100, 0x30},
/* #define CSEM_FUNC1_END          449 */
/* #define CSEM_FUNC2_START        450 */
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8040, 0x8},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x1150, 0x0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3310, 0x2},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x61c0, 0x30},
/* #define CSEM_FUNC2_END          451 */
/* #define CSEM_FUNC3_START        452 */
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8060, 0x8},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x1154, 0x0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3318, 0x2},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6280, 0x30},
/* #define CSEM_FUNC3_END          453 */
/* #define CSEM_FUNC4_START        454 */
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x8080, 0x8},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x1158, 0x0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3320, 0x2},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6340, 0x30},
/* #define CSEM_FUNC4_END          455 */
/* #define CSEM_FUNC5_START        456 */
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x80a0, 0x8},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x115c, 0x0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3328, 0x2},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6400, 0x30},
/* #define CSEM_FUNC5_END          457 */
/* #define CSEM_FUNC6_START        458 */
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x80c0, 0x8},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x1160, 0x0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3330, 0x2},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x64c0, 0x30},
/* #define CSEM_FUNC6_END          459 */
/* #define CSEM_FUNC7_START        460 */
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x80e0, 0x8},
	{OP_WR, CSEM_REG_FAST_MEMORY + 0x1164, 0x0},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x3338, 0x2},
	{OP_ZR, CSEM_REG_FAST_MEMORY + 0x6580, 0x30},
/* #define CSEM_FUNC7_END          461 */
/* #define XPB_COMMON_START        462 */
	{OP_WR, GRCBASE_XPB + PB_REG_CONTROL, 0x28},
/* #define XPB_COMMON_END          463 */
/* #define DQ_COMMON_START         484 */
	{OP_WR, DORQ_REG_MODE_ACT, 0x2},
	{OP_WR, DORQ_REG_NORM_CID_OFST, 0x3},
	{OP_WR, DORQ_REG_OUTST_REQ, 0x4},
	{OP_WR, DORQ_REG_DPM_CID_ADDR, 0x8},
	{OP_WR, DORQ_REG_RSP_INIT_CRD, 0x2},
	{OP_WR, DORQ_REG_NORM_CMHEAD_TX, 0x90},
	{OP_WR, DORQ_REG_CMHEAD_RX, 0x90},
	{OP_WR, DORQ_REG_SHRT_CMHEAD, 0x800090},
	{OP_WR, DORQ_REG_ERR_CMHEAD, 0x8140000},
	{OP_WR, DORQ_REG_AGG_CMD0, 0x8a},
	{OP_WR, DORQ_REG_AGG_CMD1, 0x80},
	{OP_WR, DORQ_REG_AGG_CMD2, 0x81},
	{OP_WR, DORQ_REG_AGG_CMD3, 0x80},
	{OP_WR, DORQ_REG_SHRT_ACT_CNT, 0x6},
	{OP_WR, DORQ_REG_DQ_FIFO_FULL_TH, 0x7d0},
	{OP_WR, DORQ_REG_DQ_FIFO_AFULL_TH, 0x76c},
	{OP_WR, DORQ_REG_REGN, 0x7c1004},
	{OP_WR, DORQ_REG_IF_EN, 0xf},
/* #define DQ_COMMON_END           485 */
/* #define TIMERS_COMMON_START     506 */
	{OP_ZR, TM_REG_CLIN_PRIOR0_CLIENT, 0x2},
	{OP_WR, TM_REG_LIN_SETCLR_FIFO_ALFULL_THR, 0x1c},
	{OP_WR, TM_REG_CFC_AC_CRDCNT_VAL, 0x1},
	{OP_WR, TM_REG_CFC_CLD_CRDCNT_VAL, 0x1},
	{OP_WR, TM_REG_CLOUT_CRDCNT0_VAL, 0x1},
	{OP_WR, TM_REG_CLOUT_CRDCNT1_VAL, 0x1},
	{OP_WR, TM_REG_CLOUT_CRDCNT2_VAL, 0x1},
	{OP_WR, TM_REG_EXP_CRDCNT_VAL, 0x1},
	{OP_WR, TM_REG_PCIARB_CRDCNT_VAL, 0x2},
	{OP_WR_ASIC, TM_REG_TIMER_TICK_SIZE, 0x3d090},
	{OP_WR_EMUL, TM_REG_TIMER_TICK_SIZE, 0x9c},
	{OP_WR_FPGA, TM_REG_TIMER_TICK_SIZE, 0x9c4},
	{OP_WR, TM_REG_CL0_CONT_REGION, 0x8},
	{OP_WR, TM_REG_CL1_CONT_REGION, 0xc},
	{OP_WR, TM_REG_CL2_CONT_REGION, 0x10},
	{OP_WR, TM_REG_TM_CONTEXT_REGION, 0x20},
	{OP_WR, TM_REG_EN_TIMERS, 0x1},
	{OP_WR, TM_REG_EN_REAL_TIME_CNT, 0x1},
	{OP_WR, TM_REG_EN_CL0_INPUT, 0x1},
	{OP_WR, TM_REG_EN_CL1_INPUT, 0x1},
	{OP_WR, TM_REG_EN_CL2_INPUT, 0x1},
/* #define TIMERS_COMMON_END       507 */
/* #define TIMERS_PORT0_START      508 */
	{OP_WR, TM_REG_LIN0_LOGIC_ADDR, 0x0},
	{OP_WR, TM_REG_LIN0_PHY_ADDR_VALID, 0x0},
	{OP_ZR, TM_REG_LIN0_PHY_ADDR, 0x2},
/* #define TIMERS_PORT0_END        509 */
/* #define TIMERS_PORT1_START      510 */
	{OP_WR, TM_REG_LIN1_LOGIC_ADDR, 0x0},
	{OP_WR, TM_REG_LIN1_PHY_ADDR_VALID, 0x0},
	{OP_ZR, TM_REG_LIN1_PHY_ADDR, 0x2},
/* #define TIMERS_PORT1_END        511 */
/* #define XSDM_COMMON_START       528 */
	{OP_WR, XSDM_REG_CFC_RSP_START_ADDR, 0x424},
	{OP_WR, XSDM_REG_CMP_COUNTER_START_ADDR, 0x410},
	{OP_WR, XSDM_REG_Q_COUNTER_START_ADDR, 0x414},
	{OP_WR, XSDM_REG_CMP_COUNTER_MAX0, 0xffff},
	{OP_WR, XSDM_REG_CMP_COUNTER_MAX1, 0xffff},
	{OP_WR, XSDM_REG_CMP_COUNTER_MAX2, 0xffff},
	{OP_WR, XSDM_REG_CMP_COUNTER_MAX3, 0xffff},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_0, 0x20},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_1, 0x20},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_2, 0x34},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_3, 0x35},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_4, 0x23},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_5, 0x24},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_6, 0x25},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_7, 0x26},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_8, 0x27},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_9, 0x29},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_10, 0x2a},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_11, 0x2b},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_12, 0x2c},
	{OP_WR, XSDM_REG_AGG_INT_EVENT_13, 0x2d},
	{OP_ZR, XSDM_REG_AGG_INT_EVENT_14, 0x52},
	{OP_WR, XSDM_REG_AGG_INT_MODE_0, 0x1},
	{OP_ZR, XSDM_REG_AGG_INT_MODE_1, 0x1f},
	{OP_WR, XSDM_REG_ENABLE_IN1, 0x7ffffff},
	{OP_WR, XSDM_REG_ENABLE_IN2, 0x3f},
	{OP_WR, XSDM_REG_ENABLE_OUT1, 0x7ffffff},
	{OP_WR, XSDM_REG_ENABLE_OUT2, 0xf},
	{OP_RD, XSDM_REG_NUM_OF_Q0_CMD, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_Q1_CMD, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_Q3_CMD, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_Q4_CMD, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_Q5_CMD, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_Q6_CMD, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_Q7_CMD, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_Q8_CMD, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_Q9_CMD, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_Q10_CMD, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_Q11_CMD, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_PKT_END_MSG, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_PXP_ASYNC_REQ, 0x0},
	{OP_RD, XSDM_REG_NUM_OF_ACK_AFTER_PLACE, 0x0},
	{OP_WR_ASIC, XSDM_REG_TIMER_TICK, 0x3e8},
	{OP_WR_EMUL, XSDM_REG_TIMER_TICK, 0x1},
	{OP_WR_FPGA, XSDM_REG_TIMER_TICK, 0xa},
/* #define XSDM_COMMON_END         529 */
/* #define QM_COMMON_START         550 */
	{OP_WR, QM_REG_ACTCTRINITVAL_0, 0x6},
	{OP_WR, QM_REG_ACTCTRINITVAL_1, 0x5},
	{OP_WR, QM_REG_ACTCTRINITVAL_2, 0xa},
	{OP_WR, QM_REG_ACTCTRINITVAL_3, 0x5},
	{OP_WR, QM_REG_PCIREQAT, 0x2},
	{OP_WR, QM_REG_CMINITCRD_0, 0x4},
	{OP_WR, QM_REG_CMINITCRD_1, 0x4},
	{OP_WR, QM_REG_CMINITCRD_2, 0x4},
	{OP_WR, QM_REG_CMINITCRD_3, 0x4},
	{OP_WR, QM_REG_CMINITCRD_4, 0x4},
	{OP_WR, QM_REG_CMINITCRD_5, 0x4},
	{OP_WR, QM_REG_CMINITCRD_6, 0x4},
	{OP_WR, QM_REG_CMINITCRD_7, 0x4},
	{OP_WR, QM_REG_OUTLDREQ, 0x4},
	{OP_WR, QM_REG_CTXREG_0, 0x7c},
	{OP_WR, QM_REG_CTXREG_1, 0x3d},
	{OP_WR, QM_REG_CTXREG_2, 0x3f},
	{OP_WR, QM_REG_CTXREG_3, 0x9c},
	{OP_WR, QM_REG_ENSEC, 0x7},
	{OP_ZR, QM_REG_QVOQIDX_0, 0x5},
	{OP_WR, QM_REG_WRRWEIGHTS_0, 0x1010101},
	{OP_WR, QM_REG_QVOQIDX_5, 0x0},
	{OP_WR, QM_REG_QVOQIDX_6, 0x4},
	{OP_WR, QM_REG_QVOQIDX_7, 0x4},
	{OP_WR, QM_REG_QVOQIDX_8, 0x2},
	{OP_WR, QM_REG_WRRWEIGHTS_1, 0x8012004},
	{OP_WR, QM_REG_QVOQIDX_9, 0x5},
	{OP_WR, QM_REG_QVOQIDX_10, 0x5},
	{OP_WR, QM_REG_QVOQIDX_11, 0x5},
	{OP_WR, QM_REG_QVOQIDX_12, 0x5},
	{OP_WR, QM_REG_WRRWEIGHTS_2, 0x20081001},
	{OP_WR, QM_REG_QVOQIDX_13, 0x8},
	{OP_WR, QM_REG_QVOQIDX_14, 0x6},
	{OP_WR, QM_REG_QVOQIDX_15, 0x7},
	{OP_WR, QM_REG_QVOQIDX_16, 0x0},
	{OP_WR, QM_REG_WRRWEIGHTS_3, 0x1010120},
	{OP_ZR, QM_REG_QVOQIDX_17, 0x4},
	{OP_WR, QM_REG_WRRWEIGHTS_4, 0x1010101},
	{OP_WR, QM_REG_QVOQIDX_21, 0x0},
	{OP_WR, QM_REG_QVOQIDX_22, 0x4},
	{OP_WR, QM_REG_QVOQIDX_23, 0x4},
	{OP_WR, QM_REG_QVOQIDX_24, 0x2},
	{OP_WR, QM_REG_WRRWEIGHTS_5, 0x8012004},
	{OP_WR, QM_REG_QVOQIDX_25, 0x5},
	{OP_WR, QM_REG_QVOQIDX_26, 0x5},
	{OP_WR, QM_REG_QVOQIDX_27, 0x5},
	{OP_WR, QM_REG_QVOQIDX_28, 0x5},
	{OP_WR, QM_REG_WRRWEIGHTS_6, 0x20081001},
	{OP_WR, QM_REG_QVOQIDX_29, 0x8},
	{OP_WR, QM_REG_QVOQIDX_30, 0x6},
	{OP_WR, QM_REG_QVOQIDX_31, 0x7},
	{OP_WR, QM_REG_QVOQIDX_32, 0x1},
	{OP_WR, QM_REG_WRRWEIGHTS_7, 0x1010120},
	{OP_WR, QM_REG_QVOQIDX_33, 0x1},
	{OP_WR, QM_REG_QVOQIDX_34, 0x1},
	{OP_WR, QM_REG_QVOQIDX_35, 0x1},
	{OP_WR, QM_REG_QVOQIDX_36, 0x1},
	{OP_WR, QM_REG_WRRWEIGHTS_8, 0x1010101},
	{OP_WR, QM_REG_QVOQIDX_37, 0x1},
	{OP_WR, QM_REG_QVOQIDX_38, 0x4},
	{OP_WR, QM_REG_QVOQIDX_39, 0x4},
	{OP_WR, QM_REG_QVOQIDX_40, 0x2},
	{OP_WR, QM_REG_WRRWEIGHTS_9, 0x8012004},
	{OP_WR, QM_REG_QVOQIDX_41, 0x5},
	{OP_WR, QM_REG_QVOQIDX_42, 0x5},
	{OP_WR, QM_REG_QVOQIDX_43, 0x5},
	{OP_WR, QM_REG_QVOQIDX_44, 0x5},
	{OP_WR, QM_REG_WRRWEIGHTS_10, 0x20081001},
	{OP_WR, QM_REG_QVOQIDX_45, 0x8},
	{OP_WR, QM_REG_QVOQIDX_46, 0x6},
	{OP_WR, QM_REG_QVOQIDX_47, 0x7},
	{OP_WR, QM_REG_QVOQIDX_48, 0x1},
	{OP_WR, QM_REG_WRRWEIGHTS_11, 0x1010120},
	{OP_WR, QM_REG_QVOQIDX_49, 0x1},
	{OP_WR, QM_REG_QVOQIDX_50, 0x1},
	{OP_WR, QM_REG_QVOQIDX_51, 0x1},
	{OP_WR, QM_REG_QVOQIDX_52, 0x1},
	{OP_WR, QM_REG_WRRWEIGHTS_12, 0x1010101},
	{OP_WR, QM_REG_QVOQIDX_53, 0x1},
	{OP_WR, QM_REG_QVOQIDX_54, 0x4},
	{OP_WR, QM_REG_QVOQIDX_55, 0x4},
	{OP_WR, QM_REG_QVOQIDX_56, 0x2},
	{OP_WR, QM_REG_WRRWEIGHTS_13, 0x8012004},
	{OP_WR, QM_REG_QVOQIDX_57, 0x5},
	{OP_WR, QM_REG_QVOQIDX_58, 0x5},
	{OP_WR, QM_REG_QVOQIDX_59, 0x5},
	{OP_WR, QM_REG_QVOQIDX_60, 0x5},
	{OP_WR, QM_REG_WRRWEIGHTS_14, 0x20081001},
	{OP_WR, QM_REG_QVOQIDX_61, 0x8},
	{OP_WR, QM_REG_QVOQIDX_62, 0x6},
	{OP_WR, QM_REG_QVOQIDX_63, 0x7},
	{OP_WR, QM_REG_QVOQIDX_64, 0x0},
	{OP_WR, QM_REG_WRRWEIGHTS_15, 0x1010120},
	{OP_ZR, QM_REG_QVOQIDX_65, 0x4},
	{OP_WR, QM_REG_WRRWEIGHTS_16, 0x1010101},
	{OP_WR, QM_REG_QVOQIDX_69, 0x0},
	{OP_WR, QM_REG_QVOQIDX_70, 0x4},
	{OP_WR, QM_REG_QVOQIDX_71, 0x4},
	{OP_WR, QM_REG_QVOQIDX_72, 0x2},
	{OP_WR, QM_REG_WRRWEIGHTS_17, 0x8012004},
	{OP_WR, QM_REG_QVOQIDX_73, 0x5},
	{OP_WR, QM_REG_QVOQIDX_74, 0x5},
	{OP_WR, QM_REG_QVOQIDX_75, 0x5},
	{OP_WR, QM_REG_QVOQIDX_76, 0x5},
	{OP_WR, QM_REG_WRRWEIGHTS_18, 0x20081001},
	{OP_WR, QM_REG_QVOQIDX_77, 0x8},
	{OP_WR, QM_REG_QVOQIDX_78, 0x6},
	{OP_WR, QM_REG_QVOQIDX_79, 0x7},
	{OP_WR, QM_REG_QVOQIDX_80, 0x0},
	{OP_WR, QM_REG_WRRWEIGHTS_19, 0x1010120},
	{OP_ZR, QM_REG_QVOQIDX_81, 0x4},
	{OP_WR, QM_REG_WRRWEIGHTS_20, 0x1010101},
	{OP_WR, QM_REG_QVOQIDX_85, 0x0},
	{OP_WR, QM_REG_QVOQIDX_86, 0x4},
	{OP_WR, QM_REG_QVOQIDX_87, 0x4},
	{OP_WR, QM_REG_QVOQIDX_88, 0x2},
	{OP_WR, QM_REG_WRRWEIGHTS_21, 0x8012004},
	{OP_WR, QM_REG_QVOQIDX_89, 0x5},
	{OP_WR, QM_REG_QVOQIDX_90, 0x5},
	{OP_WR, QM_REG_QVOQIDX_91, 0x5},
	{OP_WR, QM_REG_QVOQIDX_92, 0x5},
	{OP_WR, QM_REG_WRRWEIGHTS_22, 0x20081001},
	{OP_WR, QM_REG_QVOQIDX_93, 0x8},
	{OP_WR, QM_REG_QVOQIDX_94, 0x6},
	{OP_WR, QM_REG_QVOQIDX_95, 0x7},
	{OP_WR, QM_REG_QVOQIDX_96, 0x1},
	{OP_WR, QM_REG_WRRWEIGHTS_23, 0x1010120},
	{OP_WR, QM_REG_QVOQIDX_97, 0x1},
	{OP_WR, QM_REG_QVOQIDX_98, 0x1},
	{OP_WR, QM_REG_QVOQIDX_99, 0x1},
	{OP_WR, QM_REG_QVOQIDX_100, 0x1},
	{OP_WR, QM_REG_WRRWEIGHTS_24, 0x1010101},
	{OP_WR, QM_REG_QVOQIDX_101, 0x1},
	{OP_WR, QM_REG_QVOQIDX_102, 0x4},
	{OP_WR, QM_REG_QVOQIDX_103, 0x4},
	{OP_WR, QM_REG_QVOQIDX_104, 0x2},
	{OP_WR, QM_REG_WRRWEIGHTS_25, 0x8012004},
	{OP_WR, QM_REG_QVOQIDX_105, 0x5},
	{OP_WR, QM_REG_QVOQIDX_106, 0x5},
	{OP_WR, QM_REG_QVOQIDX_107, 0x5},
	{OP_WR, QM_REG_QVOQIDX_108, 0x5},
	{OP_WR, QM_REG_WRRWEIGHTS_26, 0x20081001},
	{OP_WR, QM_REG_QVOQIDX_109, 0x8},
	{OP_WR, QM_REG_QVOQIDX_110, 0x6},
	{OP_WR, QM_REG_QVOQIDX_111, 0x7},
	{OP_WR, QM_REG_QVOQIDX_112, 0x1},
	{OP_WR, QM_REG_WRRWEIGHTS_27, 0x1010120},
	{OP_WR, QM_REG_QVOQIDX_113, 0x1},
	{OP_WR, QM_REG_QVOQIDX_114, 0x1},
	{OP_WR, QM_REG_QVOQIDX_115, 0x1},
	{OP_WR, QM_REG_QVOQIDX_116, 0x1},
	{OP_WR, QM_REG_WRRWEIGHTS_28, 0x1010101},
	{OP_WR, QM_REG_QVOQIDX_117, 0x1},
	{OP_WR, QM_REG_QVOQIDX_118, 0x4},
	{OP_WR, QM_REG_QVOQIDX_119, 0x4},
	{OP_WR, QM_REG_QVOQIDX_120, 0x2},
	{OP_WR, QM_REG_WRRWEIGHTS_29, 0x8012004},
	{OP_WR, QM_REG_QVOQIDX_121, 0x5},
	{OP_WR, QM_REG_QVOQIDX_122, 0x5},
	{OP_WR, QM_REG_QVOQIDX_123, 0x5},
	{OP_WR, QM_REG_QVOQIDX_124, 0x5},
	{OP_WR, QM_REG_WRRWEIGHTS_30, 0x20081001},
	{OP_WR, QM_REG_QVOQIDX_125, 0x8},
	{OP_WR, QM_REG_QVOQIDX_126, 0x6},
	{OP_WR, QM_REG_QVOQIDX_127, 0x7},
	{OP_WR, QM_REG_WRRWEIGHTS_31, 0x1010120},
	{OP_WR, QM_REG_VOQQMASK_0_LSB, 0x3f003f},
	{OP_WR, QM_REG_VOQQMASK_0_MSB, 0x0},
	{OP_WR, QM_REG_VOQQMASK_0_LSB_EXT_A, 0x3f003f},
	{OP_WR, QM_REG_VOQQMASK_0_MSB_EXT_A, 0x0},
	{OP_WR, QM_REG_VOQQMASK_1_LSB, 0x0},
	{OP_WR, QM_REG_VOQQMASK_1_MSB, 0x3f003f},
	{OP_WR, QM_REG_VOQQMASK_1_LSB_EXT_A, 0x0},
	{OP_WR, QM_REG_VOQQMASK_1_MSB_EXT_A, 0x3f003f},
	{OP_WR, QM_REG_VOQQMASK_2_LSB, 0x1000100},
	{OP_WR, QM_REG_VOQQMASK_2_MSB, 0x1000100},
	{OP_WR, QM_REG_VOQQMASK_2_LSB_EXT_A, 0x1000100},
	{OP_WR, QM_REG_VOQQMASK_2_MSB_EXT_A, 0x1000100},
	{OP_ZR, QM_REG_VOQQMASK_3_LSB, 0x2},
	{OP_WR, QM_REG_VOQQMASK_3_LSB_EXT_A, 0x0},
	{OP_WR, QM_REG_VOQQMASK_3_MSB_EXT_A, 0x0},
	{OP_WR, QM_REG_VOQQMASK_4_LSB, 0xc000c0},
	{OP_WR, QM_REG_VOQQMASK_4_MSB, 0xc000c0},
	{OP_WR, QM_REG_VOQQMASK_4_LSB_EXT_A, 0xc000c0},
	{OP_WR, QM_REG_VOQQMASK_4_MSB_EXT_A, 0xc000c0},
	{OP_WR, QM_REG_VOQQMASK_5_LSB, 0x1e001e00},
	{OP_WR, QM_REG_VOQQMASK_5_MSB, 0x1e001e00},
	{OP_WR, QM_REG_VOQQMASK_5_LSB_EXT_A, 0x1e001e00},
	{OP_WR, QM_REG_VOQQMASK_5_MSB_EXT_A, 0x1e001e00},
	{OP_WR, QM_REG_VOQQMASK_6_LSB, 0x40004000},
	{OP_WR, QM_REG_VOQQMASK_6_MSB, 0x40004000},
	{OP_WR, QM_REG_VOQQMASK_6_LSB_EXT_A, 0x40004000},
	{OP_WR, QM_REG_VOQQMASK_6_MSB_EXT_A, 0x40004000},
	{OP_WR, QM_REG_VOQQMASK_7_LSB, 0x80008000},
	{OP_WR, QM_REG_VOQQMASK_7_MSB, 0x80008000},
	{OP_WR, QM_REG_VOQQMASK_7_LSB_EXT_A, 0x80008000},
	{OP_WR, QM_REG_VOQQMASK_7_MSB_EXT_A, 0x80008000},
	{OP_WR, QM_REG_VOQQMASK_8_LSB, 0x20002000},
	{OP_WR, QM_REG_VOQQMASK_8_MSB, 0x20002000},
	{OP_WR, QM_REG_VOQQMASK_8_LSB_EXT_A, 0x20002000},
	{OP_WR, QM_REG_VOQQMASK_8_MSB_EXT_A, 0x20002000},
	{OP_ZR, QM_REG_VOQQMASK_9_LSB, 0x2},
	{OP_WR, QM_REG_VOQQMASK_9_LSB_EXT_A, 0x0},
	{OP_WR, QM_REG_VOQQMASK_9_MSB_EXT_A, 0x0},
	{OP_WR, QM_REG_VOQQMASK_10_LSB, 0x0},
	{OP_WR, QM_REG_VOQQMASK_10_MSB, 0x0},
	{OP_WR, QM_REG_VOQQMASK_10_LSB_EXT_A, 0x0},
	{OP_WR, QM_REG_VOQQMASK_10_MSB_EXT_A, 0x0},
	{OP_WR, QM_REG_VOQQMASK_11_LSB, 0x0},
	{OP_WR, QM_REG_VOQQMASK_11_MSB, 0x0},
	{OP_WR, QM_REG_VOQQMASK_11_LSB_EXT_A, 0x0},
	{OP_WR, QM_REG_VOQQMASK_11_MSB_EXT_A, 0x0},
	{OP_WR, QM_REG_VOQPORT_0, 0x0},
	{OP_WR, QM_REG_VOQPORT_1, 0x1},
	{OP_ZR, QM_REG_VOQPORT_2, 0xa},
	{OP_WR, QM_REG_CMINTVOQMASK_0, 0xc08},
	{OP_WR, QM_REG_CMINTVOQMASK_1, 0x40},
	{OP_WR, QM_REG_CMINTVOQMASK_2, 0x100},
	{OP_WR, QM_REG_CMINTVOQMASK_3, 0x20},
	{OP_WR, QM_REG_CMINTVOQMASK_4, 0x17},
	{OP_WR, QM_REG_CMINTVOQMASK_5, 0x80},
	{OP_WR, QM_REG_CMINTVOQMASK_6, 0x200},
	{OP_WR, QM_REG_CMINTVOQMASK_7, 0x0},
	{OP_WR, QM_REG_HWAEMPTYMASK_LSB, 0x1ff01ff},
	{OP_WR, QM_REG_HWAEMPTYMASK_MSB, 0x1ff01ff},
	{OP_WR, QM_REG_HWAEMPTYMASK_LSB_EXT_A, 0x1ff01ff},
	{OP_WR, QM_REG_HWAEMPTYMASK_MSB_EXT_A, 0x1ff01ff},
	{OP_WR, QM_REG_ENBYPVOQMASK, 0x13},
	{OP_WR, QM_REG_VOQCREDITAFULLTHR, 0x13f},
	{OP_WR, QM_REG_VOQINITCREDIT_0, 0x140},
	{OP_WR, QM_REG_VOQINITCREDIT_1, 0x140},
	{OP_ZR, QM_REG_VOQINITCREDIT_2, 0x2},
	{OP_WR, QM_REG_VOQINITCREDIT_4, 0xc0},
	{OP_ZR, QM_REG_VOQINITCREDIT_5, 0x7},
	{OP_WR, QM_REG_TASKCRDCOST_0, 0x48},
	{OP_WR, QM_REG_TASKCRDCOST_1, 0x48},
	{OP_ZR, QM_REG_TASKCRDCOST_2, 0x2},
	{OP_WR, QM_REG_TASKCRDCOST_4, 0x48},
	{OP_ZR, QM_REG_TASKCRDCOST_5, 0x7},
	{OP_WR, QM_REG_BYTECRDINITVAL, 0x8000},
	{OP_WR, QM_REG_BYTECRDCOST, 0x25e4},
	{OP_WR, QM_REG_BYTECREDITAFULLTHR, 0x7fff},
	{OP_WR, QM_REG_ENBYTECRD_LSB, 0xf000f},
	{OP_WR, QM_REG_ENBYTECRD_MSB, 0xf000f},
	{OP_WR, QM_REG_ENBYTECRD_LSB_EXT_A, 0xf000f},
	{OP_WR, QM_REG_ENBYTECRD_MSB_EXT_A, 0xf000f},
	{OP_WR, QM_REG_BYTECRDPORT_LSB, 0x0},
	{OP_WR, QM_REG_BYTECRDPORT_MSB, 0xffffffff},
	{OP_WR, QM_REG_BYTECRDPORT_LSB_EXT_A, 0x0},
	{OP_WR, QM_REG_BYTECRDPORT_MSB_EXT_A, 0xffffffff},
	{OP_WR, QM_REG_PQ2PCIFUNC_0, 0x0},
	{OP_WR, QM_REG_PQ2PCIFUNC_1, 0x2},
	{OP_WR, QM_REG_PQ2PCIFUNC_2, 0x1},
	{OP_WR, QM_REG_PQ2PCIFUNC_3, 0x3},
	{OP_WR, QM_REG_PQ2PCIFUNC_4, 0x4},
	{OP_WR, QM_REG_PQ2PCIFUNC_5, 0x6},
	{OP_WR, QM_REG_PQ2PCIFUNC_6, 0x5},
	{OP_WR, QM_REG_PQ2PCIFUNC_7, 0x7},
	{OP_WR, QM_REG_CMINTEN, 0xff},
/* #define QM_COMMON_END           551 */
/* #define PBF_COMMON_START        572 */
	{OP_WR, PBF_REG_INIT, 0x1},
	{OP_WR, PBF_REG_INIT_P4, 0x1},
	{OP_WR, PBF_REG_MAC_LB_ENABLE, 0x1},
	{OP_WR, PBF_REG_IF_ENABLE_REG, 0x7fff},
	{OP_WR, PBF_REG_INIT_P4, 0x0},
	{OP_WR, PBF_REG_INIT, 0x0},
	{OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P4, 0x0},
/* #define PBF_COMMON_END          573 */
/* #define PBF_PORT0_START         574 */
	{OP_WR, PBF_REG_INIT_P0, 0x1},
	{OP_WR, PBF_REG_MAC_IF0_ENABLE, 0x1},
	{OP_WR, PBF_REG_INIT_P0, 0x0},
	{OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P0, 0x0},
/* #define PBF_PORT0_END           575 */
/* #define PBF_PORT1_START         576 */
	{OP_WR, PBF_REG_INIT_P1, 0x1},
	{OP_WR, PBF_REG_MAC_IF1_ENABLE, 0x1},
	{OP_WR, PBF_REG_INIT_P1, 0x0},
	{OP_WR, PBF_REG_DISABLE_NEW_TASK_PROC_P1, 0x0},
/* #define PBF_PORT1_END           577 */
/* #define XCM_COMMON_START        594 */
	{OP_WR, XCM_REG_XX_OVFL_EVNT_ID, 0x32},
	{OP_WR, XCM_REG_XQM_XCM_HDR_P, 0x3150020},
	{OP_WR, XCM_REG_XQM_XCM_HDR_S, 0x3150020},
	{OP_WR, XCM_REG_TM_XCM_HDR, 0x1000030},
	{OP_WR, XCM_REG_ERR_XCM_HDR, 0x8100000},
	{OP_WR, XCM_REG_ERR_EVNT_ID, 0x33},
	{OP_WR, XCM_REG_EXPR_EVNT_ID, 0x30},
	{OP_WR, XCM_REG_STOP_EVNT_ID, 0x31},
	{OP_WR, XCM_REG_STORM_WEIGHT, 0x3},
	{OP_WR, XCM_REG_TSEM_WEIGHT, 0x6},
	{OP_WR, XCM_REG_CSEM_WEIGHT, 0x3},
	{OP_WR, XCM_REG_USEM_WEIGHT, 0x3},
	{OP_WR, XCM_REG_DORQ_WEIGHT, 0x2},
	{OP_WR, XCM_REG_PBF_WEIGHT, 0x0},
	{OP_WR, XCM_REG_NIG0_WEIGHT, 0x2},
	{OP_WR, XCM_REG_CP_WEIGHT, 0x0},
	{OP_WR, XCM_REG_XSDM_WEIGHT, 0x6},
	{OP_WR, XCM_REG_XQM_P_WEIGHT, 0x4},
	{OP_WR, XCM_REG_XQM_S_WEIGHT, 0x2},
	{OP_WR, XCM_REG_TM_WEIGHT, 0x2},
	{OP_WR, XCM_REG_XCM_XQM_USE_Q, 0x1},
	{OP_WR, XCM_REG_XQM_BYP_ACT_UPD, 0x6},
	{OP_WR, XCM_REG_UNA_GT_NXT_Q, 0x0},
	{OP_WR, XCM_REG_AUX1_Q, 0x2},
	{OP_WR, XCM_REG_AUX_CNT_FLG_Q_19, 0x1},
	{OP_WR, XCM_REG_GR_ARB_TYPE, 0x1},
	{OP_WR, XCM_REG_GR_LD0_PR, 0x1},
	{OP_WR, XCM_REG_GR_LD1_PR, 0x2},
	{OP_WR, XCM_REG_CFC_INIT_CRD, 0x1},
	{OP_WR, XCM_REG_FIC0_INIT_CRD, 0x40},
	{OP_WR, XCM_REG_FIC1_INIT_CRD, 0x40},
	{OP_WR, XCM_REG_TM_INIT_CRD, 0x4},
	{OP_WR, XCM_REG_XQM_INIT_CRD, 0x20},
	{OP_WR, XCM_REG_XX_INIT_CRD, 0x2},
	{OP_WR, XCM_REG_XX_MSG_NUM, 0x20},
	{OP_ZR, XCM_REG_XX_TABLE, 0x12},
	{OP_SW, XCM_REG_XX_DESCR_TABLE, 0x1f032a},
	{OP_WR, XCM_REG_N_SM_CTX_LD_0, 0xf},
	{OP_WR, XCM_REG_N_SM_CTX_LD_1, 0x7},
	{OP_WR, XCM_REG_N_SM_CTX_LD_2, 0xb},
	{OP_WR, XCM_REG_N_SM_CTX_LD_3, 0xe},
	{OP_WR, XCM_REG_N_SM_CTX_LD_4, 0xe},
	{OP_ZR, XCM_REG_N_SM_CTX_LD_5, 0x3},
	{OP_WR, XCM_REG_XCM_REG0_SZ, 0x4},
	{OP_WR, XCM_REG_XCM_STORM0_IFEN, 0x1},
	{OP_WR, XCM_REG_XCM_STORM1_IFEN, 0x1},
	{OP_WR, XCM_REG_XCM_XQM_IFEN, 0x1},
	{OP_WR, XCM_REG_STORM_XCM_IFEN, 0x1},
	{OP_WR, XCM_REG_XQM_XCM_IFEN, 0x1},
	{OP_WR, XCM_REG_XSDM_IFEN, 0x1},
	{OP_WR, XCM_REG_TM_XCM_IFEN, 0x1},
	{OP_WR, XCM_REG_XCM_TM_IFEN, 0x1},
	{OP_WR, XCM_REG_TSEM_IFEN, 0x1},
	{OP_WR, XCM_REG_CSEM_IFEN, 0x1},
	{OP_WR, XCM_REG_USEM_IFEN, 0x1},
	{OP_WR, XCM_REG_DORQ_IFEN, 0x1},
	{OP_WR, XCM_REG_PBF_IFEN, 0x1},
	{OP_WR, XCM_REG_NIG0_IFEN, 0x1},
	{OP_WR, XCM_REG_NIG1_IFEN, 0x1},
	{OP_WR, XCM_REG_CDU_AG_WR_IFEN, 0x1},
	{OP_WR, XCM_REG_CDU_AG_RD_IFEN, 0x1},
	{OP_WR, XCM_REG_CDU_SM_WR_IFEN, 0x1},
	{OP_WR, XCM_REG_CDU_SM_RD_IFEN, 0x1},
	{OP_WR, XCM_REG_XCM_CFC_IFEN, 0x1},
/* #define XCM_COMMON_END          595 */
/* #define XCM_FUNC0_START         600 */
	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
	{OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0},
/* #define XCM_FUNC0_END           601 */
/* #define XCM_FUNC1_START         602 */
	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
	{OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0},
/* #define XCM_FUNC1_END           603 */
/* #define XCM_FUNC2_START         604 */
	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
	{OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0},
/* #define XCM_FUNC2_END           605 */
/* #define XCM_FUNC3_START         606 */
	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
	{OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0},
/* #define XCM_FUNC3_END           607 */
/* #define XCM_FUNC4_START         608 */
	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
	{OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0},
/* #define XCM_FUNC4_END           609 */
/* #define XCM_FUNC5_START         610 */
	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
	{OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0},
/* #define XCM_FUNC5_END           611 */
/* #define XCM_FUNC6_START         612 */
	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_0, 0xc8},
	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_0, 0x2},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD00, 0x0},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD10, 0x0},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD00, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD10, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL00, 0xff},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL10, 0xff},
	{OP_WR, XCM_REG_PHYS_QNUM3_0, 0x0},
/* #define XCM_FUNC6_END           613 */
/* #define XCM_FUNC7_START         614 */
	{OP_WR, XCM_REG_GLB_DEL_ACK_TMR_VAL_1, 0xc8},
	{OP_WR, XCM_REG_GLB_DEL_ACK_MAX_CNT_1, 0x2},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD01, 0x0},
	{OP_WR, XCM_REG_WU_DA_SET_TMR_CNT_FLG_CMD11, 0x0},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD01, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_CMD11, 0x2},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL01, 0xff},
	{OP_WR, XCM_REG_WU_DA_CNT_UPD_VAL11, 0xff},
	{OP_WR, XCM_REG_PHYS_QNUM3_1, 0x0},
/* #define XCM_FUNC7_END           615 */
/* #define XSEM_COMMON_START       616 */
	{OP_ZP, XSEM_REG_INT_TABLE, 0xc00000},
	{OP_WR_64, XSEM_REG_INT_TABLE + 0x3a8, 0xb0349},
	{OP_ZP, XSEM_REG_PRAM, 0x32fc0000},
	{OP_ZP, XSEM_REG_PRAM + 0x8000, 0x35780cc0},
	{OP_ZP, XSEM_REG_PRAM + 0x10000, 0x3ac11a1f},
	{OP_ZP, XSEM_REG_PRAM + 0x18000, 0x39e228d0},
	{OP_ZP, XSEM_REG_PRAM + 0x20000, 0x1c3e3749},
	{OP_WR_64, XSEM_REG_PRAM + 0x23710, 0x391e034b},
	{OP_RD, XSEM_REG_MSG_NUM_FIC0, 0x0},
	{OP_RD, XSEM_REG_MSG_NUM_FIC1, 0x0},
	{OP_RD, XSEM_REG_MSG_NUM_FOC0, 0x0},
	{OP_RD, XSEM_REG_MSG_NUM_FOC1, 0x0},
	{OP_RD, XSEM_REG_MSG_NUM_FOC2, 0x0},
	{OP_RD, XSEM_REG_MSG_NUM_FOC3, 0x0},
	{OP_WR, XSEM_REG_ARB_ELEMENT0, 0x1},
	{OP_WR, XSEM_REG_ARB_ELEMENT1, 0x2},
	{OP_WR, XSEM_REG_ARB_ELEMENT2, 0x3},
	{OP_WR, XSEM_REG_ARB_ELEMENT3, 0x0},
	{OP_WR, XSEM_REG_ARB_ELEMENT4, 0x4},
	{OP_WR, XSEM_REG_ARB_CYCLE_SIZE, 0x1},
	{OP_WR, XSEM_REG_TS_0_AS, 0x0},
	{OP_WR, XSEM_REG_TS_1_AS, 0x1},
	{OP_WR, XSEM_REG_TS_2_AS, 0x4},
	{OP_WR, XSEM_REG_TS_3_AS, 0x0},
	{OP_WR, XSEM_REG_TS_4_AS, 0x1},
	{OP_WR, XSEM_REG_TS_5_AS, 0x3},
	{OP_WR, XSEM_REG_TS_6_AS, 0x0},
	{OP_WR, XSEM_REG_TS_7_AS, 0x1},
	{OP_WR, XSEM_REG_TS_8_AS, 0x4},
	{OP_WR, XSEM_REG_TS_9_AS, 0x0},
	{OP_WR, XSEM_REG_TS_10_AS, 0x1},
	{OP_WR, XSEM_REG_TS_11_AS, 0x3},
	{OP_WR, XSEM_REG_TS_12_AS, 0x0},
	{OP_WR, XSEM_REG_TS_13_AS, 0x1},
	{OP_WR, XSEM_REG_TS_14_AS, 0x4},
	{OP_WR, XSEM_REG_TS_15_AS, 0x0},
	{OP_WR, XSEM_REG_TS_16_AS, 0x4},
	{OP_WR, XSEM_REG_TS_17_AS, 0x3},
	{OP_ZR, XSEM_REG_TS_18_AS, 0x2},
	{OP_WR, XSEM_REG_ENABLE_IN, 0x3fff},
	{OP_WR, XSEM_REG_ENABLE_OUT, 0x3ff},
	{OP_WR, XSEM_REG_FIC0_DISABLE, 0x0},
	{OP_WR, XSEM_REG_FIC1_DISABLE, 0x0},
	{OP_WR, XSEM_REG_PAS_DISABLE, 0x0},
	{OP_WR, XSEM_REG_THREADS_LIST, 0xffff},
	{OP_ZR, XSEM_REG_PASSIVE_BUFFER, 0x800},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x18bc0, 0x1},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x18000, 0x0},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x18040, 0x18},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x18080, 0xc},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x180c0, 0x66},
	{OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18300, 0x7a120},
	{OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18300, 0x138},
	{OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18300, 0x1388},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x183c0, 0x1f4},
	{OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18340, 0x1f4},
	{OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18340, 0x0},
	{OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18340, 0x5},
	{OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b4},
	{OP_WR_ASIC, XSEM_REG_FAST_MEMORY + 0x18380, 0x1dcd6500},
	{OP_WR_EMUL, XSEM_REG_FAST_MEMORY + 0x11480, 0x0},
	{OP_WR_FPGA, XSEM_REG_FAST_MEMORY + 0x18380, 0x4c4b40},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x11480, 0x1},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x29c8, 0x4},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x29c8 + 0x10, 0x2034d},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2080, 0x48},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x9020, 0xc8},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x9000, 0x2},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x21a8, 0x86},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2000, 0x20},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x23c8, 0x0},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x23d0, 0x2034f},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2498, 0x40351},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x2c50, 0x0},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x2c10, 0x0},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2c08, 0x20355},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x3000, 0x20357},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x3000 + 0x8, 0x100},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x4040, 0x10},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x4000, 0x100359},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x6ac0, 0x2},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x6b00, 0x4},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x8408, 0x20369},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x0},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x10c00, 0x10036b},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x1000000},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x10c40, 0x8037b},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x10800, 0x2000000},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x10c60, 0x80383},
/* #define XSEM_COMMON_END         617 */
/* #define XSEM_PORT0_START        618 */
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xc000, 0xd8},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x24a8, 0x14},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2548, 0x22},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2548 + 0x88, 0x2038b},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2668, 0x22},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2668 + 0x88, 0x2038d},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2788, 0x22},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2788 + 0x88, 0x2038f},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x28a8, 0x22},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x28a8 + 0x88, 0x20391},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xa000, 0x28},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xa140, 0xc},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x29e0, 0x20393},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5020, 0x2},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5030, 0x2},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5000, 0x2},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5010, 0x2},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x5208, 0x1},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x6ac8, 0x20395},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x6b10, 0x42},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x6d20, 0x4},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xbcd0, 0x2},
/* #define XSEM_PORT0_END          619 */
/* #define XSEM_PORT1_START        620 */
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xc360, 0xd8},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x24f8, 0x14},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x25d8, 0x22},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x25d8 + 0x88, 0x20397},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x26f8, 0x22},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x26f8 + 0x88, 0x20399},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2818, 0x22},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2818 + 0x88, 0x2039b},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x2938, 0x22},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2938 + 0x88, 0x2039d},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xa0a0, 0x28},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xa170, 0xc},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x29e8, 0x2039f},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5028, 0x2},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5038, 0x2},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5008, 0x2},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5018, 0x2},
	{OP_WR, XSEM_REG_FAST_MEMORY + 0x520c, 0x1},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x6ad0, 0x203a1},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x6c18, 0x42},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x6d30, 0x4},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xbcd8, 0x2},
/* #define XSEM_PORT1_END          621 */
/* #define XSEM_FUNC0_START        622 */
	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6c0, 0x0},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x29f0, 0x1003a3},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5048, 0xe},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb000, 0x6},
/* #define XSEM_FUNC0_END          623 */
/* #define XSEM_FUNC1_START        624 */
	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6c4, 0x0},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2a30, 0x1003b3},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5080, 0xe},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb018, 0x6},
/* #define XSEM_FUNC1_END          625 */
/* #define XSEM_FUNC2_START        626 */
	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6c8, 0x0},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2a70, 0x1003c3},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x50b8, 0xe},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb030, 0x6},
/* #define XSEM_FUNC2_END          627 */
/* #define XSEM_FUNC3_START        628 */
	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6cc, 0x0},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2ab0, 0x1003d3},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x50f0, 0xe},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb048, 0x6},
/* #define XSEM_FUNC3_END          629 */
/* #define XSEM_FUNC4_START        630 */
	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6d0, 0x0},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2af0, 0x1003e3},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5128, 0xe},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb060, 0x6},
/* #define XSEM_FUNC4_END          631 */
/* #define XSEM_FUNC5_START        632 */
	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6d4, 0x0},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2b30, 0x1003f3},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5160, 0xe},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb078, 0x6},
/* #define XSEM_FUNC5_END          633 */
/* #define XSEM_FUNC6_START        634 */
	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6d8, 0x0},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2b70, 0x100403},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x5198, 0xe},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb090, 0x6},
/* #define XSEM_FUNC6_END          635 */
/* #define XSEM_FUNC7_START        636 */
	{OP_WR, XSEM_REG_FAST_MEMORY + 0xc6dc, 0x0},
	{OP_SW, XSEM_REG_FAST_MEMORY + 0x2bb0, 0x100413},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0x51d0, 0xe},
	{OP_ZR, XSEM_REG_FAST_MEMORY + 0xb0a8, 0x6},
/* #define XSEM_FUNC7_END          637 */
/* #define CDU_COMMON_START        638 */
	{OP_WR, CDU_REG_CDU_CONTROL0, 0x1},
	{OP_WR, CDU_REG_MF_MODE, 0x1},
	{OP_WR, CDU_REG_CDU_CHK_MASK0, 0x3d000},
	{OP_WR, CDU_REG_CDU_CHK_MASK1, 0x3d},
	{OP_WB, CDU_REG_L1TT, 0x2000423},
	{OP_WB, CDU_REG_MATT, 0x280623},
	{OP_ZR, CDU_REG_MATT + 0xa0, 0x18},
/* #define CDU_COMMON_END          639 */
/* #define DMAE_COMMON_START       660 */
	{OP_ZR, DMAE_REG_CMD_MEM, 0xe0},
	{OP_WR, DMAE_REG_CRC16C_INIT, 0x0},
	{OP_WR, DMAE_REG_CRC16T10_INIT, 0x1},
	{OP_WR, DMAE_REG_PXP_REQ_INIT_CRD, 0x2},
	{OP_WR, DMAE_REG_PCI_IFEN, 0x1},
	{OP_WR, DMAE_REG_GRC_IFEN, 0x1},
/* #define DMAE_COMMON_END         661 */
/* #define PXP_COMMON_START        682 */
	{OP_WB, PXP_REG_HST_INBOUND_INT + 0x400, 0x5064b},
	{OP_WB, PXP_REG_HST_INBOUND_INT, 0x50650},
	{OP_WB, PXP_REG_HST_INBOUND_INT + 0x20, 0x50655},
/* #define PXP_COMMON_END          683 */
/* #define CFC_COMMON_START        704 */
	{OP_ZR, CFC_REG_LINK_LIST, 0x100},
	{OP_WR, CFC_REG_CONTROL0, 0x10},
	{OP_WR, CFC_REG_DISABLE_ON_ERROR, 0x3fff},
	{OP_WR, CFC_REG_INTERFACES, 0x280000},
	{OP_WR, CFC_REG_LCREQ_WEIGHTS, 0x84924a},
	{OP_WR, CFC_REG_INTERFACES, 0x0},
/* #define CFC_COMMON_END          705 */
/* #define HC_FUNC0_START          732 */
	{OP_WR, HC_REG_CONFIG_0, 0x1080},
	{OP_WR, HC_REG_FUNC_NUM_P0, 0x0},
	{OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
	{OP_WR, HC_REG_ATTN_IDX, 0x0},
	{OP_ZR, HC_REG_ATTN_BIT, 0x2},
	{OP_WR, HC_REG_VQID_0, 0x2b5},
	{OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
	{OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
	{OP_WR, HC_REG_INT_MASK, 0x1ffff},
	{OP_ZR, HC_REG_PBA_COMMAND, 0x2},
	{OP_WR, HC_REG_CONFIG_0, 0x1a80},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
/* #define HC_FUNC0_END            733 */
/* #define HC_FUNC1_START          734 */
	{OP_WR, HC_REG_CONFIG_1, 0x1080},
	{OP_WR, HC_REG_FUNC_NUM_P1, 0x1},
	{OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
	{OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
	{OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
	{OP_WR, HC_REG_VQID_1, 0x2b5},
	{OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
	{OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
	{OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
	{OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
	{OP_WR, HC_REG_CONFIG_1, 0x1a80},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
/* #define HC_FUNC1_END            735 */
/* #define HC_FUNC2_START          736 */
	{OP_WR, HC_REG_CONFIG_0, 0x1080},
	{OP_WR, HC_REG_FUNC_NUM_P0, 0x2},
	{OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
	{OP_WR, HC_REG_ATTN_IDX, 0x0},
	{OP_ZR, HC_REG_ATTN_BIT, 0x2},
	{OP_WR, HC_REG_VQID_0, 0x2b5},
	{OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
	{OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
	{OP_WR, HC_REG_INT_MASK, 0x1ffff},
	{OP_ZR, HC_REG_PBA_COMMAND, 0x2},
	{OP_WR, HC_REG_CONFIG_0, 0x1a80},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
/* #define HC_FUNC2_END            737 */
/* #define HC_FUNC3_START          738 */
	{OP_WR, HC_REG_CONFIG_1, 0x1080},
	{OP_WR, HC_REG_FUNC_NUM_P1, 0x3},
	{OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
	{OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
	{OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
	{OP_WR, HC_REG_VQID_1, 0x2b5},
	{OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
	{OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
	{OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
	{OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
	{OP_WR, HC_REG_CONFIG_1, 0x1a80},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
/* #define HC_FUNC3_END            739 */
/* #define HC_FUNC4_START          740 */
	{OP_WR, HC_REG_CONFIG_0, 0x1080},
	{OP_WR, HC_REG_FUNC_NUM_P0, 0x4},
	{OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
	{OP_WR, HC_REG_ATTN_IDX, 0x0},
	{OP_ZR, HC_REG_ATTN_BIT, 0x2},
	{OP_WR, HC_REG_VQID_0, 0x2b5},
	{OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
	{OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
	{OP_WR, HC_REG_INT_MASK, 0x1ffff},
	{OP_ZR, HC_REG_PBA_COMMAND, 0x2},
	{OP_WR, HC_REG_CONFIG_0, 0x1a80},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
/* #define HC_FUNC4_END            741 */
/* #define HC_FUNC5_START          742 */
	{OP_WR, HC_REG_CONFIG_1, 0x1080},
	{OP_WR, HC_REG_FUNC_NUM_P1, 0x5},
	{OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
	{OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
	{OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
	{OP_WR, HC_REG_VQID_1, 0x2b5},
	{OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
	{OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
	{OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
	{OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
	{OP_WR, HC_REG_CONFIG_1, 0x1a80},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
/* #define HC_FUNC5_END            743 */
/* #define HC_FUNC6_START          744 */
	{OP_WR, HC_REG_CONFIG_0, 0x1080},
	{OP_WR, HC_REG_FUNC_NUM_P0, 0x6},
	{OP_WR, HC_REG_ATTN_NUM_P0, 0x10},
	{OP_WR, HC_REG_ATTN_IDX, 0x0},
	{OP_ZR, HC_REG_ATTN_BIT, 0x2},
	{OP_WR, HC_REG_VQID_0, 0x2b5},
	{OP_WR, HC_REG_PCI_CONFIG_0, 0x0},
	{OP_ZR, HC_REG_P0_PROD_CONS, 0x4a},
	{OP_WR, HC_REG_INT_MASK, 0x1ffff},
	{OP_ZR, HC_REG_PBA_COMMAND, 0x2},
	{OP_WR, HC_REG_CONFIG_0, 0x1a80},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS, 0x24},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x120, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x370, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x5c0, 0x4a},
/* #define HC_FUNC6_END            745 */
/* #define HC_FUNC7_START          746 */
	{OP_WR, HC_REG_CONFIG_1, 0x1080},
	{OP_WR, HC_REG_FUNC_NUM_P1, 0x7},
	{OP_WR, HC_REG_ATTN_NUM_P1, 0x10},
	{OP_WR, HC_REG_ATTN_IDX + 0x4, 0x0},
	{OP_ZR, HC_REG_ATTN_BIT + 0x8, 0x2},
	{OP_WR, HC_REG_VQID_1, 0x2b5},
	{OP_WR, HC_REG_PCI_CONFIG_1, 0x0},
	{OP_ZR, HC_REG_P1_PROD_CONS, 0x4a},
	{OP_WR, HC_REG_INT_MASK + 0x4, 0x1ffff},
	{OP_ZR, HC_REG_PBA_COMMAND + 0x8, 0x2},
	{OP_WR, HC_REG_CONFIG_1, 0x1a80},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x90, 0x24},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x248, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x498, 0x4a},
	{OP_ZR, HC_REG_STATISTIC_COUNTERS + 0x6e8, 0x4a},
/* #define HC_FUNC7_END            747 */
/* #define PXP2_COMMON_START       748 */
	{OP_WR, PXP2_REG_RQ_DRAM_ALIGN, 0x1},
	{OP_WR, PXP2_REG_PGL_CONTROL0, 0xe38340},
	{OP_WR, PXP2_REG_PGL_CONTROL1, 0x3c10},
	{OP_WR, PXP2_REG_RQ_ELT_DISABLE, 0x1},
	{OP_WR, PXP2_REG_WR_REV_MODE, 0x0},
	{OP_WR, PXP2_REG_PGL_INT_TSDM_0, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_TSDM_1, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_TSDM_2, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_TSDM_3, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_TSDM_4, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_TSDM_5, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_TSDM_6, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_TSDM_7, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_USDM_2, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_USDM_3, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_USDM_4, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_USDM_5, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_USDM_6, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_USDM_7, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_XSDM_1, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_XSDM_2, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_XSDM_3, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_XSDM_4, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_XSDM_5, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_XSDM_6, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_XSDM_7, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_CSDM_0, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_CSDM_1, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_CSDM_2, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_CSDM_3, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_CSDM_4, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_CSDM_5, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_CSDM_6, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_CSDM_7, 0xffffffff},
	{OP_WR, PXP2_REG_PGL_INT_XSDM_0, 0xff802000},
	{OP_WR, PXP2_REG_PGL_INT_USDM_0, 0xf0005000},
	{OP_WR, PXP2_REG_PGL_INT_USDM_1, 0xf0001000},
	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ6, 0x8},
	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ9, 0x8},
	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ10, 0x8},
	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ11, 0x2},
	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ17, 0x4},
	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ18, 0x5},
	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ19, 0x4},
	{OP_WR, PXP2_REG_RD_MAX_BLKS_VQ22, 0x0},
	{OP_WR, PXP2_REG_RD_START_INIT, 0x1},
	{OP_WR, PXP2_REG_WR_DMAE_TH, 0x3f},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD0, 0x40},
	{OP_WR, PXP2_REG_PSWRQ_BW_ADD1, 0x1808},
	{OP_WR, PXP2_REG_PSWRQ_BW_ADD2, 0x803},
	{OP_WR, PXP2_REG_PSWRQ_BW_ADD3, 0x803},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD4, 0x40},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD5, 0x3},
	{OP_WR, PXP2_REG_PSWRQ_BW_ADD6, 0x803},
	{OP_WR, PXP2_REG_PSWRQ_BW_ADD7, 0x803},
	{OP_WR, PXP2_REG_PSWRQ_BW_ADD8, 0x803},
	{OP_WR, PXP2_REG_PSWRQ_BW_ADD9, 0x10003},
	{OP_WR, PXP2_REG_PSWRQ_BW_ADD10, 0x803},
	{OP_WR, PXP2_REG_PSWRQ_BW_ADD11, 0x803},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD12, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD13, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD14, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD15, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD16, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD17, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD18, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD19, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD20, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD22, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD23, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD24, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD25, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD26, 0x3},
	{OP_WR, PXP2_REG_RQ_BW_RD_ADD27, 0x3},
	{OP_WR, PXP2_REG_PSWRQ_BW_ADD28, 0x2403},
	{OP_WR, PXP2_REG_RQ_BW_WR_ADD29, 0x2f},
	{OP_WR, PXP2_REG_RQ_BW_WR_ADD30, 0x9},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND0, 0x19},
	{OP_WR, PXP2_REG_PSWRQ_BW_UB1, 0x184},
	{OP_WR, PXP2_REG_PSWRQ_BW_UB2, 0x183},
	{OP_WR, PXP2_REG_PSWRQ_BW_UB3, 0x306},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND4, 0x19},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND5, 0x6},
	{OP_WR, PXP2_REG_PSWRQ_BW_UB6, 0x306},
	{OP_WR, PXP2_REG_PSWRQ_BW_UB7, 0x306},
	{OP_WR, PXP2_REG_PSWRQ_BW_UB8, 0x306},
	{OP_WR, PXP2_REG_PSWRQ_BW_UB9, 0xc86},
	{OP_WR, PXP2_REG_PSWRQ_BW_UB10, 0x306},
	{OP_WR, PXP2_REG_PSWRQ_BW_UB11, 0x306},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND12, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND13, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND14, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND15, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND16, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND17, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND18, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND19, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND20, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND22, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND23, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND24, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND25, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND26, 0x6},
	{OP_WR, PXP2_REG_RQ_BW_RD_UBOUND27, 0x6},
	{OP_WR, PXP2_REG_PSWRQ_BW_UB28, 0x306},
	{OP_WR, PXP2_REG_RQ_BW_WR_UBOUND29, 0x13},
	{OP_WR, PXP2_REG_RQ_BW_WR_UBOUND30, 0x6},
	{OP_WR, PXP2_REG_PSWRQ_BW_L1, 0x1004},
	{OP_WR, PXP2_REG_PSWRQ_BW_L2, 0x1004},
	{OP_WR, PXP2_REG_PSWRQ_BW_RD, 0x106440},
	{OP_WR, PXP2_REG_PSWRQ_BW_WR, 0x106440},
	{OP_WR, PXP2_REG_RQ_ILT_MODE, 0x1},
	{OP_WR, PXP2_REG_RQ_RBC_DONE, 0x1},
/* #define PXP2_COMMON_END         749 */
/* #define MISC_AEU_COMMON_START   770 */
	{OP_ZR, MISC_REG_AEU_GENERAL_ATTN_0, 0x16},
	{OP_WR, MISC_REG_AEU_ENABLE1_NIG_0, 0x55540000},
	{OP_WR, MISC_REG_AEU_ENABLE2_NIG_0, 0x55555555},
	{OP_WR, MISC_REG_AEU_ENABLE3_NIG_0, 0x5555},
	{OP_WR, MISC_REG_AEU_ENABLE4_NIG_0, 0xf0000000},
	{OP_WR, MISC_REG_AEU_ENABLE1_PXP_0, 0x55540000},
	{OP_WR, MISC_REG_AEU_ENABLE2_PXP_0, 0x55555555},
	{OP_WR, MISC_REG_AEU_ENABLE3_PXP_0, 0x5555},
	{OP_WR, MISC_REG_AEU_ENABLE4_PXP_0, 0xf0000000},
	{OP_WR, MISC_REG_AEU_ENABLE1_NIG_1, 0x55540000},
	{OP_WR, MISC_REG_AEU_ENABLE2_NIG_1, 0x55555555},
	{OP_WR, MISC_REG_AEU_ENABLE3_NIG_1, 0x5555},
	{OP_WR, MISC_REG_AEU_ENABLE4_NIG_1, 0xf0000000},
	{OP_WR, MISC_REG_AEU_ENABLE1_PXP_1, 0x0},
	{OP_WR, MISC_REG_AEU_ENABLE2_PXP_1, 0x10000},
	{OP_WR, MISC_REG_AEU_ENABLE3_PXP_1, 0x5014},
	{OP_WR, MISC_REG_AEU_ENABLE4_PXP_1, 0x0},
	{OP_WR, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0xc00},
	{OP_WR, MISC_REG_AEU_GENERAL_MASK, 0x3},
/* #define MISC_AEU_COMMON_END     771 */
/* #define MISC_AEU_PORT0_START    772 */
	{OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0, 0xff5c0000},
	{OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_0, 0xfff55fff},
	{OP_WR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_0, 0xffff},
	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 0xf00003e0},
	{OP_WR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1, 0x0},
	{OP_WR, MISC_REG_AEU_ENABLE2_FUNC_0_OUT_1, 0xa000},
	{OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_0_OUT_1, 0x5},
	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_2, 0xfe00000},
	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_3, 0x7},
	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_4, 0x400},
	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_5, 0x3},
	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_5, 0x1000},
	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_6, 0x3},
	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_6, 0x4000},
	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_0_OUT_7, 0x3},
	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_0_OUT_7, 0x10000},
	{OP_ZR, MISC_REG_AEU_INVERTER_1_FUNC_0, 0x4},
/* #define MISC_AEU_PORT0_END      773 */
/* #define MISC_AEU_PORT1_START    774 */
	{OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0, 0xff5c0000},
	{OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_0, 0xfff55fff},
	{OP_WR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_0, 0xffff},
	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 0xf00003e0},
	{OP_WR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1, 0x0},
	{OP_WR, MISC_REG_AEU_ENABLE2_FUNC_1_OUT_1, 0xa000},
	{OP_ZR, MISC_REG_AEU_ENABLE3_FUNC_1_OUT_1, 0x5},
	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_2, 0xfe00000},
	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_3, 0x7},
	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_4, 0x800},
	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_5, 0x3},
	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_5, 0x2000},
	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_6, 0x3},
	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_6, 0x8000},
	{OP_ZR, MISC_REG_AEU_ENABLE1_FUNC_1_OUT_7, 0x3},
	{OP_WR, MISC_REG_AEU_ENABLE4_FUNC_1_OUT_7, 0x20000},
	{OP_ZR, MISC_REG_AEU_INVERTER_1_FUNC_1, 0x4},
/* #define MISC_AEU_PORT1_END      775 */

};

static const u16 init_ops_offsets_e1h[] = {
	0x0000, 0x0031, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0031, 0x0032, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0032,
	0x0056, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0056, 0x008c, 0x0000, 0x0000, 0x0000, 0x0000,
	0x008c, 0x0090, 0x0090, 0x0094, 0x0094, 0x0098, 0x0098, 0x009c, 0x009c,
	0x00a0, 0x00a0, 0x00a4, 0x00a4, 0x00a8, 0x00a8, 0x00ac, 0x00ac, 0x00b1,
	0x00b1, 0x00b3, 0x00b3, 0x00b5, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x00b5, 0x0102, 0x0102, 0x010a, 0x010a, 0x0112, 0x0112,
	0x011b, 0x011b, 0x0124, 0x0124, 0x012d, 0x012d, 0x0136, 0x0136, 0x013f,
	0x013f, 0x0148, 0x0148, 0x0151, 0x0151, 0x015a, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x015a, 0x015f, 0x0000, 0x0000, 0x0000,
	0x0000, 0x015f, 0x0160, 0x0160, 0x0161, 0x0161, 0x0162, 0x0162, 0x0163,
	0x0163, 0x0164, 0x0164, 0x0165, 0x0165, 0x0166, 0x0166, 0x0167, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0167, 0x016c, 0x016c, 0x0179, 0x0179, 0x0186,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0186, 0x0187, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0187, 0x01be, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x01be, 0x01e9, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x01e9, 0x021a, 0x0000, 0x0000,
	0x0000, 0x0000, 0x021a, 0x0221, 0x0221, 0x0228, 0x0228, 0x022f, 0x022f,
	0x0236, 0x0236, 0x023d, 0x023d, 0x0244, 0x0244, 0x024b, 0x024b, 0x0252,
	0x0252, 0x028a, 0x0000, 0x0000, 0x0000, 0x0000, 0x028a, 0x028e, 0x028e,
	0x0292, 0x0292, 0x0296, 0x0296, 0x029a, 0x029a, 0x029e, 0x029e, 0x02a2,
	0x02a2, 0x02a6, 0x02a6, 0x02aa, 0x02aa, 0x02fa, 0x02fa, 0x0311, 0x0311,
	0x0328, 0x0328, 0x032b, 0x032b, 0x032e, 0x032e, 0x0331, 0x0331, 0x0334,
	0x0334, 0x0337, 0x0337, 0x033a, 0x033a, 0x033d, 0x033d, 0x0340, 0x0340,
	0x0381, 0x0381, 0x0388, 0x0388, 0x038f, 0x038f, 0x0393, 0x0393, 0x0397,
	0x0397, 0x039b, 0x039b, 0x039f, 0x039f, 0x03a3, 0x03a3, 0x03a7, 0x03a7,
	0x03ab, 0x03ab, 0x03af, 0x03af, 0x03b0, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03b0, 0x03c2,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x03c2, 0x03d7, 0x03d7, 0x03da, 0x03da, 0x03dd, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x03dd, 0x040a, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x040a, 0x050d, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x050d, 0x0514, 0x0514, 0x0518,
	0x0518, 0x051c, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x051c, 0x055c, 0x0000, 0x0000, 0x0000, 0x0000, 0x055c, 0x0565, 0x0565,
	0x056e, 0x056e, 0x0577, 0x0577, 0x0580, 0x0580, 0x0589, 0x0589, 0x0592,
	0x0592, 0x059b, 0x059b, 0x05a4, 0x05a4, 0x05fd, 0x05fd, 0x0613, 0x0613,
	0x0629, 0x0629, 0x062d, 0x062d, 0x0631, 0x0631, 0x0635, 0x0635, 0x0639,
	0x0639, 0x063d, 0x063d, 0x0641, 0x0641, 0x0645, 0x0645, 0x0649, 0x0649,
	0x0650, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0650, 0x0656, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0656, 0x0659,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0659, 0x065f, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x065f, 0x066e, 0x066e, 0x067d, 0x067d, 0x068c,
	0x068c, 0x069b, 0x069b, 0x06aa, 0x06aa, 0x06b9, 0x06b9, 0x06c8, 0x06c8,
	0x06d7, 0x06d7, 0x0748, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0748, 0x075b, 0x075b, 0x076c,
	0x076c, 0x077d, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
	0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000
};

static const u32 init_data_e1h[] = {
	0x00010000, 0x000204c0, 0x00030980, 0x00040e40, 0x00051300, 0x000617c0,
	0x00071c80, 0x00082140, 0x00092600, 0x000a2ac0, 0x000b2f80, 0x000c3440,
	0x000d3900, 0x000e3dc0, 0x000f4280, 0x00104740, 0x00114c00, 0x001250c0,
	0x00135580, 0x00145a40, 0x00155f00, 0x001663c0, 0x00176880, 0x00186d40,
	0x00197200, 0x001a76c0, 0x001b7b80, 0x001c8040, 0x001d8500, 0x001e89c0,
	0x001f8e80, 0x00209340, 0x00002000, 0x00004000, 0x00006000, 0x00008000,
	0x0000a000, 0x0000c000, 0x0000e000, 0x00010000, 0x00012000, 0x00014000,
	0x00016000, 0x00018000, 0x0001a000, 0x0001c000, 0x0001e000, 0x00020000,
	0x00022000, 0x00024000, 0x00026000, 0x00028000, 0x0002a000, 0x0002c000,
	0x0002e000, 0x00030000, 0x00032000, 0x00034000, 0x00036000, 0x00038000,
	0x0003a000, 0x0003c000, 0x0003e000, 0x00040000, 0x00042000, 0x00044000,
	0x00046000, 0x00048000, 0x0004a000, 0x0004c000, 0x0004e000, 0x00050000,
	0x00052000, 0x00054000, 0x00056000, 0x00058000, 0x0005a000, 0x0005c000,
	0x0005e000, 0x00060000, 0x00062000, 0x00064000, 0x00066000, 0x00068000,
	0x0006a000, 0x0006c000, 0x0006e000, 0x00070000, 0x00072000, 0x00074000,
	0x00076000, 0x00078000, 0x0007a000, 0x0007c000, 0x0007e000, 0x00080000,
	0x00082000, 0x00084000, 0x00086000, 0x00088000, 0x0008a000, 0x0008c000,
	0x0008e000, 0x00090000, 0x00092000, 0x00094000, 0x00096000, 0x00098000,
	0x0009a000, 0x0009c000, 0x0009e000, 0x000a0000, 0x000a2000, 0x000a4000,
	0x000a6000, 0x000a8000, 0x000aa000, 0x000ac000, 0x000ae000, 0x000b0000,
	0x000b2000, 0x000b4000, 0x000b6000, 0x000b8000, 0x000ba000, 0x000bc000,
	0x000be000, 0x000c0000, 0x000c2000, 0x000c4000, 0x000c6000, 0x000c8000,
	0x000ca000, 0x000cc000, 0x000ce000, 0x000d0000, 0x000d2000, 0x000d4000,
	0x000d6000, 0x000d8000, 0x000da000, 0x000dc000, 0x000de000, 0x000e0000,
	0x000e2000, 0x000e4000, 0x000e6000, 0x000e8000, 0x000ea000, 0x000ec000,
	0x000ee000, 0x000f0000, 0x000f2000, 0x000f4000, 0x000f6000, 0x000f8000,
	0x000fa000, 0x000fc000, 0x000fe000, 0x00100000, 0x00102000, 0x00104000,
	0x00106000, 0x00108000, 0x0010a000, 0x0010c000, 0x0010e000, 0x00110000,
	0x00112000, 0x00114000, 0x00116000, 0x00118000, 0x0011a000, 0x0011c000,
	0x0011e000, 0x00120000, 0x00122000, 0x00124000, 0x00126000, 0x00128000,
	0x0012a000, 0x0012c000, 0x0012e000, 0x00130000, 0x00132000, 0x00134000,
	0x00136000, 0x00138000, 0x0013a000, 0x0013c000, 0x0013e000, 0x00140000,
	0x00142000, 0x00144000, 0x00146000, 0x00148000, 0x0014a000, 0x0014c000,
	0x0014e000, 0x00150000, 0x00152000, 0x00154000, 0x00156000, 0x00158000,
	0x0015a000, 0x0015c000, 0x0015e000, 0x00160000, 0x00162000, 0x00164000,
	0x00166000, 0x00168000, 0x0016a000, 0x0016c000, 0x0016e000, 0x00170000,
	0x00172000, 0x00174000, 0x00176000, 0x00178000, 0x0017a000, 0x0017c000,
	0x0017e000, 0x00180000, 0x00182000, 0x00184000, 0x00186000, 0x00188000,
	0x0018a000, 0x0018c000, 0x0018e000, 0x00190000, 0x00192000, 0x00194000,
	0x00196000, 0x00198000, 0x0019a000, 0x0019c000, 0x0019e000, 0x001a0000,
	0x001a2000, 0x001a4000, 0x001a6000, 0x001a8000, 0x001aa000, 0x001ac000,
	0x001ae000, 0x001b0000, 0x001b2000, 0x001b4000, 0x001b6000, 0x001b8000,
	0x001ba000, 0x001bc000, 0x001be000, 0x001c0000, 0x001c2000, 0x001c4000,
	0x001c6000, 0x001c8000, 0x001ca000, 0x001cc000, 0x001ce000, 0x001d0000,
	0x001d2000, 0x001d4000, 0x001d6000, 0x001d8000, 0x001da000, 0x001dc000,
	0x001de000, 0x001e0000, 0x001e2000, 0x001e4000, 0x001e6000, 0x001e8000,
	0x001ea000, 0x001ec000, 0x001ee000, 0x001f0000, 0x001f2000, 0x001f4000,
	0x001f6000, 0x001f8000, 0x001fa000, 0x001fc000, 0x001fe000, 0x00200000,
	0x00202000, 0x00204000, 0x00206000, 0x00208000, 0x0020a000, 0x0020c000,
	0x0020e000, 0x00210000, 0x00212000, 0x00214000, 0x00216000, 0x00218000,
	0x0021a000, 0x0021c000, 0x0021e000, 0x00220000, 0x00222000, 0x00224000,
	0x00226000, 0x00228000, 0x0022a000, 0x0022c000, 0x0022e000, 0x00230000,
	0x00232000, 0x00234000, 0x00236000, 0x00238000, 0x0023a000, 0x0023c000,
	0x0023e000, 0x00240000, 0x00242000, 0x00244000, 0x00246000, 0x00248000,
	0x0024a000, 0x0024c000, 0x0024e000, 0x00250000, 0x00252000, 0x00254000,
	0x00256000, 0x00258000, 0x0025a000, 0x0025c000, 0x0025e000, 0x00260000,
	0x00262000, 0x00264000, 0x00266000, 0x00268000, 0x0026a000, 0x0026c000,
	0x0026e000, 0x00270000, 0x00272000, 0x00274000, 0x00276000, 0x00278000,
	0x0027a000, 0x0027c000, 0x0027e000, 0x00280000, 0x00282000, 0x00284000,
	0x00286000, 0x00288000, 0x0028a000, 0x0028c000, 0x0028e000, 0x00290000,
	0x00292000, 0x00294000, 0x00296000, 0x00298000, 0x0029a000, 0x0029c000,
	0x0029e000, 0x002a0000, 0x002a2000, 0x002a4000, 0x002a6000, 0x002a8000,
	0x002aa000, 0x002ac000, 0x002ae000, 0x002b0000, 0x002b2000, 0x002b4000,
	0x002b6000, 0x002b8000, 0x002ba000, 0x002bc000, 0x002be000, 0x002c0000,
	0x002c2000, 0x002c4000, 0x002c6000, 0x002c8000, 0x002ca000, 0x002cc000,
	0x002ce000, 0x002d0000, 0x002d2000, 0x002d4000, 0x002d6000, 0x002d8000,
	0x002da000, 0x002dc000, 0x002de000, 0x002e0000, 0x002e2000, 0x002e4000,
	0x002e6000, 0x002e8000, 0x002ea000, 0x002ec000, 0x002ee000, 0x002f0000,
	0x002f2000, 0x002f4000, 0x002f6000, 0x002f8000, 0x002fa000, 0x002fc000,
	0x002fe000, 0x00300000, 0x00302000, 0x00304000, 0x00306000, 0x00308000,
	0x0030a000, 0x0030c000, 0x0030e000, 0x00310000, 0x00312000, 0x00314000,
	0x00316000, 0x00318000, 0x0031a000, 0x0031c000, 0x0031e000, 0x00320000,
	0x00322000, 0x00324000, 0x00326000, 0x00328000, 0x0032a000, 0x0032c000,
	0x0032e000, 0x00330000, 0x00332000, 0x00334000, 0x00336000, 0x00338000,
	0x0033a000, 0x0033c000, 0x0033e000, 0x00340000, 0x00342000, 0x00344000,
	0x00346000, 0x00348000, 0x0034a000, 0x0034c000, 0x0034e000, 0x00350000,
	0x00352000, 0x00354000, 0x00356000, 0x00358000, 0x0035a000, 0x0035c000,
	0x0035e000, 0x00360000, 0x00362000, 0x00364000, 0x00366000, 0x00368000,
	0x0036a000, 0x0036c000, 0x0036e000, 0x00370000, 0x00372000, 0x00374000,
	0x00376000, 0x00378000, 0x0037a000, 0x0037c000, 0x0037e000, 0x00380000,
	0x00382000, 0x00384000, 0x00386000, 0x00388000, 0x0038a000, 0x0038c000,
	0x0038e000, 0x00390000, 0x00392000, 0x00394000, 0x00396000, 0x00398000,
	0x0039a000, 0x0039c000, 0x0039e000, 0x003a0000, 0x003a2000, 0x003a4000,
	0x003a6000, 0x003a8000, 0x003aa000, 0x003ac000, 0x003ae000, 0x003b0000,
	0x003b2000, 0x003b4000, 0x003b6000, 0x003b8000, 0x003ba000, 0x003bc000,
	0x003be000, 0x003c0000, 0x003c2000, 0x003c4000, 0x003c6000, 0x003c8000,
	0x003ca000, 0x003cc000, 0x003ce000, 0x003d0000, 0x003d2000, 0x003d4000,
	0x003d6000, 0x003d8000, 0x003da000, 0x003dc000, 0x003de000, 0x003e0000,
	0x003e2000, 0x003e4000, 0x003e6000, 0x003e8000, 0x003ea000, 0x003ec000,
	0x003ee000, 0x003f0000, 0x003f2000, 0x003f4000, 0x003f6000, 0x003f8000,
	0x003fa000, 0x003fc000, 0x003fe000, 0x003fe001, 0x00000000, 0x000001ff,
	0x00000200, 0x00007ff8, 0x00007ff8, 0x00000cdf, 0x00001500, 0x00000001,
	0x00000001, 0x00000001, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x00000000,
	0xffffffff, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff,
	0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000,
	0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff,
	0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff, 0x00000000,
	0xffffffff, 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20, 0xffffffff,
	0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003, 0x00bebc20,
	0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff, 0x00000003,
	0x00bebc20, 0xffffffff, 0x00000000, 0xffffffff, 0x00000000, 0xffffffff,
	0x00000003, 0x00bebc20, 0x00002000, 0x000040c0, 0x00006180, 0x00008240,
	0x0000a300, 0x0000c3c0, 0x0000e480, 0x00010540, 0x00012600, 0x000146c0,
	0x00016780, 0x00018840, 0x0001a900, 0x0001c9c0, 0x0001ea80, 0x00020b40,
	0x00022c00, 0x00024cc0, 0x00026d80, 0x00028e40, 0x0002af00, 0x0002cfc0,
	0x0002f080, 0x00031140, 0x00033200, 0x000352c0, 0x00037380, 0x00039440,
	0x0003b500, 0x0003d5c0, 0x0003f680, 0x00041740, 0x00043800, 0x000458c0,
	0x00047980, 0x00049a40, 0x00008000, 0x00010380, 0x00018700, 0x00020a80,
	0x00028e00, 0x00031180, 0x00039500, 0x00041880, 0x00049c00, 0x00051f80,
	0x0005a300, 0x00062680, 0x0006aa00, 0x00072d80, 0x0007b100, 0x00083480,
	0x0008b800, 0x00093b80, 0x0009bf00, 0x000a4280, 0x000ac600, 0x000b4980,
	0x000bcd00, 0x000c5080, 0x000cd400, 0x000d5780, 0x000ddb00, 0x00007ff8,
	0x00007ff8, 0x0000192a, 0x00003500, 0x00001900, 0x00100000, 0x00000000,
	0x00000000, 0xffffffff, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x00007ff8, 0x00007ff8,
	0x000005c7, 0x00001500, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff,
	0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x00001000, 0x00002080, 0x00003100, 0x00004180, 0x00005200, 0x00006280,
	0x00007300, 0x00008380, 0x00009400, 0x0000a480, 0x0000b500, 0x0000c580,
	0x0000d600, 0x0000e680, 0x0000f700, 0x00010780, 0x00011800, 0x00012880,
	0x00013900, 0x00014980, 0x00015a00, 0x00016a80, 0x00017b00, 0x00018b80,
	0x00019c00, 0x0001ac80, 0x0001bd00, 0x0001cd80, 0x0001de00, 0x0001ee80,
	0x0001ff00, 0x00007ff8, 0x00007ff8, 0x0000112e, 0x00003500, 0x10000000,
	0x000028ad, 0x00000000, 0x00010001, 0x000d0205, 0xccccccc5, 0xffffffff,
	0xffffffff, 0x7058103c, 0x00000000, 0x00000000, 0x00000001, 0xcccc0201,
	0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201,
	0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201, 0xcccccccc, 0xcccc0201,
	0xcccccccc, 0xcccc0201, 0xcccccccc, 0x00000000, 0xffffffff, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000, 0x40000000,
	0x40000000, 0x002625a0, 0x00000000, 0x002625a0, 0x00000000, 0x002625a0,
	0x00000000, 0x002625a0, 0x00000000, 0x000e0232, 0x011600d6, 0x00100000,
	0x00000000, 0x002625a0, 0x00000000, 0x002625a0, 0x00000000, 0x002625a0,
	0x00000000, 0x002625a0, 0x00000000, 0x00720236, 0x012300f3, 0x00100000,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff, 0x00000000, 0x0000ffff,
	0x00000000, 0x0000ffff, 0x00000000, 0xfffffff3, 0x318fffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
	0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
	0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
	0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
	0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
	0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
	0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
	0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xfffffff7, 0x31efffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
	0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
	0xcdcdcdcd, 0xfffffff3, 0x318fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
	0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
	0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
	0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014,
	0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
	0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
	0xcdcdcdcd, 0xfffffff7, 0x30efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
	0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5, 0x304fffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3,
	0x31efffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c,
	0xcdcdcdcd, 0xfffffff1, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
	0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406,
	0x1cbfffff, 0x0c30c305, 0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c,
	0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
	0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa, 0x302fffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97,
	0x056fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c,
	0xcdcdcdcd, 0xfffffff5, 0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
	0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xfffffff3, 0x320fffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1,
	0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c,
	0xcdcdcdcd, 0xfffffff6, 0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
	0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xfffff406, 0x1cbfffff, 0x0c30c305,
	0xc30c30c3, 0xcf300014, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2,
	0x304fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c,
	0xcdcdcdcd, 0xffffff8a, 0x042fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cc000,
	0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffff97, 0x05cfffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cc000, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff5,
	0x310fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c,
	0xcdcdcdcd, 0xfffffff3, 0x316fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
	0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xfffffff1, 0x302fffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xfffffff6,
	0x305fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0002cf3c,
	0xcdcdcdcd, 0xfffffff6, 0x30bfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf314,
	0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xfffffff2, 0x304fffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xfffffffa,
	0x302fffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0010cf3c,
	0xcdcdcdcd, 0xfffffff7, 0x31cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf300,
	0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xfffffff0, 0x307fffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf300, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff,
	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c,
	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
	0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff,
	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c,
	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
	0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff,
	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c,
	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
	0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff,
	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c,
	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
	0xf3cf3cf3, 0x0002cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff,
	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c,
	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
	0xf3cf3cf3, 0x0010cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff,
	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c,
	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
	0xf3cf3cf3, 0x0000cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0001cf3c, 0xcdcdcdcd, 0xffffffff,
	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0002cf3c,
	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
	0xf3cf3cf3, 0x0004cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0008cf3c, 0xcdcdcdcd, 0xffffffff,
	0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0010cf3c,
	0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c, 0xc30c30c3, 0xcf3cf3cc,
	0xf3cf3cf3, 0x0020cf3c, 0xcdcdcdcd, 0xffffffff, 0x30cfffff, 0x0c30c30c,
	0xc30c30c3, 0xcf3cf3cc, 0xf3cf3cf3, 0x0040cf3c, 0xcdcdcdcd, 0x000c0000,
	0x000700c0, 0x00028130, 0x000b8158, 0x00020210, 0x00010230, 0x000f0240,
	0x00010330, 0x000c0000, 0x000800c0, 0x00028140, 0x000b8168, 0x00020220,
	0x00010240, 0x00070250, 0x000202c0, 0x000f0000, 0x000800f0, 0x00028170,
	0x000b8198, 0x00020250, 0x00010270, 0x000b8280, 0x00080338, 0x00100000,
	0x00080100, 0x00028180, 0x000b81a8, 0x00020260, 0x00018280, 0x000e8298,
	0x00080380, 0x000b0000, 0x000100b0, 0x000280c0, 0x000580e8, 0x00020140,
	0x00010160, 0x000e0170, 0x00038250, 0xcccccccc, 0xcccccccc, 0xcccccccc,
	0xcccccccc, 0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc,
	0x00002000, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0xcccccccc, 0x04002000
};

static const u8 tsem_int_table_data_e1h[] = {
	0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xfb, 0x51,
	0xcf, 0xc0, 0xf0, 0x03, 0x8a, 0x59, 0x05, 0x19, 0x18, 0xac, 0x84, 0x11,
	0x7c, 0x7a, 0x60, 0x7e, 0x4e, 0xca, 0xf4, 0x3b, 0xf2, 0x32, 0x30, 0x38,
	0x03, 0xb1, 0x2b, 0x10, 0x37, 0x00, 0xf1, 0x61, 0x6e, 0x06, 0x86, 0x23,
	0xdc, 0xc4, 0xeb, 0x3f, 0x29, 0x8f, 0x60, 0x7b, 0xcb, 0x32, 0x30, 0x94,
	0x03, 0xf1, 0x76, 0x69, 0x06, 0x06, 0x13, 0x39, 0x84, 0xb8, 0xae, 0x02,
	0x03, 0xc3, 0x3c, 0x20, 0x3f, 0x01, 0x2a, 0xf6, 0x14, 0x48, 0x67, 0xcb,
	0x53, 0xe6, 0xee, 0xc1, 0x82, 0x15, 0x54, 0x31, 0xc5, 0x64, 0x95, 0x11,
	0x6c, 0x45, 0x2c, 0xf2, 0xc8, 0x58, 0x09, 0x4d, 0xbe, 0x46, 0x19, 0x95,
	0xaf, 0x4c, 0x40, 0xff, 0x40, 0xe3, 0x78, 0x1d, 0x54, 0x7e, 0x8f, 0x16,
	0x84, 0x7e, 0xad, 0x0d, 0xa1, 0x13, 0xd0, 0xe4, 0x7b, 0xa1, 0xf2, 0x8e,
	0x50, 0x7f, 0x25, 0xea, 0x60, 0x37, 0xd7, 0x89, 0x48, 0x7f, 0xa7, 0xb2,
	0xa0, 0xb9, 0x07, 0x8d, 0xdf, 0xca, 0x88, 0xca, 0x37, 0xe3, 0x40, 0xe5,
	0x27, 0x41, 0xd5, 0x03, 0x00, 0x07, 0x49, 0x30, 0x0a, 0xc8, 0x03, 0x00,
	0x00, 0x00, 0x00, 0x00
};

static const u8 tsem_pram_data_e1h[] = {
	0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d,
	0x0d, 0x78, 0x54, 0xd5, 0xb5, 0xe8, 0x3e, 0x73, 0xce, 0x9c, 0x99, 0x49,
	0xce, 0x4c, 0x26, 0xbf, 0x4c, 0x20, 0xc0, 0x49, 0x08, 0x21, 0x68, 0xa4,
	0xc7, 0x00, 0x69, 0xb0, 0x58, 0x4f, 0x20, 0x60, 0xa8, 0xd4, 0x0e, 0x14,
	0x69, 0xac, 0x8a, 0x03, 0x22, 0x44, 0x08, 0x24, 0x52, 0xeb, 0xc3, 0xab,
	0xfd, 0x32, 0x81, 0x00, 0x01, 0x02, 0x04, 0xb1, 0x34, 0x14, 0xa4, 0x43,
	0x00, 0xa5, 0xb7, 0xb4, 0x37, 0x52, 0xb4, 0xd4, 0x52, 0x3a, 0xe0, 0xa7,
	0xc5, 0xd6, 0xf7, 0xbd, 0xe0, 0xb3, 0x56, 0xaf, 0xb6, 0x6f, 0xb4, 0x14,
	0x7f, 0x8a, 0x12, 0xf3, 0xae, 0xd6, 0xbe, 0x6b, 0xeb, 0xdb, 0x6b, 0xed,
	0xbd, 0x93, 0x73, 0x4e, 0x66, 0x48, 0x10, 0xbd, 0xed, 0x7d, 0xef, 0xc6,
	0xcf, 0xef, 0xb0, 0xcf, 0xd9, 0x3f, 0x6b, 0xaf, 0xbf, 0xbd, 0xd6, 0xda,
	0x6b, 0xef, 0x71, 0xbb, 0xfc, 0x24, 0x6f, 0x34, 0x21, 0x1f, 0xc3, 0xdf,
	0x75, 0x84, 0xfc, 0x2f, 0x8d, 0x10, 0x92, 0xdb, 0xff, 0x74, 0x7b, 0x49,
	0x34, 0xfd, 0x73, 0x84, 0x64, 0xe6, 0x98, 0xd1, 0x44, 0x19, 0x21, 0xc3,
	0x72, 0xcc, 0x38, 0x99, 0x44, 0xdf, 0x07, 0x55, 0xdd, 0x23, 0xf5, 0xb7,
	0x13, 0xcf, 0x93, 0x99, 0x33, 0x43, 0x50, 0xaf, 0x25, 0xd7, 0x0c, 0x11,
	0xda, 0x47, 0x4b, 0xe6, 0x7c, 0x12, 0x81, 0xbe, 0x22, 0x75, 0x84, 0xe4,
	0x11, 0xa2, 0x78, 0x09, 0xfe, 0x89, 0xfa, 0xee, 0xe0, 0x5c, 0x2f, 0x29,
	0xc3, 0x57, 0x7f, 0xfb, 0x58, 0x7c, 0x97, 0x09, 0x59, 0x17, 0x2c, 0xca,
	0x80, 0x76, 0xce, 0xfe, 0x09, 0x89, 0x11, 0x32, 0xd9, 0x5a, 0x76, 0x11,
	0x22, 0xfa, 0xa4, 0xed, 0xbc, 0x00, 0x6f, 0x06, 0x85, 0x57, 0xa7, 0x2f,
	0x28, 0x9c, 0x69, 0x93, 0x5c, 0xb1, 0xeb, 0x0b, 0x29, 0xdc, 0x7a, 0x0c,
	0xe1, 0x4e, 0x2f, 0xa0, 0x70, 0xd3, 0xf2, 0xc9, 0x91, 0xcf, 0x78, 0xc7,
	0xd0, 0xf2, 0xa6, 0x6b, 0x5d, 0x86, 0x07, 0x5b, 0xdf, 0x4d, 0x48, 0x05,
	0x21, 0xab, 0xa0, 0x2f, 0xda, 0x76, 0xd3, 0x55, 0x71, 0xfe, 0x5d, 0x31,
	0xa0, 0x3c, 0x43, 0x3e, 0xdc, 0xac, 0x42, 0x7b, 0x9d, 0x18, 0x1e, 0x5a,
	0xf6, 0x5f, 0xd5, 0x18, 0x57, 0xb1, 0x9d, 0xa9, 0xe5, 0xd3, 0x76, 0x41,
	0xc2, 0xda, 0x05, 0x4b, 0x97, 0xcc, 0x26, 0x13, 0x08, 0xc9, 0x30, 0xd5,
	0x7e, 0xb8, 0x58, 0x3d, 0x9c, 0x7f, 0x3a, 0xaf, 0xe7, 0xd1, 0xe9, 0xf7,
	0xd2, 0xfe, 0xef, 0xe9, 0xa4, 0xed, 0x3d, 0x39, 0x00, 0xa5, 0x04, 0x09,
	0xfb, 0x69, 0xff, 0x95, 0x8e, 0xef, 0xa5, 0x33, 0xdf, 0x80, 0x7e, 0xd3,
	0x89, 0xa5, 0x5f, 0x3a, 0x8f, 0xed, 0xf0, 0x8f, 0x7c, 0x42, 0xbe, 0x40,
	0xfc, 0x39, 0xe7, 0xa0, 0xf3, 0xcf, 0x93, 0xcf, 0x03, 0x1e, 0x48, 0x75,
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	0x72, 0xa8, 0xf7, 0x9e, 0x2a, 0x05, 0xe4, 0x2b, 0xc0, 0xef, 0x94, 0xc3,
	0xa3, 0xe6, 0xa2, 0x1f, 0xda, 0xb3, 0x9a, 0xe4, 0x92, 0x7a, 0x35, 0xec,
	0x2f, 0xfa, 0x4d, 0xff, 0x76, 0xa3, 0xb0, 0xe7, 0xb8, 0x9c, 0x2b, 0x16,
	0x72, 0xad, 0x18, 0xfb, 0xc1, 0x75, 0xe4, 0x0c, 0x24, 0x79, 0x57, 0x24,
	0xc6, 0x1d, 0x63, 0xad, 0x27, 0x7d, 0x7a, 0x2c, 0xf3, 0x0a, 0xff, 0x8e,
	0xf0, 0x83, 0x3c, 0xb0, 0x97, 0xec, 0xc0, 0xff, 0x0d, 0x9f, 0x4d, 0x61,
	0x77, 0x60, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00
};

static const u8 usem_int_table_data_e1h[] = {
	0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xfb, 0x51,
	0xcf, 0xc0, 0xf0, 0x03, 0x8a, 0xf9, 0x2c, 0x18, 0x18, 0x56, 0x59, 0x31,
	0x30, 0xdc, 0xb0, 0x66, 0x60, 0x70, 0xb4, 0x61, 0x60, 0xd8, 0x6c, 0x8e,
	0x90, 0xbb, 0x21, 0x8e, 0x60, 0x53, 0x13, 0x3f, 0x97, 0xa7, 0x4c, 0xff,
	0x3c, 0x49, 0x06, 0x86, 0x05, 0x40, 0xbc, 0x08, 0x88, 0x97, 0x48, 0x92,
	0xae, 0xff, 0xb7, 0x16, 0x82, 0x5d, 0xac, 0xca, 0xc0, 0xf0, 0x07, 0xc8,
	0x77, 0x01, 0xd2, 0x5f, 0xd5, 0x19, 0x18, 0x6e, 0x03, 0xd9, 0x7f, 0x81,
	0xb8, 0x03, 0xc8, 0x5f, 0x03, 0xc4, 0x3b, 0x80, 0x58, 0x04, 0xc8, 0xbf,
	0x09, 0xa4, 0x99, 0xd5, 0x18, 0x18, 0x9e, 0x00, 0xe9, 0x7f, 0x40, 0xbe,
	0x34, 0x90, 0x7d, 0x44, 0x0d, 0xbb, 0xf9, 0xff, 0xb5, 0xf0, 0xdb, 0xbf,
	0x5d, 0x03, 0x95, 0xff, 0x12, 0x8d, 0x7f, 0x41, 0x1d, 0xbf, 0xfe, 0x28,
	0x4d, 0xfc, 0xf2, 0xaf, 0x09, 0xc8, 0x63, 0xc3, 0x5e, 0xf6, 0xe4, 0xc7,
	0x47, 0x1f, 0x05, 0x7a, 0x07, 0x02, 0xaf, 0x47, 0x4b, 0xd7, 0xe2, 0xa6,
	0x0c, 0x0c, 0x7a, 0x66, 0x0c, 0x0c, 0x85, 0xd0, 0xb4, 0xbf, 0x06, 0x49,
	0xbe, 0x19, 0x28, 0x26, 0x61, 0x0a, 0x61, 0x7f, 0xd1, 0x03, 0xe6, 0x17,
	0x20, 0x7f, 0x25, 0x8e, 0x7c, 0xf1, 0x15, 0x28, 0xcf, 0x0f, 0x94, 0xef,
	0x37, 0xc7, 0x6f, 0xbf, 0x38, 0x33, 0x5a, 0x7a, 0xe1, 0xc1, 0x54, 0xf3,
	0x96, 0x09, 0xc1, 0xae, 0x17, 0x42, 0x95, 0xdb, 0x24, 0x8c, 0xa9, 0xfe,
	0xa7, 0x08, 0x03, 0x03, 0x00, 0xe9, 0x28, 0x50, 0x78, 0xd8, 0x03, 0x00,
	0x00, 0x00, 0x00, 0x00
};

static const u8 usem_pram_data_e1h[] = {
	0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xe5, 0x7d,
	0x0f, 0x74, 0x54, 0xd5, 0xb5, 0xf7, 0xb9, 0x73, 0xef, 0xdc, 0x99, 0x24,
	0x77, 0x26, 0x93, 0x10, 0x60, 0x42, 0x02, 0x4e, 0x12, 0xd4, 0x58, 0x03,
	0x8c, 0x18, 0x30, 0x26, 0x13, 0xb8, 0x21, 0x09, 0x84, 0x24, 0xe0, 0x00,
	0x7e, 0x34, 0x56, 0x5a, 0x07, 0xe4, 0x21, 0xb6, 0x40, 0xa3, 0xb5, 0xad,
	0xed, 0xf3, 0x95, 0xe1, 0x8f, 0x31, 0x5a, 0xac, 0xd0, 0xf2, 0xfa, 0xd4,
	0x76, 0x7d, 0xdf, 0x40, 0xd5, 0xd5, 0xf6, 0xb9, 0xde, 0x0a, 0x8a, 0x4a,
	0x43, 0x42, 0x27, 0x90, 0x50, 0x24, 0x88, 0x11, 0x2d, 0xd6, 0x6a, 0xfb,
	0xa2, 0x76, 0xd9, 0xf8, 0x1a, 0xed, 0x80, 0xc1, 0xc6, 0xef, 0xa3, 0x8f,
	0xef, 0xec, 0x7d, 0xce, 0xc9, 0xcc, 0x3d, 0x99, 0x49, 0x42, 0xf5, 0xad,
	0x7e, 0x7f, 0x64, 0xb5, 0x37, 0xf7, 0xde, 0x73, 0xcf, 0xd9, 0x67, 0x9f,
	0xbd, 0xf7, 0xf9, 0xed, 0x7d, 0xf6, 0x39, 0x63, 0xb7, 0xb9, 0x88, 0xe7,
	0x0a, 0x42, 0x2e, 0xc1, 0x7f, 0x0b, 0x09, 0xf9, 0x5c, 0x2e, 0x21, 0x64,
	0x5e, 0xfc, 0x2a, 0x9e, 0x2f, 0x72, 0x92, 0x70, 0xc6, 0x1c, 0x42, 0xb2,
	0x9c, 0x07, 0x7a, 0x67, 0xe7, 0x10, 0xb2, 0xd8, 0x50, 0xfd, 0x4b, 0x7c,
	0x84, 0x4c, 0x75, 0xae, 0xed, 0x26, 0xa5, 0x84, 0x04, 0x88, 0xc3, 0xe7,
	0x50, 0x08, 0xe9, 0x52, 0x5e, 0xe8, 0x9d, 0x4d, 0xef, 0x8f, 0xbb, 0xec,
	0x7e, 0x07, 0x81, 0xff, 0xee, 0x22, 0x64, 0x3e, 0x21, 0x77, 0x3b, 0xe9,
	0x9f, 0xb4, 0xfc, 0xf1, 0x73, 0xf4, 0x0a, 0xef, 0x3f, 0xb1, 0x45, 0x08,
	0x2d, 0x5f, 0xab, 0x36, 0x12, 0x05, 0xbe, 0x77, 0x2a, 0x7e, 0x87, 0x0f,
	0xca, 0x9b, 0xc6, 0xb2, 0x29, 0x84, 0xd4, 0x10, 0xf6, 0xdf, 0x82, 0x73,
	0xa4, 0x46, 0xa1, 0xcf, 0x6b, 0xbc, 0x77, 0x34, 0x92, 0xd9, 0x84, 0x54,
	0x7b, 0x68, 0xad, 0x4e, 0xf6, 0xee, 0x12, 0xfe, 0xbf, 0x49, 0x08, 0x2d,
	0x5f, 0x41, 0x58, 0xfd, 0xa6, 0xd3, 0xfa, 0xbe, 0x82, 0xec, 0x3a, 0xa7,
	0xba, 0xe1, 0x2e, 0xa6, 0x06, 0x67, 0xd1, 0xfa, 0x2e, 0xea, 0xd6, 0xf7,
	0xde, 0x25, 0x7f, 0x24, 0x6e, 0x28, 0x97, 0xf0, 0xbc, 0x80, 0xf6, 0x03,
	0xfe, 0xa0, 0x3c, 0xb8, 0x8a, 0xb8, 0x72, 0xde, 0xcb, 0xa0, 0x7f, 0xdf,
	0x40, 0x6e, 0xb8, 0xa4, 0xd2, 0xab, 0x36, 0x89, 0x90, 0x1b, 0xe3, 0x7c,
	0x91, 0xaf, 0x84, 0x84, 0x09, 0x99, 0x4c, 0x48, 0x3b, 0xff, 0x5e, 0x23,
	0xc1, 0xd9, 0x70, 0x4f, 0xc8, 0x33, 0xd8, 0x7e, 0xb6, 0xe0, 0x63, 0x5d,
	0x3f, 0xf1, 0xd2, 0x7e, 0xe7, 0x94, 0x11, 0xff, 0x12, 0xca, 0x87, 0xa9,
	0x75, 0x66, 0x17, 0xa1, 0x7c, 0xad, 0xa8, 0xd1, 0x19, 0x1f, 0x6b, 0xe7,
	0xe7, 0xf6, 0x1b, 0x84, 0xfc, 0xe0, 0x83, 0xb6, 0x3c, 0x52, 0x42, 0x3f,
	0x8f, 0x6c, 0x42, 0x3e, 0xe6, 0x70, 0x3e, 0x76, 0x7d, 0xf0, 0xfc, 0x9b,
	0x5b, 0x80, 0x6f, 0x75, 0x04, 0xf9, 0x76, 0xd8, 0xee, 0xcf, 0x0d, 0x96,
	0x8c, 0xa6, 0x27, 0x50, 0x97, 0x9d, 0x46, 0x68, 0x3d, 0x7b, 0x82, 0x47,
	0x33, 0xb0, 0x1e, 0x42, 0xfe, 0xf3, 0xd2, 0x14, 0x5e, 0x4f, 0x11, 0x21,
	0x1d, 0xc1, 0xc2, 0xcc, 0x50, 0x92, 0xef, 0xc4, 0xf5, 0x91, 0xad, 0x1e,
	0x42, 0x1c, 0xf1, 0xfb, 0xdd, 0x26, 0xa9, 0x6b, 0x33, 0x46, 0x97, 0x7b,
	0x1e, 0x06, 0x73, 0x1e, 0x54, 0xbf, 0x06, 0xe9, 0xac, 0xe0, 0xbc, 0xfc,
	0x81, 0x42, 0x9a, 0xda, 0xb0, 0xdd, 0x26, 0x1c, 0xa7, 0xc3, 0x9c, 0xfe,
	0x6e, 0xf3, 0x68, 0x46, 0x7f, 0x09, 0xbc, 0x8f, 0x66, 0xd8, 0x68, 0x3f,
	0xc2, 0xe7, 0x6c, 0xe4, 0x49, 0x5a, 0x45, 0xc7, 0xe0, 0xa2, 0x74, 0xa0,
	0x77, 0xbb, 0x69, 0x8b, 0xc2, 0xf3, 0x8e, 0x41, 0x3d, 0x02, 0xfc, 0x20,
	0xde, 0xb6, 0xbc, 0x15, 0xb3, 0x46, 0xd3, 0x7f, 0xf8, 0xdc, 0xba, 0xb9,
	0xd8, 0xaf, 0xd0, 0x26, 0x4b, 0xbb, 0xdf, 0x1f, 0xa4, 0xfd, 0x35, 0xa0,
	0x7f, 0xcf, 0x64, 0x2c, 0xa6, 0xf5, 0x9c, 0x1f, 0xb4, 0x79, 0x54, 0x3a,
	0xae, 0x7b, 0xf8, 0xf3, 0xc3, 0xa1, 0xb6, 0x0c, 0x0f, 0x7c, 0x37, 0x90,
	0x8d, 0xe3, 0xf9, 0xc8, 0x56, 0xfa, 0xf7, 0xd5, 0xa9, 0xf9, 0xf1, 0xc8,
	0x82, 0x2f, 0x17, 0x86, 0x0c, 0x28, 0xe7, 0xb4, 0xf2, 0x63, 0xf0, 0xfc,
	0x89, 0x22, 0x3a, 0x6e, 0x1d, 0x7b, 0x35, 0x3f, 0xf4, 0x6b, 0x3c, 0x7e,
	0x7e, 0x9f, 0xb7, 0x23, 0xee, 0xb3, 0xfd, 0xd1, 0x6a, 0x0f, 0xad, 0x37,
	0x10, 0xf3, 0x2b, 0xa0, 0x17, 0xd9, 0x83, 0x84, 0x4c, 0x2a, 0x00, 0xbd,
	0xe8, 0x38, 0xe6, 0x86, 0xf1, 0x6d, 0x24, 0xa8, 0x47, 0x81, 0xe0, 0xa2,
	0xb4, 0x2b, 0x59, 0x3f, 0xfc, 0xaa, 0x0f, 0xde, 0x9f, 0x52, 0x41, 0x3e,
	0x02, 0x9e, 0x28, 0xf6, 0x63, 0x84, 0x1e, 0xa0, 0xef, 0x6a, 0xa0, 0xd3,
	0x8b, 0xd7, 0x47, 0x79, 0x7b, 0x3f, 0x84, 0x71, 0xc4, 0xfe, 0x6d, 0x4f,
	0xbb, 0x8a, 0xd2, 0x7b, 0xbe, 0x4c, 0xc3, 0x7a, 0xf6, 0x9b, 0xdb, 0xab,
	0x34, 0xac, 0xef, 0x62, 0x54, 0x05, 0x79, 0xdc, 0xc4, 0xe4, 0x29, 0xc7,
	0x17, 0xda, 0x66, 0x07, 0xfe, 0xaf, 0x27, 0xfe, 0xb0, 0x0f, 0xea, 0x25,
	0xd8, 0xef, 0xff, 0xce, 0xfb, 0xff, 0x63, 0x5e, 0x9f, 0x68, 0xa7, 0x63,
	0x30, 0xbb, 0x4a, 0x03, 0xfa, 0x9a, 0x88, 0x1f, 0xd4, 0xa4, 0x56, 0xbd,
	0xaf, 0x0b, 0xbe, 0x0f, 0x6c, 0x64, 0xf4, 0xcf, 0xb8, 0xb7, 0x59, 0x01,
	0xfe, 0x5d, 0x71, 0x5f, 0x3f, 0x5e, 0x23, 0x9c, 0xce, 0xdd, 0xf0, 0x3d,
	0x2d, 0x90, 0xdf, 0x1c, 0x53, 0x80, 0x6f, 0xd3, 0xef, 0x89, 0xe2, 0x75,
	0xef, 0xb6, 0xb7, 0xba, 0x80, 0xbe, 0xcc, 0x9d, 0x24, 0x0d, 0x6c, 0xc1,
	0x9e, 0x1a, 0x5b, 0x16, 0x7c, 0xb7, 0x67, 0xf1, 0xb4, 0x34, 0x78, 0xef,
	0x0e, 0x52, 0xc5, 0xa7, 0xf6, 0x20, 0xe0, 0xf7, 0xdc, 0xd5, 0x4d, 0xfb,
	0xb3, 0xb7, 0x46, 0x43, 0x3a, 0xf7, 0x0e, 0x52, 0xfe, 0xd3, 0x72, 0xee,
	0xb0, 0xc7, 0x0f, 0x7a, 0xed, 0x0e, 0xfb, 0xf8, 0xd5, 0xef, 0x87, 0xf2,
	0xbf, 0xe4, 0xfc, 0x38, 0xcc, 0xdb, 0xed, 0xe4, 0x74, 0xb8, 0xc3, 0x26,
	0x2f, 0xd7, 0x5c, 0x02, 0xe5, 0xdc, 0xe1, 0x30, 0x5e, 0x23, 0xbc, 0x9f,
	0xc4, 0xb7, 0x19, 0xe5, 0xee, 0x6e, 0x2e, 0x77, 0xbf, 0xb4, 0x87, 0x3e,
	0x07, 0x7c, 0xcf, 0x19, 0x24, 0x5e, 0x42, 0xf5, 0xf9, 0xf0, 0x87, 0xf5,
	0xb9, 0xd0, 0xae, 0xa8, 0x5f, 0x2e, 0xff, 0xd4, 0xe3, 0xff, 0xf3, 0x7a,
	0x78, 0x3f, 0x79, 0x90, 0xbc, 0x6d, 0x9f, 0x0d, 0xd7, 0xe8, 0x5a, 0x68,
	0xef, 0x6a, 0xe8, 0x87, 0x1b, 0xee, 0xfb, 0xd6, 0x2a, 0x68, 0xa7, 0x22,
	0xa8, 0x47, 0xe6, 0x45, 0x1b, 0x21, 0xc5, 0x71, 0x3b, 0x95, 0x33, 0x1c,
	0x5c, 0x7a, 0x13, 0xda, 0xc7, 0x5a, 0xd4, 0x23, 0x61, 0x07, 0x2a, 0x06,
	0x75, 0x9b, 0x92, 0x99, 0xa8, 0x67, 0x35, 0xa8, 0x07, 0x7b, 0xb9, 0x1e,
	0xd4, 0x0c, 0x46, 0x51, 0x4e, 0xa8, 0x9e, 0x1d, 0xb3, 0x51, 0x3e, 0x85,
	0x3f, 0xa0, 0x7a, 0x46, 0xe5, 0xeb, 0x70, 0xd0, 0x86, 0xe3, 0xfd, 0x44,
	0x4c, 0x47, 0x3b, 0x4c, 0x8a, 0xa3, 0x79, 0x2b, 0x5c, 0xa3, 0xf5, 0xa8,
	0xe3, 0xdc, 0x86, 0xb9, 0xc0, 0x6f, 0xa1, 0x4f, 0xa3, 0xed, 0xc7, 0xff,
	0x1b, 0xfa, 0xb5, 0x97, 0xf6, 0x23, 0x94, 0xc4, 0xae, 0x89, 0xf6, 0x84,
	0xbe, 0xc9, 0xef, 0xc7, 0xd5, 0x37, 0x4f, 0x18, 0xf5, 0xad, 0x83, 0xea,
	0x5b, 0x18, 0xf8, 0x19, 0xb4, 0xa5, 0xcd, 0x04, 0xfd, 0x6b, 0xb5, 0xa1,
	0x9e, 0x78, 0x6b, 0xda, 0xba, 0x98, 0xbe, 0x6c, 0x42, 0x7d, 0xcb, 0x59,
	0xcf, 0xe8, 0x99, 0xba, 0x26, 0x82, 0x7a, 0x30, 0x9e, 0xde, 0xed, 0xf5,
	0x79, 0xaa, 0x34, 0xa8, 0xbf, 0x89, 0xe9, 0x69, 0xc7, 0xe0, 0x3b, 0xdb,
	0x1c, 0x30, 0x1e, 0x6b, 0x08, 0xb7, 0x13, 0x17, 0xbb, 0xe0, 0x3e, 0x70,
	0x2f, 0xd3, 0x6b, 0x59, 0xcf, 0x64, 0x3d, 0xcc, 0x0c, 0xf4, 0xa1, 0x7e,
	0x16, 0xec, 0x8c, 0x11, 0xb8, 0xfa, 0x76, 0x34, 0xa2, 0x5c, 0xd3, 0x56,
	0xd2, 0x50, 0xff, 0x52, 0xe8, 0x61, 0x07, 0xe8, 0x61, 0xe9, 0xff, 0x3f,
	0x7a, 0x58, 0x23, 0xe6, 0x71, 0xca, 0x98, 0x2c, 0xca, 0xff, 0xfa, 0x18,
	0x61, 0x78, 0xc8, 0xb3, 0x0f, 0xf1, 0x50, 0xad, 0x8f, 0xe3, 0xa1, 0x82,
	0xd7, 0x6f, 0xfd, 0x2a, 0x7d, 0xff, 0xa2, 0x3d, 0x03, 0xc7, 0xf5, 0xc5,
	0xc9, 0xf4, 0x21, 0xde, 0xab, 0x11, 0x02, 0x38, 0xe3, 0xca, 0x7f, 0x59,
	0x73, 0x37, 0x2d, 0x5f, 0x9f, 0x23, 0xf0, 0xcf, 0x46, 0xd4, 0xef, 0x3a,
	0xae, 0xdf, 0xc7, 0xe0, 0x11, 0xd5, 0x9f, 0xaa, 0x7e, 0x85, 0xcc, 0xcf,
	0x86, 0x72, 0xef, 0xee, 0xae, 0xa6, 0xe5, 0x4f, 0x0e, 0x10, 0x3f, 0xbc,
	0x3a, 0xe9, 0x53, 0x11, 0x4f, 0x75, 0x0f, 0x12, 0xac, 0x4f, 0xe8, 0x67,
	0x1d, 0xef, 0x6f, 0x37, 0xbc, 0x07, 0x79, 0x1b, 0x26, 0x11, 0xd0, 0x4f,
	0x81, 0x23, 0x6a, 0xb9, 0x7e, 0x9f, 0xcc, 0x61, 0xef, 0xbb, 0x2f, 0x12,
	0xb4, 0x03, 0xa2, 0xfc, 0x49, 0xa2, 0x44, 0x54, 0x7a, 0x7f, 0x9c, 0xcb,
	0xdf, 0xf9, 0xe2, 0xdb, 0xff, 0x87, 0xbb, 0x90, 0x90, 0x3f, 0x6f, 0x8b,
	0xcd, 0x8e, 0xd2, 0xe7, 0xff, 0x6e, 0x8b, 0x7d, 0xdd, 0x46, 0x8b, 0xfe,
	0x7e, 0x99, 0xef, 0x69, 0xb8, 0x1f, 0xe0, 0xe5, 0xfe, 0x83, 0xcb, 0xe9,
	0x20, 0xc7, 0x0d, 0x27, 0xae, 0x0d, 0xdd, 0xa4, 0x50, 0xfc, 0x53, 0x49,
	0x62, 0x1b, 0xee, 0x86, 0xef, 0xbc, 0x45, 0x8f, 0xcc, 0x25, 0x50, 0xdf,
	0x47, 0x33, 0x08, 0x65, 0xed, 0x57, 0xaf, 0xfe, 0xcb, 0x7b, 0xa4, 0x10,
	0x28, 0x69, 0xd3, 0x83, 0xae, 0xb8, 0x5e, 0x89, 0xfa, 0x44, 0x3d, 0x2f,
	0x78, 0x43, 0x4d, 0x0a, 0x1d, 0x8f, 0x81, 0xc8, 0xbb, 0x6e, 0x18, 0xbf,
	0x0f, 0x0e, 0x7e, 0x34, 0x1b, 0xae, 0xc4, 0x98, 0x84, 0x38, 0x6b, 0x3c,
	0x3c, 0x16, 0x10, 0xe3, 0x15, 0xeb, 0xdb, 0x01, 0xb8, 0x83, 0xd4, 0x50,
	0xb9, 0x98, 0x1f, 0x97, 0x8b, 0xa9, 0xb1, 0xbe, 0x63, 0x88, 0x63, 0x87,
	0x18, 0xfe, 0x22, 0x75, 0x9b, 0x71, 0x1c, 0x2a, 0x3d, 0x8c, 0x4f, 0x5d,
	0x17, 0xce, 0xe6, 0xc1, 0x77, 0x47, 0x38, 0x5d, 0x9d, 0xe7, 0xfa, 0xf2,
	0xd0, 0x1e, 0xd6, 0x59, 0xeb, 0xe9, 0xb4, 0xf7, 0xaf, 0x09, 0xb2, 0xfa,
	0xf1, 0xfb, 0x80, 0x87, 0x8d, 0xa3, 0xa0, 0xa7, 0x5d, 0xd8, 0x07, 0x45,
	0xe0, 0x25, 0x36, 0x5e, 0x01, 0xfe, 0x7d, 0xb9, 0xd6, 0x37, 0x69, 0x0e,
	0xe5, 0x7f, 0xf9, 0x09, 0xd5, 0xbf, 0x8d, 0x7e, 0x57, 0x3e, 0xdc, 0x5f,
	0x43, 0x92, 0xd8, 0x9d, 0x88, 0x92, 0x85, 0xfd, 0xaa, 0x18, 0xb0, 0xca,
	0x67, 0xe7, 0x85, 0xe3, 0x2a, 0xf0, 0x85, 0xd2, 0xab, 0x02, 0xbd, 0x95,
	0xb1, 0x3e, 0x95, 0xd9, 0x6d, 0x26, 0x57, 0x01, 0x2e, 0x57, 0x95, 0xb1,
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	0xa6, 0xc8, 0x0b, 0xf4, 0xd7, 0x73, 0x3d, 0xa2, 0xc4, 0xfd, 0x27, 0xe7,
	0x09, 0xec, 0x6f, 0x96, 0x27, 0xc4, 0xfb, 0x2f, 0xbf, 0x0d, 0x7c, 0x0a,
	0x7e, 0xeb, 0xf0, 0x50, 0x0a, 0xb3, 0xe7, 0x5f, 0x1e, 0x4b, 0x39, 0x80,
	0xf8, 0xbb, 0xba, 0x7e, 0xf3, 0xcc, 0x74, 0xa8, 0x57, 0x9f, 0x4b, 0x21,
	0x25, 0xdc, 0x1e, 0xa9, 0xf2, 0x0b, 0xcd, 0xf5, 0x3a, 0xc9, 0x9c, 0xa1,
	0x95, 0x4f, 0x90, 0x8a, 0x74, 0xc0, 0xb7, 0x93, 0xf2, 0x06, 0xf5, 0x3a,
	0xa6, 0xdf, 0x6f, 0xe6, 0x0d, 0xea, 0x85, 0x0b, 0xac, 0x2e, 0xe3, 0xf4,
	0x0d, 0x13, 0x7f, 0x48, 0x2f, 0xa1, 0x48, 0xff, 0x50, 0x10, 0xfd, 0x8c,
	0xc3, 0xed, 0xd4, 0x3e, 0x4c, 0x26, 0xe7, 0x11, 0x60, 0xe2, 0x22, 0xb2,
	0x08, 0x4e, 0x51, 0x7f, 0x96, 0xe5, 0x95, 0xed, 0x9d, 0xd4, 0x2e, 0x8a,
	0xdf, 0x9e, 0x5f, 0xc8, 0x93, 0xe3, 0x0c, 0x1d, 0xe1, 0x4c, 0x3d, 0xf2,
	0x79, 0xcb, 0x1b, 0x84, 0xe0, 0xbb, 0xad, 0xc9, 0x79, 0x86, 0x7a, 0x86,
	0xf7, 0xab, 0xc9, 0x93, 0xc1, 0x5a, 0x7c, 0x8f, 0x55, 0xae, 0xb3, 0xa2,
	0x3d, 0x4b, 0x8e, 0x17, 0x20, 0x9f, 0xa0, 0xfd, 0x4f, 0x8e, 0x13, 0xce,
	0xab, 0xe3, 0xf7, 0x38, 0x4f, 0xc6, 0x2b, 0x61, 0x19, 0xdf, 0x57, 0xcb,
	0xb8, 0x44, 0x19, 0x97, 0x7c, 0xff, 0xbd, 0x75, 0xea, 0x7c, 0x44, 0x72,
	0x7b, 0x97, 0xdc, 0xde, 0x5b, 0x5f, 0xdd, 0x8f, 0xf7, 0x17, 0x58, 0xa1,
	0x23, 0x68, 0x07, 0x7a, 0xeb, 0x5d, 0xa6, 0xf2, 0x84, 0xf9, 0x5c, 0x75,
	0xfc, 0x1d, 0xcd, 0x6e, 0xcc, 0x5b, 0xe4, 0x24, 0xe6, 0x2d, 0x78, 0x7e,
	0x22, 0x39, 0x5f, 0xa1, 0xe8, 0x29, 0xc7, 0xf0, 0xd7, 0x1e, 0xbc, 0xff,
	0x3d, 0x11, 0x1e, 0x4f, 0xf2, 0x17, 0xf0, 0xf8, 0xa6, 0xe3, 0xb8, 0xf3,
	0x34, 0xca, 0x7d, 0x7c, 0x9f, 0xdc, 0xde, 0xee, 0x81, 0x3b, 0x8e, 0x31,
	0x1c, 0x65, 0xcf, 0x24, 0xfc, 0x5c, 0xc4, 0xc4, 0xe3, 0x5e, 0x2c, 0xce,
	0x50, 0xbd, 0xe2, 0x8b, 0x13, 0xa9, 0x48, 0x3f, 0x2f, 0xd8, 0x2b, 0xd4,
	0x4b, 0x67, 0xca, 0x77, 0xa6, 0xa1, 0x3e, 0x59, 0x21, 0xd4, 0x50, 0x91,
	0xc5, 0xbb, 0x6f, 0xc6, 0xbf, 0x31, 0x3e, 0xb5, 0xfa, 0x9d, 0xd6, 0x65,
	0x04, 0xed, 0x7f, 0xe3, 0xfc, 0x51, 0xa4, 0x7b, 0xe3, 0x7a, 0x03, 0x7b,
	0x87, 0xa4, 0xd8, 0xab, 0xd5, 0xef, 0x34, 0x79, 0x78, 0xfb, 0xfe, 0x1d,
	0x16, 0x6c, 0x9f, 0x4d, 0xed, 0x66, 0x11, 0xbf, 0xd7, 0xbb, 0xf0, 0xfb,
	0xf2, 0x57, 0xa2, 0x18, 0xe9, 0x23, 0x2b, 0x91, 0xda, 0x20, 0x37, 0xb1,
	0x33, 0x17, 0x05, 0x94, 0x97, 0xdc, 0x19, 0xbe, 0x9f, 0xa1, 0x7f, 0xe4,
	0x68, 0x90, 0xe3, 0xe0, 0xeb, 0xb9, 0x7d, 0x6d, 0x8c, 0x34, 0x18, 0x48,
	0xda, 0x64, 0x7b, 0x77, 0xb2, 0xf8, 0x4b, 0xe6, 0x47, 0x5f, 0x8d, 0x38,
	0x58, 0x7c, 0x3b, 0x1b, 0xf3, 0xaf, 0xb6, 0xb8, 0xbd, 0x70, 0x1c, 0x03,
	0x3b, 0x94, 0xfe, 0x97, 0xb3, 0x43, 0xbd, 0x75, 0x56, 0x46, 0xcf, 0x79,
	0x60, 0x87, 0x70, 0x3f, 0x59, 0x0d, 0x3c, 0x4f, 0x98, 0x7c, 0xff, 0x2e,
	0xf9, 0xfe, 0xa7, 0xb2, 0x2b, 0x53, 0xe9, 0x51, 0xb4, 0x23, 0xba, 0x45,
	0x5c, 0x6e, 0x68, 0x41, 0xdc, 0xfe, 0x8a, 0xe8, 0x5f, 0xdf, 0x11, 0xb7,
	0xc3, 0xd6, 0x30, 0xd4, 0xf3, 0xbf, 0x21, 0xee, 0x2d, 0xe3, 0xac, 0xcc,
	0x29, 0x70, 0xd8, 0x2f, 0x65, 0x7e, 0x9f, 0xf2, 0xfd, 0x46, 0xf8, 0xfb,
	0x89, 0x83, 0x1f, 0xaa, 0xfb, 0x81, 0xc4, 0xc1, 0x65, 0x3f, 0x47, 0x89,
	0x87, 0x2b, 0x7e, 0x51, 0x9a, 0x8c, 0x63, 0x95, 0x32, 0xdd, 0xc3, 0xe9,
	0xfe, 0xbf, 0x7e, 0xbf, 0x8c, 0xc6, 0x51, 0xf3, 0xfd, 0x72, 0x96, 0xf6,
	0xfb, 0xe5, 0x0d, 0x03, 0x14, 0x71, 0x86, 0xf2, 0x7e, 0x79, 0xc4, 0x48,
	0x9c, 0x87, 0x72, 0xf0, 0xdd, 0x1e, 0x25, 0xdb, 0x51, 0xbe, 0x43, 0x0d,
	0x0c, 0xe7, 0x8c, 0x3c, 0xfb, 0xfb, 0xbe, 0x97, 0xe1, 0x7b, 0xc7, 0x20,
	0xb5, 0xa2, 0xf9, 0x69, 0x1f, 0x18, 0x65, 0x76, 0xba, 0x1d, 0x70, 0x0d,
	0xc3, 0x43, 0x91, 0x4f, 0x79, 0x9c, 0x6a, 0x80, 0xbf, 0x37, 0x6d, 0x0f,
	0x53, 0x49, 0x2b, 0x0e, 0xba, 0x40, 0xb6, 0xcf, 0xb5, 0x12, 0x61, 0x7a,
	0xa3, 0x5d, 0x7e, 0xd7, 0xe7, 0x19, 0xe4, 0x72, 0x1d, 0x8f, 0x13, 0xfd,
	0x5c, 0x48, 0x8c, 0x13, 0xf9, 0xc5, 0x58, 0xae, 0xf2, 0x5e, 0x30, 0xc4,
	0xed, 0x93, 0xe6, 0xbb, 0xbe, 0x0e, 0x32, 0xce, 0xde, 0x03, 0x76, 0xb4,
	0x52, 0x7b, 0x14, 0xbe, 0x27, 0xc7, 0x8d, 0x92, 0xe3, 0x45, 0x4f, 0xca,
	0xef, 0x00, 0xa7, 0x8c, 0x1b, 0x49, 0xdf, 0xed, 0xbd, 0xdf, 0x9f, 0xea,
	0xd2, 0x73, 0x3e, 0x06, 0x16, 0x50, 0xe2, 0xcf, 0x05, 0xb5, 0x3c, 0x4e,
	0xd4, 0xe4, 0xa3, 0x14, 0xe7, 0x37, 0xe9, 0xbc, 0x6d, 0xec, 0xdd, 0xef,
	0x71, 0x6a, 0xd5, 0x7a, 0x3f, 0x9a, 0xea, 0xe1, 0x76, 0x67, 0xb9, 0x1c,
	0xbf, 0x7d, 0xd1, 0xc8, 0xf9, 0xe1, 0xc5, 0x3b, 0x29, 0x7b, 0x4f, 0xbf,
	0x9c, 0xf0, 0x38, 0xed, 0x8b, 0xc7, 0xf9, 0xbb, 0xfa, 0x17, 0xab, 0xf9,
	0xbb, 0x7a, 0x25, 0x5e, 0xab, 0xbc, 0x97, 0xbf, 0x3d, 0x1e, 0xaf, 0xdd,
	0x83, 0xf1, 0x5a, 0xe5, 0x9d, 0xbd, 0xf2, 0x6e, 0x9e, 0x90, 0x10, 0xbb,
	0x87, 0x86, 0xbd, 0x96, 0x28, 0xe2, 0x8d, 0xc7, 0x0c, 0x03, 0x05, 0x28,
	0x8f, 0xca, 0x7b, 0xa3, 0xa3, 0x75, 0xdc, 0xde, 0x59, 0x52, 0x48, 0xa7,
	0x96, 0x7c, 0x7e, 0x55, 0xe7, 0x3c, 0x5a, 0xc7, 0xfa, 0xe9, 0xa6, 0x88,
	0x77, 0xfa, 0xf2, 0x3d, 0x1a, 0x71, 0x20, 0x9f, 0xec, 0xb7, 0x15, 0x7b,
	0xa6, 0xc4, 0xe9, 0xa2, 0x27, 0x57, 0x85, 0xd3, 0x59, 0x3d, 0x19, 0xa7,
	0xff, 0xa5, 0xe2, 0xb5, 0x47, 0xea, 0xc8, 0x54, 0xfb, 0xbf, 0x5f, 0x1b,
	0xaf, 0x4d, 0xea, 0x77, 0xf1, 0x16, 0xfb, 0x9d, 0xab, 0xd3, 0xa0, 0xc7,
	0x4e, 0x39, 0x7e, 0x92, 0x4c, 0xdf, 0x1e, 0x8f, 0xa2, 0x87, 0xa7, 0x5b,
	0x19, 0x3f, 0xdd, 0xdc, 0x3f, 0xe1, 0xf9, 0x5c, 0x39, 0xee, 0x35, 0x22,
	0xdb, 0xb9, 0x20, 0x15, 0x7f, 0x77, 0x17, 0xcb, 0x7f, 0x19, 0x58, 0xfe,
	0x4b, 0xd1, 0x33, 0xc1, 0x74, 0x3e, 0xff, 0xdd, 0xb2, 0x9e, 0x51, 0xca,
	0x7b, 0xe5, 0x32, 0x68, 0xd0, 0x8e, 0xd3, 0x74, 0xc9, 0xed, 0x73, 0x0a,
	0xa5, 0x95, 0x78, 0x8f, 0x95, 0x2f, 0xa9, 0xe3, 0x66, 0x73, 0x07, 0xd4,
	0x71, 0xb3, 0x79, 0xe1, 0x2c, 0x55, 0x7d, 0x7e, 0xf4, 0x36, 0x55, 0x7f,
	0xc7, 0xe9, 0x52, 0x55, 0x7b, 0x4d, 0x6c, 0x8e, 0xaa, 0xfd, 0x8e, 0x73,
	0xd5, 0xaa, 0xfa, 0xe2, 0xb1, 0x3b, 0x55, 0xfd, 0xef, 0xfa, 0xc4, 0xa5,
	0xaa, 0xff, 0x68, 0x5c, 0x1d, 0x37, 0x5b, 0x72, 0x4d, 0x1d, 0x37, 0x53,
	0xf8, 0xdb, 0x09, 0x1c, 0x91, 0x38, 0xce, 0x6d, 0xfa, 0x1b, 0x55, 0xbf,
	0xa2, 0x56, 0xf5, 0xb9, 0x8a, 0x3b, 0xd5, 0xe7, 0x9a, 0xd9, 0xad, 0x3e,
	0x97, 0x32, 0x6f, 0x49, 0x40, 0x7d, 0xbe, 0xb2, 0xa0, 0xfa, 0x7c, 0x59,
	0x18, 0xd7, 0xb7, 0xfd, 0xf9, 0x71, 0xfd, 0xf1, 0x5a, 0x51, 0x8e, 0xeb,
	0x97, 0x99, 0x71, 0xdc, 0xee, 0xfa, 0x72, 0x33, 0xe2, 0x18, 0x3d, 0xe6,
	0x31, 0xe1, 0xfb, 0xff, 0x00, 0x1d, 0xad, 0xb3, 0x67, 0x00, 0x34, 0x00,
	0x00, 0x00, 0x00, 0x00
};

static const u8 csem_int_table_data_e1h[] = {
	0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xe3, 0x14,
	0x60, 0x60, 0xf8, 0x51, 0x0f, 0xc1, 0xd3, 0xf9, 0x19, 0x18, 0x36, 0xf3,
	0x23, 0xf8, 0xf4, 0xc0, 0xc7, 0x98, 0x19, 0x18, 0x8e, 0x83, 0x30, 0x23,
	0x03, 0xc3, 0x3e, 0x20, 0xde, 0x0a, 0xc4, 0x6b, 0x80, 0xf8, 0x3d, 0x03,
	0x03, 0xc3, 0x52, 0x20, 0x3d, 0x07, 0x88, 0x27, 0x03, 0x71, 0x17, 0x10,
	0xbf, 0x04, 0x8a, 0xd5, 0xb1, 0x62, 0x37, 0x87, 0x85, 0x8d, 0x81, 0x81,
	0x0d, 0x88, 0x4f, 0x02, 0xcd, 0x3a, 0xc5, 0x4c, 0xbc, 0xfd, 0x8a, 0x7c,
	0x08, 0xf6, 0x21, 0x5e, 0x06, 0x86, 0xb5, 0x40, 0x7c, 0x94, 0x97, 0xbe,
	0x61, 0x30, 0xd8, 0xf0, 0x0c, 0x41, 0xfa, 0xd9, 0xf5, 0x0c, 0x6a, 0xd7,
	0x6e, 0xd1, 0x81, 0xf7, 0x37, 0x08, 0xb3, 0x8a, 0x33, 0x30, 0x30, 0x4a,
	0x20, 0xf8, 0xfd, 0x12, 0xa8, 0xf2, 0x6c, 0xe2, 0x08, 0x76, 0x96, 0x0c,
	0x65, 0x76, 0x95, 0x01, 0xf5, 0x03, 0x00, 0x29, 0x51, 0x28, 0x15, 0x80,
	0x03, 0x00, 0x00, 0x00
};

static const u8 csem_pram_data_e1h[] = {
	0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d,
	0x09, 0x78, 0x54, 0x45, 0xb6, 0x70, 0xdd, 0xee, 0x7b, 0x7b, 0x49, 0xba,
	0x3b, 0x9d, 0x90, 0x95, 0x25, 0x74, 0x80, 0x20, 0x2a, 0x4b, 0xcb, 0x12,
	0x01, 0x11, 0x3b, 0x21, 0x89, 0x01, 0x03, 0x06, 0x44, 0x09, 0x28, 0xd2,
	0x6c, 0x21, 0x84, 0x24, 0x9d, 0x01, 0x66, 0x1e, 0x3e, 0xfd, 0xff, 0x6e,
	0x08, 0x42, 0xc4, 0xd1, 0x89, 0x8a, 0x1a, 0xfc, 0x19, 0x5f, 0x83, 0xe0,
	0x04, 0x07, 0x9d, 0xe0, 0xa0, 0x13, 0x9d, 0xc0, 0x34, 0x8b, 0x88, 0x33,
	0xe8, 0x04, 0xc7, 0x05, 0x97, 0x79, 0x5f, 0x40, 0x1e, 0x20, 0x42, 0x12,
	0xa3, 0x38, 0xe8, 0xf3, 0xc9, 0xab, 0x73, 0xaa, 0x6e, 0xba, 0xeb, 0x76,
	0x37, 0x69, 0xb7, 0xff, 0xf9, 0x7f, 0xff, 0x84, 0x0f, 0x8a, 0xba, 0x55,
	0xf7, 0xd4, 0xa9, 0xb3, 0xd5, 0xa9, 0x53, 0x75, 0x4f, 0x14, 0x9d, 0x95,
	0x24, 0xdd, 0x40, 0xc8, 0x25, 0xf8, 0xa1, 0xe5, 0xab, 0x0a, 0x21, 0x24,
	0x25, 0x58, 0x76, 0x48, 0x9d, 0xc3, 0xe5, 0x81, 0xc1, 0xf6, 0xb5, 0x5e,
	0x17, 0x71, 0x19, 0x09, 0x79, 0xc0, 0x6b, 0xc2, 0x72, 0xbd, 0x37, 0x9d,
	0xb8, 0xae, 0xa0, 0xcf, 0x47, 0xeb, 0x8a, 0xfc, 0x16, 0x42, 0xee, 0xf7,
	0xda, 0xf1, 0xf9, 0xe3, 0xde, 0x12, 0x2c, 0x1f, 0xf5, 0x96, 0x62, 0xf9,
	0x88, 0xd7, 0x8d, 0xfd, 0x1e, 0xf2, 0x96, 0x63, 0xf9, 0x2b, 0x6f, 0x0d,
	0x96, 0xf7, 0x7a, 0x8b, 0xb0, 0xbd, 0xce, 0xbb, 0x0a, 0xeb, 0x37, 0x2a,
	0x0b, 0xd2, 0x60, 0x5c, 0x42, 0x5c, 0xa6, 0xac, 0x64, 0x42, 0x3c, 0x2f,
	0x0f, 0x1c, 0xb9, 0x81, 0xd6, 0xd6, 0x67, 0x8e, 0x4f, 0x90, 0x47, 0xd3,
	0xfa, 0x5f, 0xf5, 0x44, 0x9f, 0x45, 0xdf, 0x1b, 0x2d, 0x17, 0xf9, 0x87,
	0xd2, 0x06, 0xb9, 0xa4, 0x28, 0x6b, 0x74, 0xb0, 0x9f, 0x8a, 0xe7, 0x8d,
	0x4a, 0x5e, 0x5f, 0x80, 0xf3, 0xf8, 0x58, 0x1d, 0xeb, 0x67, 0xaa, 0x79,
	0x2d, 0x3b, 0x72, 0xbf, 0x2c, 0x32, 0x86, 0xe2, 0x39, 0x56, 0x46, 0xfc,
	0x89, 0xa5, 0x64, 0x72, 0x76, 0x72, 0xc4, 0x7e, 0x83, 0x01, 0xde, 0x23,
	0x43, 0xd9, 0x3c, 0x89, 0xdd, 0xf9, 0xda, 0xa0, 0xc8, 0xf0, 0xae, 0x06,
	0x78, 0x0f, 0x0d, 0xe5, 0xf8, 0x25, 0xdb, 0x27, 0x0f, 0x8a, 0x0c, 0xcf,
	0x09, 0xfd, 0x7e, 0xe5, 0xe4, 0xf0, 0xd2, 0x3b, 0x0f, 0x0f, 0x8c, 0xdc,
	0x6f, 0x0c, 0xf4, 0xab, 0x73, 0x72, 0x78, 0x7d, 0x7d, 0xa6, 0x01, 0x91,
	0xc7, 0x1d, 0x0f, 0xfd, 0x62, 0xe0, 0x13, 0xc5, 0x89, 0x10, 0x5f, 0x8b,
	0xd1, 0x9f, 0x9d, 0xf5, 0xfd, 0xf9, 0x45, 0x5c, 0xf4, 0x2f, 0xc5, 0xa7,
	0x63, 0xaf, 0x79, 0xeb, 0x06, 0x09, 0xf9, 0x37, 0x0d, 0xe8, 0xb4, 0xd6,
	0xbe, 0xfc, 0xcc, 0x16, 0x3a, 0x4e, 0x7b, 0xcb, 0x30, 0xa7, 0xde, 0x41,
	0xc8, 0x67, 0x2e, 0x67, 0x82, 0xdd, 0x12, 0x13, 0xdf, 0x6e, 0x81, 0x79,
	0xc4, 0xc0, 0xb7, 0x52, 0x18, 0x27, 0x06, 0xbe, 0xcd, 0x8d, 0x91, 0x6f,
	0x0b, 0xa0, 0x5f, 0x0c, 0x7c, 0x5b, 0x02, 0xfd, 0x62, 0xe0, 0x5b, 0x65,
	0x8c, 0x7c, 0xfb, 0xd9, 0x4f, 0x84, 0x6f, 0xf7, 0x02, 0x1e, 0xdf, 0x83,
	0x6f, 0x1b, 0x62, 0xd4, 0xb7, 0x5f, 0xc5, 0xc8, 0xb7, 0x8d, 0x31, 0xf2,
	0x6d, 0x53, 0x8c, 0xfa, 0xf6, 0x64, 0x8c, 0x7c, 0x7b, 0x2a, 0x94, 0x6f,
	0xea, 0x73, 0xb5, 0xdc, 0x41, 0x24, 0xb4, 0x8b, 0x37, 0x2a, 0x25, 0x3b,
	0xa0, 0x9f, 0x27, 0xb3, 0xcd, 0x36, 0x20, 0xeb, 0x27, 0xc1, 0xbf, 0x3d,
	0xdf, 0x53, 0xef, 0xf6, 0xc7, 0xc8, 0xbf, 0x57, 0x63, 0xe4, 0xdf, 0x11,
	0xa0, 0x4f, 0x0c, 0xfc, 0x3b, 0x1a, 0x23, 0xff, 0xde, 0x89, 0x91, 0x7f,
	0x1f, 0xc4, 0xa8, 0x77, 0x6d, 0xb8, 0xce, 0x58, 0xe4, 0xaf, 0xda, 0x86,
	0x10, 0xfc, 0xb9, 0x34, 0x00, 0xfe, 0xb5, 0xd8, 0x4f, 0x5d, 0xcd, 0xeb,
	0x7a, 0xc0, 0x3b, 0x89, 0x90, 0x8c, 0x70, 0x39, 0x50, 0x4b, 0xca, 0x51,
	0x94, 0x07, 0x99, 0xb8, 0xdb, 0xd9, 0xba, 0x55, 0xf0, 0xcd, 0xa5, 0x1c,
	0x42, 0x56, 0x98, 0xe8, 0x7f, 0xe9, 0xfb, 0xbe, 0x3c, 0x12, 0xd0, 0xd3,
	0xf1, 0x7d, 0x36, 0xe2, 0xaf, 0x95, 0x84, 0xfe, 0x9f, 0x03, 0x9e, 0x84,
	0xe4, 0x7f, 0x73, 0x29, 0x55, 0xe8, 0xef, 0xd3, 0x45, 0xec, 0x4f, 0x74,
	0xd0, 0xfe, 0x30, 0xc8, 0x15, 0xe5, 0xff, 0x66, 0xef, 0x10, 0x2c, 0xeb,
	0xb9, 0x1c, 0x6d, 0x2e, 0xd2, 0xa1, 0x3c, 0xf8, 0x92, 0x0d, 0x28, 0x5f,
	0x4f, 0x78, 0x9d, 0xd8, 0xde, 0xe0, 0x1d, 0x8b, 0xe5, 0x63, 0x5c, 0x2e,
	0x37, 0x72, 0x39, 0x7a, 0x00, 0xe4, 0xee, 0x0a, 0x90, 0xc3, 0x52, 0x2e,
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	0x10, 0xea, 0xe3, 0x5d, 0xa7, 0x62, 0x07, 0xe3, 0x78, 0x7b, 0x79, 0xdb,
	0xcd, 0xaf, 0x4d, 0xfc, 0x7b, 0xf6, 0x10, 0x1f, 0x0d, 0x99, 0x17, 0x13,
	0x0e, 0xdf, 0xc3, 0x04, 0xdf, 0xa5, 0x7a, 0x3e, 0x0e, 0x63, 0x1d, 0x43,
	0xe6, 0x8c, 0x0c, 0xbf, 0x5f, 0xdb, 0x17, 0x1f, 0x5b, 0x33, 0x88, 0x8f,
	0x3b, 0x22, 0xf8, 0x58, 0x5b, 0x6f, 0x3d, 0x7e, 0xcf, 0x07, 0xe3, 0x80,
	0x16, 0x33, 0x7d, 0xcf, 0x07, 0xf3, 0xd7, 0x8e, 0x30, 0x39, 0x19, 0x9a,
	0xc1, 0xf5, 0xcf, 0x58, 0xf1, 0xfd, 0x9e, 0xf1, 0xcc, 0x47, 0xdf, 0x39,
	0x1c, 0x2b, 0xbe, 0xe3, 0x33, 0x5e, 0x61, 0x01, 0x25, 0x1e, 0xf7, 0xcd,
	0x02, 0x32, 0xdf, 0xf7, 0xe5, 0xe7, 0x2d, 0xc6, 0x08, 0x7e, 0x1e, 0xab,
	0x04, 0x5a, 0xb1, 0x8e, 0x62, 0xbc, 0xd8, 0xe7, 0x99, 0xc0, 0xda, 0xe9,
	0xb9, 0x29, 0x2c, 0x48, 0xad, 0x9b, 0xd9, 0xe9, 0x1c, 0x45, 0x11, 0x73,
	0x51, 0x3b, 0xce, 0x12, 0x98, 0x8e, 0xee, 0x54, 0x4e, 0x7d, 0x3d, 0xd5,
	0x25, 0x06, 0x92, 0x15, 0xc7, 0x79, 0x8b, 0x38, 0xaf, 0xd1, 0x0b, 0xdd,
	0x42, 0xeb, 0x57, 0xe8, 0xbb, 0x3d, 0xc4, 0x9f, 0x32, 0x9e, 0xd7, 0xe9,
	0xfd, 0xbb, 0x2f, 0xb3, 0x33, 0xb8, 0xdc, 0xd3, 0xc7, 0x45, 0x90, 0xbe,
	0x97, 0x18, 0xe5, 0xb9, 0xf0, 0x7b, 0x6d, 0x38, 0xc9, 0x44, 0x85, 0x95,
	0x63, 0x7d, 0xd3, 0x64, 0x85, 0x59, 0xa2, 0x01, 0xde, 0x5d, 0x87, 0x0c,
	0x24, 0xcf, 0x2d, 0x1d, 0xaa, 0x1f, 0xeb, 0x53, 0x5d, 0x09, 0xe2, 0xbd,
	0xcf, 0x19, 0xd5, 0xe1, 0x8e, 0x75, 0x73, 0x79, 0x45, 0x93, 0x83, 0xf5,
	0x18, 0xda, 0x7a, 0xf5, 0x78, 0x98, 0x00, 0xe3, 0x61, 0x9e, 0x6d, 0xac,
	0x02, 0x91, 0x28, 0xe1, 0x31, 0x40, 0xf3, 0xdd, 0xc8, 0xf8, 0x39, 0x92,
	0x42, 0xa6, 0x52, 0xfd, 0x73, 0x69, 0x46, 0xa6, 0xd0, 0xf7, 0x41, 0x8a,
	0xa3, 0x8a, 0x21, 0x8e, 0x42, 0x7d, 0x6f, 0xb0, 0xf8, 0x08, 0x1f, 0xd3,
	0x33, 0x54, 0xba, 0x8f, 0xfb, 0x25, 0xb1, 0x30, 0xce, 0x84, 0x8d, 0x12,
	0x7b, 0x0f, 0xf7, 0x3f, 0xb2, 0xf8, 0x7a, 0xb5, 0xf1, 0x27, 0x00, 0x23,
	0xe0, 0xf9, 0xc2, 0xe9, 0x19, 0xdc, 0x9e, 0x61, 0x4a, 0xf5, 0xbd, 0x78,
	0xbe, 0x8f, 0x12, 0x4b, 0x05, 0xcd, 0x25, 0x76, 0xfe, 0x9d, 0xa3, 0x64,
	0xfa, 0xce, 0xd1, 0xf5, 0xe2, 0xb5, 0x2b, 0x99, 0x7f, 0xef, 0x32, 0xf6,
	0xce, 0x60, 0xe7, 0xcf, 0x0a, 0x42, 0xfb, 0x49, 0x2e, 0xfc, 0xee, 0x51,
	0x6c, 0xe8, 0x3b, 0x9b, 0x2e, 0xed, 0xdf, 0x83, 0x08, 0x44, 0xfe, 0x7b,
	0x10, 0x77, 0x64, 0x2c, 0xf9, 0x11, 0xf2, 0xa3, 0x56, 0xaf, 0xc7, 0xbc,
	0xfc, 0xdf, 0x7d, 0xd0, 0xd7, 0xeb, 0x85, 0xd5, 0xe7, 0xb1, 0x0b, 0x61,
	0xe7, 0xb0, 0xb5, 0xba, 0x92, 0x6d, 0xfe, 0xd9, 0x2a, 0x9e, 0xf3, 0x5b,
	0x90, 0x68, 0xa1, 0x73, 0xbf, 0x79, 0x96, 0xfe, 0xf9, 0x68, 0xc7, 0x06,
	0x3a, 0xbd, 0x34, 0xfe, 0xfb, 0xd2, 0xf6, 0xc1, 0x34, 0x98, 0xe2, 0x1f,
	0xed, 0x89, 0x09, 0xf1, 0xbb, 0x95, 0xb9, 0xc7, 0x21, 0xbe, 0x43, 0x75,
	0x83, 0xfc, 0x3b, 0x50, 0xdd, 0xe7, 0xae, 0x92, 0x19, 0x9d, 0x57, 0xb4,
	0x9a, 0x79, 0x7d, 0xe5, 0x63, 0x20, 0x1f, 0xf8, 0x1d, 0x26, 0x90, 0x2e,
	0x15, 0xeb, 0x68, 0xd8, 0x83, 0xc5, 0x54, 0x8f, 0xb9, 0xde, 0x61, 0x71,
	0xe1, 0x79, 0x09, 0x33, 0xc2, 0x6d, 0x0d, 0xc1, 0x5d, 0x6b, 0x11, 0xdf,
	0x05, 0xb5, 0xf0, 0x7d, 0x71, 0x7d, 0x3d, 0x68, 0xad, 0xcd, 0x40, 0xdf,
	0x1d, 0xad, 0x65, 0xd1, 0x74, 0x0e, 0x3d, 0x29, 0xda, 0xbb, 0x2e, 0x03,
	0xe0, 0xba, 0x2f, 0xa6, 0x88, 0xce, 0x77, 0x67, 0xef, 0x9c, 0xe4, 0x44,
	0xbf, 0x31, 0x7c, 0xfd, 0x93, 0xb4, 0xf5, 0x1b, 0x7a, 0xd6, 0x47, 0xc2,
	0x7a, 0x1f, 0xc9, 0xe8, 0xa5, 0x1e, 0x51, 0x5b, 0xa7, 0xf6, 0xef, 0x76,
	0xd8, 0x05, 0xfe, 0xb4, 0x75, 0xdb, 0xb5, 0x73, 0x4a, 0x6e, 0x25, 0xe2,
	0x9c, 0x92, 0x86, 0x8f, 0xc7, 0xa2, 0xf9, 0xba, 0x8d, 0xb8, 0xf3, 0x9f,
	0x45, 0xef, 0xaa, 0xa8, 0x37, 0xf4, 0xeb, 0xfd, 0xff, 0xdc, 0x29, 0xbc,
	0x16, 0xa0, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00
};

static const u8 xsem_int_table_data_e1h[] = {
	0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xb3, 0xd3,
	0x66, 0x60, 0xf8, 0x51, 0x8f, 0xc0, 0xc1, 0x9a, 0x0c, 0x0c, 0x5d, 0xd2,
	0xa8, 0x62, 0xb4, 0xc4, 0x1d, 0x12, 0x0c, 0x0c, 0x97, 0x80, 0xf8, 0x0b,
	0x10, 0x67, 0x02, 0xed, 0xf5, 0x92, 0x64, 0x60, 0xf0, 0x06, 0xe2, 0x6d,
	0x40, 0xbc, 0x1d, 0x88, 0xc5, 0xa5, 0x18, 0x18, 0x02, 0x80, 0x38, 0x10,
	0x88, 0xfb, 0x80, 0xfc, 0x7e, 0x20, 0x4e, 0x07, 0xe2, 0x24, 0xa8, 0x1b,
	0xb3, 0x05, 0x19, 0x18, 0x72, 0x81, 0x38, 0x1f, 0x88, 0x0b, 0x81, 0x58,
	0x48, 0x80, 0x81, 0x41, 0x58, 0x80, 0x78, 0xfb, 0x8b, 0x15, 0x19, 0x18,
	0x5e, 0xab, 0x22, 0xf8, 0x5a, 0x6a, 0x0c, 0x0c, 0xc9, 0x1a, 0xf4, 0xf3,
	0xff, 0x60, 0xc3, 0x81, 0xb6, 0xf4, 0xb5, 0xef, 0x16, 0xd0, 0xbe, 0xe5,
	0x6e, 0x08, 0xbe, 0x04, 0x90, 0xbd, 0xc2, 0x0d, 0x55, 0xcd, 0x4a, 0x37,
	0xfc, 0x66, 0xac, 0x42, 0x93, 0x5f, 0x8d, 0xc6, 0x5f, 0x83, 0x47, 0x7f,
	0x81, 0x0d, 0x2a, 0x7f, 0xab, 0x29, 0x2a, 0x7f, 0xaf, 0x39, 0x03, 0xc3,
	0x07, 0x24, 0x35, 0xdb, 0x4c, 0xf1, 0xbb, 0x05, 0x1d, 0x2b, 0x00, 0xfd,
	0xa7, 0x88, 0x27, 0x4c, 0x97, 0x30, 0xa2, 0xf2, 0x27, 0x32, 0xa1, 0xf2,
	0xf9, 0xa1, 0x7c, 0x00, 0xbe, 0x1e, 0x31, 0x3c, 0xa8, 0x03, 0x00, 0x00,
	0x00, 0x00, 0x00, 0x00
};

static const u8 xsem_pram_data_e1h[] = {
	0x1f, 0x8b, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0b, 0xed, 0x7d,
	0x0d, 0x78, 0x54, 0xd5, 0x99, 0xf0, 0xb9, 0x3f, 0x73, 0x67, 0x26, 0x99,
	0x99, 0xdc, 0x24, 0x43, 0x32, 0x60, 0x12, 0x6e, 0x7e, 0xd0, 0xa0, 0x01,
	0x87, 0x98, 0x60, 0xb0, 0x58, 0x6e, 0x20, 0xe1, 0x47, 0xa3, 0x0e, 0x08,
	0x2c, 0xb4, 0x40, 0x26, 0x28, 0x88, 0x16, 0x6d, 0xc4, 0x9f, 0xc6, 0xdd,
	0x50, 0x06, 0x09, 0xbf, 0x09, 0x21, 0xe1, 0x4f, 0x70, 0xd1, 0x1d, 0x10,
	0x5d, 0xea, 0x63, 0xfb, 0xc5, 0x56, 0x5b, 0x75, 0xbb, 0x76, 0x82, 0xd6,
	0x46, 0xab, 0x35, 0x68, 0xd7, 0x87, 0x76, 0x77, 0x65, 0xa0, 0x15, 0xbf,
	0xba, 0x76, 0x1b, 0xd9, 0x6d, 0x97, 0x6e, 0xbb, 0xf5, 0x7b, 0xdf, 0xf7,
	0x9c, 0xcb, 0xcc, 0xbd, 0x99, 0x00, 0xfe, 0xec, 0xb7, 0xbb, 0xdf, 0xf3,
	0xc5, 0xc7, 0xe7, 0x70, 0xee, 0x3d, 0x3f, 0xef, 0x79, 0xcf, 0xfb, 0x7f,
	0xde, 0x73, 0xc7, 0x25, 0xfb, 0x59, 0x70, 0x1a, 0x63, 0x1f, 0xe3, 0x1f,
	0x94, 0x13, 0x73, 0x19, 0x63, 0xb5, 0xa9, 0xb2, 0xc5, 0xc3, 0x62, 0xd9,
	0x39, 0x8c, 0xe5, 0x76, 0x48, 0x8c, 0xd5, 0x30, 0xb6, 0xb2, 0x5d, 0x89,
	0xcf, 0x82, 0x7f, 0x16, 0x76, 0xb4, 0xbc, 0x82, 0xf5, 0xe5, 0x6d, 0x6e,
	0xc3, 0x5d, 0xca, 0x58, 0xff, 0x03, 0x6e, 0x7f, 0x0d, 0xd4, 0x4f, 0x6f,
	0x57, 0xc2, 0x6e, 0xe8, 0xda, 0xa8, 0xf8, 0xa8, 0xbe, 0xac, 0xcb, 0x15,
	0x76, 0x1b, 0xf0, 0x7c, 0xeb, 0x47, 0x2f, 0xe7, 0xe3, 0xfb, 0x8d, 0x52,
	0x98, 0x41, 0x9d, 0xb1, 0xbb, 0x19, 0x9b, 0xcc, 0xd8, 0x1a, 0x0f, 0xfc,
	0x13, 0xea, 0xcb, 0x2a, 0x92, 0x1d, 0xf8, 0xfe, 0xdd, 0x2d, 0x52, 0x38,
	0x86, 0xaf, 0x99, 0xe9, 0x9b, 0x04, 0xef, 0x6f, 0x65, 0xfc, 0x7d, 0xf3,
	0x03, 0x8a, 0xc6, 0x64, 0xa8, 0xef, 0xbb, 0xad, 0x89, 0x4d, 0x64, 0xec,
	0x96, 0x1e, 0x98, 0xc5, 0x43, 0x0d, 0xd9, 0xc7, 0xbc, 0x3d, 0x63, 0x05,
	0x8c, 0x45, 0xf8, 0x23, 0xd6, 0xb2, 0x05, 0xde, 0x57, 0xa6, 0xde, 0x47,
	0x58, 0xd7, 0x47, 0x0a, 0xf4, 0x6b, 0x8e, 0x39, 0x9e, 0xef, 0x9b, 0xf5,
	0x3e, 0x0b, 0xe0, 0x7b, 0x2d, 0xf5, 0x1c, 0xd6, 0x73, 0x0c, 0xff, 0x31,
	0x85, 0xb1, 0x4b, 0x99, 0x3f, 0x78, 0x3a, 0x1b, 0xfe, 0x1d, 0x66, 0xe1,
	0x8f, 0x15, 0x28, 0x1b, 0xf2, 0x19, 0x1b, 0x9d, 0xc2, 0x97, 0xb3, 0x64,
	0x0c, 0xa0, 0x1f, 0xc5, 0xd8, 0x5c, 0xc6, 0x5c, 0xac, 0x1c, 0xc6, 0xa9,
	0xbd, 0xcc, 0xc5, 0xca, 0x60, 0x7d, 0x16, 0x1e, 0xdb, 0x38, 0x1e, 0x97,
	0x35, 0x49, 0x84, 0xc7, 0x65, 0x3e, 0x46, 0xf5, 0x77, 0xe7, 0x4a, 0xf1,
	0x07, 0x4b, 0xa9, 0x1f, 0x9b, 0x5e, 0x0d, 0x25, 0x3c, 0x2f, 0xc8, 0x83,
	0x32, 0xc8, 0xcc, 0x42, 0x28, 0x23, 0x1e, 0x96, 0xc8, 0x06, 0xf8, 0xe7,
	0xb6, 0x5d, 0xf6, 0x1e, 0xae, 0x7f, 0x03, 0x4e, 0x35, 0x9a, 0xda, 0x27,
	0x02, 0xf0, 0x7e, 0x01, 0x8b, 0xba, 0x18, 0xc0, 0xf7, 0x67, 0x2c, 0x46,
	0xe5, 0x62, 0x16, 0xa7, 0xf2, 0xcb, 0x2c, 0x41, 0x70, 0x2c, 0x65, 0x43,
	0x25, 0x2a, 0xd4, 0xef, 0x52, 0x12, 0x9b, 0x18, 0xcc, 0x13, 0x0e, 0x45,
	0xa7, 0xe3, 0xfe, 0xfe, 0xae, 0xfe, 0xd8, 0xbb, 0x12, 0xbc, 0xbf, 0xbf,
	0x5a, 0xaa, 0x9d, 0x02, 0x25, 0xf3, 0xe5, 0xd1, 0xba, 0x2f, 0xb4, 0x3e,
	0x6b, 0x7e, 0x95, 0x45, 0xae, 0xc3, 0x71, 0x18, 0x93, 0x5d, 0x11, 0x3f,
	0x63, 0xe3, 0xad, 0x75, 0x1e, 0x66, 0xb1, 0x8a, 0x20, 0x63, 0x7a, 0x8f,
	0x8f, 0xd3, 0xcb, 0x61, 0xd6, 0xcf, 0xa0, 0x3e, 0xbe, 0x41, 0xd0, 0x4b,
	0xe3, 0xfb, 0x72, 0x08, 0xd6, 0xdd, 0xf3, 0x3c, 0x0b, 0x63, 0x3d, 0x04,
	0x9b, 0x39, 0x05, 0xea, 0xa1, 0xae, 0xac, 0xf8, 0x06, 0xa8, 0xf7, 0x3c,
	0x1e, 0xab, 0x47, 0xbc, 0x1c, 0x6b, 0x01, 0xcc, 0x43, 0xff, 0x63, 0x8d,
	0x6e, 0x29, 0x5a, 0x05, 0xa5, 0x4b, 0x77, 0x45, 0xa0, 0x0c, 0xa9, 0x8c,
	0x29, 0x80, 0xa7, 0xfa, 0x86, 0xf5, 0x92, 0x02, 0xed, 0xe6, 0x46, 0xf9,
	0x38, 0xe3, 0x4d, 0x4d, 0x66, 0x57, 0x42, 0xfd, 0x70, 0x4c, 0x52, 0xc5,
	0x73, 0xec, 0xaf, 0xeb, 0x31, 0x49, 0x87, 0xfa, 0x78, 0xa8, 0x3f, 0x28,
	0xe1, 0x7b, 0xdd, 0xc5, 0x60, 0x9c, 0x86, 0x86, 0x5c, 0x57, 0xb2, 0x0a,
	0xf1, 0xdd, 0x33, 0x46, 0x87, 0xb2, 0xe2, 0xb0, 0x96, 0x90, 0x01, 0xbf,
	0xf5, 0xa6, 0x4e, 0xcf, 0x19, 0x5b, 0x44, 0x74, 0x35, 0x5e, 0xd0, 0xda,
	0x5c, 0x93, 0xf7, 0x9b, 0x7b, 0x38, 0xcf, 0xcf, 0xe8, 0x3d, 0xfb, 0xd3,
	0xc7, 0xd6, 0x7b, 0xc0, 0xef, 0x25, 0x45, 0x7c, 0xdf, 0x8e, 0x1d, 0x2e,
	0xcb, 0x41, 0x78, 0x59, 0xd4, 0xde, 0xbf, 0x48, 0x65, 0x31, 0x4f, 0x5e,
	0x0a, 0xcf, 0x3b, 0xd7, 0xc1, 0x0b, 0x77, 0x0a, 0xbf, 0xbb, 0x0e, 0x97,
	0x6d, 0x45, 0xbc, 0x1d, 0xeb, 0x53, 0xc3, 0x82, 0x94, 0x6d, 0xe3, 0xc3,
	0xb8, 0xbd, 0x0d, 0xf0, 0xfe, 0x4c, 0x95, 0x1c, 0x56, 0x0c, 0xe4, 0xb3,
	0x22, 0x0e, 0x7f, 0x85, 0xee, 0xd7, 0x7d, 0xa9, 0x71, 0x76, 0xae, 0x83,
	0xf6, 0x97, 0xa5, 0xe0, 0x68, 0x54, 0xa6, 0xf6, 0x13, 0x3e, 0x4c, 0x46,
	0xfc, 0x38, 0xb7, 0x06, 0xda, 0x57, 0xa5, 0xda, 0x3f, 0x81, 0xed, 0x01,
	0x8e, 0x3d, 0x08, 0x0f, 0xf5, 0x5b, 0x73, 0xd4, 0x8b, 0xf3, 0x44, 0x18,
	0xcd, 0x33, 0x12, 0x3d, 0xbc, 0xb0, 0x4e, 0xa7, 0x7e, 0x83, 0x62, 0x1d,
	0xd7, 0xfc, 0xef, 0x30, 0xed, 0xd3, 0xdc, 0x86, 0x16, 0x89, 0xcf, 0x2b,
	0xe0, 0x6b, 0xb0, 0xc3, 0x67, 0x95, 0x16, 0x7c, 0x23, 0x8d, 0x7f, 0x4c,
	0xc0, 0x65, 0x8d, 0x6f, 0xcd, 0xf7, 0xc4, 0xba, 0x10, 0x95, 0x8d, 0x4a,
	0xd5, 0x23, 0xf7, 0xe2, 0xba, 0x8e, 0x68, 0x7c, 0x5d, 0xf3, 0x8d, 0xc7,
	0x77, 0x23, 0xfe, 0x8e, 0x78, 0xc2, 0x31, 0xa8, 0x3f, 0x79, 0xdd, 0xdf,
	0x8c, 0xb9, 0x17, 0x86, 0xb8, 0x62, 0xfa, 0xf3, 0x97, 0x3f, 0xc3, 0x70,
	0xbe, 0xe5, 0x0f, 0xdf, 0x8e, 0xeb, 0x7a, 0x2e, 0x8b, 0xd6, 0xf5, 0xd4,
	0x87, 0x67, 0x5e, 0xbb, 0x91, 0x0d, 0x9f, 0xf7, 0x2d, 0x81, 0x87, 0x9f,
	0x9e, 0x9b, 0x3f, 0x44, 0x75, 0x6b, 0xfe, 0xb9, 0xa6, 0x34, 0x46, 0x02,
	0x3a, 0xab, 0x34, 0xa5, 0x84, 0x0b, 0xe8, 0xe5, 0x58, 0xfd, 0x57, 0x1e,
	0xbe, 0xd7, 0xc0, 0x7a, 0xbf, 0x89, 0xf2, 0xa4, 0xd2, 0x3c, 0x66, 0x4a,
	0x50, 0x4e, 0x84, 0x61, 0x68, 0xbf, 0x99, 0xfa, 0xa7, 0x8f, 0x41, 0x9e,
	0x55, 0x42, 0x77, 0xe4, 0xc7, 0x49, 0x0d, 0x52, 0x0b, 0xb6, 0x7b, 0xe2,
	0xc6, 0x87, 0xbe, 0x74, 0x1f, 0x3c, 0xfa, 0xa9, 0x8b, 0xc3, 0x7d, 0xc5,
	0x5f, 0x72, 0xb8, 0x2f, 0xbb, 0x7e, 0xed, 0x93, 0x08, 0xef, 0x65, 0x37,
	0xae, 0xfd, 0xf9, 0x33, 0x50, 0xbf, 0x02, 0x85, 0x20, 0xf0, 0xdd, 0xa5,
	0x37, 0xed, 0x5f, 0xf3, 0x77, 0xf0, 0xcf, 0x6f, 0x2c, 0xfc, 0xcb, 0xe5,
	0x7b, 0x18, 0xc9, 0x85, 0x58, 0x36, 0xc0, 0x91, 0x6b, 0x4a, 0x0c, 0xf7,
	0x77, 0xd9, 0xf7, 0xdd, 0x36, 0xb9, 0x72, 0xec, 0x79, 0x3f, 0xc9, 0x95,
	0x42, 0xb3, 0x34, 0x86, 0xfc, 0xb7, 0xac, 0x4f, 0x22, 0xf9, 0xdc, 0xdf,
	0xe8, 0x66, 0x41, 0x7c, 0xff, 0x33, 0x77, 0xdc, 0x8d, 0xfc, 0xf5, 0x80,
	0x64, 0x52, 0xfb, 0x67, 0xdd, 0x71, 0x94, 0x0f, 0xc7, 0x5c, 0x8c, 0xa1,
	0x3c, 0x5e, 0x76, 0xdc, 0x1b, 0x47, 0x7e, 0x61, 0xab, 0x96, 0x91, 0xbc,
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	0x75, 0x82, 0x54, 0x93, 0xac, 0x13, 0x00, 0x46, 0x9d, 0x00, 0x2d, 0xea,
	0x04, 0xe8, 0x47, 0x9d, 0x00, 0x30, 0xea, 0x04, 0x80, 0x51, 0x27, 0x00,
	0x8c, 0x3a, 0x01, 0x5a, 0xd4, 0x09, 0xd0, 0xff, 0xc5, 0x7c, 0xf9, 0x5e,
	0x26, 0x40, 0x42, 0x2c, 0xeb, 0x97, 0x11, 0x6c, 0xdf, 0xef, 0x6b, 0x56,
	0xbd, 0x88, 0xcf, 0xef, 0x3b, 0x2c, 0xef, 0xa1, 0xee, 0x6b, 0x54, 0xf8,
	0x9d, 0xd6, 0x45, 0xfa, 0x3e, 0xfc, 0xdc, 0x35, 0xef, 0x75, 0x0e, 0x6a,
	0xef, 0x75, 0x7c, 0xdb, 0xf8, 0x5e, 0xaf, 0xae, 0x4d, 0x75, 0x82, 0x55,
	0x75, 0xa6, 0xbe, 0x63, 0xa8, 0xeb, 0xd4, 0xb5, 0x2a, 0xce, 0x35, 0xb0,
	0x2f, 0xf5, 0xf3, 0xf9, 0xfb, 0x1b, 0x3b, 0x73, 0xde, 0x2d, 0x45, 0x7f,
	0xb3, 0xc9, 0x69, 0x70, 0x80, 0x4f, 0x97, 0xe2, 0x50, 0xaf, 0xaa, 0xec,
	0x6c, 0xe6, 0xfa, 0x53, 0x41, 0xfc, 0x61, 0x33, 0xf3, 0xb7, 0x45, 0x11,
	0xa8, 0x97, 0xde, 0x65, 0x91, 0x79, 0x6e, 0x8d, 0x4a, 0xbd, 0x53, 0xf8,
	0x3e, 0x94, 0xe3, 0xe0, 0x1a, 0x4b, 0x37, 0xe7, 0x1f, 0x55, 0x7b, 0x15,
	0x7b, 0x59, 0xf0, 0x7d, 0xee, 0x4d, 0x9f, 0xb1, 0x1d, 0x58, 0x6b, 0x8b,
	0x6a, 0x02, 0x9e, 0x35, 0x3e, 0x9b, 0xbd, 0x6c, 0x88, 0xf7, 0x1f, 0x7c,
	0x2f, 0xec, 0x10, 0x57, 0xef, 0x9b, 0x97, 0xc9, 0x29, 0xa2, 0x26, 0xa2,
	0x88, 0xef, 0x9b, 0x97, 0xe1, 0x9e, 0x99, 0x5a, 0xa1, 0x7e, 0x65, 0xe4,
	0xfb, 0x63, 0x4a, 0x4c, 0x87, 0x43, 0x1e, 0xf1, 0xae, 0x2a, 0x03, 0x66,
	0xdd, 0x2e, 0xf5, 0x3e, 0xe4, 0x3d, 0x55, 0x65, 0x67, 0xeb, 0xfa, 0x44,
	0x71, 0xed, 0x3d, 0x34, 0x2a, 0x03, 0xe0, 0x7f, 0xe8, 0xfd, 0xb3, 0xbb,
	0x30, 0x32, 0xf6, 0x4c, 0x38, 0x0c, 0x85, 0x98, 0x8c, 0xb8, 0xa9, 0xf8,
	0xf1, 0xb2, 0xfd, 0x6d, 0xf4, 0xbd, 0xfe, 0xad, 0x16, 0x8e, 0x3b, 0x56,
	0xe6, 0xbb, 0x97, 0x43, 0x8e, 0x8e, 0x99, 0x5c, 0x5c, 0x27, 0x39, 0x76,
	0xd8, 0xc6, 0xf9, 0xd1, 0xc7, 0xdb, 0xc6, 0x0f, 0xaa, 0x93, 0x7c, 0xee,
	0x72, 0x57, 0x17, 0xf2, 0xfd, 0xfc, 0x68, 0xae, 0x5b, 0xac, 0x32, 0x29,
	0xec, 0x97, 0xf3, 0x8b, 0xc7, 0xc5, 0xf3, 0xbb, 0x81, 0xe3, 0x26, 0xf6,
	0x3f, 0x1d, 0xae, 0x92, 0x5a, 0xcc, 0x5b, 0x35, 0xc9, 0xc1, 0xf5, 0xa9,
	0x42, 0x8b, 0xb8, 0x9f, 0xf7, 0xd1, 0xde, 0x69, 0x51, 0xcb, 0xfa, 0x54,
	0xb8, 0x56, 0xf1, 0x1a, 0x08, 0x5e, 0x2c, 0x9c, 0x66, 0xe8, 0xcf, 0x22,
	0x22, 0x1b, 0xcb, 0x8b, 0x29, 0x62, 0x03, 0xde, 0x53, 0x2d, 0x12, 0xf2,
	0x7d, 0x83, 0x2e, 0x37, 0xab, 0xb6, 0x29, 0x1c, 0x17, 0x70, 0xa1, 0x20,
	0x0e, 0xf7, 0x92, 0x92, 0xbe, 0x8b, 0x3a, 0xff, 0xed, 0x32, 0xde, 0x2f,
	0x2c, 0xb5, 0xc8, 0xf8, 0x35, 0xd1, 0x20, 0xef, 0xb3, 0x13, 0x37, 0xc9,
	0xf7, 0x2d, 0x3f, 0x12, 0x6e, 0x33, 0xfc, 0xed, 0x72, 0xf2, 0x8b, 0x68,
	0xc9, 0x4f, 0xfe, 0xae, 0x87, 0xfa, 0xdd, 0xe1, 0xa3, 0x93, 0x64, 0x7c,
	0xee, 0x88, 0xc7, 0xfe, 0x8b, 0x4f, 0x98, 0xf8, 0xbd, 0x6f, 0x61, 0xfc,
	0xf7, 0xd3, 0xdd, 0xec, 0xaf, 0x0b, 0xf8, 0x1d, 0x83, 0xe2, 0xbf, 0x47,
	0xbd, 0x72, 0xc3, 0xf5, 0xf5, 0x27, 0xf4, 0x1d, 0xc3, 0x31, 0x93, 0xb4,
	0x2f, 0x44, 0x47, 0xce, 0x8b, 0xba, 0x20, 0x97, 0x5c, 0x9f, 0x71, 0x73,
	0x7b, 0xa2, 0xbe, 0x9c, 0xdb, 0x19, 0x33, 0xa5, 0x9d, 0xbe, 0xfa, 0x2e,
	0x91, 0x78, 0x64, 0x07, 0xfe, 0xe1, 0x7d, 0xef, 0x23, 0x5f, 0x4c, 0x8c,
	0x8f, 0x74, 0xc2, 0xde, 0xe9, 0x7a, 0x7f, 0xcd, 0xfb, 0xc4, 0x30, 0xd9,
	0xea, 0xef, 0x13, 0xc7, 0x50, 0x2b, 0x82, 0xde, 0x27, 0x6e, 0x71, 0x39,
	0x78, 0xff, 0x44, 0xc3, 0xc9, 0xa9, 0x0e, 0xd0, 0xe3, 0xaf, 0x11, 0x4e,
	0xd0, 0x43, 0x7f, 0xa7, 0xb8, 0x65, 0x66, 0xc9, 0x2e, 0xf0, 0xc9, 0x15,
	0x25, 0x3c, 0xf8, 0x2e, 0xee, 0x51, 0xb6, 0x12, 0x5d, 0x8b, 0x70, 0x10,
	0x05, 0x75, 0x6e, 0x9f, 0x4b, 0x45, 0xdd, 0xfa, 0xb0, 0x62, 0xe7, 0x77,
	0xd1, 0xd7, 0xd8, 0xc9, 0x6d, 0x0f, 0xe3, 0x1d, 0x4f, 0x5d, 0xaa, 0x62,
	0x57, 0x1c, 0xa8, 0x87, 0x6f, 0x2d, 0x8c, 0x23, 0xbc, 0x8b, 0x52, 0x92,
	0x19, 0xef, 0xba, 0x76, 0x59, 0x2f, 0x65, 0x0a, 0xc5, 0xa1, 0x9e, 0xae,
	0xe9, 0x83, 0xcb, 0xdd, 0x56, 0x38, 0x62, 0xa0, 0x7f, 0x8e, 0xa6, 0x17,
	0xbd, 0x34, 0x5f, 0xca, 0xc9, 0x2d, 0x5e, 0xc8, 0xdb, 0xb7, 0xa8, 0xa3,
	0x3e, 0x87, 0xf9, 0x1e, 0x61, 0x73, 0x36, 0x6b, 0xf9, 0x1a, 0xf8, 0x3e,
	0xe7, 0x86, 0x31, 0x5c, 0x4f, 0xd5, 0xe5, 0xa6, 0xbf, 0x25, 0xbe, 0x09,
	0x72, 0xf3, 0x46, 0xa1, 0xf4, 0x33, 0xa5, 0xa5, 0xef, 0x98, 0x10, 0x07,
	0x74, 0xe5, 0xba, 0x8f, 0xe2, 0xfc, 0x0b, 0xcb, 0x3e, 0x7b, 0x38, 0x8e,
	0xcf, 0x37, 0x74, 0x1d, 0x8b, 0xec, 0x28, 0xdf, 0x4b, 0x86, 0xd6, 0xb1,
	0x74, 0xbb, 0xbc, 0x5b, 0xab, 0x83, 0xc3, 0x7e, 0x1a, 0xb5, 0x3a, 0xab,
	0x51, 0xab, 0xb3, 0x1a, 0xb5, 0x3a, 0xab, 0x51, 0xab, 0xb3, 0x1a, 0xb5,
	0x3a, 0xab, 0x51, 0xab, 0xb3, 0x1a, 0xb5, 0x3a, 0xab, 0x51, 0xab, 0xb3,
	0x1a, 0xb5, 0x3a, 0xab, 0x91, 0xeb, 0x77, 0x2b, 0xb8, 0x7d, 0xbb, 0x7e,
	0x35, 0xb7, 0xdd, 0xf5, 0x1e, 0x1e, 0x0f, 0xb2, 0xff, 0xef, 0x5d, 0xc7,
	0xfe, 0x87, 0xd6, 0x41, 0x3f, 0xc2, 0xbc, 0xd0, 0x3a, 0xa8, 0xb0, 0x3a,
	0xa2, 0xd9, 0x8f, 0x92, 0x7e, 0xcb, 0xfa, 0x73, 0x48, 0xdd, 0xb3, 0x78,
	0xf8, 0x92, 0x0d, 0x44, 0xbf, 0xfc, 0x06, 0xb3, 0x13, 0x5d, 0x7a, 0x1d,
	0x14, 0xef, 0x97, 0xef, 0x8b, 0x60, 0x7b, 0x70, 0xb1, 0x70, 0xc8, 0xfa,
	0xa7, 0x4e, 0xb7, 0x08, 0xae, 0x97, 0xf6, 0x0b, 0xdb, 0x14, 0xd0, 0x3f,
	0x2f, 0x63, 0x9c, 0xd1, 0x40, 0xe3, 0x7f, 0xd5, 0xf8, 0xa0, 0xd7, 0x1f,
	0xa1, 0x1f, 0x38, 0x1f, 0xf4, 0x03, 0x2d, 0xf4, 0xc3, 0x98, 0x36, 0xa0,
	0x1f, 0xcf, 0x98, 0x49, 0x85, 0xb3, 0xa5, 0xbf, 0xf7, 0xb0, 0xbf, 0xb7,
	0x31, 0x5f, 0xd7, 0xaf, 0x21, 0xfb, 0x41, 0xf0, 0x52, 0x61, 0x1f, 0x64,
	0x3f, 0x2e, 0x86, 0xd8, 0x0f, 0x4a, 0x3c, 0xee, 0x06, 0x1e, 0xcb, 0x3a,
	0xe5, 0xbb, 0x26, 0xfd, 0xfd, 0x66, 0x1e, 0x35, 0x5f, 0x4e, 0x19, 0xc2,
	0x9e, 0xf8, 0xa4, 0x3d, 0x19, 0x13, 0xe6, 0xdb, 0x87, 0xef, 0x8c, 0xa9,
	0x0d, 0xe3, 0xf7, 0xc1, 0xc7, 0xb4, 0xf7, 0x58, 0xc7, 0x36, 0xca, 0x77,
	0x71, 0x65, 0xa2, 0x84, 0xbf, 0x3b, 0x84, 0x5d, 0x89, 0x02, 0x3f, 0x96,
	0x0e, 0xef, 0x7b, 0xff, 0x69, 0x9a, 0xbf, 0x74, 0x73, 0x04, 0xc7, 0x2d,
	0xeb, 0x47, 0x2e, 0x9b, 0xf6, 0xbf, 0xb1, 0x2b, 0x9f, 0x15, 0x0a, 0xa6,
	0xdb, 0x6f, 0xea, 0xfd, 0x95, 0x1f, 0x13, 0x2e, 0x05, 0x61, 0x52, 0xfe,
	0x0a, 0xcc, 0x22, 0x03, 0xf7, 0x35, 0xc2, 0x10, 0xc6, 0x7a, 0x50, 0xa8,
	0x6e, 0x51, 0x70, 0x3f, 0xba, 0xea, 0x5e, 0x31, 0x19, 0x7c, 0x2e, 0xb0,
	0x94, 0xec, 0x00, 0x9e, 0xf1, 0xda, 0xfd, 0xb6, 0x88, 0xd5, 0xea, 0xad,
	0xc6, 0xee, 0x8a, 0x3d, 0x04, 0x9f, 0x8c, 0x4b, 0x74, 0xe2, 0x5e, 0x6b,
	0x74, 0xc2, 0x21, 0x81, 0xf7, 0x4f, 0x85, 0x75, 0xc5, 0x99, 0xb0, 0x8b,
	0xfe, 0x31, 0xee, 0x09, 0x45, 0x39, 0x78, 0xbf, 0xbc, 0x55, 0xc1, 0xfa,
	0xf0, 0x4c, 0x79, 0xfe, 0x3b, 0x8a, 0xc3, 0x9b, 0x20, 0x57, 0x81, 0xc3,
	0xe3, 0x73, 0xc0, 0xef, 0x79, 0x16, 0x47, 0x1b, 0xea, 0x00, 0xce, 0xa2,
	0x84, 0xa5, 0xc8, 0xf3, 0xe7, 0x45, 0x3b, 0x72, 0x50, 0x07, 0x70, 0x76,
	0x8d, 0x92, 0x70, 0xbc, 0xa3, 0x4d, 0x71, 0x22, 0x94, 0x4d, 0x58, 0x5a,
	0xc0, 0xef, 0xcf, 0xac, 0x5b, 0x3f, 0xb6, 0xe2, 0xdd, 0x9a, 0x22, 0xa2,
	0xe9, 0x5c, 0x96, 0x61, 0xee, 0x1c, 0x7c, 0xa7, 0xa6, 0xf8, 0x53, 0x99,
	0x37, 0x8b, 0x3e, 0xf6, 0x63, 0x37, 0x17, 0xc9, 0xfc, 0x6b, 0xc4, 0x6b,
	0xc2, 0x8f, 0x7b, 0xab, 0xbe, 0x59, 0x91, 0x7c, 0x7f, 0x26, 0x32, 0x1d,
	0x39, 0x18, 0xa7, 0xb8, 0xf2, 0xbb, 0x45, 0x24, 0x1f, 0x7f, 0xfc, 0x9e,
	0xeb, 0x16, 0xac, 0x4f, 0xd4, 0xf0, 0x8c, 0xc7, 0x2d, 0xa2, 0x0a, 0xae,
	0x76, 0xdb, 0xd0, 0x9e, 0xd0, 0xee, 0xf3, 0xba, 0x0c, 0xee, 0x52, 0xb4,
	0x45, 0x51, 0x1e, 0x23, 0xf7, 0x1b, 0xbc, 0xd9, 0x68, 0xdf, 0x34, 0xf8,
	0x7e, 0x8c, 0x7e, 0x92, 0xe7, 0x22, 0xec, 0x57, 0xf4, 0xd8, 0xe4, 0x89,
	0x19, 0x04, 0x27, 0x5a, 0x7c, 0x6c, 0x27, 0x3b, 0x5c, 0xae, 0x5b, 0xb1,
	0xff, 0xab, 0x33, 0x5d, 0xc5, 0x18, 0x0f, 0xad, 0x9f, 0x83, 0xb7, 0xc8,
	0xf3, 0x09, 0x9f, 0xdb, 0x30, 0x2f, 0xf4, 0x1d, 0x96, 0xce, 0xcf, 0xa5,
	0x45, 0x52, 0xee, 0xcb, 0x8a, 0xa4, 0xfd, 0x98, 0xbe, 0x56, 0xde, 0xc7,
	0x86, 0xf2, 0xbd, 0xac, 0xc8, 0xa0, 0xd9, 0xb7, 0xbf, 0x8f, 0x37, 0xe1,
	0x5b, 0x8a, 0xef, 0xe9, 0xf8, 0x8b, 0xad, 0x8b, 0xb3, 0x81, 0x0f, 0xe1,
	0x7b, 0x2f, 0xf0, 0x24, 0x7c, 0x17, 0x62, 0x5c, 0x44, 0xc4, 0x70, 0xbd,
	0xe3, 0xfa, 0x72, 0xe6, 0xe1, 0xef, 0x95, 0x15, 0x49, 0xf9, 0x22, 0x7b,
	0x56, 0xf5, 0xb1, 0xb4, 0x67, 0xdc, 0xa6, 0x1b, 0xbd, 0xc3, 0x10, 0x3f,
	0x8e, 0xfa, 0x85, 0x77, 0x18, 0xf0, 0x1d, 0xd5, 0xd8, 0x67, 0xc3, 0xbf,
	0xc3, 0x78, 0xd6, 0xd3, 0x67, 0x83, 0x7f, 0x7f, 0xf6, 0xc1, 0x3e, 0x1b,
	0xfa, 0x9f, 0x75, 0xc9, 0x77, 0xd2, 0xa1, 0xfb, 0x37, 0x16, 0xc9, 0xf7,
	0x13, 0xe9, 0xd3, 0xfb, 0x78, 0xfd, 0x58, 0xfa, 0x56, 0x37, 0xc7, 0xe9,
	0x7d, 0xc3, 0x10, 0x47, 0xa5, 0x97, 0x7f, 0xbc, 0x5e, 0xde, 0xbb, 0x64,
	0xb0, 0x7f, 0x19, 0xab, 0xf9, 0x97, 0xb1, 0xbf, 0x48, 0x69, 0xef, 0x21,
	0x79, 0x1b, 0xfb, 0x64, 0x34, 0xdf, 0x6f, 0x8b, 0x82, 0x58, 0x1e, 0xaf,
	0xb4, 0x4a, 0x3d, 0xad, 0xfc, 0x45, 0xd9, 0xa1, 0x36, 0x6a, 0xc7, 0x6f,
	0x27, 0x7c, 0x83, 0xe2, 0xaf, 0x09, 0x5e, 0xc2, 0x7b, 0x50, 0x5c, 0x64,
	0xec, 0x97, 0xef, 0x2d, 0x09, 0x06, 0x9d, 0xf6, 0x9a, 0x18, 0x86, 0xcc,
	0x22, 0xbe, 0xaa, 0x11, 0xf2, 0xbd, 0xe5, 0x28, 0xcd, 0x6e, 0x20, 0x6e,
	0x2b, 0x25, 0xbb, 0x50, 0x53, 0x7e, 0xf4, 0x32, 0xbf, 0x03, 0xc0, 0x7a,
	0xec, 0x8f, 0x3b, 0x5b, 0xc8, 0x5f, 0xbb, 0x49, 0xc2, 0xe4, 0xae, 0x91,
	0x8f, 0x2e, 0x9f, 0xbf, 0xa6, 0x8b, 0xf3, 0xc3, 0xed, 0x57, 0xfb, 0xb5,
	0x7c, 0xb3, 0x75, 0x3d, 0xf2, 0x67, 0x8a, 0xdf, 0x06, 0xf5, 0x57, 0x96,
	0x1d, 0xe9, 0x82, 0xbf, 0xa9, 0xda, 0x3b, 0xb8, 0xbf, 0x66, 0xc5, 0x67,
	0x9c, 0xc7, 0x52, 0xfc, 0x36, 0xa8, 0xff, 0xde, 0x1f, 0x7f, 0xc0, 0xef,
	0x6c, 0xea, 0xda, 0x07, 0xf7, 0x13, 0x7f, 0x9f, 0x02, 0x9f, 0x75, 0xfe,
	0x1e, 0x33, 0xf9, 0x26, 0x20, 0xdf, 0x3b, 0x56, 0x13, 0xe6, 0x94, 0xff,
	0x7e, 0xc0, 0xb7, 0x12, 0xfa, 0xde, 0x54, 0x1d, 0xc1, 0xef, 0x67, 0x77,
	0xfd, 0x3a, 0x8f, 0xe5, 0x46, 0xe7, 0x37, 0xad, 0x6f, 0xfa, 0x76, 0xf2,
	0xb1, 0x96, 0xe7, 0x7b, 0xf2, 0x44, 0x06, 0xf4, 0xe1, 0x9b, 0xda, 0x5e,
	0xd8, 0xa7, 0xb4, 0x41, 0xf6, 0xc9, 0xc3, 0x75, 0xbe, 0xd9, 0x91, 0x6c,
	0x77, 0xea, 0xb4, 0xfc, 0xaa, 0xb6, 0xcc, 0xce, 0x7e, 0x3e, 0xb1, 0xd6,
	0xca, 0xf6, 0xab, 0x50, 0x0d, 0x73, 0x02, 0xae, 0x35, 0x4a, 0x3b, 0x23,
	0x8a, 0x55, 0xcd, 0x4e, 0xf9, 0x58, 0xff, 0x4f, 0xde, 0x3e, 0x8c, 0xeb,
	0x79, 0x7c, 0x00, 0xc0, 0x31, 0x93, 0xf8, 0xdd, 0x71, 0xdc, 0x5a, 0x09,
	0xf7, 0x8d, 0xb0, 0xb0, 0x7d, 0x28, 0x34, 0x94, 0x54, 0xef, 0xa1, 0xf6,
	0xa8, 0x61, 0x05, 0xdb, 0x81, 0x04, 0xbc, 0xb8, 0x24, 0xbe, 0x3f, 0x03,
	0xfb, 0xa0, 0x42, 0x7f, 0x65, 0x5d, 0xb5, 0xce, 0xec, 0x53, 0xe4, 0xfd,
	0xbe, 0x23, 0x07, 0xf9, 0xae, 0x7e, 0xdf, 0xd4, 0xb0, 0xd1, 0xdb, 0x7a,
	0x10, 0xf9, 0xb2, 0xe2, 0x7d, 0x72, 0x19, 0xea, 0x8a, 0x77, 0x46, 0xf0,
	0xfd, 0x41, 0x00, 0xf5, 0x46, 0x3a, 0x4f, 0xc3, 0x30, 0x69, 0x47, 0x1b,
	0x16, 0xa4, 0xb3, 0x1f, 0x08, 0x88, 0x92, 0xd2, 0x95, 0x88, 0x43, 0xe6,
	0x87, 0x71, 0xfd, 0xb1, 0x61, 0x98, 0xe3, 0x51, 0xdc, 0x27, 0x36, 0x54,
	0x4c, 0xe4, 0x38, 0xfa, 0xd0, 0x7f, 0x4b, 0xbf, 0xdb, 0x37, 0xd7, 0xea,
	0x44, 0x1c, 0xd5, 0x30, 0xd9, 0xb1, 0x06, 0xef, 0x55, 0x1a, 0x7e, 0xe1,
	0xe0, 0xf1, 0x57, 0x14, 0xb9, 0x9f, 0xe7, 0x51, 0x49, 0x9f, 0x86, 0xb9,
	0xf2, 0xfc, 0x0d, 0x15, 0x31, 0x9c, 0xf7, 0xe8, 0x7c, 0x68, 0x68, 0x74,
	0x8d, 0xc4, 0xfd, 0xd4, 0xcc, 0x31, 0xee, 0xff, 0x00, 0xdf, 0x47, 0x69,
	0xf7, 0x73, 0x0d, 0xc9, 0xd4, 0x4f, 0xed, 0x13, 0x4a, 0xc9, 0x82, 0x1f,
	0x61, 0x9f, 0x49, 0x12, 0xdf, 0x19, 0x33, 0x1d, 0xac, 0x77, 0xc7, 0x16,
	0x4c, 0x7c, 0x74, 0xb7, 0x83, 0xdd, 0x89, 0x1f, 0xf7, 0x44, 0x75, 0xb3,
	0x23, 0x07, 0xe5, 0xc5, 0xff, 0x03, 0x3c, 0x75, 0x9d, 0x8b, 0x10, 0x37,
	0x00, 0x00, 0x00, 0x00
};

void bnx2x_init_e1h_firmware(struct bnx2x *bp)
{
	INIT_OPS(bp)                  = (struct raw_op *)init_ops_e1h;
	INIT_DATA(bp)                 = (u32 *)init_data_e1h;
	INIT_OPS_OFFSETS(bp)          = (u16 *)init_ops_offsets_e1h;
	INIT_TSEM_INT_TABLE_DATA(bp)  = tsem_int_table_data_e1h;
	INIT_TSEM_PRAM_DATA(bp)       = tsem_pram_data_e1h;
	INIT_USEM_INT_TABLE_DATA(bp)  = usem_int_table_data_e1h;
	INIT_USEM_PRAM_DATA(bp)       = usem_pram_data_e1h;
	INIT_XSEM_INT_TABLE_DATA(bp)  = xsem_int_table_data_e1h;
	INIT_XSEM_PRAM_DATA(bp)       = xsem_pram_data_e1h;
	INIT_CSEM_INT_TABLE_DATA(bp)  = csem_int_table_data_e1h;
	INIT_CSEM_PRAM_DATA(bp)       = csem_pram_data_e1h;
}