/*
 * Copyright (C) 2006 Mindspeed Technologies, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_COMCERTO		1
#define CONFIG_ARMV7 		1
#define CONFIG_COMCERTO_2000	1	/* It's an  SoC */
#define CONFIG_BOARD_C2KASIC	1
#undef  CONFIG_USE_IRQ		/* we don't need IRQ/FIQ stuff  */

#define	CONFIG_ARM_EXCEPTIONS	1
#define	CONFIG_ARCH_HAS_LOWLEVEL_INIT	1
#define	CONFIG_MMU	1
#define CFG_HZ_CLOCK          250000000
#define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */

#define CPU_3XX_ES20            1
#define	CMD_SAVEENV	1
#include <asm/hardware.h>

/* Mindspeed version */
#define CONFIG_IDENT_STRING	" Mindspeed $Name: uboot_c2k_1_00"

/*
 * Linux boot configuration
 */

#define CONFIG_CMDLINE_TAG		1	/* enable passing of ATAGs      */
#define CONFIG_SETUP_MEMORY_TAGS	1
//#define CONFIG_INITRD_TAG		1

#define LINUX_BOOTPARAM_ADDR		(PHYS_SDRAM + MSP_BOTTOM_MEMORY_RESERVED_SIZE + 0x100)

/*
 *	Relocation options
 */
//#define CONFIG_SKIP_RELOCATE_UBOOT
//#define CONFIG_SKIP_LOWLEVEL_INIT

/*
 * RAM configuration
 */

/*
 * Memory Mapping
 */

#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM		COMCERTO_AXI_DDR_BASE
#define PHYS_SDRAM_SIZE		(512 * 1024 * 1024)

/*
 * Hardware drivers
 */

/*
 * UART configuration
 */
/* define one of these to choose the UART0 or UART1 as console */
#define CONFIG_UART0		1
#define CONFIG_BAUDRATE		115200
#define CFG_BAUDRATE_TABLE	{115200, 19200, 38400, 57600, 9600}

/*
 * Gemac Settings
 */
#define EMAC0_PHY_ADDR  4
#define EMAC1_PHY_ADDR  5
#define EMAC0_FLAGS     0
#define EMAC1_FLAGS     0 
#define EMAC2_FLAGS     0

#define CONFIG_NET_MULTI	1

/*
 * Shell configuration
 */
#define CONFIG_COMMANDS		(CFG_CMD_FLASH | CFG_CMD_ENV  | CFG_CMD_MEMORY | CFG_CMD_MEMTEST | CFG_CMD_MII  | CFG_CMD_RUN | CFG_CMD_NET | CFG_CMD_NAND | CFG_CMD_JFFS2 |  CFG_CMD_PING | CFG_CMD_NFS  | CFG_CMD_I2C | CFG_CMD_EEPROM /*| CFG_CMD_ELF| CFG_CMD_SPI*/)

#define	CFG_LONGHELP					/* undef to save memory		*/
#define CFG_PROMPT		"Comcerto-2000 > "	/* Monitor Command Prompt */
#define CFG_CBSIZE		256			/* Console I/O Buffer Size */
#define CFG_MAXARGS		16			/* max number of command args */
#define CFG_PBSIZE		(CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)	/* Print Buffer Size */

/*
 * User Interface
 */
#define	CONFIG_EXTRA_ENV_SETTINGS				\
	"hostname=comcerto2000\0"						\
	"netdev=eth0\0"									\
	"nfsargs=setenv bootargs init=${init_process} root=/dev/nfs rw "		\
		"nfsroot=${serverip}:${rootpath}\0"				\
	"flashargs=setenv bootargs init=${init_process} root=/dev/mtdblock4 rootfstype=${rootfstype} rw\0"	\
	"rootfstype=jffs2\0" \
	"init_process=/etc/preinit\0" \
	"addip=setenv bootargs ${bootargs} "				\
		"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"	\
		":${hostname}:${netdev}:off\0" \
	"addeth=setenv bootargs ${bootargs} " \
	"hwaddress=${netdev},${ethaddr}\0" \
	"addtty=setenv bootargs ${bootargs} console=ttyS0,115200n8\0" \
	"addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \
	"flash_self=run flashargs addip addtty;"		\
		"bootm ${kernel_addr}\0"				\
	"boot_nfs=nfs 80600000 ${rootpath}/boot/${kernelfile};run nfsargs addeth addip addtty;"     \
	        "bootm 80600000\0"						\
	"boot_flash=run flashargs addeth addtty addmtd; bootm 0xc0080000\0" \
	"boot_flashold=run flashargs addeth addtty addmtd; fsload /boot/uImage; bootm\0" \
	"rootpath=/devel/fs-c2kasic\0" \
	"kernelfile=uImage\0" \
	"bootfile=u-boot.bin\0" \
	"mtdids=" MTDIDS_DEFAULT "\0" \
	"mtdparts=" MTDPARTS_DEFAULT "\0" \
	"partition=" MTDPARTITION_DEFAULT "\0" \
	"mtddevnum=2\0" \
	"mtddevname=fs\0" \
	"fsfile=root.jffs2-128k\0" \
 	"updatefs=tftp 3000000 ${fsfile};protect off 1:35-127\;erase 1:35-127;cp.b 3000000 c0480000 ${filesize}\0" \
 	"updatekernel=tftp 3000000 ${kernelfile};protect off 1:4-35\;erase 1:4-35;cp.b 3000000 c0080000 ${filesize}\0" \
	"updateboot=tftp 3000000 ${bootfile};protect off 1:1-3\;erase 1:1-3;cp.b 3000000 c0020000 ${filesize}\0" \
	"updateuloader=tftp 3000000 uloader.bin;protect off 1:0-1\;erase 1:0-1;cp.b 3000000 c0000000 ${filesize}\0" \
	""

#define CONFIG_ETHADDR		00:aa:bb:cc:dd:ee
#define CONFIG_IPADDR		192.168.0.2
#define CONFIG_SERVERIP		192.168.0.1
//#define CONFIG_BOOTDELAY	3

#include <cmd_confdefs.h>

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/


#define CONFIG_SYS_LOAD_ADDR CFG_LOAD_ADDR

#define CFG_LOAD_ADDR		(PHYS_SDRAM + 0x01000000)	/* default load address */

#define CFG_MEMTEST_START	CFG_LOAD_ADDR	/* memtest works on */
#define CFG_MEMTEST_END		(CFG_MEMTEST_START + 0x800000)

//#define BOARD_LATE_INIT
#define MSP_BOTTOM_MEMORY_RESERVED_SIZE	0x800000	/* 8 MiB reserved for MSP */
#define MSP_TOP_MEMORY_RESERVED_SIZE	0x0		/* 0 MiB reserved for MSP */


/*
 * Network Configuration
 */
#define CONFIG_NET_RETRY_COUNT		5

/*
 * Flash Configuration - Using CFI driver
 */
//#define CFG_FLASH_AM040_DRIVER	1		/* enable AM040 flash driver */
#undef CFG_FLASH_AM040_DRIVER				/* disable AM040 flash driver */

//#define CFG_FLASH_AMLV640U_DRIVER	1		/* enable AMLV640U flash driver */
#undef CFG_FLASH_AMLV640U_DRIVER			/* disable AMLV640U flash driver */
//#define CFG_FLASH_AMLV640U_SIZE	0x400000	/* (Acessible) Size of the AMLV640U flash device */

#define CFG_FLASH_CFI_DRIVER		1	/* enable CFI driver */
//#undef CFG_FLASH_CFI_DRIVER			/* disable CFI driver */

#define CFG_MAX_FLASH_SECT		1024	/* max # of sectors on one chip */
#undef CFG_FLASH_PROTECTION

#define PHYS_FLASH1			0xC0000000 //EXP_CS0_BASEADDR	/* Flash Bank #1 */
#define PHYS_FLASH1_SECT_SIZE		0x00020000	/* 128 KiB sectors */

#define CFG_MAX_FLASH_BANKS		1       /* max num of flash banks */
#define CFG_FLASH_BANKS_LIST		{ PHYS_FLASH1 }

#define CFG_FLASH_ERASE_TOUT		(2 * CFG_HZ)	/* Timeout for Flash Erase */
#define CFG_FLASH_WRITE_TOUT		(1 * CFG_HZ)	/* Timeout for Flash Write */

/*
 * CFI driver
 */
#if defined(CFG_FLASH_CFI_DRIVER)
#define CFG_FLASH_CFI			1	/* flash is CFI conformant      */
#define CFG_FLASH_USE_BUFFER_WRITE	1	/* use buffered writes (20x faster) */
#define CFG_FLASH_QUIET_TEST
#undef CFG_FLASH_COMPLEX_MAPPINGS
//#define CFG_FLASH_COMPLEX_MAPPINGS

/*
 * Monitor configuration
 */
#define CFG_MONITOR_BASE        PHYS_FLASH1
#define CFG_MONITOR_LEN         (1 * PHYS_FLASH1_SECT_SIZE)	/* Reserve 128 KiB for Monitor */

/*
 * Enviroment in flash
 */
#define CFG_ENV_IS_IN_FLASH	1
#define CFG_ENV_SIZE          0x4000  /* Total Size of Environment 16KiB */
#endif

/*
 * I2C support
 */
#if defined(CFG_CMD_I2C)
#define CONFIG_HARD_I2C
#define CFG_TCLK                       CFG_HZ_CLOCK
#define CFG_I2C_SPEED                  40000
#define CFG_I2C_SLAVE                  0
#if defined(CFG_CMD_EEPROM)
#define CFG_I2C_EEPROM_ADDR            0x50
#define CFG_I2C_EEPROM_ADDR_LEN        2 /* Bytes of address */
#define CFG_EEPROM_PAGE_WRITE_BITS     6 /* max 64 byte */
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#endif
#endif

#if defined(CFG_ENV_IS_IN_FLASH)
#define CFG_ENV_ADDR		(PHYS_FLASH1 + 3 * PHYS_FLASH1_SECT_SIZE)	/* Keep 2 sectors for U-boot image */
#define CFG_ENV_SECT_SIZE	PHYS_FLASH1_SECT_SIZE
//#define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
#endif

#define CONFIG_ENV_OVERWRITE	1


#define CONFIG_CMD_NAND
#define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */
#define CFG_64BIT_STRTOUL

#define EXP_CS0_BASE_VAL	0x0
#define EXP_CS0_SEG_SIZE_VAL    0x7FFF
#define EXP_CS0_SEG_END_VAL     (EXP_CS0_BASE_VAL + EXP_CS0_SEG_SIZE_VAL)

#define EXP_CS1_BASE_VAL        (EXP_CS0_SEG_END_VAL + 1)
#define EXP_CS1_SEG_SIZE_VAL    0xFF
#define EXP_CS1_SEG_END_VAL     (EXP_CS1_BASE_VAL + EXP_CS1_SEG_SIZE_VAL)

#define EXP_CS2_BASE_VAL        (EXP_CS1_SEG_END_VAL + 1)
#define EXP_CS2_SEG_SIZE_VAL    0xFF
#define EXP_CS2_SEG_END_VAL     (EXP_CS2_BASE_VAL + EXP_CS2_SEG_SIZE_VAL)

#define EXP_CS3_BASE_VAL        (EXP_CS2_SEG_END_VAL + 1)
#define EXP_CS3_SEG_SIZE_VAL    0xFF
#define EXP_CS3_SEG_END_VAL     (EXP_CS3_BASE_VAL + EXP_CS3_SEG_SIZE_VAL)

#define EXP_CS4_BASE_VAL        (EXP_CS3_SEG_END_VAL + 1)
#define EXP_CS4_SEG_SIZE_VAL    0xFF
#define EXP_CS4_SEG_END_VAL     (EXP_CS4_BASE_VAL + EXP_CS4_SEG_SIZE_VAL)

#define SHIFT_4K_MUL    12

#define COMCERTO_EXP_CS4_BASE_ADDR      (COMCERTO_AXI_EXP_BASE + (EXP_CS4_BASE_VAL << SHIFT_4K_MUL))

#define CONFIG_SYS_NAND_BASE_LIST       { COMCERTO_EXP_CS4_BASE_ADDR }
#define CONFIG_SYS_NAND_BASE       COMCERTO_EXP_CS4_BASE_ADDR

/*
 * NAND Configuration
 */
#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#define CONFIG_SYS_MAX_NAND_DEVICE      1         /* Max number of NAND devices */

#define CONFIG_SYS_NAND_SELF_INIT

#define CONFIG_SYS_NAND_ONFI_DETECTION

/* NAND debugging */
#define CFG_DFC_DEBUG1 /* usefull */
#define CFG_DFC_DEBUG2  /* noisy */
#define CFG_DFC_DEBUG3  /* extremly noisy  */

#define CONFIG_MTD_DEBUG
#define CONFIG_MTD_DEBUG_VERBOSE 1

//In case MLC NAND is used on the Asic Board, comment this out
//#define CONFIG_NAND_TYPE_SLC

#if defined (CONFIG_NAND_TYPE_SLC)
#define COMCERTO_NAND_FLASH_SIZE        (512UL * 1024UL * 1024UL)
#else
#define COMCERTO_NAND_FLASH_SIZE        (2UL * 1024UL * 1024UL * 1024UL)
#endif

#define CFG_NAND_BASE			COMCERTO_EXP_CS4_BASE_ADDR
#define CFG_MAX_NAND_DEVICE		1
#define NAND_MAX_CHIPS			1
#define CONFIG_JFFS2_NAND		1

#endif
#if (CONFIG_COMMANDS & CFG_CMD_FLASH)
//TODO
#else
/*
 *EEPORM boot loader does the relocate and lowlevel init work
 */
//#define CONFIG_SKIP_RELOCATE_UBOOT
//#define CONFIG_SKIP_LOWLEVEL_INIT
/* Environment is in NAND */
#define CFG_ENV_IS_IN_NAND	1
#define CFG_ENV_OFFSET		0x00040000	/* Offset of Environment Sector */
#define NAND_MAX_CHIPS          1
#define CFG_ENV_SIZE		0x20000	/* Total Size of Environment 128KiB */
#endif


/* NAND GPIOs config */
#define CFG_NAND_BR_GPIO	29
#define CFG_NAND_CE_GPIO	28
#define CFG_NAND_CLE		0x00000400
#define CFG_NAND_ALE		0x00000200

/*
 * JFFS2 Configuration
 */
/* mtdparts command line support */
//#define CONFIG_JFFS2_CMDLINE
#if (CONFIG_COMMANDS & CFG_CMD_JFFS2)
//#define CFG_JFFS2_SORT_FRAGMENTS
#endif /* CFG_CMD_JFFS2 */

#if (CONFIG_COMMANDS & CFG_CMD_NAND)
#define MTDIDS_DEFAULT		"nand0=comcertonand"
#define MTDPARTS_DEFAULT	"mtdparts=comcertonand:256k(u-boot),128k(env),16000k(fs)"
#define MTDPARTITION_DEFAULT	"nand0,2"
#define ROOT_MTDBLOCK		"/dev/mtdblock3"
#else
#define MTDIDS_DEFAULT		"nor0=comcertoflash.0"
#define MTDPARTS_DEFAULT	"mtdparts=comcertoflash.0:128k(uloader),256k(u-boot),128k(env),4M(kernel),16M(fs)"
#define MTDPARTITION_DEFAULT	"nor0,3"
#define ROOT_MTDBLOCK		"/dev/mtdblock3"
#endif

#define CFG_HZ                  1000

#if 0
#define CFG_REFCLKFREQ		24000000	/* 24 MHz */

#define CFG_HZ			2000
//#define CFG_CLK			CFG_CLK_650_187_375
//#define CFG_PHY_CLOCK		125000000	/* 125 MHz*/
//#define CFG_GEM0_CLOCK		 25000000	/*  25 MHz*/
//#define CFG_GEM1_CLOCK		 25000000	/*  25 MHz*/
#endif

/*
 * Initial stack configuration
 */
#define CFG_INIT_RAM_ADDR	0x83000000	//0x0A000000 /* ARAM_BASEADDR Base address */
#define CFG_INIT_RAM_END	0x00020000 /* 128K */
#define CFG_ARAM_CODE_SIZE	0x00010000 /* 64K */

#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET - CFG_ARAM_CODE_SIZE


/*
 * Malloc/stack configuration
 */
#define CONFIG_SYS_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
#define CFG_MALLOC_LEN		(CFG_ENV_SIZE + 128 * 1024)
#define	CONFIG_SYS_GBL_DATA_SIZE	128
#define CFG_GBL_DATA_SIZE	128	/* size in bytes reserved for initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)

#define CONFIG_STACKSIZE	(32 * 1024)	/* regular stack */

#ifdef CONFIG_USE_IRQ
#error CONFIG_USE_IRQ not supported
#endif

#endif /* __CONFIG_H */