diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib.c b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib.c
index 766ec4d..f0ef953 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib.c
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvLib.c
@@ -153,8 +153,10 @@
 	MV_U32 norDev	= 0xFFFFFFFF;
 	MV_U32 syncCtrl	= 0;
 	MV_BOARD_BOOT_SRC bootSrc;
+	MV_U32 boardId  = 0;
 
-	mvBoardSet(mvBoardIdGet());
+	boardId = mvBoardIdGet();
+	mvBoardSet(boardId);
 	if (mvBoardConfigAutoDetectEnabled())
 		mvBoardModuleAutoDetect();
 	bootSrc = mvBoardBootDeviceGroupSet();
@@ -207,12 +209,34 @@
 
 	/* take PHYs & MMC out of reset */
 	udelay(1000);
-	MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT12);	// PCIe0_RESET_n
-	MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT17);	// 88E1322_RST_L
-	MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT20);	// MCU_RST#
-	MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT29);	// 88x3220_RST_n
-	MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), BIT0);	// 88x2011_RST_n
-	MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), BIT15);	// SD_RST_n
+	if (boardId == A38X_GFCH100_ID) {
+		/* Hardware revision 1.0 */
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT12);	// PCIe0_RESET_n
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT17);	// 88E1322_RST_L
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT20);	// MCU_RST#
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT29);	// 88x3220_RST_n
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), BIT0);	// 88x2011_RST_n
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), BIT15);	// SD_RST_n
+	} else if (boardId == A38X_GFCH100_UNKNOWN_ID) {
+		/* Unknown board type, don't take anything out of reset */
+		mvOsPrintf("board A38X_GFCH100_UNKNOWN_ID - minimal initialization\n");
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT17);	// 88E1322_RST_L
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT20);	// MCU_RST#
+	} else if (boardId == A38X_GFCH100_12A_ID) {
+		/* TODO(poist) take devices out of reset. */
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT20);	// MCU_RST#
+	} else if (boardId == A38X_GFCH100_12B_ID) {
+		/* TODO(poist) take devices out of reset. */
+		mvOsPrintf("board A38X_GFCH100_12B_ID - initialized\n");
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT10);	// TPM_RESETn
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT12);	// I2C_SFPMUX_RESET_n
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT17);	// 88E1322_RST_L
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT20);	// MCU_RST#
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT30);	// 3240(QPHY)_RESET_n
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(0), BIT31);	// I2C_IO_RESET_n
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), BIT0);	// 88x2011_RST_n
+		MV_REG_BIT_SET(GPP_DATA_OUT_REG(1), BIT3);	// I2C SW RESET
+	}
 #endif
 
 	/* Call callback function for board specific post GPP configuration */
@@ -2245,6 +2269,18 @@
 	#elif CONFIG_GFCH100
 		gBoardId = GFCH100_ID;
 	#endif
+#ifdef CONFIG_GFCH100
+	// TODO(nealo): Remove when Chimera 1.0 cards are decommissioned.
+	// Differentiate between 1.0 and 1.2 boards by examining GPIO14's
+	// initial input value.  On 1.2 boards this pin is pulled up. On
+	// 1.0 boards it is tied directly to the K60 (without a pullup
+	// or pulldown) and in limited testing is always low when sampled
+	// here (before the K60 is enabled).
+	u32 gpio_lo = MV_REG_READ(GPP_DATA_IN_REG(0));
+	if (gpio_lo & BIT14) {
+		gBoardId = A38X_GFCH100_12A_ID;
+	}
+#endif
 #else /* !CONFIG_CUSTOMER_BOARD_SUPPORT */
 	/* Temporarily set generic board struct pointer, to set/get EEPROM i2c address, and read board ID */
 	board = marvellBoardInfoTbl[mvBoardIdIndexGet(MV_DEFAULT_BOARD_ID)];
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec.h b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec.h
index a6920a5..611a754 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec.h
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec.h
@@ -85,7 +85,10 @@
 #define A38X_CUSTOMER_BOARD_ID1			(A38X_CUTOMER_BOARD_ID_BASE + 1)
 #define A38X_CLEARFOG_BOARD_ID			(A38X_CUTOMER_BOARD_ID_BASE + 2)
 #define A38X_GFCH100_ID				(A38X_CUTOMER_BOARD_ID_BASE + 3)
-#define A38X_MV_MAX_CUSTOMER_BOARD_ID		(A38X_CUTOMER_BOARD_ID_BASE + 4)
+#define A38X_GFCH100_UNKNOWN_ID			(A38X_CUTOMER_BOARD_ID_BASE + 4)
+#define A38X_GFCH100_12A_ID			(A38X_CUTOMER_BOARD_ID_BASE + 5)
+#define A38X_GFCH100_12B_ID			(A38X_CUTOMER_BOARD_ID_BASE + 6)
+#define A38X_MV_MAX_CUSTOMER_BOARD_ID		(A38X_CUTOMER_BOARD_ID_BASE + 7)
 #define A38X_MV_CUSTOMER_BOARD_NUM		(A38X_MV_MAX_CUSTOMER_BOARD_ID - A38X_CUTOMER_BOARD_ID_BASE)
 
 /* Armada-38x Marvell boards */
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.c b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.c
index a5e1e4d..cd4facd 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.c
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.c
@@ -537,13 +537,13 @@
 MV_BOARD_MAC_INFO armada_38x_gfch100_BoardMacInfo[] = {
 	/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
 	   MV_32 boardEthSmiAddr0 , MV_BOOL boardMacEnabled;}} */
-	{ BOARD_MAC_SPEED_1000M, -1, -1, MV_TRUE},	/* switch, no phy, no addr */
+	{ BOARD_MAC_SPEED_1000M, -1,  -1, MV_TRUE},	/* switch, no phy, no addr */
 	{ BOARD_MAC_SPEED_AUTO, 0x3, 0x0, MV_TRUE},	/* craft, phy port 3, no addr */
 };
 
 MV_DEV_CS_INFO armada_38x_gfch100_BoardDeCsInfo[] = {
 	/*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
-	{ SPI0_CS0,		N_A, BOARD_DEV_SPI_FLASH,	8,	8,	0,	MV_TRUE },	/* SPI0 DEV */
+	{ SPI0_CS0,	N_A, BOARD_DEV_SPI_FLASH,	8,	8,	0,	MV_TRUE },	/* SPI0 DEV */
 };
 
 MV_BOARD_MPP_INFO armada_38x_gfch100_BoardMppConfigValue[] = {
@@ -637,6 +637,331 @@
 	.boardOptionsModule		= MV_MODULE_NO_MODULE,
 };
 
+/*******************************************************************************
+ * A38x GFCH100 UNKNOWN
+ *******************************************************************************/
+/* Use same NAND and NOR configurations as 1.0 board */
+
+MV_BOARD_MAC_INFO armada_38x_gfch100_unknown_BoardMacInfo[] = {
+	/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+	   MV_32 boardEthSmiAddr0 , MV_BOOL boardMacEnabled;}} */
+	{ BOARD_MAC_SPEED_1000M, -1,  -1, MV_TRUE},	/* switch, no phy, no addr */
+	{ BOARD_MAC_SPEED_AUTO, 0x3, 0x0, MV_TRUE},	/* craft, phy port 3, no addr */
+};
+
+MV_DEV_CS_INFO armada_38x_gfch100_unknown_BoardDeCsInfo[] = {
+	/*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
+	{ SPI0_CS0,	N_A, BOARD_DEV_SPI_FLASH,	8,	8,	0,	MV_TRUE },	/* SPI0 DEV */
+};
+
+MV_BOARD_MPP_INFO armada_38x_gfch100_unknown_BoardMppConfigValue[] = {
+	{ {
+		A38x_GFCH100_UNKNOWN_MPP0_7,
+		A38x_GFCH100_UNKNOWN_MPP8_15,
+		A38x_GFCH100_UNKNOWN_MPP16_23,
+		A38x_GFCH100_UNKNOWN_MPP24_31,
+		A38x_GFCH100_UNKNOWN_MPP32_39,
+		A38x_GFCH100_UNKNOWN_MPP40_47,
+		A38x_GFCH100_UNKNOWN_MPP48_55,
+		A38x_GFCH100_UNKNOWN_MPP56_63,
+	} }
+};
+
+struct MV_BOARD_IO_EXPANDER armada_38x_gfch100_unknown_IoExpanderInfo[] = {
+	{0, 6, 0xF4}, /* Configuration registers: Bit on --> Input bits  */
+	{0, 7, 0xC3}, /* Configuration registers: Bit on --> Input bits  */
+	{0, 2, 0x0B}, /* Output Data, register#0 */
+	{0, 3, 0x18}, /* Output Data, register#1 */
+	{1, 6, 0xE7}, /* Configuration registers: Bit on --> Input bits  */
+	{1, 7, 0xF9}, /* Configuration registers: Bit on --> Input bits  */
+	{1, 2, 0x08}, /* Output Data, register#0 */
+	{1, 3, 0x00}  /* Output Data, register#1 */
+};
+
+MV_BOARD_USB_INFO armada_38x_gfch100_unknown_UsbInfo[] = {
+/* {MV_UNIT_ID usbType, MV_U8 usbPortNum, MV_BOOL isActive} */
+	{ USB_UNIT_ID,  0, MV_TRUE},
+	{ USB_UNIT_ID,  1, MV_TRUE},
+};
+
+MV_BOARD_INFO armada_38x_gfch100_unknown_info = {
+	.boardName			= "A38x-gfch100-unknown",
+	.numBoardNetComplexValue	= 0,
+	.pBoardNetComplexInfo		= NULL,
+	.pBoardMppConfigValue		= armada_38x_gfch100_unknown_BoardMppConfigValue,
+	.intsGppMaskLow			= 0,
+	.intsGppMaskMid			= 0,
+	.intsGppMaskHigh		= 0,
+	.numBoardDeviceIf		= ARRSZ(armada_38x_gfch100_unknown_BoardDeCsInfo),
+	.pDevCsInfo			= armada_38x_gfch100_unknown_BoardDeCsInfo,
+	.numBoardTwsiDev		= 0,
+	.pBoardTwsiDev			= NULL,
+	.numBoardMacInfo		= ARRSZ(armada_38x_gfch100_unknown_BoardMacInfo),
+	.pBoardMacInfo			= armada_38x_gfch100_unknown_BoardMacInfo,
+	.numBoardGppInfo		= 0,
+	.pBoardGppInfo			= 0,
+	.activeLedsNumber		= 0,
+	.pLedGppPin			= NULL,
+	.ledsPolarity			= 0,
+
+	/* PMU Power */
+	.pmuPwrUpPolarity		= 0,
+	.pmuPwrUpDelay			= 80000,
+
+	/* GPP values */
+	.gppOutEnValLow			= A38x_GFCH100_UNKNOWN_GPP_OUT_ENA_LOW,
+	.gppOutEnValMid			= A38x_GFCH100_UNKNOWN_GPP_OUT_ENA_MID,
+	.gppOutValLow			= A38x_GFCH100_UNKNOWN_GPP_OUT_VAL_LOW,
+	.gppOutValMid			= A38x_GFCH100_UNKNOWN_GPP_OUT_VAL_MID,
+	.gppPolarityValLow		= A38x_GFCH100_UNKNOWN_GPP_POL_LOW,
+	.gppPolarityValMid		= A38x_GFCH100_UNKNOWN_GPP_POL_MID,
+
+	/* TDM */
+	.numBoardTdmInfo		= {},
+	.pBoardTdmInt2CsInfo		= {},
+	.boardTdmInfoIndex		= -1,
+
+	.pBoardSpecInit			= NULL,
+
+	/* USB */
+	.numBoardUsbInfo		= ARRSZ(armada_38x_gfch100_unknown_UsbInfo),
+	.pBoardUsbInfo			= armada_38x_gfch100_unknown_UsbInfo,
+
+	/* NAND init params */
+	.nandFlashReadParams		= A38x_GFCH100_NAND_READ_PARAMS,
+	.nandFlashWriteParams		= A38x_GFCH100_NAND_WRITE_PARAMS,
+	.nandFlashControl		= A38x_GFCH100_NAND_CONTROL,
+	.nandIfMode			= NAND_IF_NFC,
+
+	.isSdMmcConnected		= MV_TRUE,
+
+	/* NOR init params */
+	.norFlashReadParams		= A38x_GFCH100_NOR_READ_PARAMS,
+	.norFlashWriteParams		= A38x_GFCH100_NOR_WRITE_PARAMS,
+	/* Enable modules auto-detection. */
+	.configAutoDetect		= MV_FALSE,
+	.numIoExp			= ARRSZ(armada_38x_gfch100_unknown_IoExpanderInfo),
+	.pIoExp				= armada_38x_gfch100_unknown_IoExpanderInfo,
+	.boardOptionsModule		= MV_MODULE_NO_MODULE,
+};
+
+/*******************************************************************************
+ * A38x GFCH100 1.2a
+ *******************************************************************************/
+/* Use same NAND and NOR configurations as 1.0 board */
+
+MV_BOARD_MAC_INFO armada_38x_gfch100_12a_BoardMacInfo[] = {
+	/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+	   MV_32 boardEthSmiAddr0 , MV_BOOL boardMacEnabled;}} */
+	{ BOARD_MAC_SPEED_1000M, -1,  -1, MV_TRUE},	/* switch, no phy, no addr */
+	{ BOARD_MAC_SPEED_AUTO, 0x3, 0x0, MV_TRUE},	/* craft, phy port 3, no addr */
+};
+
+MV_DEV_CS_INFO armada_38x_gfch100_12a_BoardDeCsInfo[] = {
+	/*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
+	{ SPI0_CS0,	N_A, BOARD_DEV_SPI_FLASH,	8,	8,	0,	MV_TRUE },	/* SPI0 DEV */
+};
+
+MV_BOARD_MPP_INFO armada_38x_gfch100_12a_BoardMppConfigValue[] = {
+	{ {
+		A38x_GFCH100_12A_MPP0_7,
+		A38x_GFCH100_12A_MPP8_15,
+		A38x_GFCH100_12A_MPP16_23,
+		A38x_GFCH100_12A_MPP24_31,
+		A38x_GFCH100_12A_MPP32_39,
+		A38x_GFCH100_12A_MPP40_47,
+		A38x_GFCH100_12A_MPP48_55,
+		A38x_GFCH100_12A_MPP56_63,
+	} }
+};
+
+struct MV_BOARD_IO_EXPANDER armada_38x_gfch100_12a_IoExpanderInfo[] = {
+	{0, 6, 0xF4}, /* Configuration registers: Bit on --> Input bits  */
+	{0, 7, 0xC3}, /* Configuration registers: Bit on --> Input bits  */
+	{0, 2, 0x0B}, /* Output Data, register#0 */
+	{0, 3, 0x18}, /* Output Data, register#1 */
+	{1, 6, 0xE7}, /* Configuration registers: Bit on --> Input bits  */
+	{1, 7, 0xF9}, /* Configuration registers: Bit on --> Input bits  */
+	{1, 2, 0x08}, /* Output Data, register#0 */
+	{1, 3, 0x00}  /* Output Data, register#1 */
+};
+
+MV_BOARD_USB_INFO armada_38x_gfch100_12a_UsbInfo[] = {
+/* {MV_UNIT_ID usbType, MV_U8 usbPortNum, MV_BOOL isActive} */
+	{ USB_UNIT_ID,  0, MV_TRUE},
+	{ USB_UNIT_ID,  1, MV_TRUE},
+};
+
+MV_BOARD_INFO armada_38x_gfch100_12a_info = {
+	.boardName			= "A38x-gfch100-12a",
+	.numBoardNetComplexValue	= 0,
+	.pBoardNetComplexInfo		= NULL,
+	.pBoardMppConfigValue		= armada_38x_gfch100_12a_BoardMppConfigValue,
+	.intsGppMaskLow			= 0,
+	.intsGppMaskMid			= 0,
+	.intsGppMaskHigh		= 0,
+	.numBoardDeviceIf		= ARRSZ(armada_38x_gfch100_12a_BoardDeCsInfo),
+	.pDevCsInfo			= armada_38x_gfch100_12a_BoardDeCsInfo,
+	.numBoardTwsiDev		= 0,
+	.pBoardTwsiDev			= NULL,
+	.numBoardMacInfo		= ARRSZ(armada_38x_gfch100_12a_BoardMacInfo),
+	.pBoardMacInfo			= armada_38x_gfch100_12a_BoardMacInfo,
+	.numBoardGppInfo		= 0,
+	.pBoardGppInfo			= 0,
+	.activeLedsNumber		= 0,
+	.pLedGppPin			= NULL,
+	.ledsPolarity			= 0,
+
+	/* PMU Power */
+	.pmuPwrUpPolarity		= 0,
+	.pmuPwrUpDelay			= 80000,
+
+	/* GPP values */
+	.gppOutEnValLow			= A38x_GFCH100_12A_GPP_OUT_ENA_LOW,
+	.gppOutEnValMid			= A38x_GFCH100_12A_GPP_OUT_ENA_MID,
+	.gppOutValLow			= A38x_GFCH100_12A_GPP_OUT_VAL_LOW,
+	.gppOutValMid			= A38x_GFCH100_12A_GPP_OUT_VAL_MID,
+	.gppPolarityValLow		= A38x_GFCH100_12A_GPP_POL_LOW,
+	.gppPolarityValMid		= A38x_GFCH100_12A_GPP_POL_MID,
+
+	/* TDM */
+	.numBoardTdmInfo		= {},
+	.pBoardTdmInt2CsInfo		= {},
+	.boardTdmInfoIndex		= -1,
+
+	.pBoardSpecInit			= NULL,
+
+	/* USB */
+	.numBoardUsbInfo		= ARRSZ(armada_38x_gfch100_12a_UsbInfo),
+	.pBoardUsbInfo			= armada_38x_gfch100_12a_UsbInfo,
+
+	/* NAND init params */
+	.nandFlashReadParams		= A38x_GFCH100_NAND_READ_PARAMS,
+	.nandFlashWriteParams		= A38x_GFCH100_NAND_WRITE_PARAMS,
+	.nandFlashControl		= A38x_GFCH100_NAND_CONTROL,
+	.nandIfMode			= NAND_IF_NFC,
+
+	.isSdMmcConnected		= MV_TRUE,
+
+	/* NOR init params */
+	.norFlashReadParams		= A38x_GFCH100_NOR_READ_PARAMS,
+	.norFlashWriteParams		= A38x_GFCH100_NOR_WRITE_PARAMS,
+	/* Enable modules auto-detection. */
+	.configAutoDetect		= MV_FALSE,
+	.numIoExp			= ARRSZ(armada_38x_gfch100_12a_IoExpanderInfo),
+	.pIoExp				= armada_38x_gfch100_12a_IoExpanderInfo,
+	.boardOptionsModule		= MV_MODULE_NO_MODULE,
+};
+
+/*******************************************************************************
+ * A38x GFCH100 1.2b
+ *******************************************************************************/
+/* Use same NAND and NOR configurations as 1.0 board */
+
+MV_BOARD_MAC_INFO armada_38x_gfch100_12b_BoardMacInfo[] = {
+	/* {{MV_BOARD_MAC_SPEED boardMacSpeed, MV_32 boardEthSmiAddr ,
+	   MV_32 boardEthSmiAddr0 , MV_BOOL boardMacEnabled;}} */
+	{ BOARD_MAC_SPEED_1000M, -1,  -1, MV_TRUE},	/* switch, no phy, no addr */
+	{ BOARD_MAC_SPEED_AUTO, 0x3, 0x0, MV_TRUE},	/* craft, phy port 3, no addr */
+};
+
+MV_DEV_CS_INFO armada_38x_gfch100_12b_BoardDeCsInfo[] = {
+	/*{deviceCS, params, devType, devWidth, busWidth, busNum, active }*/
+	{ SPI0_CS0,	N_A, BOARD_DEV_SPI_FLASH,	8,	8,	0,	MV_TRUE },	/* SPI0 DEV */
+};
+
+MV_BOARD_MPP_INFO armada_38x_gfch100_12b_BoardMppConfigValue[] = {
+	{ {
+		A38x_GFCH100_12B_MPP0_7,
+		A38x_GFCH100_12B_MPP8_15,
+		A38x_GFCH100_12B_MPP16_23,
+		A38x_GFCH100_12B_MPP24_31,
+		A38x_GFCH100_12B_MPP32_39,
+		A38x_GFCH100_12B_MPP40_47,
+		A38x_GFCH100_12B_MPP48_55,
+		A38x_GFCH100_12B_MPP56_63,
+	} }
+};
+
+struct MV_BOARD_IO_EXPANDER armada_38x_gfch100_12b_IoExpanderInfo[] = {
+	{0, 6, 0xF4}, /* Configuration registers: Bit on --> Input bits  */
+	{0, 7, 0xC3}, /* Configuration registers: Bit on --> Input bits  */
+	{0, 2, 0x0B}, /* Output Data, register#0 */
+	{0, 3, 0x18}, /* Output Data, register#1 */
+	{1, 6, 0xE7}, /* Configuration registers: Bit on --> Input bits  */
+	{1, 7, 0xF9}, /* Configuration registers: Bit on --> Input bits  */
+	{1, 2, 0x08}, /* Output Data, register#0 */
+	{1, 3, 0x00}  /* Output Data, register#1 */
+};
+
+MV_BOARD_USB_INFO armada_38x_gfch100_12b_UsbInfo[] = {
+/* {MV_UNIT_ID usbType, MV_U8 usbPortNum, MV_BOOL isActive} */
+	{ USB_UNIT_ID,  0, MV_TRUE},
+	{ USB_UNIT_ID,  1, MV_TRUE},
+};
+
+MV_BOARD_INFO armada_38x_gfch100_12b_info = {
+	.boardName			= "A38x-gfch100-12b",
+	.numBoardNetComplexValue	= 0,
+	.pBoardNetComplexInfo		= NULL,
+	.pBoardMppConfigValue		= armada_38x_gfch100_12b_BoardMppConfigValue,
+	.intsGppMaskLow			= 0,
+	.intsGppMaskMid			= 0,
+	.intsGppMaskHigh		= 0,
+	.numBoardDeviceIf		= ARRSZ(armada_38x_gfch100_12b_BoardDeCsInfo),
+	.pDevCsInfo			= armada_38x_gfch100_12b_BoardDeCsInfo,
+	.numBoardTwsiDev		= 0,
+	.pBoardTwsiDev			= NULL,
+	.numBoardMacInfo		= ARRSZ(armada_38x_gfch100_12b_BoardMacInfo),
+	.pBoardMacInfo			= armada_38x_gfch100_12b_BoardMacInfo,
+	.numBoardGppInfo		= 0,
+	.pBoardGppInfo			= 0,
+	.activeLedsNumber		= 0,
+	.pLedGppPin			= NULL,
+	.ledsPolarity			= 0,
+
+	/* PMU Power */
+	.pmuPwrUpPolarity		= 0,
+	.pmuPwrUpDelay			= 80000,
+
+	/* GPP values */
+	.gppOutEnValLow			= A38x_GFCH100_12B_GPP_OUT_ENA_LOW,
+	.gppOutEnValMid			= A38x_GFCH100_12B_GPP_OUT_ENA_MID,
+	.gppOutValLow			= A38x_GFCH100_12B_GPP_OUT_VAL_LOW,
+	.gppOutValMid			= A38x_GFCH100_12B_GPP_OUT_VAL_MID,
+	.gppPolarityValLow		= A38x_GFCH100_12B_GPP_POL_LOW,
+	.gppPolarityValMid		= A38x_GFCH100_12B_GPP_POL_MID,
+
+	/* TDM */
+	.numBoardTdmInfo		= {},
+	.pBoardTdmInt2CsInfo		= {},
+	.boardTdmInfoIndex		= -1,
+
+	.pBoardSpecInit			= NULL,
+
+	/* USB */
+	.numBoardUsbInfo		= ARRSZ(armada_38x_gfch100_12b_UsbInfo),
+	.pBoardUsbInfo			= armada_38x_gfch100_12b_UsbInfo,
+
+	/* NAND init params */
+	.nandFlashReadParams		= A38x_GFCH100_NAND_READ_PARAMS,
+	.nandFlashWriteParams		= A38x_GFCH100_NAND_WRITE_PARAMS,
+	.nandFlashControl		= A38x_GFCH100_NAND_CONTROL,
+	.nandIfMode			= NAND_IF_NFC,
+
+	.isSdMmcConnected		= MV_TRUE,
+
+	/* NOR init params */
+	.norFlashReadParams		= A38x_GFCH100_NOR_READ_PARAMS,
+	.norFlashWriteParams		= A38x_GFCH100_NOR_WRITE_PARAMS,
+	/* Enable modules auto-detection. */
+	.configAutoDetect		= MV_FALSE,
+	.numIoExp			= ARRSZ(armada_38x_gfch100_12b_IoExpanderInfo),
+	.pIoExp				= armada_38x_gfch100_12b_IoExpanderInfo,
+	.boardOptionsModule		= MV_MODULE_NO_MODULE,
+};
+
+
 /*
  * All supported A380 customer boards
  */
@@ -645,6 +970,9 @@
 	&armada_38x_customer_board_1_info,
 	&armada_38x_clearfog_board_info,
 	&armada_38x_gfch100_info,
+	&armada_38x_gfch100_unknown_info,
+	&armada_38x_gfch100_12a_info,
+	&armada_38x_gfch100_12b_info,
 };
 
 
diff --git a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.h b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.h
index eeb5868..b23d425 100644
--- a/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.h
+++ b/board/mv_ebu/a38x/armada_38x_family/boardEnv/mvBoardEnvSpec38x.h
@@ -163,6 +163,70 @@
 #define A38x_GFCH100_GPP_POL_LOW	0x0
 #define A38x_GFCH100_GPP_POL_MID	0x0
 
+/*******************************************************************************
+ * A38X_GFCH100_UNKNOWN_ID GFCH100 unknown
+ *******************************************************************************/
+/* see 88F6810_MPP_information.xls */
+/* see https://goto.google.com/chimerampp */
+#define A38x_GFCH100_UNKNOWN_MPP0_7		0x00110011
+#define A38x_GFCH100_UNKNOWN_MPP8_15		0x00000000
+#define A38x_GFCH100_UNKNOWN_MPP16_23		0x11100000
+#define A38x_GFCH100_UNKNOWN_MPP24_31		0x00000011
+#define A38x_GFCH100_UNKNOWN_MPP32_39		0x00000000
+#define A38x_GFCH100_UNKNOWN_MPP40_47		0x00000000
+#define A38x_GFCH100_UNKNOWN_MPP48_55		0x55550555
+#define A38x_GFCH100_UNKNOWN_MPP56_63		0x00005550
+
+#define A38x_GFCH100_UNKNOWN_GPP_OUT_ENA_LOW	(~(BIT17|BIT20))	/*0-31*/
+#define A38x_GFCH100_UNKNOWN_GPP_OUT_ENA_MID	0		/* 32-59 */
+#define A38x_GFCH100_UNKNOWN_GPP_OUT_VAL_LOW	0		/* 0-31 */
+#define A38x_GFCH100_UNKNOWN_GPP_OUT_VAL_MID	0		/* 32-59 */
+#define A38x_GFCH100_UNKNOWN_GPP_POL_LOW	0x0
+#define A38x_GFCH100_UNKNOWN_GPP_POL_MID	0x0
+
+
+/*******************************************************************************
+ * A38X_GFCH100_12A_ID
+ *******************************************************************************/
+/* see 88F6810_MPP_information.xls */
+/* see https://goto.google.com/chimerampp */
+#define A38x_GFCH100_12A_MPP0_7			0x00111111
+#define A38x_GFCH100_12A_MPP8_15		0x00000000
+#define A38x_GFCH100_12A_MPP16_23		0x11100000
+#define A38x_GFCH100_12A_MPP24_31		0x00003311
+#define A38x_GFCH100_12A_MPP32_39		0x00000000
+#define A38x_GFCH100_12A_MPP40_47		0x00000110
+#define A38x_GFCH100_12A_MPP48_55		0x55550555
+#define A38x_GFCH100_12A_MPP56_63		0x00005550
+
+#define A38x_GFCH100_12A_GPP_OUT_ENA_LOW	0x1FE9E97F	/*0-31*/
+#define A38x_GFCH100_12A_GPP_OUT_ENA_MID	0xFFFF67E4	/* 32-59 */
+#define A38x_GFCH100_12A_GPP_OUT_VAL_LOW	0xC0021000	/* 0-31 */
+#define A38x_GFCH100_12A_GPP_OUT_VAL_MID	0x00001010	/* 32-59 */
+#define A38x_GFCH100_12A_GPP_POL_LOW		0x0
+#define A38x_GFCH100_12A_GPP_POL_MID		0x0
+
+/*******************************************************************************
+ * A38X_GFCH100_12B_ID
+ *******************************************************************************/
+/* see 88F6810_MPP_information.xls */
+/* see https://goto.google.com/chimerampp */
+#define A38x_GFCH100_12B_MPP0_7			0x00111111
+#define A38x_GFCH100_12B_MPP8_15		0x00000000
+#define A38x_GFCH100_12B_MPP16_23		0x11100000
+#define A38x_GFCH100_12B_MPP24_31		0x00003311
+#define A38x_GFCH100_12B_MPP32_39		0x00000000
+#define A38x_GFCH100_12B_MPP40_47		0x00000110
+#define A38x_GFCH100_12B_MPP48_55		0x55550555
+#define A38x_GFCH100_12B_MPP56_63		0x00005550
+
+#define A38x_GFCH100_12B_GPP_OUT_ENA_LOW	(~(BIT7|BIT8|BIT10|BIT12|BIT17|BIT20|BIT30|BIT31))	/*0-31*/
+#define A38x_GFCH100_12B_GPP_OUT_ENA_MID	(~(BIT0|BIT1|BIT3|BIT11|BIT12|BIT15))	/* 32-59 */
+#define A38x_GFCH100_12B_GPP_OUT_VAL_LOW	(BIT8)		/* 0-31 */
+#define A38x_GFCH100_12B_GPP_OUT_VAL_MID	(BIT11)		/* 32-59 */
+#define A38x_GFCH100_12B_GPP_POL_LOW		0x0
+#define A38x_GFCH100_12B_GPP_POL_MID		0x0
+
 /******************************* Marvell Boards *******************************/
 
 /*******************************************************************************
diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_topology.h b/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_topology.h
index 3ac5580..1171ead 100755
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_topology.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_topology.h
@@ -134,6 +134,27 @@
     /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_device_width  mem_size     frequency  casL casWL      temperature */
 	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1600K, BUS_WIDTH_8 , MEM_2G, DDR_FREQ_400, 0 ,   0 , MV_HWS_TEMP_LOW}},
     INTERFACE_BUS_MASK_32BIT_ECC  /* Buses mask */
+    },
+    /* GFCH100 UNKNOWN */
+    {
+    0x1, /* active interfaces */
+    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_device_width  mem_size     frequency  casL casWL      temperature */
+	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1600K, BUS_WIDTH_8 , MEM_2G, DDR_FREQ_400, 0 ,   0 , MV_HWS_TEMP_LOW}},
+    INTERFACE_BUS_MASK_32BIT_ECC  /* Buses mask */
+    },
+    /* GFCH100 1.2A */
+    {
+    0x1, /* active interfaces */
+    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_device_width  mem_size     frequency  casL casWL      temperature */
+	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1600K, BUS_WIDTH_8 , MEM_2G, DDR_FREQ_400, 0 ,   0 , MV_HWS_TEMP_LOW}},
+    INTERFACE_BUS_MASK_32BIT_ECC  /* Buses mask */
+    },
+    /* GFCH100 1.2B */
+    {
+    0x1, /* active interfaces */
+    /*cs_mask, mirror, dqs_swap, ck_swap X PUPs                                     speed_bin             memory_device_width  mem_size     frequency  casL casWL      temperature */
+	{{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1600K, BUS_WIDTH_8 , MEM_2G, DDR_FREQ_400, 0 ,   0 , MV_HWS_TEMP_LOW}},
+    INTERFACE_BUS_MASK_32BIT_ECC  /* Buses mask */
     }
 };
 
diff --git a/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_vars.h b/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_vars.h
index 7b51135..ff81a31 100755
--- a/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_vars.h
+++ b/tools/marvell/bin_hdr/inc/ddr3_soc/a38x/ddr3_a38x_vars.h
@@ -88,6 +88,9 @@
 	{"a38x_customer_0_800",	DDR_FREQ_800,	0,	0x0,	A38X_CUSTOMER_BOARD_ID0,	ddr3_customer_800},
 	{"a38x_customer_1_800",	DDR_FREQ_800,	0,	0x0,	A38X_CUSTOMER_BOARD_ID1,	ddr3_customer_800},
 	{"gfch100",		DDR_FREQ_800,	0,	0x0,	GFCH100_ID,			ddr3_customer_800},
+	{"gfch100-unknown",	DDR_FREQ_800,	0,	0x0,	A38X_GFCH100_UNKNOWN_ID,	ddr3_customer_800},
+	{"gfch100-12a",		DDR_FREQ_800,	0,	0x0,	A38X_GFCH100_12A_ID,		ddr3_customer_800},
+	{"gfch100-12b",		DDR_FREQ_800,	0,	0x0,	A38X_GFCH100_12B_ID,		ddr3_customer_800},
 #else
 	{"a38x_533",		DDR_FREQ_533,	0,	0x0,		MARVELL_BOARD,		ddr3_a38x_533},
 	{"a38x_667",		DDR_FREQ_667,	0,	0x0,		MARVELL_BOARD,		ddr3_a38x_667},
diff --git a/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.c b/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.c
index 0b6a6d3..d46d26d 100755
--- a/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.c
+++ b/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.c
@@ -332,6 +332,7 @@
 	#elif CONFIG_CLEARFOG_BOARD
 		gBoardId = A38X_CLEARFOG_BOARD_ID;
 	#elif CONFIG_GFCH100
+		/* All GFCH100 board variants use the same SERDES/RAM config */
 		gBoardId = GFCH100_ID;
 	#endif
 #else
diff --git a/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.h b/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.h
index 5829e32..d2d7cb2 100755
--- a/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.h
+++ b/tools/marvell/bin_hdr/platform/sysEnv/a38x/mvSysEnvLib.h
@@ -299,6 +299,7 @@
 #define A38X_CUSTOMER_BOARD_ID1			(A38X_CUSTOMER_BOARD_ID_BASE + 1)
 #define A38X_CLEARFOG_BOARD_ID			(A38X_CUSTOMER_BOARD_ID_BASE + 2)
 #define A38X_GFCH100_ID				(A38X_CUSTOMER_BOARD_ID_BASE + 3)
+/* GFCH100 1.0, 1.2a, 1.2b all use the same SERDES/RAM config. */
 #define A38X_MV_MAX_CUSTOMER_BOARD_ID		(A38X_CUSTOMER_BOARD_ID_BASE + 4)
 #define A38X_MV_CUSTOMER_BOARD_NUM		(A38X_MV_MAX_CUSTOMER_BOARD_ID - A38X_CUSTOMER_BOARD_ID_BASE)
 
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Os/gtOs/mvXor.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Os/gtOs/mvXor.c
index 0541982..2cb0b5b 100755
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Os/gtOs/mvXor.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Os/gtOs/mvXor.c
@@ -543,7 +543,7 @@
         ecc_configuration.tClkTicks = 0;           /* not enabled */
         ecc_configuration.sectorSize = 30;         /* 1GB sector size */
 
-        GT_STATUS status = mvXorEccClean(0, &ecc_configuration);
+        mvXorEccClean(0, &ecc_configuration);
         while (mvXorStateGet(0) != MV_IDLE);
     }
 
diff --git a/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c b/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
index c267219..5d4e4c2 100755
--- a/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
+++ b/tools/marvell/bin_hdr/src_phy/a38x/mvHighSpeedTopologySpec-38x.c
@@ -104,6 +104,7 @@
 },
 {
 	/* GFCH100 Topology */
+	/* All CFCH100 board variants use the same SERDES configuration */
 	{ SGMII0,		__1_25Gbps,	SERDES_DEFAULT_MODE,		MV_FALSE,	MV_FALSE },
 	{ PEX0,			__2_5Gbps,	PEX_ROOT_COMPLEX_x1,		MV_FALSE,	MV_FALSE },
 	{ SGMII1,		__1_25Gbps,	SERDES_DEFAULT_MODE,		MV_FALSE,	MV_FALSE },