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| *******************************************************************************/ |
| |
| #ifndef _INC_A38X_TOPOLOGY_H |
| #define _INC_A38X_TOPOLOGY_H |
| |
| #include "mvDdr3LoggingDef.h" |
| |
| /*Bus mask variants*/ |
| #define INTERFACE_BUS_MASK_32BIT 0xF |
| #define INTERFACE_BUS_MASK_32BIT_ECC 0x1F |
| #define INTERFACE_BUS_MASK_16BIT 0x3 |
| #define INTERFACE_BUS_MASK_16BIT_ECC 0x13 |
| #define INTERFACE_BUS_MASK_16BIT_ECC_PUP3 0xB |
| |
| #define DYNAMIC_CS_SIZE_CONFIG |
| #define DISABLE_L2_FILTERING_DURING_DDR_TRAINING |
| |
| #ifdef CONFIG_DDR3 |
| #define SPEED_BIN_DDR_CUST_BOARD_1 SPEED_BIN_DDR_1866L |
| #define BUS_WIDTH_CUST_BOARD_1 BUS_WIDTH_8 |
| #define SPEED_BIN_DDR_CUST_BOARD_2 SPEED_BIN_DDR_1866L |
| #define BUS_WIDTH_CUST_BOARD_2 BUS_WIDTH_8 |
| #define SPEED_BIN_DDR_CLEARFOG_BOARD SPEED_BIN_DDR_1600K |
| #define BUS_WIDTH_CLEARFOG_BOARD BUS_WIDTH_16 |
| |
| #define SPEED_BIN_DDR_DB_68XX SPEED_BIN_DDR_1866L |
| #define BUS_WIDTH_DB_68XX BUS_WIDTH_8 |
| #define SPEED_BIN_DDR_DB_BP_6821 SPEED_BIN_DDR_1866L |
| #define BUS_WIDTH_DB_BP_6821 BUS_WIDTH_8 |
| #else |
| /*Elpida by 16 is 2400R Micron by 8 is 2133P Samsung by 16 is 2133P Hynux by16 is 2133P*/ |
| #define SPEED_BIN_DDR_CUST_BOARD_1 SPEED_BIN_DDR_2400R |
| #define BUS_WIDTH_CUST_BOARD_1 BUS_WIDTH_16 |
| #define SPEED_BIN_DDR_CUST_BOARD_2 SPEED_BIN_DDR_2400R |
| #define BUS_WIDTH_CUST_BOARD_2 BUS_WIDTH_16 |
| |
| #define SPEED_BIN_DDR_DB_68XX SPEED_BIN_DDR_2400R |
| #define BUS_WIDTH_DB_68XX BUS_WIDTH_16 |
| #define SPEED_BIN_DDR_DB_BP_6821 SPEED_BIN_DDR_2400R |
| #define BUS_WIDTH_DB_BP_6821 BUS_WIDTH_16 |
| #endif |
| |
| |
| #ifdef CONFIG_CUSTOMER_BOARD_SUPPORT |
| /************************************* Customer Boards Topology *************************************/ |
| MV_HWS_TOPOLOGY_MAP TopologyMap[] = |
| { |
| /* 1st Customer board - reference from DB */ |
| { |
| 0x1, /* active interfaces */ |
| /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_device_width mem_size frequency casL casWL temperature */ |
| {{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_CUST_BOARD_1, BUS_WIDTH_CUST_BOARD_1 , MEM_4G, DDR_FREQ_800, 0 , 0 , MV_HWS_TEMP_LOW}}, |
| INTERFACE_BUS_MASK_32BIT /* Buses mask */ |
| }, |
| /* 2nd Customer board - GP Board*/ |
| { |
| 0x1, /* active interfaces */ |
| /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_device_width mem_size frequency casL casWL temperature */ |
| {{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_CUST_BOARD_2, BUS_WIDTH_CUST_BOARD_2 , MEM_4G, DDR_FREQ_800, 0 , 0 , MV_HWS_TEMP_LOW}}, |
| INTERFACE_BUS_MASK_32BIT /* Buses mask */ |
| }, |
| /* 3rd Customer board - SolidRun ClearFog-A1 REV2.0 */ |
| { |
| 0x1, /* active interfaces */ |
| /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_device_width mem_size frequency casL casWL temperature */ |
| {{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_CLEARFOG_BOARD, BUS_WIDTH_CLEARFOG_BOARD , MEM_4G, DDR_FREQ_800, 0 , 0 , MV_HWS_TEMP_LOW}}, |
| INTERFACE_BUS_MASK_32BIT /* Buses mask */ |
| }, |
| /* GFCH100 */ |
| { |
| 0x1, /* active interfaces */ |
| /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_device_width mem_size frequency casL casWL temperature */ |
| {{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1600K, BUS_WIDTH_8 , MEM_2G, DDR_FREQ_400, 0 , 0 , MV_HWS_TEMP_LOW}}, |
| INTERFACE_BUS_MASK_32BIT_ECC /* Buses mask */ |
| } |
| }; |
| |
| #else /* CONFIG_CUSTOMER_BOARD_SUPPORT */ |
| |
| /************************************* Marvell Boards Topology *************************************/ |
| MV_HWS_TOPOLOGY_MAP TopologyMap[] = |
| { |
| /* Marvell board - Board_ID = RD_NAS_68XX_ID = 0*/ |
| { |
| 0x1, /* active interfaces */ |
| /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_device_width mem_size frequency casL casWL temperature */ |
| {{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 , 0 , MV_HWS_TEMP_LOW}}, |
| INTERFACE_BUS_MASK_32BIT /* Buses mask */ |
| }, |
| /* Marvell board - Board_ID = DB_68XX_ID = 1 (DDR3/4)*/ |
| { |
| 0x1, /* active interfaces */ |
| /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_device_width mem_size frequency casL casWL temperature */ |
| {{{{0x3,2,0,0}, {0x3,2,0,0}, {0x3,2,0,0}, {0x3,2,0,0}, {0x3,2,0,0}}, SPEED_BIN_DDR_DB_68XX, BUS_WIDTH_DB_68XX , MEM_4G, DDR_FREQ_800, 0 , 0 , MV_HWS_TEMP_LOW}}, |
| INTERFACE_BUS_MASK_32BIT /* Buses mask */ |
| }, |
| /* Marvell board - Board_ID = RD_AP_68XX_ID = 2 */ |
| { |
| 0x1, /* active interfaces */ |
| /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_device_width mem_size frequency casL casWL temperature */ |
| {{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 , 0 , MV_HWS_TEMP_LOW}}, |
| INTERFACE_BUS_MASK_32BIT /* Buses mask */ |
| }, |
| /* Marvell board - Board_ID = DB_AP_68XX_ID = 3 */ |
| { |
| 0x1, /* active interfaces */ |
| /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_device_width mem_size frequency casL casWL temperature */ |
| {{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 , 0 , MV_HWS_TEMP_LOW}}, |
| INTERFACE_BUS_MASK_32BIT /* Buses mask */ |
| }, |
| /* Marvell board - Board_ID = DB_GP_68XX_ID = 4 */ |
| { |
| 0x1, /* active interfaces */ |
| /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_device_width mem_size frequency casL casWL temperature */ |
| {{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 , 0 , MV_HWS_TEMP_LOW}}, |
| INTERFACE_BUS_MASK_32BIT /* Buses mask */ |
| }, |
| /* Marvell board - Board_ID = DB_BP_6821_ID = 5 (DDR3/4) */ |
| { |
| 0x1, /* active interfaces */ |
| /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_device_width mem_size frequency casL casWL temperature */ |
| {{{{0x1,0x1,0,0}, {0x1,0x1,0,0}, {0x1,0x1,0,0}, {0x1,0x1,0,0}, {0x1,0x1,0,0}}, SPEED_BIN_DDR_DB_BP_6821, BUS_WIDTH_DB_BP_6821, MEM_4G, DDR_FREQ_800, 0 , 0 , MV_HWS_TEMP_LOW}}, |
| INTERFACE_BUS_MASK_16BIT /* Buses mask */ |
| }, |
| /* Marvell board - Board_ID = DB_AMC_6820_ID = 6 */ |
| { |
| 0x1, /* active interfaces */ |
| /*cs_mask, mirror, dqs_swap, ck_swap X PUPs speed_bin memory_device_width mem_size frequency casL casWL temperature */ |
| {{{{0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}, {0x1,0,0,0}}, SPEED_BIN_DDR_1866L, BUS_WIDTH_8 , MEM_4G, DDR_FREQ_800, 0 , 0 , MV_HWS_TEMP_LOW}}, |
| INTERFACE_BUS_MASK_32BIT /* Buses mask */ |
| }, |
| }; |
| #endif /* CONFIG_CUSTOMER_BOARD_SUPPORT */ |
| |
| #endif /* _INC_A38X_TOPOLOGY_H */ |
