diff --git a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c
index ddfaac4..64ab410 100644
--- a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c
@@ -2225,8 +2225,8 @@
 	MV_32 reg = 0;
 
 	/* Initiates TSEN hardware reset once */
-	if ((MV_REG_READ(TSEN_CONF_REG) & TSEN_CONF_RST_MASK) == 0)
-		MV_REG_BIT_SET(TSEN_CONF_REG, TSEN_CONF_RST_MASK);
+	if ((MV_REG_READ(TSEN_CONTROL_MSB_REG) & TSEN_CONTROL_MSB_RST_MASK) == 0)
+		MV_REG_BIT_SET(TSEN_CONTROL_MSB_REG, TSEN_CONTROL_MSB_RST_MASK);
 	mvOsDelay(10);
 
 	/* Check if the readout field is valid */
diff --git a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.h b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.h
index 93390b8..ccccf95 100644
--- a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.h
+++ b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.h
@@ -170,13 +170,11 @@
 
 
 /* Termal Sensor Registers */
-#define TSEN_STATE_REG						0xE4070
-#define TSEN_STATE_OFFSET					31
-#define TSEN_STATE_MASK						(0x1 << TSEN_STATE_OFFSET)
+#define TSEN_CONTROL_LSB_REG					0xE4070
 
-#define TSEN_CONF_REG						0xE4074
-#define TSEN_CONF_RST_OFFSET					8
-#define TSEN_CONF_RST_MASK					(0x1 << TSEN_CONF_RST_OFFSET)
+#define TSEN_CONTROL_MSB_REG					0xE4074
+#define TSEN_CONTROL_MSB_RST_OFFSET				8
+#define TSEN_CONTROL_MSB_RST_MASK				(0x1 << TSEN_CONTROL_MSB_RST_OFFSET)
 
 #define TSEN_STATUS_REG						0xE4078
 #define TSEN_STATUS_READOUT_VALID_OFFSET			10
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Silicon/mvHwsDdr3A38x.h b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Silicon/mvHwsDdr3A38x.h
index c6f3d61..e55296b 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Silicon/mvHwsDdr3A38x.h
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/h/Silicon/mvHwsDdr3A38x.h
@@ -38,12 +38,10 @@
 #define __mvHwsDdr3_A38x_H
 
 /* Termal Sensor Registers */
-#define TSEN_STATE_REG						0xE4070
-#define TSEN_STATE_OFFSET					31
-#define TSEN_STATE_MASK						(0x1 << TSEN_STATE_OFFSET)
-#define TSEN_CONF_REG						0xE4074
-#define TSEN_CONF_RST_OFFSET				8
-#define TSEN_CONF_RST_MASK					(0x1 << TSEN_CONF_RST_OFFSET)
+#define TSEN_CONTROL_LSB_REG					0xE4070
+#define TSEN_CONTROL_MSB_REG					0xE4074
+#define TSEN_CONTROL_MSB_RST_OFFSET				8
+#define TSEN_CONTROL_MSB_RST_MASK				(0x1 << TSEN_CONTROL_MSB_RST_OFFSET)
 #define TSEN_STATUS_REG						0xE4078
 #define TSEN_STATUS_READOUT_VALID_OFFSET	10
 #define TSEN_STATUS_READOUT_VALID_MASK		(0x1 << TSEN_STATUS_READOUT_VALID_OFFSET)
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
index 91011fe..00e7946 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
@@ -314,8 +314,8 @@
 	GT_32 reg = 0;
 
 	/* Initiates TSEN hardware reset once */
-	if ((MV_REG_READ(TSEN_CONF_REG) & TSEN_CONF_RST_MASK) == 0)
-		MV_REG_BIT_SET(TSEN_CONF_REG, TSEN_CONF_RST_MASK);
+	if ((MV_REG_READ(TSEN_CONTROL_MSB_REG) & TSEN_CONTROL_MSB_RST_MASK) == 0)
+		MV_REG_BIT_SET(TSEN_CONTROL_MSB_REG, TSEN_CONTROL_MSB_RST_MASK);
 	mvOsDelay(10);
 
 	/* Check if the readout field is valid */