diff --git a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c
index c454f11..6e77d41 100644
--- a/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c
+++ b/board/mv_ebu/a38x/armada_38x_family/ctrlEnv/mvCtrlEnvLib.c
@@ -2227,7 +2227,7 @@
 	/* Initiates TSEN hardware reset once */
 	if ((MV_REG_READ(TSEN_CONTROL_MSB_REG) & TSEN_CONTROL_MSB_RST_MASK) == 0) {
 		MV_REG_BIT_SET(TSEN_CONTROL_MSB_REG, TSEN_CONTROL_MSB_RST_MASK);
-		/* set TSEN TC Trim value */
+		/* set Tsen Tc Trim to correct default value (errata #132698) */
 		reg = MV_REG_READ(TSEN_CONTROL_LSB_REG);
 		reg &= ~TSEN_CONTROL_LSB_TC_TRIM_MASK;
 		reg |= 0x3 << TSEN_CONTROL_LSB_TC_TRIM_OFFSET;
diff --git a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
index 6dc8e24..412104a 100644
--- a/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
+++ b/tools/marvell/bin_hdr/src_ddr/ddr3libv2/src/Silicon/mvHwsDdr3a38x.c
@@ -316,7 +316,7 @@
 	/* Initiates TSEN hardware reset once */
 	if ((MV_REG_READ(TSEN_CONTROL_MSB_REG) & TSEN_CONTROL_MSB_RST_MASK) == 0) {
 		MV_REG_BIT_SET(TSEN_CONTROL_MSB_REG, TSEN_CONTROL_MSB_RST_MASK);
-		/* set TSEN TC Trim value */
+		/* set Tsen Tc Trim to correct default value (errata #132698) */
 		reg = MV_REG_READ(TSEN_CONTROL_LSB_REG);
 		reg &= ~TSEN_CONTROL_LSB_TC_TRIM_MASK;
 		reg |= 0x3 << TSEN_CONTROL_LSB_TC_TRIM_OFFSET;